JP2023101937A - Nonvolatile memory, device using memory, and vehicle - Google Patents

Abstract

To enhance usability of a nonvolatile memory.SOLUTION: A nonvolatile memory includes: a memory area having a prescribed storage capacity; a setting data retaining circuit which is configured to retain setting data; and a control circuit which is configured to allow the nonvolatile memory to operate as a memory having a storage capacity of one of a plurality of candidate capacity volumes on the basis of the retained setting data. The candidate capacity volumes are the prescribed storage capacity or less and different from each other.SELECTED DRAWING: Figure 7

Description

The present disclosure relates to non-volatile memory, memory-utilizing devices, and vehicles.

A manufacturer that manufactures a set device including a non-volatile memory obtains a non-volatile memory having a storage capacity corresponding to the specifications of each set device from a parts manufacturer for each type of set device. For example, if 200 1-kilobit nonvolatile memories are required for manufacturing the first set device, 200 or more 1-kilobit nonvolatile memories are obtained from the parts manufacturer.

JP-A-2007-47993

As a manufacturer, it is necessary to perform delivery date management and inventory management for each type of nonvolatile memory so as not to interfere with the manufacture of set devices. These management burdens are heavy. If a certain type of non-volatile memory were to be in short supply, it would hinder the manufacture of set devices that require such non-volatile memory. Thus, there is room for improvement regarding the convenience of non-volatile memory.

The present disclosure aims to provide a non-volatile memory that contributes to improved convenience (specifically, for example, contributes to a reduction in the burden of managing parts or stable production of a device having a non-volatile memory), and a memory-using device and vehicle that use the non-volatile memory.

A nonvolatile memory according to the present disclosure includes a memory area having a predetermined storage capacity, a setting data holding circuit configured to hold setting data, and a control circuit configured to operate the nonvolatile memory as a memory having any one of a plurality of candidate capacities based on the held setting data, and the plurality of candidate capacities are equal to or less than the predetermined storage capacity and different from each other.

According to the present disclosure, it is possible to provide a non-volatile memory that contributes to improved convenience (specifically, for example, contributes to a reduction in the burden of managing parts or stable production of a device having a non-volatile memory), and a memory-using device and vehicle that use the non-volatile memory.

FIG. 1 is a schematic configuration diagram of a nonvolatile memory according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of a nonvolatile memory according to an embodiment of the present disclosure; FIG. 3 is a diagram illustrating how a nonvolatile memory and an MPU are mounted on a substrate, according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating how multiple nonvolatile memories and MPUs are mounted on a substrate, according to an embodiment of the present disclosure. FIG. 5 is a diagram showing how a memory space is set for a memory area of a nonvolatile memory according to an embodiment of the present disclosure. FIG. 6 is a diagram showing a configuration register structure of a non-volatile memory according to an embodiment of the present disclosure. FIG. 7 is an operational flowchart of a device including a non-volatile memory and an MPU, according to an embodiment of the present disclosure. FIG. 8 is a structure diagram of a write command according to the first example belonging to the embodiment of the present disclosure. FIG. 9 is a structural diagram of one unit signal forming a command signal according to the first example belonging to the embodiment of the present disclosure. FIG. 10 is a diagram showing the relationship between operation modes and unit signals (U1, U2) according to the first example belonging to the embodiment of the present disclosure. FIG. 11 is a diagram showing how a device having a nonvolatile memory and an MPU is mounted on a vehicle according to a fourth example belonging to the embodiment of the present disclosure. FIG. 12 is a diagram showing multiple types of nonvolatile memories according to the reference method.

Prior to describing the embodiments of the present disclosure, general usage and management methods of non-volatile memory will be described as a reference method. Please refer to FIG. FIG. 12 shows nonvolatile memories MM[1K], MM[2K], MM[4K], MM[8K] and MM[16K] according to the reference method. The nonvolatile memories MM[1K], MM[2K], MM[4K], MM[8K], and MM[16K] are EEPROMs (Electrically Erasable Programmable Read-Only Memories) having storage capacities of 1, 2, 4, 8, and 16 kilobits, respectively.

A manufacturer that manufactures a set device including a nonvolatile memory obtains (purchases) the necessary nonvolatile memory from a parts manufacturer that manufactures or sells the nonvolatile memory, and manufactures the set device. For example, consider manufacturing 200 first set devices with one nonvolatile memory MM[1K], manufacturing 500 second set devices with one nonvolatile memory MM[4K], and manufacturing 300 third set devices with one nonvolatile memory MM[16K]. In this case, the manufacturer according to the reference method obtains 200 or more nonvolatile memories MM[1K], 500 or more nonvolatile memories MM[4K], and 300 or more nonvolatile memories MM[16K] from the parts maker.

In this way, the manufacturer according to the reference method obtains non-volatile memories having storage capacities corresponding to the specifications of each set device from the parts manufacturer for each type of set device. As a manufacturer, it is necessary to perform delivery date management and inventory management for each type of nonvolatile memory so as not to interfere with the manufacture of set devices. These management burdens are heavy. If a certain type of non-volatile memory (eg, MM[4K]) is in short supply, the production of set devices (eg, second set devices) that require such non-volatile memory will suffer.

It should be noted that when a certain storage capacity of non-volatile memory is required, it is difficult or undesirable to substitute another storage capacity of non-volatile memory. For example, the nonvolatile memory MM[1K] cannot be applied to a set device that requires the nonvolatile memory MM[4K] (capacity is insufficient). It is also considered to use the nonvolatile memory MM[16K] as a substitute for the nonvolatile memory MM[4K] for the set device that requires the nonvolatile memory MM[4K].

For example, the addresses in the non-volatile memory MM[4K] are represented by "0x000" to "0x1ff". However, since the address specification method (protocol for decoding the instruction signal) differs between the memories MM[4K] and MM[16K], when the above substitution is performed, although the address "0x100" is intended to be accessed, the address "0x300" (the address "0x300 in the memory MM[16K]" is mistakenly ”). Also, for example, if the nonvolatile memory MM[4K] is actually used, after accessing up to the address "0x1ff", the next access should be the highest address "0x000". However, when the above substitution is performed, after accessing up to the address "0x1ff", the next access will be the address "0x200". In order to prevent such unintended access, it becomes necessary to change the circuit and software that issue instructions to the nonvolatile memory. This may be burdensome for the manufacturer, or such changes may not be practical.

An example of an embodiment of the present disclosure that contributes to the reduction of the management burden and the stable production of set devices as described above will be specifically described below with reference to the drawings. In each figure referred to, the same parts are denoted by the same reference numerals, and redundant descriptions of the same parts are omitted in principle. In this specification, for simplification of description, by describing a symbol or code that refers to information, a signal, a physical quantity, an element or a part, etc., the name of the information, signal, physical quantity, element or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, a clock terminal referred to by "SCL" (see FIG. 3) below may be written as clock terminal SCL or abbreviated as terminal SCL, but they all refer to the same thing.

In addition, in the description of the embodiments of the present disclosure, a line refers to a wiring through which an electric signal is propagated or applied. The ground refers to a reference conductive portion having a potential of 0 V (zero volt) as a reference, or refers to a potential of 0 V itself. The reference conductive portion is made of a conductor such as metal. A potential of 0 V is sometimes referred to as a ground potential. In embodiments of the present disclosure, voltages shown without specific reference represent potentials with respect to ground.

FIG. 1 is a schematic configuration diagram of a nonvolatile memory 1 (hereinafter simply referred to as memory 1) according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the memory 1. FIG. The memory 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) containing the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the memory 1. A memory 1 is formed by enclosing a semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the memory 1 and the type of housing of the memory 1 shown in FIG. 2 are merely examples, and they can be designed arbitrarily.

The memory 1 according to the present embodiment is provided with setting terminals A0, A1 and A2, a ground terminal GND, a power supply terminal VCC, a write protect terminal WP, a clock terminal SCL, and a data terminal SDA as the plurality of external terminals. The memory 1 includes a memory area 10, a control circuit 20, and a setting register 30 as functional units formed of the semiconductor integrated circuit. Assume that the memory 1 is an EEPROM in this embodiment.

The memory 1 performs serial communication with an external device connected to itself. Referring to FIG. 3, it is assumed here that memory 1 and MPU (Micro Processing Unit) 2, which is an example of an arithmetic processing unit, are mounted on substrate SUB. MPU 2 is an example of the external device and is connected to memory 1 . The MPU 2 is an electronic component having a form similar to that of the memory 1. As part of the external terminals of the MPU 2, only a power supply terminal VCC2, a ground terminal GND2, a clock terminal SCL2, and a data terminal SDA2 are shown in FIG.

The power supply voltage Vcc is input to the power supply terminal VCC of the memory 1 and the power supply terminal VCC2 of the MPU 2 on the substrate SUB. Power supply voltage Vcc has a predetermined positive DC voltage value (eg, 3.3 V or 5.0 V). In the substrate SUB, the ground terminal GND of the memory 1 and the ground terminal GND2 of the MPU 2 are grounded. Each functional unit in the memory 1 operates based on the power supply voltage Vcc with reference to the ground potential. The same is true for MPU2. Although not particularly shown, the memory 1 is provided with a high voltage generation circuit that generates a voltage higher than the power supply voltage Vcc from the power supply voltage Vcc, and the memory area 10 uses the voltage generated by the high voltage generation circuit to store necessary data.

In this embodiment, storage of data or values and storage of data or values are synonymous. In this embodiment, high level refers to a potential higher than a predetermined threshold voltage, and low level refers to a potential lower than the predetermined threshold voltage. The threshold voltage here is a voltage higher than 0V and lower than the power supply voltage Vcc, for example half the power supply voltage Vcc. In the following, it is assumed that the high level is the power supply voltage Vcc level and the low level is the ground level.

The memory 1 according to this embodiment performs serial communication with the MPU 2 . In this embodiment, it is assumed that an I ² C (Inter-Integrated Circuit) interface is used as a serial communication interface. In other words, it is assumed that serial communication by I ² C is performed as serial communication between the memory 1 and the MPU 2 . In the substrate SUB, a clock bus B- _SCL for transmitting clock signals and a data bus B _-SDA for transmitting data signals are provided. Although not shown, pull-up resistors may be provided between the clock bus _BSCL and data bus _BSDA and the power supply lines to which the power supply voltage Vcc is applied. Clock terminal SCL of memory 1 and clock terminal SCL2 of MPU 2 are connected to clock bus _BSCL . That is, the clock terminal SCL is connected to the clock terminal SCL2 via the clock bus _BSCL . Data terminal SDA of memory 1 and data terminal SDA2 of MPU 2 are connected to data bus _BSDA . That is, the data terminal SDA is connected to the data terminal _SDA2 via the data bus BSDA. In I ² C serial communication, the MPU 2 functions as a master and the memory 1 functions as a slave.

Although only one memory 1 is shown in FIG. 3, a plurality of memories 1 may be mounted on the substrate SUB and connected to the MPU 2 as shown in FIG. In this case, the clock terminal SCL of each memory 1 is connected to the clock bus _BSCL and the data terminal SDA of each memory 1 is connected to the data bus _BSDA . When only one memory 1 is connected to the MPU 2, the clock bus _{B_SCL} and data bus _{B_SDA} do not exist, and it can be simply considered that the clock terminals SCL and SCL2 are connected together and the data terminals SDA and SDA2 are connected together.

A high level or low level voltage is applied to the terminals A2 to A0, WP, SCL and SDA of the memory 1 . In the substrate SUB, high-level or low-level voltages are individually and fixedly input to the setting terminals A2 to A0 of the memory 1. FIG. However, one or more of the setting terminals A2 to A0 may be in an open state depending on the operation mode to be described later. The voltages input to the setting terminals A2 to A0 are collectively referred to as terminal setting voltages, and expressed as "(A2, A1, A0)=(a, b, c)". Alternatively, the voltages input to the setting terminals A2 and A1 are collectively referred to as terminal setting voltages and expressed as "(A2, A1)=(a, b)". Alternatively, the voltage input to the setting terminal A2 is referred to as a terminal setting voltage and is expressed as "A2=a".

The variables a, b and c in the notation "(A2, A1, A0)=(a, b, c)", "(A2, A1)=(a, b)" or "A2=a" take 1 or 0 respectively. In the notation "(A2, A1, A0)=(a, b, c)", "(A2, A1)=(a, b)" or "A2=a", when the variable a is 1, it means that a high level voltage is applied to the setting terminal A2, and when the variable a is 0, it means that a low level voltage is applied to the setting terminal A2. Similarly, in the notation "(A2, A1, A0)=(a, b, c)" or "(A2, A1)=(a, b)", when the variable b is 1, it means that a high level voltage is applied to the setting terminal A1, and when the variable b is 0, it means that a low level voltage is applied to the setting terminal A1. Similarly, in the notation "(A2, A1, A0)=(a, b, c)", a variable c of 1 means that a high level voltage is applied to the setting terminal A0, and a variable c of 0 means that a low level voltage is applied to the setting terminal A0.

In the example of FIG. 3, the setting terminals A2-A0 of a single memory 1 are all connected to ground, so (A2, A1, A0)=(0,0,0). As shown in FIG. 4, when there are a plurality of memories 1 connected to the clock bus B- _SCL and the data bus B- _SDA , different terminal setting voltages are input to the plurality of memories 1 . A plurality of slaves as a plurality of memories 1 are distinguished by the terminal setting voltage.

A high-level or low-level voltage is input to the write protect terminal WP. When the input voltage to the write protect terminal WP is at high level, the control circuit 20 prohibits writing data to the memory area 10 . In this embodiment, it is assumed that the input voltage to the write protect terminal WP is fixed at a low level (that is, writing data to the memory area 10 is permitted).

MPU2 outputs a clock signal from clock terminal SCL2. A clock signal is input to the clock terminal SCL of the memory 1 via the clock bus _BSCL . Thus, the clock terminal SCL2 functions as a clock output terminal that outputs a clock signal, and the clock terminal SCL functions as a clock input terminal that receives the clock signal. The clock signal is a rectangular wave signal that alternates between low and high signal levels.

Each of the data terminals SDA and SDA2 sometimes functions as a data output terminal for outputting a data signal to the data bus _BSDA and sometimes functions as a data input terminal for receiving a data signal transmitted through the data bus _BSDA . A device that outputs a data signal to the data bus _BSDA is called a transmitter, and a device that receives the data signal transmitted on the data bus _BSDA is called a receiver. The device here is MPU2 or memory1. According to the ^I2C specification, only one of the devices connected to the data bus _{B_SDA} can be the transmitter at any given time.

Memory area 10 is a non-volatile storage area having a predetermined storage capacity C-- _REF . The storage capacity C-- _REF is arbitrary. Here, for concreteness of explanation, it is assumed that the storage capacity C _{- - REF} is a storage capacity of 16 kilobits. One kilobit is 1024 bits. In the memory 1, data can be written in the memory area 10 in units of words, and data can be read out from the memory area 10 in units of words. In this embodiment, 1 word is 1 byte. However, multiple bytes may correspond to one word. 1 byte consists of 8 bits.

The control circuit 20 sets (in other words, defines) the memory space MS in the memory area 10 as shown in FIG. Although the details will be described later, the control circuit 20 may set the memory space MS for the entire memory area 10 or may set the memory space MS for a part of the memory area 10 . The memory space MS may be referred to as an actual use memory space. A unique address is assigned every 8 bits (ie, 1 byte) in the memory space MS. In the following description, addresses refer to addresses in memory space MS. An address is represented by a numerical value, and an address indicated by a smaller numerical value is an address on the lower side of the observed address, and an address indicated by a larger numerical value is an address on the upper side of the observed address. When the memory space MS is set for the entire area of the memory area 10, the memory space MS corresponds to a storage capacity of 16 kilobits (that is, a storage capacity of 2 kilobytes), so the lowest address in the memory space MS is "0x000" and the highest address in the memory space MS is "0x7ff". In addition, in this embodiment, the addresses are appropriately expressed in hexadecimal numbers. The character string "0x" added to the beginning of the numerical value indicating the address indicates that the numerical value following the character string "0x" is a hexadecimal number. Therefore, "0x000" represents "0" in decimal notation, and "0x7ff" represents "2047" in decimal notation.

The MPU 2 can output multiple types of instructions to the memory 1 . Signals representing commands are specifically referred to as command signals. The MPU 2 can output an arbitrary instruction to the memory 1 by outputting an instruction signal representing an arbitrary instruction from the data terminal SDA2 while outputting a clock signal from the clock terminal SCL2 according to a predetermined protocol. The memory 1 receives the command by receiving the command signal at the data terminal SDA according to the above protocol while receiving the clock signal at the clock terminal SCL. The above protocol is a communication protocol defined by I ² C and a communication protocol defined between the memory 1 and the CPU 2 .

The multiple types of instructions include write instructions and read instructions. A plurality of types of write instructions can exist as write instructions. Here, however, it is assumed that the write instruction is an instruction to write 1-byte write data to the target address, and that the target address is specified in the write instruction. In the write command, the target address indicates the address to be written. The write data is 1-byte data specified in the write command. A plurality of types of read instructions can exist as read instructions. Here, however, it is assumed that the read instruction is an instruction to read one byte of data stored at the target address, and that the target address is specified in the read instruction. In the read instruction, the target address indicates the address to be read.

The control circuit 20 accesses the memory space MS (in other words, the memory area 10) according to the content of the instruction received from the MPU2. When the control circuit 20 receives a write command (that is, receives a command signal representing the write command at the terminal SDA), the control circuit 20 writes write data to a target address in the memory space MS. When the control circuit 20 receives a read command (that is, receives a command signal representing the read command at the terminal SDA), the control circuit 20 reads 1-byte data stored at the target address in the memory space MS and outputs the read data from the terminal SDA as serial data. Thus, the write instruction and the read instruction are instructions to access the target address in the memory space MS. The access includes a write access for writing write data to a target address within the memory space MS and a read access for reading data stored at the target address within the memory space MS.

A control circuit 20 is connected to terminals A0-A2, WP, SCL and SDA (see FIG. 1). The control circuit 20 permits or prohibits write access based on the voltage at the write protect terminal WP. The control circuit 20 performs serial communication with the MPU 2 by I ² C through terminals SCL and SDA. During the serial communication, the set terminal voltages for the terminals A0 to A2 are referred to (this will be explained later).

The setting register 30 is a storage area connected to the control circuit 20 . The setting register 30 may be a register built into the control circuit 20 . As shown in FIG. 6, the setting register 30 has a storage area 31 for 3 bits. The storage area 31 is a non-volatile storage area. The storage area 31 consists of first to third bits, and the values of the first, second and third bits of the storage area 31 are represented by X, Y and Z, respectively. Configuration register 30 may include other storage areas in addition to storage area 31 . Various setting information can be stored in other storage areas. The control circuit 20 can read data stored in the setting register 30 and can write necessary data to the setting register 30 .

The control circuit 20 operates the memory 1 as a memory (nonvolatile memory) having a storage capacity of any one of the first to n-th candidate capacities according to the data stored in the storage area 31, that is, according to the values of X, Y and Z. The 3-bit data consisting of the values of X, Y, and Z is setting data for determining which of the first to n-th candidate capacities the memory 1 should operate as a memory (non-volatile memory). n is an arbitrary integer of 2 or more. In this embodiment, as a specific example, "n=5" and the first, second, third, fourth, and fifth candidate capacities are 1 kilobit, 2 kilobits, 4 kilobits, 8 kilobits, and 16 kilobits, respectively. The MPU 2 can arbitrarily rewrite the setting data (X, Y, Z) by giving a specific command to the memory 1 .

Therefore, a manufacturer that manufactures a set device including the substrate SUB can incorporate the memory 1 into the set device as a memory having a required storage capacity simply by purchasing the memory 1 in advance. That is, for example, when manufacturing a set device that needs to incorporate a 1-kilobit nonvolatile memory, the memory 1 set to operate as a 1-kilobit memory may be applied to the set device. Similarly, for example, when manufacturing a set device that needs to incorporate a 4-kilobit nonvolatile memory, the memory 1 set to operate as a 4-kilobit memory may be applied to the set device. A manufacturer who manufactures a set device only has to manage the delivery date and inventory of the memory 1, which is one type of component, as the delivery date management and inventory management for the non-volatile memory. In addition, the production (mass production) of the setting device can be stabilized by reducing the number of types of parts that require delivery date management and inventory management.

The control circuit 20 reads setting data (X, Y, Z) from the setting register 30, and selects any one of the first to n-th candidate capacitors as a target capacitor according to the setting data (X, Y, Z). The control circuit 20 sets a memory space MS having a target capacity in the memory area 10 . That is, the target capacity is the capacity of the memory space MS shown in FIG. The target capacity corresponds to the capacity of the storage area actually accessed in response to the command signal (actual used capacity).

The control circuit 20 operates in any one of first to n-th operation modes according to set data (X, Y, Z). Since "n=5" is assumed in this embodiment, the n-th operation mode is the fifth operation mode. Here, the control circuit 20
operate in the first operation mode when "(X, Y, Z)=(0, 0, 0)";
operate in the second operation mode when "(X, Y, Z)=(1, 0, 0)";
operate in the third operation mode when "(X, Y, Z)=(0, 1, 0)";
operate in the fourth operation mode when "(X, Y, Z)=(1, 1, 0)";
It is assumed that when "(X, Y, Z)=(0, 0, 1)", it operates in the fifth operation mode. The initial values of X, Y and Z (the initial values of X, Y and Z at the time of manufacture or shipment of the memory 1) are arbitrary. By way of example only, the initial values for X, Y and Z may be zero.

The i-th operation mode is an operation mode for operating the memory 1 as a memory (nonvolatile memory) having the i-th candidate capacity. i represents an arbitrary integer. That is, for example, the first operation mode is an operation mode in which the memory 1 is operated as a memory (nonvolatile memory) having a storage area of 1 kilobit, and the second operation mode is an operation mode in which the memory 1 is operated as a memory (nonvolatile memory) having a storage area of 2 kilobits. The same applies to the third to fifth operation modes.

Control circuit 20 sets memory space MS to 1/16 of the entire area of memory area 10 in the first operation mode (more specifically, when operating in the first operation mode). Therefore, the memory space MS in the first operation mode has a storage capacity of (C _REF ×1/16). Therefore, in the first operation mode, the control circuit 20 recognizes that the lowest address and highest address of the memory space MS are "0x00" and "0x7f", respectively.
Control circuit 20 sets memory space MS for 1/8 of the entire area of memory area 10 in the second operation mode (more specifically, when operating in the second operation mode). Therefore, the memory space MS in the second operation mode has a storage capacity of (C _REF ×1/8). Therefore, in the second operation mode, the control circuit 20 recognizes that the lowest address and highest address of the memory space MS are "0x00" and "0xff", respectively.
Control circuit 20 sets memory space MS to 1/4 of the entire area of memory area 10 in the third operation mode (more specifically, when operating in the third operation mode). Therefore, the memory space MS in the third operation mode has a storage capacity of (C _REF ×1/4). Therefore, the control circuit 20 recognizes that the lowest address and highest address of the memory space MS are "0x000" and "0x1ff" respectively in the third operation mode.
Control circuit 20 sets memory space MS to 1/2 of the entire area of memory area 10 in the fourth operation mode (more specifically, when operating in the fourth operation mode). Therefore, the memory space MS in the fourth operation mode has a storage capacity of (C _REF ×1/2). Therefore, in the fourth operation mode, the control circuit 20 recognizes that the lowest address and highest address of the memory space MS are "0x000" and "0x3ff", respectively.
Control circuit 20 sets memory space MS for the entire area of memory area 10 in the fifth operation mode (more specifically, when operating in the fifth operation mode). Therefore, the memory space MS in the fifth operation mode has a storage capacity of (C _REF ×1). Therefore, in the fifth operation mode, the control circuit 20 recognizes that the lowest address and highest address of the memory space MS are "0x000" and "0x7ff", respectively.

The memory 1 receives a command signal representing a command at the data terminal SDA, and the control circuit 20 accesses the memory space MS in response to the command signal in each operation mode (more specifically, write access or read access to the target address in the memory space MS).

Therefore, the problems described in relation to the reference method do not occur. For example, when the memory 1 operates as a memory having a storage capacity of 1 kilobit, the memory 1 operates in exactly the same way as the nonvolatile memory MM[1K] for the MPU2, and when the memory 1 operates as a memory having a storage capacity of 4 kilobits, the memory 1 operates in exactly the same way as the nonvolatile memory MM[4K] for the MPU2.

The command signal is an encoded signal, and the control circuit 20 decodes the command signal in one of a plurality of different protocols based on the setting data (X, Y, Z).

As a result, correct decoding can be performed according to the size of the memory space MS, and the problems described in relation to the reference method do not occur.

The plurality of protocols are n types of protocols, and the n types of protocols are referred to as first to n-th protocols. When outputting a command signal to the memory 1 in which the i-th candidate capacity is selected as the target capacity, the MPU 2 generates the command signal by encoding according to the i-th protocol. The control circuit 20 decodes the instruction signal in the i-th protocol in the i-th operation mode (more specifically, when operating in the i-th operation mode). That is, for example, the control circuit 20 decodes the command signal according to the first protocol in the first operation mode (more specifically, when operating in the first operation mode), and decodes the command signal according to the second protocol in the second operation mode (more specifically, when operating in the second operation mode). The same applies to the third to fifth operation modes.

As described above, the target address is specified in the command signal representing the write command or read command. As will be explained later, the command signal is a multi-bit signal (digital signal). The control circuit 20 recognizes the target address based on the i-th bit group data in the command signal in the i-th operation mode (more specifically, when operating in the i-th operation mode). That is, for example, the control circuit 20 recognizes the target address based on the data of the first bit group in the command signal in the first operation mode (specifically, when operating in the first operating mode), and recognizes the target address based on the data of the second bit group in the command signal in the second operating mode (specifically, when operating in the second operating mode). The same applies to the third to fifth operation modes.

Specifically, in the i-th operation mode (more specifically, when operating in the i-th operation mode), the control circuit 20 decodes the instruction signal according to the i-th protocol, thereby recognizing the data of the i-th bit group in the instruction signal as data specifying the target address. The first mode of operation corresponds to 1 kilobit (ie 128 bytes), 128=2 ⁷ , so the bit length of the first bit group is 7. That is, in the first operation mode, the target address is designated by 7-bit data in the command signal. Considering similarly, the second mode of operation corresponds to 2 kilobits (ie 256 bytes), 256=2 ⁸ , so the bit length of the second bit group is 8. That is, in the second operation mode, the target address is designated by 8-bit data in the command signal. Similarly, the bit length of the third bit group, the bit length of the fourth bit group, and the bit length of the fifth bit group are 9, 10, and 11, respectively.

Correct decoding can be performed by changing the method of recognizing the target address according to the size of the memory space MS to be actually accessed.

As described above, the MPU 2 can arbitrarily rewrite the setting data (X, Y, Z) by giving specific commands to the memory 1 . Focusing on the memory 1, the memory 1 changes the setting data (X, Y, Z) according to the specific command when it receives the specific command. The specific instruction is called a storage capacity designation instruction. FIG. 7 shows an operation flowchart of the setting device provided with the substrate SUB. A set device equipped with the substrate SUB is, for example, a memory utilization device 310 (see FIG. 11), which will be described later. After the memory 1 and the MPU 2 are mounted on the substrate SUB, the MPU 2 outputs a storage capacity designation command to the memory 1 in step S1. Similar to a write command or a read command, the memory 1 receives a storage capacity specification command by receiving a command signal representing the storage capacity specification command at a data terminal SDA while receiving a clock signal at the clock terminal SCL. The values of X, Y and Z are specified in the storage capacity specifying command. The control circuit 20 writes the value specified by the storage capacity specification command to the storage area 31 in the setting register 30 when receiving the storage capacity specification command. That is, in step S2, the control circuit 20 sets the values of X, Y and Z based on the storage capacity designation command received from the MPU1. As a result, the setting data (X, Y, Z) specified by the storage capacity specification command are held in the storage area 31 . After that, the memory 1 operates in an operation mode corresponding to the setting data (X, Y, Z) held in the storage area 31 (step S3). Since the storage area 31 is a non-volatile storage area, the MPU 1 only needs to output the storage capacity instruction command once when it is started for the first time. That is, it is sufficient to execute the processing of steps S1 and S2 only once.

Hereinafter, some specific operation examples, applied techniques, modified techniques, etc., among a plurality of embodiments will be described. The matters described above in the present embodiment are applied to each of the following examples unless otherwise stated and without contradiction. In each embodiment, if there are matters that contradict the above-described matters, the description in each embodiment may take precedence. In addition, as long as there is no contradiction, the matter described in any of the following embodiments can be applied to any other embodiment (that is, any two or more of the embodiments can be combined).

<<First embodiment>>
A first embodiment will be described. Please refer to FIG. The write command may be the write command WC shown in FIG. Focusing on the write command WC, the differences between the first to fifth protocols will be explained.

A write command WC includes three unit signals U1, U2 and U3. When the write command WC is input from the MPU 2 to the memory 1, the unit signals are input to the memory 1 in the order of the unit signals U1, U2 and U3.

FIG. 9 shows the structure of a unit signal. Each unit signal is an 8-bit serial signal and consists of 1st to 8th bit digital signals. When the unit signal is output from the MPU 2 to the memory 1, the (j+1)th bit signal is output next to the jth bit signal (where j is a natural number of 7 or less). A 1-bit signal is input/output in one clock period. One clock section refers to the section between two adjacent rising edges in the clock signal. An up edge here refers to a low-to-high transition in the level of the clock signal. When the signals at the data terminals (SDA, SDA2) are at high level, the signals have a value of "1", and when the signals at the data terminals (SDA, SDA2) are at a low level, the signals have a value of "0".

In serial communication using I ² C, command transmission starts after the start condition is established, and command transmission ends when the stop condition is established. When the device (memory 1 or MPU 2) functioning as a receiver receives the 8-bit unit signal, it functions as a transmitter for one clock period and outputs a 1-bit acknowledge signal from the data terminal (SDA or SDA2). Since the start condition, stop condition, and acknowledge signal are well known as I ² C specifications, their existence will be ignored here for explanation.

In the write command WC, the target address is specified by the unit signal U2 alone or by the unit signals U1 and U2 depending on the size of the memory space MS. In the write command WC, 8-bit write data to be written to the target address is designated by the unit signal U3.

FIG. 10 shows the relationship between the operation mode of the control circuit 20 and the unit signals U1 and U2. The values of the 1st to 4th bits in the unit signal U1 are common in all operation modes. The values of the 1st to 4th bits in the unit signal U1 are predetermined fixed values and device codes unique to the memory 1. FIG. The value of the eighth bit in the unit signal U1 indicates whether the instruction including the unit signal U1 is a write instruction or a read instruction. In the write command WC, the value of the 8th bit in the unit signal U1 is "0". In the read command, the value of the 8th bit in the unit signal U1 is set to "1".

In the first or second mode of operation, the values of the fifth, sixth and seventh bits in unit signal U1 correspond to values a2, a1 and a0, respectively. In the first or second operating mode the values a2, a1 and a0 correspond to a 3-bit slave select signal. On the substrate SUB, up to eight memories 1 operating in the first or second operating mode can be connected in parallel to the MPU 2 (in other words to the buses B _SCL and B _SDA ).

Among the memories 1 connected to the buses _BSCL and _BSDA and operating in the first or second operation mode, only the memories 1 whose terminal setting voltages (A2, A1, A0) correspond to the values (a2, a1, a0) respond to the command signal. "a2=1", "a1=1" and "a0=1" correspond to application of high level voltages to the setting terminals A2, A1 and A0, respectively. "a2=0", "a1=0", and "a0=0" correspond to applying low-level voltages to the setting terminals A2, A1, and A0, respectively.

Thus, for example, consider a first case in which first and second memories 1 operating in the first or second mode of operation are connected in parallel to buses _BSCL and _BSDA , of which "(A2, A1, A0)=(0,0,0)" for the first memory 1 and "(A2, A1, A0)=(0,0,1)" for the second memory 1. In the first case, if the unit signal U1 is "(a2, a1, a0)=(0, 0, 0)", the first memory 1 is selected as the device to respond to the command signal, and only the first memory 1 responds to the response signal. In the first case, if the unit signal U1 is "(a2, a1, a0)=(0, 0, 1)", the second memory 1 is selected as the device to respond to the command signal, and only the second memory 1 responds to the response signal.

In the third mode of operation, the values of the fifth and sixth bits in unit signal U1 correspond to values a2 and a1, respectively. In the third mode of operation the values a2 and a1 correspond to a 2-bit slave select signal. On the substrate SUB, up to four memories 1 operating in the third operating mode can be connected in parallel to the MPU 2 (in other words to the buses _BSCL and _BSDA ).

Among the memories 1 connected to the buses _BSCL and _BSDA and operating in the third operation mode, only the memories 1 whose terminal setting voltages (A2, A1) correspond to the values (a2, a1) respond to the command signal. Thus, for example, consider a second case in which first and second memories 1 operating in the third mode of operation are connected in parallel to buses B-- _SCL and B-- _SDA , of which "(A2, A1)=(0,0)" for first memory 1 and "(A2, A1)=(0,1)" for second memory 1. In the second case, if the unit signal U1 is "(a2, a1)=(0, 0)", the first memory 1 is selected as the device to respond to the command signal, and only the first memory 1 responds to the response signal. In the second case, if the unit signal U1 is "(a2, a1)=(0, 1)", the second memory 1 is selected as the device to respond to the command signal, and only the second memory 1 responds to the response signal.

In the fourth operation mode, the value of the fifth bit in unit signal U1 corresponds to value a2. In the fourth operating mode, the value a2 corresponds to a 1-bit slave select signal. On the substrate SUB, up to two memories 1 operating in the fourth operating mode can be connected in parallel to the MPU 2 (in other words to the buses B _SCL and B _SDA ).

Among the memories 1 connected to the buses _BSCL and _BSDA and operating in the fourth operation mode, only the memory 1 whose terminal setting voltage A2 corresponds to the value a2 responds to the command signal. Thus, for example, consider a third case in which first and second memories 1 operating in the fourth mode of operation are connected in parallel to buses _BSCL and _BSDA , of which "A2=0" for the first memory 1 and "A2=1" for the second memory 1. In the third case, if "a2=0" in the unit signal U1, the first memory 1 is selected as the device to respond to the command signal, and only the first memory 1 responds to the response signal. In the third case, if the unit signal U1 is "a2=1", the second memory 1 is selected as the device to respond to the command signal, and only the second memory 1 responds to the response signal.

A signal corresponding to the slave selection signal is not defined in the fifth operation mode. On the substrate SUB, only one memory 1 operating in the fifth mode of operation can be connected to the MPU 2 (in other words to the buses _BSCL and _BSDA ). When the memory 1 operating in the fifth operation mode receives a command signal, it always interprets the command signal as a command signal directed to itself and always responds to the command signal.

The control circuit 20 recognizes the target address based on the data of the target bit group in the command signal in each operation mode. The bit lengths of the target bit groups are different among the first to nth operation modes. The target bit group in the i-th operation mode corresponds to the i-th bit group described above. This will be explained below.

In the first operation mode, the target address is designated by the data (value) of the first bit group consisting of the second to eighth bits of the unit signal U2. The bit length of the first bit group is seven. In the first operation mode, the control circuit 20 recognizes the target address based on the data of the first bit group. That is, the control circuit 20, which decodes the command signal according to the first protocol, recognizes the target address based on the data of the first bit group. In the first operation mode, the 2nd to 8th bits of the unit signal U2 correspond to the bits WA6 to WA0, respectively, and the value obtained by regarding the values of the bits WA6 to WA0 as a 7-digit binary number corresponds to the target address. For example, in the first operation mode, when the values of bits WA6 to WA0 are all 0, the target address is the lowest address "0x00" of the memory space MS, and when the values of bits WA6 to WA0 are all 1, the target address is the highest address "0x7f" of the memory space MS. In the first mode of operation, the first bit of unit signal U2 has no significant value.

In the second operation mode, the target address is designated by the data (value) of the second bit group consisting of the 1st to 8th bits of the unit signal U2. The bit length of the second bit group is eight. In the second operation mode, the control circuit 20 recognizes the target address based on the data of the second bit group. That is, the control circuit 20, which decodes the command signal according to the second protocol, recognizes the target address based on the data of the second bit group. In the second operation mode, the 1st to 8th bits of the unit signal U2 correspond to the bits WA7 to WA0, respectively, and the value obtained by regarding the values of the bits WA7 to WA0 as an 8-digit binary number corresponds to the target address. For example, in the second operation mode, when the values of bits WA7 to WA0 are all 0, the target address is the lowest address "0x00" of the memory space MS, and when the values of bits WA7 to WA0 are all 1, the target address is the highest address "0xff" of the memory space MS.

In the third operation mode, the target address is designated by the data (value) of the third bit group consisting of the 7th bit of the unit signal U1 and the 1st to 8th bits of the unit signal U2. The bit length of the third bit group is nine. In the third operation mode, the control circuit 20 recognizes the target address based on the data of the third bit group. That is, the control circuit 20, which decodes the command signal according to the third protocol, recognizes the target address based on the data of the third bit group. In the third operation mode, the 7th bit of the unit signal U1 corresponds to the bit WA8, the 1st to 8th bits of the unit signal U2 correspond to the bits WA7 to WA0, respectively, and the value obtained by regarding the values of the bits WA8 to WA0 as a 9-digit binary number corresponds to the target address. For example, in the third operation mode, when the values of bits WA8 to WA0 are all 0, the target address is the lowest address "0x000" of the memory space MS, and when the values of bits WA8 to WA0 are all 1, the target address is the highest address "0x1ff" of the memory space MS.

In the fourth operation mode, the target address is designated by the data (value) of the fourth bit group consisting of the 6th and 7th bits of the unit signal U1 and the 1st to 8th bits of the unit signal U2. The bit length of the fourth bit group is ten. In the fourth operation mode, the control circuit 20 recognizes the target address based on the data of the fourth bit group. That is, the control circuit 20, which decodes the command signal according to the fourth protocol, recognizes the target address based on the data of the fourth bit group. In the fourth operation mode, the 6th and 7th bits of the unit signal U1 correspond to the bits WA9 and WA8, respectively, the 1st to 8th bits of the unit signal U2 correspond to the bits WA7 to WA0, respectively, and the value obtained by regarding the values of the bits WA9 to WA0 as a 10-digit binary number corresponds to the target address. For example, in the fourth operation mode, when the values of bits WA9 to WA0 are all 0, the target address is the lowest address "0x000" of the memory space MS, and when the values of bits WA9 to WA0 are all 1, the target address is the highest address "0x3ff" of the memory space MS.

In the fifth operation mode, the target address is designated by the data (value) of the fifth bit group consisting of the fifth to seventh bits of the unit signal U1 and the first to eighth bits of the unit signal U2. The bit length of the fifth bit group is eleven. In the fifth operation mode, the control circuit 20 recognizes the target address based on the data of the fifth bit group. That is, the control circuit 20, which decodes the command signal according to the fifth protocol, recognizes the target address based on the data of the fifth bit group. In the fifth operation mode, the 5th to 7th bits of the unit signal U1 correspond to the bits WA10 to WA8, respectively, the 1st to 8th bits of the unit signal U2 correspond to the bits WA7 to WA0, respectively, and the value obtained by regarding the values of the bits WA10 to WA0 as an 11-digit binary number corresponds to the target address. For example, in the fifth operation mode, when the values of bits WA10 to WA0 are all 0, the target address is the lowest address "0x000" of the memory space MS, and when the values of bits WA10 to WA0 are all 1, the target address is the highest address "0x7ff" of the memory space MS.

Although the method of specifying the target address in the command signal has been described by focusing on the write command, the method of specifying the target address in the read command is also the same as in the write command.

<<Second embodiment>>
A second embodiment will be described. A device other than the MPU 2 may be used as a device for outputting (transmitting) the storage capacity specifying command to the memory 1 . For example, a writing board (not shown) having a socket mounted thereon, which is different from the board SUB, is prepared, and the memory 1 is mounted on the socket of the writing board. In this mounted state, an arithmetic processing unit (not shown) mounted on or connected to the writing board supplies a memory capacity designation command to the memory 1 through the socket. As a result, the control circuit 20 may write the value specified by the storage capacity specification command to the storage area 31 in the setting register 30 . After that, the memory 1 is mounted on the substrate SUB, and thereafter the memory 1 operates in an operation mode corresponding to the setting data (X, Y, Z) held in the storage area 31 .

<<Third embodiment>>
A third embodiment will be described. Although it was mentioned above that memory 1 is formed as an EEPROM, memory 1 may be any kind of non-volatile memory. For example, memory 1 may be a flash memory.

<<Fourth Embodiment>>
A fourth embodiment will be described.

MPU 2 is an example of a command signal output circuit that outputs command signals to memory 1 . A device that uses the memory 1 is called a memory-using device. A memory utilization device is an arbitrary device having a substrate SUB on which a memory 1 and an MPU are mounted.

As shown in FIG. 11, the memory utilization device 310 may be installed in a vehicle 300 such as an automobile. Vehicle 300 includes, in addition to memory utilization device 310, an engine (not shown) that generates power for running vehicle 300, a battery (not shown) made up of a secondary battery, and the like. Engines include internal combustion engines or motors. The memory utilization device 310 is driven based on the output voltage of the battery. Memory utilization device 310 may be an ECU (Electronic Control Unit) mounted on vehicle 300 . Memory utilization device 310 may be, for example, a device that controls travel of vehicle 300 or a device that controls arbitrary electrical components (audio device, air conditioner, etc.) of vehicle 300 . It may be understood that the memory utilization device 310 is incorporated in the electrical components of the vehicle 300 .

However, the application destination of the memory utilization device is arbitrary. For example, the memory utilization device may be an information terminal device including a smart phone, a tablet terminal, a personal computer, or the like, or may be a game device, a home appliance, or the like.

In the above-described embodiment, "n=5" and 1, 2, 4, 8, and 16 kilobits are given as the first to fifth candidate capacities for the sake of concreteness of explanation. However, as already mentioned, n may be any integer of 2 or more. Therefore, for example, "n=7" and the first to seventh candidate capacities may be set to 1, 2, 4, 8, 16, 32 and 64 kilobits, respectively. Further, the candidate capacities listed here are only examples, and the first to n-th candidate capacities are arbitrary as long as they are equal to or smaller than the above storage capacity C _REF and are different from each other.

Although the configuration and operation when using I ² C as an interface for serial communication between memory 1 and MPU 2 have been described above, the interface is not limited to I ² C. For example, an SPI (Serial Peripheral Interface) or Microwire interface may be used as an interface for serial communication between the memory 1 and the MPU 2 .

The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea indicated in the scope of claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above embodiments. The specific numerical values given in the above description are merely examples and can of course be changed to various numerical values.

<<Appendix>>
Additional remarks are provided for the present disclosure in which specific configuration examples are shown in the above-described embodiments.

A nonvolatile memory according to one aspect of the present disclosure includes a memory area (10) having a predetermined storage capacity (C _REF ), a setting data holding circuit (30) configured to hold setting data, and a control circuit (20) configured to operate the nonvolatile memory as a memory having any one of a plurality of candidate capacities based on the held setting data (X, Y, Z), wherein the plurality of candidate capacities are equal to or less than the predetermined storage capacity and have different configurations (th 1).

As a result, a user who requires a nonvolatile memory can form (manufacture) a plurality of types of devices that require nonvolatile memories of various capacities simply by obtaining the nonvolatile memory according to the first configuration, which is highly convenient. For example, a manufacturer that manufactures a set device including a nonvolatile memory only has to manage the delivery date and inventory of the nonvolatile memory according to the first configuration as delivery date management and inventory management for the nonvolatile memory. In addition, the production (mass production) of the setting device can be stabilized by reducing the number of types of parts that require delivery date management and inventory management.

The nonvolatile memory according to the first configuration may further include a terminal (SDA) configured to receive an input of a command signal, and the control circuit may select one of the plurality of candidate capacities as a target capacity based on the held setting data, and access a memory space (MS) having the target capacity in response to the command signal (second configuration).

As a result, the problems described in relation to the reference method described above do not occur. A circuit that outputs a command signal is sufficient if the nonvolatile memory according to the second configuration is treated as a nonvolatile memory having a target capacity.

In the non-volatile memory according to the second configuration, the control circuit may be configured to decode the command signal using one of a plurality of mutually different protocols based on the held setting data (third configuration).

As a result, correct decoding can be performed according to the size of the memory space, and the problems described in relation to the reference method do not occur.

In the non-volatile memory according to the second or third configuration, the command signal may be a multi-bit signal that commands access to a target address in the memory space, and the control circuit may be configured to recognize the target address based on data of a group of bits corresponding to the target capacity included in the command signal (fourth configuration).

Correct decoding can be performed by varying the method of recognizing the target address according to the size (target capacity) of the memory space to be actually accessed.

In the nonvolatile memory according to the fourth configuration, the control circuit may operate in one of a plurality of operation modes corresponding to the plurality of candidate capacities based on the held setting data, the control circuit may recognize the target address based on the data of the target bit group in the command signal in each operation mode, and the bit length of the target bit group may be different among the plurality of operation modes (fifth configuration).

Correct decoding can be performed by changing the method of recognizing the target address (the bit length of the target bit group representing the target address) according to the size of the memory space that is actually the target of access.

In the nonvolatile memory according to any one of the second to fifth configurations, when a specific command signal is input to the terminal, the control circuit may hold data corresponding to the specific command signal as the setting data in the setting data holding circuit (sixth configuration).

As a result, it is possible to arbitrarily specify which memory capacity the nonvolatile memory is to operate as.

The nonvolatile memory according to any one of the first to sixth configurations may be an EEPROM or a flash memory (seventh configuration).

A memory utilization device according to an aspect of the present disclosure includes a nonvolatile memory according to any one of the second to sixth configurations, and a command signal output circuit configured to output the command signal to the nonvolatile memory (eighth configuration).

A vehicle according to an aspect of the present disclosure has a configuration (eighth configuration) in which the nonvolatile memory according to the eighth configuration is mounted.

1 nonvolatile memory 2 MPU
10 memory area 20 control circuit 30 setting register 31 storage area A0, A1, A2 setting terminal GND ground terminal VCC power supply terminal WP write protect terminal SCL, SCL2 clock terminal SDA, SDA2 data terminal SUB substrate B _SCL clock bus B _SDA data bus MS memory space 300 vehicle 310 memory using device

Claims (9)

In non-volatile memory,
a memory area having a predetermined storage capacity;
a setting data holding circuit configured to hold setting data;
a control circuit configured to operate the nonvolatile memory as a memory having any one of a plurality of candidate capacities based on the held setting data;
A nonvolatile memory, wherein the plurality of candidate capacities are equal to or less than the predetermined storage capacity and are different from each other. further comprising a terminal configured to receive an input of the command signal;
2. The nonvolatile memory according to claim 1, wherein said control circuit selects one of said plurality of candidate capacities as a target capacity based on said held setting data, and accesses a memory space having said target capacity in response to said command signal. 3. The nonvolatile memory according to claim 2, wherein said control circuit decodes said command signal according to any one of a plurality of mutually different protocols based on said held setting data. the command signal is a multi-bit signal that commands access to a target address in the memory space;
4. The nonvolatile memory according to claim 2, wherein said control circuit recognizes said target address based on data of a bit group corresponding to said target capacity, which is included in said command signal. the control circuit operates in one of a plurality of operation modes corresponding to the plurality of candidate capacitances based on the held setting data;
The control circuit recognizes the target address based on data of the target bit group in the command signal in each operation mode,
5. The nonvolatile memory according to claim 4, wherein bit lengths of said target bit group are different among said plurality of operation modes. 6. The nonvolatile memory according to any one of claims 2 to 5, wherein when a specific command signal is input to the terminal, the control circuit causes the setting data holding circuit to hold data corresponding to the specific command signal as the setting data. Non-volatile memory according to any one of claims 1 to 6, which is an EEPROM or a flash memory. a nonvolatile memory according to any one of claims 2 to 6;
a command signal output circuit configured to output the command signal to the nonvolatile memory. A vehicle equipped with the memory utilization device according to claim 8 .

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