JP2023094903A - Ferroelectric memory reading circuit, ferroelectric memory, and ferroelectric memory reading method - Google Patents

Abstract

To provide a ferroelectric memory reading circuit, a ferroelectric memory, and a ferroelectric reading method for reducing influence of noise when reading the ferroelectric memory.SOLUTION: A control circuit 11 of a reading circuit 10 controls an input voltage so that an input voltage of a memory cell 13, which is a voltage between a plate line (PL) electrically connected to the other terminal of a ferroelectric capacitor 13a and a bit line (BL), is fixed, based on the result of comparing a bit line potential, which is a potential of bit line electrically connected to one terminal of a ferroelectric capacitor 13a and a first reference potential (VREF1), when reading data from a memory cell 13, and a sense amplifier 12 determines a data value based on the comparison result between the bit line potential and a second reference potential (VREF2) when the input voltage is fixed.SELECTED DRAWING: Figure 1

Description

The present invention relates to a ferroelectric memory readout circuit, a ferroelectric memory, and a ferroelectric memory readout method.

In a ferroelectric memory, a memory cell including a ferroelectric capacitor stores data "0" or "1" depending on the polarization state of the ferroelectric material.
At the time of reading, for example, the potential of the plate line connected to one terminal of the ferroelectric capacitor (hereinafter referred to as plate line potential) is increased. At this time, the potential of the bit line electrically connected to the other terminal of the ferroelectric capacitor (hereinafter referred to as bit line potential) is determined whether "0" or "1" is stored in the memory cell. Varies depending on Such a difference in bit line potential is caused by the presence or absence of polarization reversal of the ferroelectric.

For example, when the plate line potential is raised as described above, when "1" is stored in the memory cell, the ferroelectric polarization reversal occurs and a large current flows through the bit line. On the other hand, when "0" is stored in the memory cell, polarization reversal does not occur even if the plate line potential is increased, and little current flows through the bit line. A sense amplifier connected to the bit line determines data according to the comparison result between the bit line potential and the reference potential.

The readout accompanied by the reversal of the polarization of the ferroelectric as described above is called destructive readout.
Further, in a ferroelectric memory, rewriting is performed in order to retain the same data in the same memory cell even after reading.

By the way, conventionally, according to the result of comparison between the bit line potential and the reference potential when the plate line potential is raised, charge is supplied to the bit line so that the bit line potential does not change, and based on the amount of the supplied charge, There has been a technique of discriminating data by means of data (for example, see Patent Document 1).

Conventionally, in order to prevent destabilization of the reference potential due to deterioration of the memory cell for generating the reference potential, the read potential from the memory cell storing "0" in which polarization inversion does not occur is raised to increase the reference potential. There was a technique to obtain (for example, see Patent Document 2).

Furthermore, conventionally, there is a technique of charging a bit line via a resistor, significantly changing the rate of rise of the bit line potential depending on the presence or absence of polarization reversal in a memory cell, and discriminating data at the timing when a sufficient read margin is obtained. There was (for example, see Patent Document 3).

Japanese Patent Application Laid-Open No. 2001-351374 Japanese Patent Application Laid-Open No. 2001-57071 Japanese Patent Application Laid-Open No. 2006-31800

In a ferroelectric memory, when the read margin of "0" and "1" becomes small due to fatigue deterioration of memory cells, etc., it becomes susceptible to noise, and malfunction may occur.

In one aspect, the present invention aims to provide a readout circuit that is less susceptible to noise, a ferroelectric memory having such a readout circuit, and a readout method for the ferroelectric memory.

In one embodiment, in a read circuit of a ferroelectric memory including a memory cell including a ferroelectric capacitor, when data is read from the memory cell, the terminal is electrically connected to one terminal of the ferroelectric capacitor. A plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line, based on a comparison result between the bit line potential, which is the potential of the bit line to be applied, and a first reference potential. a control circuit for controlling the input voltage so that the input voltage of the memory cell, which is a voltage between A ferroelectric memory read circuit is provided, comprising a sense amplifier for determining the value of the data based on a result of comparison between the plate line potential and a second reference potential.

Also provided in one embodiment is a ferroelectric memory.
Also, in one embodiment, a method of reading a ferroelectric memory is provided.

In one aspect, according to the present invention, it becomes less susceptible to noise when reading data from a memory cell of a ferroelectric memory.

1 is a diagram showing an example of a readout circuit of a ferroelectric memory according to a first embodiment; FIG. FIG. 4 is a diagram showing hysteresis loop characteristics of a ferroelectric capacitor; 4 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the first embodiment; FIG. 4 is a diagram showing the relationship between _VPL and the amount of charge supplied to BL; FIG. 3 is a diagram showing a part of a ferroelectric memory of a comparative example; 4 is a timing chart showing an example of read operation of a ferroelectric memory of a comparative example; It is a figure which shows an example of a ferroelectric memory. FIG. 3 is a diagram showing an example of part of a memory cell array and part of a column-related circuit section; FIG. 10 is a diagram showing an example of a readout circuit of a ferroelectric memory according to a second embodiment; FIG. 8 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the second embodiment; FIG. 4 is a diagram showing the relationship between _VPL and the amount of charge supplied to BL; FIG. 10 is a diagram showing an example of a readout circuit of a ferroelectric memory according to a third embodiment; FIG. 13 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the third embodiment; 3 is a diagram showing the relationship between _VBL and V _RBL and the amount of charge supplied to a ferroelectric capacitor; FIG. FIG. 10 is a diagram showing the relationship between the magnitude of bit line capacitance and the magnitude of read margin for a ferroelectric memory of a comparative example; 4 is a diagram showing the relationship between the magnitude of bit line capacitance and the magnitude of read margin in the ferroelectric memory of the first embodiment; FIG. FIG. 10 is a diagram showing the relationship between the magnitude of bit line capacitance and the magnitude of read margin in the ferroelectric memory of the second embodiment; FIG. 10 is a diagram showing the relationship between the magnitude of bit line capacitance and the magnitude of read margin in the ferroelectric memory of the third embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing an example of a readout circuit of a ferroelectric memory according to the first embodiment. In FIG. 1, WL represents a word line, BL a bit line, and PL a plate line.

A read circuit 10 for a ferroelectric memory according to the first embodiment is a circuit for reading data stored in memory cells 13 connected to WL, PL and BL.
The memory cell 13 has a ferroelectric capacitor 13a and an n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) (hereinafter abbreviated as nMOS) 13b. One end of the ferroelectric capacitor 13a is connected to PL, and the other end is connected to the drain of the nMOS 13b. The source of nMOS13b is connected to BL, and the gate of nMOS13b is connected to WL.

In such a memory cell 13, when the potential of WL is raised during reading or writing, the nMOS 13b is turned on, and the other end of the ferroelectric capacitor 13a and BL are electrically connected. Note that the nMOS 13b is sometimes called an access transistor or an access gate.

The read circuit 10 has a control circuit 11 and a sense amplifier (denoted as “SA” in FIG. 1) 12 .
Based on the result of comparison between the bit line potential, which is the potential of BL, and the reference potential (V _REF1 ), the control circuit 11 fixes the input voltage of the memory cell 13, which is the voltage between PL and BL. to control the input voltage.

In the ferroelectric memory readout circuit 10 of the first embodiment, the control circuit 11 has a differential amplifier 11a. The differential amplifier 11a has an inverting input terminal (marked as "-" in FIG. 1) and a non-inverting input terminal (marked as "+" in FIG. 1), and the inverting input terminal is connected to BL. , and the potential of the non-inverting input terminal is V-- _REF1 . An output terminal of the differential amplifier 11a is connected to PL. Here, _VREF1 is a constant potential, and is applied to the non-inverting input terminal of the differential amplifier 11a by a reference potential generating circuit 24 (see FIG. 7), which will be described later. V-- _REF1 is appropriately set so that the read margin becomes an appropriate size.

The differential amplifier 11a becomes effective when reading data from the memory cell 13, outputs a signal obtained by amplifying the difference between the bit line potential and _VREF1 , and raises the plate line potential. The amplification factor is, for example, 100 times, 1000 times, or the like.

Such a differential amplifier 11a fixes the input voltage of the memory cell 13 by stopping the increase of the plate line potential when the bit line potential reaches _VREF1 .
A sense amplifier 12 is connected to PL. The sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the comparison result between the plate line potential and the reference potential (V _REF2 ) when the input voltage is fixed, and outputs the determination result. and outputs DATA. Here, V _REF2 is a constant potential, which is applied to the sense amplifier 12 by a reference potential generating circuit 24 (see FIG. 7), which will be described later. _VREF2 is set, for example, to be an intermediate potential between the plate line potential when "0" is read from the memory cell 13 and the plate line potential when "1" is read from the memory cell 13. there is

Note that FIG. 1 also shows an nMOS 14 . The nMOS 14 has a drain connected to BL and a source grounded. A precharge signal PRECHG is input to the gate of the nMOS 14 . PRECHG is supplied by a controller 23 (see FIG. 7) which will be described later. Further, FIG. 1 shows bit line capacitance (parasitic capacitance of BL) 15 .

In such a readout circuit 10, charges are supplied from the PL to the ferroelectric capacitor 13a as indicated by arrows.
FIG. 2 is a diagram showing hysteresis loop characteristics of a ferroelectric capacitor. The horizontal axis represents the potential difference (V _PL -V _BL ) between PL and BL (corresponding to the input voltage of the memory cell 13 described above), and the vertical axis represents the amount of polarization Q. FIG.

As shown in FIG. 2, the ferroelectric capacitor 13a has two stable points with different polarization amounts Q when V _PL −V _BL is 0 V. The stable point on the positive side is “0” and the stable point on the negative side is “0” A dot corresponds to "1". The stable point on the positive side may be set to "1" and the stable point on the negative side may be set to "0".

As V _PL -V _BL increases, the polarization quantity Q changes in the direction of the arrow along the hysteresis loop characteristics. At this time, the amount of change ΔQ in the polarization amount Q is larger when it changes from the stable point on the negative side than when it changes from the stable point on the positive side. This is because polarization reversal occurs in the ferroelectric when changing from the stable point on the negative side.

Therefore, for example, when "1" is stored in the memory cell 13, a large current flows through BL, and when "0" is stored in the memory cell 13, polarization reversal does not occur and a small amount of current flows through BL. Not flowing.

FIG. 3 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the first embodiment. FIG. 3 shows temporal changes in potential (V) of PRECHG, OAEN which is an enable signal for the differential amplifier 11a, and SAEN which is an enable signal for the sense amplifier 12. FIG. Further, FIG. 3 shows temporal changes in V _WL which is the potential of WL, V PL which is the potential of PL, V _BL which is the potential of _BL , and the potential (V) of DATA which is the output of the sense amplifier 12 . ing.

When the potential of PRECHG, for example, falls from the power supply potential to the ground potential (for example, 0 V) (timing t1), nMOS 14 is turned off and BL becomes floating.

When _VWL rises (timing t2) and the potential of OAEN rises, the differential amplifier 11a starts operating, and _VPL and _VBL start rising. As a result, the nMOS 13b is turned on, and data reading from the memory cell 13 begins. At this time, depending on the presence or absence of the above-mentioned polarization reversal, the increase per unit time is smaller when "0" is stored in the memory cell 13 than when "1" is stored (that is, , slow rising).

Therefore, when "1" is stored in the memory cell 13, _VBL reaches _VREF1 earlier than when "0" is stored in the memory cell 13 (timing t3). , stop the rise of _VPL . As a result, V _BL also stops rising, and the input voltage (V _PL -V _BL ) of memory cell 13 is fixed.

On the other hand, when "0" is stored in the memory cell 13, _VBL reaches _VREF1 later than when "1" is stored in the memory cell 13 (timing t4). Stop the increase in _VPL . As a result, V _BL also stops rising, and the input voltage (V _PL -V _BL ) of memory cell 13 is fixed.

After that, when the potential of OAEN falls, the differential amplifier 11a stops operating ( _timing t5), and the potential _of SAEN rises. It determines the value of the data stored in the memory cell 13 and outputs DATA, which is the determination result. If V _PL ≧V _REF2 , DATA="0" (eg, ground potential), and if V _PL <V _REF2 , DATA="1" (eg, power supply potential).

After that, _VPL and _VBL are set based on the determination result (timing t6), _VWL is further increased, and rewriting to the memory cell 13 is performed. When "0" is rewritten, _VPL is further raised and _VBL is pulled down to ground potential. When "1" is rewritten, _VPL is pulled down to ground potential and _VBL is further pulled up.

When a plurality of memory cells 13 are connected to the same WL (see FIG. 8), _VPL is controlled for each memory cell according to the above read method. Therefore, when rewriting a plurality of memory cells connected to the same WL, the processing of writing "0" and the processing of writing "1" are performed at different timings as in a comparative example (see FIG. 6) described later. You don't have to.

When the potential of PRECHG rises to the power supply potential (timing t7), the nMOS 14 is turned on and _VBL is fixed at the ground potential.
FIG. 4 is a diagram showing the relationship between _VPL and the amount of charge supplied to BL. The horizontal axis represents _VPL , and the vertical axis represents the amount of charge (Q) supplied to BL.

FIG. 4 shows the relationship between _VPL and the amount of charge supplied to BL when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. In FIG. ing. Q _VREF1 represents the amount of charge delivered to BL when V _BL =V _REF1 . V _PL1 is the V _PL when Q=Q _VREF1 when "1" is stored in the memory cell 13 . _VPL0 is the _VPL when Q= _QVREF1 when "0" is stored in memory cell 13;

Therefore, in the ferroelectric memory read circuit 10 of the first embodiment, the read margin is V _PL0 -V _PL1 . Since the read margin is determined by the value of Q _VREF1 , it is affected by the bit line capacitance 15 . The relationship between the size of the bit line capacitance 15 and the size of the read margin will be described later (see FIG. 16).

In the ferroelectric memory readout circuit 10 of the first embodiment as described above, the control circuit 11 fixes the input voltage of the memory cell 13 based on the comparison result between _VBL and _VREF1 . to control the input voltage.

For example, even if _VBL temporarily exceeds _VREF1 due to noise in the process of _VPL rising and _VPL stops rising, when VBL returns to normal, _VPL continues to rise _{and VBL} drops to V When it reaches _REF1 , _VPL stops rising and the input voltage of memory cell 13 is fixed.

Since the sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the result of comparison between _VPL and _VREF2 when the input voltage is fixed, it is affected by noise. Hateful.

In the read circuit 10, the control circuit 11 includes a differential amplifier 11a, and the difference between _VBL and _VREF1 is detected by the differential amplifier 11a. It is easy to increase the gain of the differential amplifier 11a, and if the gain is large, the differential amplifier 11a can operate correctly even if there are variations in the input offset and _VREF1 of the differential amplifier 11a.

(Comparative example)
FIG. 5 is a diagram showing part of a ferroelectric memory of a comparative example. Elements that are the same as those shown in FIG. 1 are given the same reference numerals.

In FIG. 5, the sense amplifier 12 is connected to BL, determines the value of the data stored in the memory cell 13 based on the result of comparison between _VBL and _VREF , and outputs DATA, which is the determination result. Output.

FIG. 6 is a timing chart showing an example of the read operation of the ferroelectric memory of the comparative example. FIG. 6 shows changes over time in the potential (V) of PRECHG and SAEN, which is an enable signal for the sense amplifier 12 . Further, FIG. 6 shows changes over time of V _WL which is the potential of WL, V PL which is the potential of PL, V _BL which is the potential of _BL , and the potential (V) of DATA which is the output of the sense amplifier 12 . ing.

When the potential of PRECHG, for example, falls from the power supply potential to the ground potential (for example, 0V) (timing t10), nMOS 14 is turned off and BL becomes floating.

When _VWL rises (timing t11) and a predetermined _VPL is applied to PL, _VBL also starts to rise. As a result, reading of data from the memory cell 13 starts. At this time, depending on the presence or absence of the above-mentioned polarization reversal, when "0" is stored in the memory cell 13, the increase width of _VBL per unit time is greater than when "1" is stored. Small (i.e. slow rising speed).

When the potential of SAEN rises (timing t12), the sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the result of comparison between _VBL and _VREF . to output If V _BL ≧V _REF , DATA="1" (eg, power supply potential), and if V _BL <V _REF , DATA="0" (eg, ground potential).

After that, in order to rewrite "0", _VBL is lowered to the ground potential while _VPL is maintained as it is (timing t13). Next, in order to rewrite "1", _VPL is pulled down to the ground potential while _VBL is maintained as it is (timing t14).

When the potential of PRECHG rises to the power supply potential (timing t15), the nMOS 14 is turned on and _VBL is fixed at the ground potential.
Such a ferroelectric memory of the comparative example becomes susceptible to noise when the read margin becomes small due to deterioration of the ferroelectric capacitor 13a or the like.

On the other hand, the ferroelectric memory according to the first embodiment has the readout circuit 10 and is less susceptible to noise for the reason described above.
(Example of ferroelectric memory to which readout circuit 10 is applied)
FIG. 7 is a diagram showing an example of a ferroelectric memory.

The ferroelectric memory 20 has a memory cell array 21 , an address buffer 22 , a controller 23 , a reference potential generation circuit 24 , a row related circuit section 25 and a column related circuit section 26 .
The memory cell array 21 has a plurality of memory cells arranged in a matrix, a plurality of bit lines, a plurality of word lines, and a plurality of plate lines (see FIG. 8 described later).

The address buffer 22 receives an address from outside the ferroelectric memory 20 and supplies the received address to the row related circuit section 25 and the column related circuit section 26 .
The controller 23 receives commands (chip select signal, write enable signal, output enable signal, etc.) from outside the ferroelectric memory 20 . Then, the controller 23 supplies various control signals (PRECHG, SAEN, etc. described above) to the row-related circuit section 25 and the column-related circuit section 26 based on the received command.

The reference potential generation circuit 24 generates the aforementioned reference potentials (V _REF1 and V _REF2 ).
The row-related circuit section 25 includes, for example, a row decoder and a driver circuit, although illustration is omitted. The row decoder generates a row decode signal by decoding a row address (for example, upper bits of the address signal) included in the address, and supplies the generated row decode signal to the driver circuit. The driver circuit applies a predetermined voltage for a predetermined period to the word line specified by the row decode signal among the plurality of word lines according to the control signal supplied from the controller 23 .

Although not shown, the column-related circuit section 26 includes a column decoder, a write amplifier, an input/output circuit, and the readout circuit 10 shown in FIG.
FIG. 8 is a diagram showing an example of part of the memory cell array and part of the column-related circuitry.

As shown in FIG. 8, memory cell array 21 includes memory cells 13 shown in FIG. When the read circuit 10 is used, multiple memory cells connected to the same WL have different _VPLs , so the PLs are arranged orthogonally to the WL.

Also, the column-related circuit section 26 includes the nMOS 14 and the readout circuit 10 shown in FIG. Further, the column related circuit section 26 includes a column decoder/write amplifier section 26a and an input/output circuit 26b. A configuration similar to the nMOS 14 and readout circuit 10 is provided for each pair of BL and PL.

Column decoder/write amplifier section 26a includes, for example, a column decoder, a write amplifier, and a column switch. The column decoder generates a column decode signal by decoding a column address included in the address (for example, lower bits of the address signal). The generated column decode signal is supplied to a column switch, and the column switch selects one of a plurality of BLs and a plurality of PLs to be connected to the write amplifier and input/output circuit 26b based on the column decode signal.

The input/output circuit 26b includes, for example, a write buffer that holds write data supplied from the outside of the ferroelectric memory 20. FIG. The write buffer may have the function of holding data read by the sense amplifier 12 for write-back.

The input/output circuit 26b holds and outputs the data value determined by the sense amplifier 12. FIG.
The read circuit 10 can be applied to the ferroelectric memory 20 as described above.

(Second embodiment)
FIG. 9 is a diagram showing an example of a readout circuit of the ferroelectric memory according to the second embodiment. In FIG. 9, the same reference numerals are assigned to the same elements as those shown in FIG. In FIG. 1, WL is a word line, BL is a bit line, PL is a plate line, RWL is a reference word line, and RBL is a reference bit line.

The ferroelectric memory readout circuit 30 of the second embodiment has a sense amplifier 12 and a control circuit 31, like the ferroelectric memory readout circuit 10 of the first embodiment. Furthermore, the readout circuit 30 has a capacitor 32 and an nMOS 33 .

The capacitor 32 has one end electrically connected to PL and the other end connected to the drain of the nMOS 33 . The source of nMOS33 is connected to RBL, and the gate of nMOS33 is connected to RWL. Note that the capacitor 32 is not a ferroelectric capacitor, but a linear capacitor whose retained charge amount increases in proportion to an increase in applied voltage. When the memory cell 13 is read, the potential of RWL is raised, the nMOS 33 is turned on, and the other end of the capacitor 32 and BL are electrically connected.

The control circuit 31 of the read circuit 30 fixes the input voltage of the memory cell 13, which is the voltage between PL and BL, based on the comparison result between _VBL , which is the potential of BL, and _VRBL , which is the potential of RBL. control the input voltage so that

Like the control circuit 11 of the readout circuit 10, the control circuit 31 has a differential amplifier 31a, and the inverting input terminal of the differential amplifier 31a is connected to BL. On the other hand, the non-inverting input terminal of the differential amplifier 31a is connected to RBL. The output terminal of the differential amplifier 31a is connected to PL.

The differential amplifier 31a becomes effective when reading data from the memory cell 13, outputs a signal obtained by amplifying the difference between _VBL and _VRBL , and raises _VPL , which is the potential of PL. The differential amplifier 31a fixes the input voltage of the memory cell 13 by stopping the increase of _VPL when _VBL reaches _VRBL .

A sense amplifier 12 is connected to PL. The sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the comparison result between _VPL and _VREF when the input voltage is fixed, and outputs DATA as the determination result. do. Here, V _REF is a constant potential and is applied to the sense amplifier 12 by the reference potential generating circuit 24 shown in FIG. V _REF is, for example, set similarly to V _REF2 in FIG.

Note that FIG. 9 also shows an nMOS 34 . The drain of nMOS 34 is connected to RBL and the source is grounded. Also, PRECHG is input to the gate of the nMOS 34 . Further, FIG. 9 shows the bit line capacitance 35 of the RBL.

In such a readout circuit 30, charges are supplied from the PL to the ferroelectric capacitor 13a and the capacitor 32 as indicated by two arrows.
FIG. 10 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the second embodiment. FIG. 10 shows temporal changes in potential (V) of PRECHG, OAEN which is an enable signal for the differential amplifier 31a, and SAEN which is an enable signal for the sense amplifier 12. FIG. Further, FIG. 10 shows V _WL that is the potential of WL, V PL that is the potential of PL, V _BL that is the potential of _BL , V _RBL that is the potential of RBL, and the potential of DATA that is the output of the sense amplifier 12 ( V) is shown over time.

When the potential of PRECHG, for example, falls from the power supply potential to the ground potential (for example, 0V) (timing t20), nMOSs 14 and 34 are turned off, and BL and RBL are floated.

When _VWL rises (timing t21) and the potential of OAEN rises, the differential amplifier 31a starts operating, and _VPL and _VBL start rising. As a result, the nMOS 13b is turned on, and data reading from the memory cell 13 begins. At this time, depending on the presence or absence of the above-mentioned polarization reversal, when "0" is stored in the memory cell 13, the increase width of _VBL per unit time is greater than when "1" is stored. Small (i.e. slow rising speed). On the other hand, although not shown, at timing t21, the potential of RWL also rises and the nMOS 33 is turned on. As a result, V _RBL rises in proportion to time.

FIG. 10 shows an enlarged view of the rising portions of V _BL and V _RBL . A solid line indicates _VBL when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13 . On the other hand, V _RBL is indicated by a dashed line in the enlarged view, and shows the case where "0" is stored in the memory cell 13 after timing t22. Until timing t22, V _RBL changes similarly whether "0" is stored in the memory cell 13 or "1" is stored.

As shown in the enlarged view of FIG. 10, when "1" is stored in memory cell 13, _VBL reaches V _RBL at timing t22. Therefore, the differential amplifier 31a stops increasing _VPL . As a result, V _BL and V _RBL also stop rising, and the input voltage (V _PL -V _BL ) of the memory cell 13 is fixed.

On the other hand, when "0" is stored in memory cell 13, _VBL does not reach V _RBL . As a result, _VPL reaches the maximum value (for example, the power supply potential) and continues to rise. When V _PL reaches the maximum value (timing t23), V _BL and V _RBL also stop rising, and the input voltage (V _PL -V _BL ) of memory cell 13 is fixed.

After that, when the potential of OAEN falls, the differential amplifier 31a stops operating ( _timing t24), and the _potential of SAEN rises. It determines the value of the data stored in the memory cell 13 and outputs DATA, which is the determination result. If V _PL ≧V _REF , DATA="0" (eg, ground potential), and if V _PL <V _REF , DATA="1" (eg, power supply potential).

After that, _VPL and _VBL are set based on the determination result (timing t25), _VWL is further increased, and rewriting to the memory cell 13 is performed. When "0" is rewritten, _VBL is pulled down to the ground potential while _VPL is maintained. When "1" is rewritten, _VPL is pulled down to ground potential and _VBL is further pulled up.

When a plurality of memory cells 13 are connected to the same WL (see FIG. 8), _VPL is controlled for each memory cell according to the above read method. Therefore, when rewriting a plurality of memory cells connected to the same WL, writing "0" and writing "1" are performed at different timings as in the comparative example (see FIG. 6). you don't have to.

When the potential of PRECHG rises to the power supply potential (timing t26), the nMOSs 14 and 34 are turned on, and _VBL and _VRBL are fixed at the ground potential.
FIG. 11 is a diagram showing the relationship between _VPL and the amount of charge supplied to BL. The horizontal axis represents _VPL , and the vertical axis represents the amount of charge (Q) supplied to BL.

FIG. 11 shows the relationship between _VPL and the amount of charge supplied to BL when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. In FIG. ing. In FIG. 11, the relationship between _VPL and the amount of charge supplied to RBL is indicated by a broken line. The slope of the dashed line is determined by the size of capacitor 32 (C _REF ).

_VPL0 is the maximum value of _VPL obtained when "0" is stored in the memory cell 13. FIG. V _PL1 is V _PL when V _BL =V _RBL when "1" is stored in memory cell 13 .

Therefore, in the ferroelectric memory read circuit 30 of the second embodiment, the read margin is V _PL0 -V _PL1 .
In the readout circuit 30 of the ferroelectric memory of the second embodiment as described above, the control circuit 31 fixes the input voltage of the memory cell 13 based on the comparison result between _VBL and _VRBL . to control the input voltage.

For example, even if _VBL temporarily exceeds V _RBL due to noise in the process of VPL rising and _VPL stops rising, _when VBL returns to normal, _VPL continues to rise _{and VBL} drops to V When it reaches _RBL , _VPL stops rising and the input voltage of memory cell 13 is fixed.

Since the sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the result of comparison between _VPL and _VREF when the input voltage is fixed, it is affected by noise. Hateful.

In the read circuit 30, the control circuit 31 includes a differential amplifier 31a, and the differential amplifier 31a detects the difference between _VBL and V _RBL . It is easy to increase the gain of the differential amplifier 31a, and if the gain is large, the differential amplifier 31a can operate correctly even if there are variations in the input offset and _VRBL of the differential amplifier 31a.

Further, the read circuit 30 increases _VPL until it reaches its maximum value when "0" is stored in the memory cell 13, and when it reaches the maximum value, _VBL is fixed. As a result, a relatively large read margin can be obtained, and the influence of noise can be reduced.

The readout circuit 30 as described above is also applicable to the ferroelectric memory 20 as shown in FIG. The configuration of the column related circuit section 26 as shown in FIG. 8 may be changed in accordance with the circuit configuration of the readout circuit 30. When the read circuit 30 is used, multiple memory cells connected to the same WL have different _VPLs , so the PLs are arranged orthogonally to the WL.

(Third Embodiment)
FIG. 12 is a diagram showing an example of a readout circuit of the ferroelectric memory according to the third embodiment. Elements in FIG. 12 that are the same as those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 12, WL is a word line, BL is a bit line, PL is a plate line, RWL is a reference word line, and RBL is a reference bit line.

The ferroelectric memory readout circuit 40 of the third embodiment has a sense amplifier 12 and a control circuit 41, like the ferroelectric memory readout circuit 10 of the first embodiment. Furthermore, the readout circuit 40 has a capacitor 42 and an nMOS 43 .

The capacitor 42 has one end grounded and the other end connected to the source of the nMOS 43 . The drain of nMOS43 is connected to RBL, and the gate of nMOS43 is connected to RWL. Note that the capacitor 42 is not a ferroelectric capacitor but a linear capacitor in which the amount of retained charge increases in proportion to the increase in applied voltage. When the memory cell 13 is read, the potential of RWL is raised, the nMOS 43 is turned on, and the other end of the capacitor 42 and BL are electrically connected.

The control circuit 41 of the read circuit 40 fixes the input voltage of the memory cell 13, which is the voltage between PL and BL, based on the comparison result between _VBL , which is the potential of BL, and _VRBL , which is the potential of RBL. control the input voltage so that

The control circuit 41, like the control circuit 11 of the readout circuit 10, has a differential amplifier 41a. Further, the control circuit 41 includes p-channel MOSFETs (hereinafter abbreviated as pMOS) 41b and 41c.

In the differential amplifier 41a, the inverting input terminal is connected to BL, and the non-inverting input terminal is connected to RBL. Also, the output terminal of the differential amplifier 41a is connected to the gates of the pMOSs 41b and 41c. RBL is connected to the drain of pMOS 41b, and BL is connected to the drain of pMOS 41c. A power supply voltage (VDD) is applied to the sources of the pMOSs 41b and 41c.

The differential amplifier 41a becomes effective when data is read from the memory cell 13, and has a function of controlling the current amounts of BL and RBL by means of an output signal. The differential amplifier 41a outputs an output signal that turns off the pMOSs 41b and 41c when _VBL falls below _VRBL as will be described later. This stops _VBL from rising and fixes _VBL .

In the ferroelectric memory according to the third embodiment, _VPL is fixed at the ground potential (0 V, for example) when the memory cell 13 is read. Therefore, when _VBL stops rising and _VBL is fixed, the input voltage of memory cell 13 is also fixed.

In the read circuit 40, the sense amplifier 12 is connected to BL. The sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the comparison result between _VBL and _VREF when the input voltage is fixed, and outputs DATA as the determination result. do. Here, V _REF is a constant potential and is applied to the sense amplifier 12 by the reference potential generating circuit 24 shown in FIG. V _REF is, for example, set similarly to V _REF2 in FIG.

Note that FIG. 12 also shows an nMOS 44 . The drain of nMOS 44 is connected to RBL and the source is grounded. Also, PRECHG is input to the gate of the nMOS 34 . Further, FIG. 12 shows the bit line capacitance 45 of RBL.

In such a readout circuit 40, charges are supplied from RBL to capacitor 42, and charges are supplied from BL to ferroelectric capacitor 13a, as indicated by two arrows.
FIG. 13 is a timing chart showing an example of the operation of the readout circuit of the ferroelectric memory according to the third embodiment.

FIG. 13 shows changes over time in the potential (V) of PRECHG, OAEN which is the enable signal of the differential amplifier 41a, SAEN which is the enable signal of the sense amplifier 12, and AMPOUT which is the output signal of the differential amplifier 41a. ing. Further, FIG. 13 shows V _WL that is the potential of WL, V PL that is the potential of PL, V _BL that is the potential of _BL , V _RBL that is the potential of RBL, and the potential of DATA that is the output of the sense amplifier 12 ( V) is shown over time. The time change of _VRBL is indicated by a dashed line.

When the potential of OAEN is the ground potential, the differential amplifier 41a does not operate, and the output signal AMPOUT of the differential amplifier 41a is the power supply potential. That is, the initial potential of AMPOUT is the power supply potential. Therefore, the pMOSs 41b and 41c are off.

When the potential of PRECHG, for example, falls from the power supply potential to the ground potential (for example, 0 V) (timing t30), nMOSs 14 and 44 are turned off, and BL and RBL are floated.

When _VWL rises (timing t31) and the potential of OAEN rises, the nMOS 13b is turned on, the differential amplifier 41a starts operating, and _VBL starts rising. Along with this, the potential of AMPOUT also begins to fall, the pMOSs 41b and 41c are turned on, and BL and RBL are charged by VDD. Note that _VPL remains at the ground potential.

As a result, reading of data from the memory cell 13 starts. When the ferroelectric memory readout circuit 40 of the third embodiment is used, polarization reversal occurs when "0" is stored in the memory cell 13, unlike the case shown in FIG. Therefore, the amount of charge drawn from _BL to the ferroelectric capacitor 13a shown in FIG. , slow rising).

On the other hand, although not shown, at timing t31, the potential of RWL also rises and the nMOS 43 is turned on. As a result, V _RBL rises in proportion to time.

FIG. 13 shows an enlarged view of the rising portions of V _BL and V _RBL . A solid line indicates _VBL when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13 . The _VRBL , on the other hand, is indicated by a dashed line in the enlarged view. Until timing t32, V _RBL changes similarly whether "0" is stored in the memory cell 13 or "1" is stored.

As shown in the enlarged view of FIG. 13, _VBL is equal to V _RBL when "0" is stored in memory cell 13 and when "1" is stored in memory cell 13. Faster than rising speed. However, when "0" is stored in the memory cell 13, the rising speed gradually slows down, and _VBL falls below V _RBL at timing t32. At this time, the potential of AMPOUT rises, pMOS 41b and 41c are turned off, and _VBL and _VRBL are fixed.

On the other hand, when "1" is stored in the memory cell 13, _VBL reaches the power supply potential (for example, VDD) and is fixed, and then V _RBL also reaches the power supply potential and is fixed.
Since V _PL is fixed at the ground potential, the input voltage (V _PL −V _BL ) of memory cell 13 is fixed by fixing V _BL as described above.

After that, the potential of the signal OAEN falls to stop the operation of the differential amplifier 41a (timing t33), and the potential of the signal SAEN rises (timing t34). As a result, the sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the result of comparison between _VBL and _VREF , and outputs DATA, which is the determination result. If V _BL ≧V _REF , DATA="1" (eg, power supply potential), and if V _BL <V _REF , DATA="0" (eg, ground potential).

After that, _VWL is further increased, and rewriting to the memory cell 13 is performed (timing t35). _First , "1" is rewritten while _VBL and _VPL are maintained as they are _. is raised to a predetermined potential (timing t36).

When the potential of the signal PRECHG rises to the power supply potential (timing t37), the nMOSs 14 and 44 are turned on, and _VBL and _VRBL are fixed at the ground potential.
FIG. 14 is a diagram showing the relationship between V _BL and V _RBL and the amount of charge supplied to the ferroelectric capacitor. The horizontal axis represents _VPL , and the vertical axis represents the amount of charge (Q) supplied to the ferroelectric capacitor 13a.

FIG. 14 shows the relationship between V _BL and V _RBL when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13, and the amount of charge supplied to BL. It is shown. In FIG. 14, the relationship between _VBL and the charge amount is indicated by a solid line, and the relationship between V _RBL and the charge amount is indicated by a broken line. The slope of the dashed line is determined by the size of capacitor 32 (C _REF ).

V _BL0 is V _BL when V _BL =V _RBL when "0" is stored in the memory cell 13 . _VBL1 is the maximum value of _VBL obtained when "1" is stored in the memory cell 13. FIG.

Therefore, in the ferroelectric memory read circuit 40 of the third embodiment, the read margin is V _BL1 -V _BL0 .
In the ferroelectric memory readout circuit 40 of the third embodiment as described above, the control circuit 41 fixes the input voltage of the memory cell 13 based on the comparison result between _VBL and _VRBL . Control the input voltage.

Since the sense amplifier 12 determines the value of the data stored in the memory cell 13 based on the comparison result between _VBL and _VREF when the input voltage is fixed, the data is affected by noise. Hateful.

Further, in the read circuit 40, the control circuit 41 includes a differential amplifier 41a, and the difference between _VBL and V _RBL is detected by the differential amplifier 41a. It is easy to increase the gain of the differential amplifier 41a, and if the gain is large, the differential amplifier 41a can operate correctly even if there are variations in the input offset and _VRBL of the differential amplifier 41a.

The readout circuit 40 as described above is also applicable to the ferroelectric memory 20 as shown in FIG. The configuration of the column related circuit section 26 as shown in FIG. 8 may be changed in accordance with the circuit configuration of the readout circuit 40.

Note that when the readout circuit 40 is used, a plurality of memory cells connected to the same WL may have the same _VPL . may be placed.

(Relationship Between Bit Line Capacitance and Read Margin)
The relationship between the magnitude of the bit line capacitance 15 and the magnitude of the read margin when the ferroelectric memory read circuits 10, 30, and 40 of the above embodiments are used will be described below. First, the relationship between the magnitude of the bit line capacitance 15 and the magnitude of the read margin in the ferroelectric memory of the comparative example shown in FIG. 5 will be described.

FIG. 15 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin for the ferroelectric memory of the comparative example. FIG. 15 shows a V _PL -ΔQ characteristic graph in which the horizontal axis represents V _PL , the vertical axis represents ΔQ (the amount of change in charge supplied to BL), and the horizontal axis represents the magnitude of bit line capacitance 15 (C _BL ) with the vertical _axis representing _{V BL} .

In the graph showing the V _PL -ΔQ characteristic, a straight line having a slope of C _BL and represented by the formula ΔQ=C _BL ×V _BL is shown. _VBL is determined by capacitance division between the ferroelectric capacitor 13a and the bit line capacitance 15. FIG.

The potential difference between the intersections of the straight line represented by the above formula and the V _PL -ΔQ characteristic lines when "0" and "1" are stored in the memory cell 13 is It corresponds to the read margin (ΔV _BL in the comparative example).

In the ferroelectric memory of the comparative example, as shown in the graph showing the C _BL -V _BL characteristics, ΔV _BL is small when C _BL =C _BL1 and increases when C _BL =C _BL2 is increased. A further increase to C _BL =C _BL3 reduces it.

FIG. 16 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin for the ferroelectric memory of the first embodiment. FIG. 16 shows a V _PL -ΔQ characteristic graph in which the horizontal axis represents V _PL , the vertical axis represents ΔQ (amount of change in charge supplied to BL), and the horizontal axis represents the magnitude of bit line capacitance 15 (C _BL ) with _the vertical axis representing _{V PL} .

In the graph showing the V _PL -ΔQ characteristic, the V _PL when V _BL =ΔQ/C _BL =V _REF1 is stored in the memory cell 13 when "0" and "1" are stored. determined for each case.

In FIG. 16, V _PL0 when V _BL0 =ΔQ/C _BL2 =V _REF1 when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13 shows V _PL1 when V _BL1 =ΔQ/C _BL2 =V _REF1 . The difference (ΔV _PL ) between V _PL0 and V _PL1 corresponds to the read margin when C _BL =C _BL2 .

In the ferroelectric memory of the first embodiment, ΔV _PL is small at C _BL =C _BL1 and increases to C _BL =C _BL2 , as shown in the graph showing the C _BL -V _PL characteristics. Larger, but smaller with further increase to C _BL =C _BL3 .

Thus, in the ferroelectric memories of the comparative example and the first embodiment, it is desirable to set _CBL of the bit line capacitance 15 to an appropriate value in order to increase the read margin.
FIG. 17 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin for the ferroelectric memory of the second embodiment. FIG. 17 shows a V _PL -ΔQ characteristic graph in which the horizontal axis represents V _PL , the vertical axis represents ΔQ (the amount of change in charge supplied to BL), and the horizontal axis represents the magnitude of bit line capacitance 15 (C _BL ) with _the vertical axis representing _{V PL} .

In the V _PL -ΔQ characteristic graph, the relationship between V _PL and the amount of change in charge supplied to RBL is indicated by a broken line. The slope of the dashed line is determined by the size of capacitor 32 (C _REF ).

In the ferroelectric memory of the second embodiment, V _PL is fixed to the maximum value (V _PL0 ) during reading when "0" is stored in the memory cell 13, as described above. On the other hand, ΔQ at the time of reading when "1" is stored in the memory cell 13 is the intersection of the dashed line in FIG. 17 and the V _PL -ΔQ characteristic line, and is constant regardless of _CBL .

FIG. 17 shows V _PL1 when C _BL =C _BL2 when "1" is stored in memory cell 13 . The difference (ΔV _PL ) between V _PL0 and V _PL1 corresponds to the read margin when C _BL =C _BL2 .

In the ferroelectric memory of the second embodiment, ΔV _PL increases as C _BL increases, as shown in the graph showing the C _BL -V _PL characteristics.
Thus, in the ferroelectric memory of the second embodiment, the read margin can be increased by increasing _CBL . However, when _CBL increases, the input signal to the differential amplifier 31a decreases, so how much _CBL can be increased depends on the capability of the differential amplifier 31a.

FIG. 18 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin for the ferroelectric memory of the third embodiment. FIG. 18 shows a V _BL -ΔQ characteristic graph in which the horizontal axis represents V _BL , the vertical axis represents ΔQ (the amount of change in charge supplied to the ferroelectric capacitor 13a), and the horizontal axis represents the magnitude of the bit line capacitance 15. A graph is shown showing the C _BL -V _BL characteristic, representing the height (C _BL ), with the vertical axis representing V _BL .

In the V _BL -ΔQ characteristic graph, the broken line indicates the relationship between V _RBL and the amount of change in charge supplied to RBL. The slope of the dashed line is determined by the size of capacitor 42 (C _REF ).

In the ferroelectric memory of the third embodiment, as described above, V _BL is fixed to the maximum value (V _BL1 ) during reading when "1" is stored in the memory cell 13 . On the other hand, ΔQ at the time of reading when "1" is stored in the memory cell 13 is the intersection of the dashed line in FIG. 18 and the V _BL -ΔQ characteristic line, and is constant regardless of _CBL . The difference between V _BL1 and V _BL0 at this intersection point, that is, V _BL0 −V _BL1 , corresponds to the read margin.

In the ferroelectric memory of the third embodiment, ΔV _BL is constant regardless of C _BL , as shown in the graph showing the C _BL -V _BL characteristics.
Thus, in the ferroelectric memory according to the third embodiment, the read margin can be made constant regardless of the _CBL . However, when _CBL increases, the input signal to the differential amplifier 41a decreases, so how much _CBL can be increased depends on the capability of the differential amplifier 41a.

As described above, one aspect of the reading circuit of the ferroelectric memory, the ferroelectric memory, and the reading method of the ferroelectric memory of the present invention has been described based on the embodiments, but these are only examples, and the above description is not limited to

For example, the circuit configuration can be changed as appropriate, such as using pMOS instead of nMOS.

REFERENCE SIGNS LIST 10 readout circuit 11 control circuit 11a differential amplifier 12 sense amplifier 13 memory cell 13a ferroelectric capacitor 13b, 14 nMOS
15 bit line capacity

Claims (9)

In a ferroelectric memory readout circuit comprising memory cells including ferroelectric capacitors,
When reading data from the memory cell, based on a comparison result between a bit line potential, which is the potential of the bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential, A control circuit for controlling the input voltage between the plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line so that the input voltage of the memory cell is fixed. and,
a sense amplifier that determines the value of the data based on a comparison result between the bit line potential or the plate line potential, which is the potential of the plate line when the input voltage is fixed, and a second reference potential; ,
A readout circuit of a ferroelectric memory having 2. The ferroelectric memory readout circuit according to claim 1, wherein said control circuit includes a differential amplifier having a first input terminal at said bit line potential and a second input terminal at said first reference potential. . the first reference potential is a constant potential;
3. The ferroelectric according to claim 1, wherein said control circuit fixes said input voltage by stopping said plate line potential from increasing when said bit line potential reaches said first reference potential. body memory readout circuit. a capacitor having one end electrically connected to the plate line and the other end electrically connected to a reference bit line;
the first reference potential is the potential of the reference bit line;
3. A reading circuit for a ferroelectric memory according to claim 1 or 2. the control circuit fixes the plate line potential when the bit line potential reaches the potential of the reference bit line when a first value is stored in the memory cell;
If the memory cell stores a second value different from the first value, the plate line potential rises until reaching a maximum value, and when the maximum value is reached, the bit line potential the potential is fixed,
5. A reading circuit for a ferroelectric memory according to claim 4. a capacitor having one end grounded and the other end electrically connected to a reference bit line;
the first reference potential is the potential of the reference bit line;
3. A reading circuit for a ferroelectric memory according to claim 1 or 2. 7. The ferroelectric memory read circuit according to claim 6, wherein said control circuit fixes said bit line potential when said bit line potential falls below the potential of said reference bit line. a memory cell including a ferroelectric capacitor;
When reading data from the memory cell, based on a comparison result between a bit line potential, which is the potential of the bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential, A control circuit for controlling the input voltage between the plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line so that the input voltage of the memory cell is fixed. and a sense for determining the value of the data based on the result of comparison between the bit line potential or the plate line potential, which is the potential of the plate line when the input voltage is fixed, and a second reference potential. a readout circuit comprising an amplifier; and
ferroelectric memory with In a reading method of a ferroelectric memory having memory cells including ferroelectric capacitors,
A control circuit compares a bit line potential, which is a potential of a bit line electrically connected to one terminal of the ferroelectric capacitor, with a first reference potential when data is read from the memory cell. , the input voltage is fixed such that the input voltage of the memory cell, which is the voltage between the plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line, is fixed. control and
A sense amplifier determines the value of the data based on a comparison result between the bit line potential or the plate line potential, which is the potential of the plate line when the input voltage is fixed, and a second reference potential. do,
A reading method of a ferroelectric memory.

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