JP2023093562A - Precise plasma control system - Google Patents

Abstract

To provide a system capable of precise plasma control.SOLUTION: Embodiments include a plasma system comprising a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator may be electrically coupled with the plasma chamber and may produce a plurality of RF bursts, each of the plurality of RF bursts including RF waveforms, each of the plurality of RF bursts having an RF burst turn on time and an RF burst turn off time. The bias generator may be electrically coupled with the plasma chamber and may produce a plurality of bias bursts, each of the plurality of bias bursts including bias pulses, each of the plurality of bias bursts having a bias burst turn on time and a bias burst turn off time. In some embodiments, the controller is in communication with the RF plasma generator and the bias generator that control timing of various bursts or waveforms.SELECTED DRAWING: Figure 1

Description

The present invention relates to precision plasma control systems.

It has become standard in thin film fabrication techniques to utilize RF-excited gas discharges. The simplest shape most commonly used is that of two planar electrodes with a voltage applied between them.

Positive ions produced within the plasma volume are accelerated within the plasma sheath, with an ion energy determined by the magnitude and waveform of the time-dependent potential difference within the sheath, gas pressure, the physical geometry of the reactor, and/or other factors. Arrive at the electrode or wafer with a distribution function (IEDF). The energy distribution of this ion bombardment may determine the degree of anisotropy in thin film etching, the amount of surface damage due to ion bombardment, and so on.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems in the prior art.

Some embodiments include a plasma chamber, an RF plasma generator electrically coupled with the plasma chamber, a bias generator electrically coupled with the plasma chamber, and/or electrically with the plasma chamber. a controller coupled and in communication with the RF plasma generator and/or the bias generator.

Some embodiments include a plasma system that includes a plasma chamber, an RF plasma generator, a bias generator, and a controller. An RF plasma generator may be electrically coupled to the plasma chamber and may generate a plurality of RF bursts, each of the plurality of RF bursts comprising an RF waveform, each of the plurality of RF bursts comprising an RF It has a burst turn-on time and an RF burst turn-off time. A bias generator may be electrically coupled to the plasma chamber and may generate a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst turn-on time and a bias burst turn-on time. It has a bias burst turn-off time. In some embodiments, the controller communicates with the RF plasma generator and bias generator that control the timing of the various bursts or waveforms.

In some embodiments, multiple RF bursts generate and/or drive a plasma within the plasma chamber, and multiple bias bursts accelerate ions within the plasma.

In some embodiments, the plasma system includes an electrode positioned within the plasma chamber and coupled to the bias generator. In some embodiments, the plasma system includes an electrode positioned within the plasma chamber and coupled to the RF generator. In some embodiments, the plasma system includes an inductive antenna positioned within the plasma chamber and coupled to the RF plasma generator.

In some embodiments, a plasma system includes a wafer positioned within a plasma chamber, the wafer coupled to a bias generator. In some embodiments, a plasma system includes a wafer positioned within a plasma chamber, the wafer coupled to an RF generator.

In some embodiments, the RF burst turn-on time leads the bias burst turn-on time by less than 10 ms. In some embodiments, the bias burst turn-on time precedes the RF burst turn-off time by less than 10 ms. In some embodiments, the difference between the RF burst turn-on time and the RF burst turn-off time is less than about 1 ms. In some embodiments, the difference between the biased burst turn-on time and the biased burst turn-off time is less than about 1 ms.

In some embodiments, the bias pulse has a pulse repetition frequency greater than 1 kHz. In some embodiments, the bias pulse has a voltage greater than 1 kilovolt. In some embodiments, the RF waveform has a frequency greater than 10 MHz.

2. The plasma system of claim 1, wherein said plurality of RF bursts generate and/or drive a plasma within said plasma chamber and said plurality of bias bursts accelerate ions within said plasma.

In some embodiments, the controller controls the timing of the RF burst turn-on time, RF burst turn-off time, bias turn-on time, and bias turn-off time based on feedback from the plasma chamber.

In some embodiments, the bias generator includes a nanosecond pulser. In some embodiments, the bias generator includes bias compensation circuitry. In some embodiments, the bias generator includes an energy recovery circuit. In some embodiments the bias generator includes an RF generator.

In some embodiments, the RF plasma generator includes either a full bridge circuit or a half bridge circuit and a resonant circuit.

Some embodiments include the steps of driving the RF plasma generator, resting for a first period of time, pulsing with a pulse having a first voltage with a nanosecond pulser, and resting for a second period of time. , deactivating the RF plasma generator, resting for a third period of time, and deactivating pulsing of the nanosecond pulser.

In some embodiments, the method comprises: resting for a fourth period of time; deactivating the RF plasma generator; resting for a first period of time; further comprising pulsing the pulser, pausing for a second period of time, deactivating the RF plasma generator, pausing for a third period of time, and stopping pulsing of the nanosecond pulser. obtain.

In some embodiments, the second voltage is greater than the first voltage.

In some embodiments, the method comprises: resting for a fourth period; deactivating the RF plasma generator; resting for a fifth period different from the first period; pulsing the nanosecond pulser with a pulse having a voltage; resting for a sixth period different from the first period; deactivating the RF plasma generator; It may further include resting for a period of 7 and turning off the nanosecond pulser.

In some embodiments, the first period of time may be less than about 10 ms, the second period of time may be less than about 10 ms, and/or the third period of time may be less than about 10 ms. good too. In some embodiments, the first period of time is shorter than the second period of time. In some embodiments, the first period of time is shorter than the second period of time.

These exemplary embodiments are mentioned not to limit or define the disclosure, but to provide examples to aid understanding of the disclosure. Additional embodiments are described in the Detailed Description and further description is provided there. Advantages provided by one or more of the various embodiments may be further understood by reviewing the specification or by practicing one or more of the presented embodiments.

1 is a block diagram of a plasma system according to some embodiments; FIG. FIG. 4 is an illustration of an exemplary waveform showing two bursts of pulses according to some embodiments; FIG. 4 is an illustration of an exemplary RF burst and an exemplary bias burst, according to some embodiments; 1 is a block diagram of a plasma control system according to some embodiments; FIG. FIG. 4 is a diagram of a plasma system control process according to some embodiments. FIG. 4 is a circuit diagram of a bias generator according to some embodiments; Figure 7 is a waveform diagram from the bias generator shown in Figure 6; 8 is an enlarged view of the waveform shown in FIG. 7; FIG. FIG. 4 is a circuit diagram of a bias generator according to some embodiments; FIG. 4 is a circuit diagram of a bias generator according to some embodiments; FIG. 4 is a circuit diagram of a bias generator according to some embodiments; 1 is a circuit diagram of an RF plasma generator according to some embodiments; FIG. 1 is a circuit diagram of an RF plasma generator according to some embodiments; FIG. 1 is a circuit diagram of an exemplary resonant circuit; FIG. 1 is a circuit diagram of an exemplary resonant circuit; FIG. 1 is a circuit diagram of an exemplary resonant circuit; FIG. 1 is a circuit diagram of an exemplary resonant circuit; FIG. FIG. 4 is a circuit diagram of a bias generator with energy recovery circuitry according to some embodiments; 1 is a circuit diagram of a bias generator with active energy recovery circuitry according to some embodiments; FIG. 1 is a circuit diagram of a bias generator including passive bias compensation circuitry and energy recovery circuitry according to some embodiments; FIG. 1 is a circuit diagram of a bias generator including an active bias compensation circuit with energy recovery circuit, according to some embodiments; FIG. 1 is a circuit diagram of a bias generator including an active bias compensation circuit with active energy recovery circuit, according to some embodiments; FIG. FIG. 4 is a circuit diagram of a bias generator with energy recovery circuitry according to some embodiments; FIG. 4 is a circuit diagram of a bias generator with an energy recovery circuit driving a capacitive load, according to some embodiments; 1 is a block diagram of a high voltage switch with isolated power, according to some embodiments; FIG. 1 is a circuit diagram of a bias generator including an RF source, active bias compensation circuitry, and energy recovery circuitry, according to some embodiments; FIG. FIG. 4B is a diagram of another exemplary bias generator according to some embodiments; 1 is a block diagram of a computing system according to some embodiments; FIG.

Some embodiments include a plasma system that includes a plasma chamber, an RF plasma generator, a bias generator, and a controller. An RF plasma generator may be electrically coupled to the plasma chamber and may generate a plurality of RF bursts, each of the plurality of RF bursts comprising an RF waveform, each of the plurality of RF bursts comprising an RF burst It has a turn-on time and an RF burst turn-off time. A bias generator may be electrically coupled to the plasma chamber and may generate a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst turn-on time. and bias burst turn-off time. In some embodiments, the controller communicates with the RF plasma generator and bias generator that control the timing of the various bursts or waveforms.

As used throughout this disclosure, the term "high voltage" may include voltages greater than 500V, 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc., and the term "high frequency" may include 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz. , 1 MHz, etc.; "Fall time" may include fall times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc., and the term "short pulse width" includes about 1 ns, 10 ns, 50 ns, 100 ns, Pulse widths of less than 250 ns, 500 ns, 1,000 ns, etc. may be included.

FIG. 1 is a block diagram of a plasma system 100 according to some embodiments. In some embodiments, plasma system 100 includes plasma chamber 110 , RF plasma generator 105 , bias generator 115 and/or controller 120 . In some embodiments, the RF plasma generator 105 may be used to generate plasma within the plasma chamber. In some embodiments, bias generator 115 may provide pulses that may be used to accelerate ions within the plasma generated within plasma chamber 110 .

In some embodiments, controller 120 may include any type of controller such as, for example, an FPGA, microcontroller, or the like. In some embodiments, controller 120 receives signals from plasma chamber 110 (or elsewhere) to time bursts or pulses provided by either RF plasma generator 105 and/or bias generator 115. , duration, frequency, amplitude, etc. may be changed or adapted.

In some embodiments, controller 120 may be any of the following: FPGAs, ASICs, complex programmable logic devices, microcontrollers, system-on-chips (SoCs), supervisory control, data acquisition (SCADA) and programmable logic controllers (PLCs). or any combination thereof. In some embodiments, controller 120 may include any or all of the components of computing system 2600 . In some embodiments, controller 120 may include a standard microcontroller such as, for example, Broadcom Arm Cortex, Intel ARM Cortex, PIC32, or the like.

In some embodiments, RF plasma generator 105 may generate plasma on a microsecond timescale (eg, 1-1000 microseconds) within the plasma chamber. In some embodiments, RF plasma generator 105 may allow plasma maintenance and/or plasma drive on a microsecond timescale to direct current, adjustable in microsecond increments. In some embodiments, RF plasma generator 105 may provide very high peak power (eg, 1-10000 kW). In some embodiments, RF plasma generator 105 may produce a variable supply CW power (eg, 0.1-100 kW).

In some embodiments, RF plasma generator 105 may include RF plasma generator 1200 or RF plasma generator 1300 . Any RF power source may be used.

In some embodiments, RF plasma generator 105 may induce plasma formation within plasma chamber 110 on small timescales, such as, for example, timescales of about 1 μs to about 1000 μs. In some embodiments, the RF plasma generator 105 may generate waveforms with arbitrary and/or controllable pulse widths, pulse repetition frequencies, pulse durations, maximum voltages, and the like. In some embodiments, the RF plasma generator 105 may produce waveforms with high peak powers, such as from about 1 kW to about 10,000 kW. In some embodiments, the RF plasma generator 105 may generate a waveform with variable and/or continuous wave (CW) power, eg, from about 1 kW to about 100 kW.

In some embodiments, bias generator 115 may control the wafer bias voltage on a small timescale, such as from about 1 μs to about 1000 μs, for example. In some embodiments, bias generator 115 may generate waveforms with arbitrary and/or controllable pulse widths, pulse repetition frequencies, pulse durations, maximum voltages, and the like. In some embodiments, bias generator 115 may generate waveforms with high peak powers, such as, for example, from about 1 kW to about 100,000 kW. In some embodiments, bias generator 115 may generate a waveform with variable continuous power, such as from about 1 kW to about 100 kW, for example.

In some embodiments, bias generator 115 includes bias generator 600, bias generator 900, bias generator 1000, bias generator 1100, bias generator 1600, bias generator 1700, bias generator 1800, bias generator generator 1900, bias generator 2000, bias generator 2100, bias generator 2200, bias generator 2400, and bias generator 2500. In some embodiments, bias generator 115 may include RF plasma generator 1200 or RF plasma generator 1300 .

In some embodiments, controller 120 may provide timing control of pulses from both RF plasma generator 105 and bias generator 115 . RF waveform 305 is an example output from RF plasma generator 105 and bias burst 310 is an example output from bias generator 115 .

In some embodiments, the timing from the controller 120 can be used, for example, to enable faster plasma etching within the plasma chamber 110, less/more erosion of various masks, straighter and deeper holes. / trench, control of specific plasma properties such as temperature and density while etch voltage is present, drive different chemistries/reactions, change the rate of reactions, control some etch parameters, and/or some plasma It can contribute to control of generation and the like.

で表すことができる。バースト繰り返し周波数は、バースト周期の逆数

で表すことができる。パルス繰り返し周波数は、パルス周期の逆数

で表すことができる。 FIG. 2 is an illustration of an example waveform showing two bursts of pulses according to some embodiments. A single burst may contain multiple pulses. The burst duration is the time T _on when the burst is on and the time T _0ff when the burst is off. The pulse width P _width is the duration that the pulse is on. The pulse period P _period is the period during which the pulse is on and off. Duty cycle is the on-time Ton divided by the burst duration

can be expressed as The burst repetition frequency is the reciprocal of the burst period

can be expressed as The pulse repetition frequency is the reciprocal of the pulse period

can be expressed as

In some embodiments, the burst repetition frequency may be between about 10 Hz and about 1000 Hz. In some embodiments, the pulse repetition frequency may be greater than about 10 kHz.

FIG. 3 is an illustration of an exemplary RF burst and an exemplary bias burst, according to some embodiments.

Time t1 represents the beginning of RF waveform 305 (eg, the turn-on time of the RF burst). Time t3 represents the end of RF waveform 305 (eg, RF burst turn-off time). Period w1 may represent the period of the portion when RF waveform 305 is driving the plasma. Time t2 represents the beginning of bias burst 310 (eg, bias burst turn-on time). Time t4 represents the end of bias burst 310 (eg, bias burst turn-off time). Period w2 may represent the duration of bias burst 310 .

The RF waveform 305 may create and drive a plasma within the plasma chamber 110 . For example, period w3 may include the initial ring-up period. The period w4 may be a period during which plasma is formed. Period w1 may be the period during which the plasma is driven by the RF signal in the chamber.

In some embodiments, t3 may begin when plasma is formed in chamber 110, eg, at the end of either or both w3 or w4. In some embodiments, the controller 120 senses, for example, the amplitude of the initial ring-up of the RF waveform 305, or via a sensor located within the chamber 110, or the number of cycles of the RF waveform 305. The formation of the plasma may be sensed, such as by doing so. Controller 120 may initiate burst 310 based on, for example, the controller sensing plasma formation or predicting plasma formation within chamber 110 .

In some embodiments, t1 may precede t2 by less than about 10 ms. In some embodiments, t3 may precede t4 by less than about 10 ms.

In some embodiments, the difference between t2 and t1 may be from about 10 μs to about 10 ms. In some embodiments, the difference between t2 and t1 may be less than about 1 μs. In some embodiments, the difference between t2 and t1 may be less than about 740ns. In some embodiments, the difference between t2 and t1 may be greater than about 10 cycles or periods of RF waveform 305. FIG.

In some embodiments, t2 and t1 may occur substantially simultaneously. In some embodiments, t2 may be triggered based on when controller 120 detects that plasma formation has occurred within plasma chamber 110 .

In some embodiments, the difference between t4 and t2 (or w2) may be between about 10 μs and about 10 ms. In some embodiments, w1 may be between about 10 μs and about 10 ms. In some embodiments, w2 may be consecutive.

In some embodiments, the frequency of RF waveform 305 may have a frequency between about 10 kHz and about 10 MHz. In some embodiments, RF waveform 305 may have a frequency of 13.56 MHz or any multiple thereof (eg, 27.12 MHz, 40.68 MHz, etc.). In some embodiments, the frequency of RF waveform 305 may have a frequency greater than 10 MHz.

In some embodiments, w1 may be continuous, eg, greater than 10 ms, 1 ms, 1 second, 10 seconds, and the like. In some embodiments, the frequency of pulses within bias burst 310 may be between about 10 Hz and about 10 kHz. In some embodiments, the frequency of pulses within bias burst 310 may be greater than 1 kHz. In some embodiments, the frequency of pulses within bias burst 310 may be greater than 10 kHz. In some embodiments, the frequency of pulses within bias burst 310 may be between 10 kHz and 20 MHz. In some embodiments, the frequency of pulses within bias burst 310 may be greater than about 400 kHz.

In some embodiments, w3 (eg, t3-w1-t1-w4) may be less than about 10 ms.

In some embodiments, a flat or ramped or other segment of bias burst 310 may be between 10 μs and 10 ms in duration.

In some embodiments, a flat or ramped or other segment of RF waveform 305 may be between 10 μs and 10 ms in duration.

In some embodiments, t2 may precede t3 by less than about 10 ms.

In some embodiments, t3 may precede t2 by less than about 10 ms.

In some embodiments, t2 may occur any time during w4. In some embodiments, t2 may occur any time before the start of w1. In some embodiments, t2 may occur during plasma formation. In some embodiments, t2 may occur during the initial ringup of the RF waveform 305, after the initial ringup, or during the initial ringup.

In some embodiments, t2 may precede t4 by less than about 10 ms.

In some embodiments, controller 120 controls RF plasma generator 105 and/or bias generator 115 to provide arbitrary or selectable pulse widths (eg, w1+w3+w4 or w2), duty cycle, pulse repetition frequency. , and/or a burst of multiple pulses having a burst frequency.

In some embodiments, controller 120 may control RF plasma generator 105 and/or bias generator 115 to also include slow start and/or slow DC stop capabilities.

In some embodiments, controller 120 may send and/or receive external commands from an external controller (eg, an industrial controller). These external commands may control the pulse width, duty cycle, pulse repetition frequency, and/or burst frequency of either or both RF plasma generator 105 and/or bias generator 115 .

In some embodiments, the controller 120 may automate control of the high voltage DC power supply, including turning the high voltage DC power supply on/off, changing voltage and amperage settings, and/or securing the device in an emergency. .

In some embodiments, the controller 120 may have a feedback circuit from the output of the RF plasma generator 105 so it can analyze the waveform entering the plasma chamber. This allows the controller 120 to self-adjust to different loads and load conditions.

In some embodiments, controller 120 may control bias generator 115 based on settings that go to RF plasma generator 105 .

In some embodiments, controller 120 may control bias generator 115 to generate pulses having pulse widths between 40ns and 200ns.

In some embodiments, controller 120 may generate bursts with duty cycles between 1% and 100%.

In some embodiments, controller 120 may control bias generator 115 to generate pulses having a burst repetition frequency of 200-1000 Hz.

In some embodiments, controller 120 starts generating pulses with a minimum pulse width (eg, ~40 ns) and increases to longer pulse widths in 4 ns increments (eg, 40 ns, 44 ns, 48 ns, 52 ns, etc.). The bias generator 115 may be controlled so as to

In some embodiments, controller 120 may control bias generator 115 to generate pulses that ramp the DC voltage down from the maximum voltage to 0V in selectable steps.

In some embodiments, controller 120 may control bias generator 115 to generate arbitrary pulses with low jitter, eg, jitter of less than about 10 nanoseconds.

In some embodiments, controller 120 may self-correct for load conditions.

In some embodiments, plasma chamber 110 may include any type of plasma chamber.

In some embodiments, plasma chamber 110 may have a load capacitance of less than 20 nF. In some embodiments, a potential can be established within plasma chamber 110 to accelerate ions to the surface under the action of bias generator 115 . In some embodiments, the plasma within plasma chamber 110 may be generally capacitive. In some embodiments, the plasma within plasma chamber 110 may include a dielectric barrier discharge.

In some embodiments, the plasma chamber 110 includes capacitors, capacitors in series with resistors, capacitors in series with inductors, dielectric barrier discharges, plasma loads, semiconductor wafer processing loads, and capacitors, inductors, resistors, and/or or as any other arrangement of active and/or passive components. In some embodiments, the load in the chamber is such that when energized and charged, the charge/voltage remains for longer than desired (e.g., longer than the designed or desired fall time). It can include any load that may continue to exist (for a long time). For example, such phenomena can often occur in high voltage switching applications.

In some embodiments, the plasma chamber 110 may include a capacitive load, one or more electrodes, a plasma load, one or more dielectric barriers, a semiconductor fabrication plasma, a semiconductor load, a grid, a medical load, etc. good. In some embodiments, plasma chamber 110 may include a plasma deposition system, a plasma etching system, or a plasma sputtering system.

In some embodiments, RF plasma generator 105 may include circuitry and/or processes for driving switched power to the plasma chamber without a matching network. In some embodiments, RF plasma generator 105 may include a full (or half) bridge circuit topology that may be used to drive a resonant circuit at or near its resonant frequency. Since the resonant circuit is driven at its resonant frequency, the output voltage of the resonant circuit may be higher than the input voltage. In some embodiments, this resonant condition may allow voltages of about 4 kV or higher with drive voltages of several hundred volts.

FIG. 4 is a block diagram of a plasma control system 400 with a bias generator and an RF plasma generator, according to some embodiments. In some embodiments, plasma control system 400 may be electrically coupled to bias generator 115 at one or more locations and/or to RF plasma generator 105 at one or more locations. For example, first HV signal 405A (or second HV signal 405B) may comprise the voltage signal at the point of bias generator 115 between the pulser, transformer stage, and bias compensation circuit. As another example, first HV signal 405A (or second HV signal 405B) may comprise a voltage signal at a point between the load stage and the bias compensation circuit. As another example, the first HV signal 405A (or the second HV signal 405B) may include the voltage of the previous portion of the resistive output stage or energy recovery state. As another example, first HV signal 405A (or second HV signal 405B) may include voltages on a wafer, chuck, or electrode. Although two signals are shown, any number of signals may be received. As another example, the first HV signal 405A (or the second HV signal 405B) may comprise a voltage across a resistor of a resistive output stage or energy recovery circuit, which induces ion current in the chamber. can be expressed As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage in an energy recovery circuit, such as the voltage across an energy recovery inductor, which is responsible for ions in the chamber. can represent current.

In some embodiments, first HV signal 405A and second HV signal 405B are the voltage or current across a capacitor of a bias compensation circuit (eg, capacitor C12 of bias compensation circuit 104 or bias compensation circuit 134). signal may be included. Any number or type of other signals may be received.

In some embodiments, first HV signal 405A or second HV signal 405B may comprise voltage signals provided to the load. In some embodiments, first HV signal 405A or second HV signal 405B may comprise voltage signals provided to bias compensation circuitry. In some embodiments, the first HV signal 405A or the second HV signal 405B may comprise voltage signals provided to the pulser and transformer stages may be measured. In some embodiments, first HV signal 405A or second HV signal 405B may comprise voltage signals provided to a resistive output stage or energy recovery circuit.

First HV signal 405 A and second HV signal 405 B may be collectively or individually referred to as HV input signal 405 . HV signal 405 may provide waveforms from bias generator 115 and/or RF plasma generator 105 .

In some embodiments, HV input signal 405 may be divided by voltage divider 410 . Voltage divider 410 may include, for example, high value resistors or low value capacitors to divide a high voltage HV input signal (eg, greater than 1 kV) into a low voltage signal (eg, less than 50V). Voltage divider 410 may, for example, divide voltage by a ratio of 500:1, a ratio of 1000:1, a ratio of 10,000:1, a ratio of 100,000:1, and the like. The voltage divider 410 may, for example, divide the voltage of the HV input signal 405 between 0-10 kV into a voltage between 0-20V. Voltage divider 410 may divide with minimal power loss, eg, less than about 5W power loss.

In some embodiments, voltage divider 410 may include a low value capacitor, a large value capacitor, a low value resistor, and a large value resistor. Low value capacitors may include, for example, capacitors having capacitance values of about 0.1 pF, 0.5 pF, 1.0 pF, 2.5 pF, 5.0 pF, 10.0 pF, 100 pF, 1 nF, 10 nF, and the like. A large value capacitor may include, for example, a capacitor having a capacitance value of approximately 500 pF. In some embodiments, the high value capacitor may have a capacitance value that is approximately 50, 100, 250, 500, 1000, 2,500, 5,000 pF, or the like greater than the capacitance value of the low value capacitor.

The low value resistors may have resistance values of 1.0 kΩ, 2.5 kΩ, 5.0 kΩ, 10 kΩ, 25 kΩ, 50 kΩ, 100 kΩ, and the like. The large value resistors may have resistance values of approximately 0.5 MΩ, 1.0 MΩ, 2.5 MΩ, 5.0 MΩ, 10 MΩ, 25 MΩ, 50 MΩ, 100 MΩ, and the like. In some embodiments, the high value resistor has a resistance greater than the resistance of the low value resistor, such as about 50Ω, 100Ω, 250Ω, 500Ω, 1,000Ω, 2,500Ω, 5,000Ω. may have. In some embodiments, the ratio of low value capacitors to high value capacitors may be substantially the same as the ratio of low value resistors to high value resistors.

In some embodiments, voltage divider 410 may receive the HV input signal and output a divided voltage signal. The divided voltage signal may be, for example, 100 times, 250 times, 500 times, 750 times, 1000 times, etc. smaller than the HV input signal.

Some embodiments may include a filter 415 to filter any noise from the divided voltage signal, for example. Filters may include, for example, any type of lowpass, bandpass, bandstop, or highpass filter.

In some embodiments, the divided voltage signal may be digitized by the first ADC 420 . The first ADC 420 may include an analog-to-digital converter. Any type of analog-to-digital converter may be used. The first ADC 420 may generate a digitized waveform signal. In some embodiments, the first ADC 420 may capture data at 100, 250, 500, 1,000, 2,000, 5,000 MSPS (mega samples per second or millions of samples per second) . In some embodiments, the digitized waveform signal may be communicated to controller 120 using any type of communication protocol, such as SPI, UART, RS232, USB, I2C, for example.

In some embodiments, either voltage divider 410, filter 415, or first ADC 420 may be isolated from bias generator 115 via galvanic isolation or via a fiber optic link.

In some embodiments, controller 120 may send and/or receive signals or data from RF plasma generator 105 . For example, the controller 120 may send timing signals to the RF plasma generator 105 that instruct the RF plasma generator regarding burst repetition frequency, burst voltage, burst frequency, burst duty cycle, burst duration, and the like.

In some embodiments, controller 120 may send and/or receive signals or data to and from bias generator 115 via output 435 . For example, the controller 120 may send timing signals to the bias generator 115 that instruct the bias generator regarding burst repetition frequency, burst voltage, burst frequency, burst duty cycle, burst duration, and the like.

In some embodiments, controller 120 may receive a trigger signal from trigger 430 . In other embodiments, first ADC 420 may receive the trigger signal from trigger 430 . The trigger signal may provide timing for data acquisition in the first ADC 420 . The trigger signal may be, for example, a 5V TTL trigger. The trigger signal may have a 50 ohm termination, for example.

The digitized signal is then output from controller 120 via one or more output ports, such as, for example, first output 435A or second output 435B (individually or collectively output 435). may These outputs may be combined with one or more nanosecond pulsers (eg, bias generator 115). Either or both outputs 435 may include electrical connectors such as, for example, LVDS, TTL, LVTTL connectors. Either or both outputs 435 may send data to the nanosecond pulser controller using any type of communication protocol such as SPI, UART, RS-232, USB, I2C, EtherCat, Ethernet, Profibus, PROFINET. may provide.

In some embodiments, plasma control system 400 may couple to bias generator 115 via a 4 mm multiram receptacle on plasma control system 400 .

In some embodiments, the plasma control system 400 includes a second sensor that receives input from a first sensor 450A and a second sensor 450B (individually or collectively sensors 450) (or any number of sensors). may include an ADC 445 of A second ADC 445 may include an analog-to-digital converter. In some embodiments, second ADC 445 may digitize the analog signal from sensor 450 . Sensors 450 may include, for example, sensors that sense inlet water temperature, dielectric fluid temperature, dielectric fluid pressure, enclosure air temperature, voltage, fluid flow, fluid leak sensors, and the like. In some embodiments, second ADC 445 may include ARM, PIC32, AVR, PSOC, or PIC32.

In some embodiments, second ADC 445 and first ADC 420 may comprise a single ADC device. Either or both of the second ADC 445 or the first ADC 420 may be part of the controller 120 in some embodiments. In some embodiments, the first ADC 420 may operate at a higher acquisition rate than the second ADC.

In some embodiments, the control system may measure the full width at half maximum, peak voltage, DC bias, rise time, fall time, etc. of the pulse in the bias generator 115 .

In some embodiments, the plasma control system 400 may monitor the voltage, frequency, pulse width, etc. of the pulse and, in response, the input of the bias generator 115 and/or the RF plasma generator 105. Adjust the supplied voltage, pulse repetition frequency, pulse width, burst repetition frequency (if one burst contains multiple pulses), RF burst turn-on time, RF burst turn-off time, bias burst turn-on time, bias burst turn-off time, etc. You may For example, the first ADC 420 may monitor the voltage amplitude of the waveform. This voltage data may be provided to controller 120, which may adjust the amplitude or frequency of the signal by communicating to the nanosecond pulser or RF plasma generator.

In some embodiments, plasma control system 400 may output an optional pulse signal to one or more bias generators 115 via output 435 . Output 435 may include, for example, either fiber connections or electrical connections. In some embodiments, plasma control system 400 can include, for example, multiple output pulse channels (eg, 1, 2, 5, 8, 20, 50, 100, etc.) that can be independent of each other. A plurality of output pulse channels may output pulses with sub-nanosecond resolution, for example.

For example, if the pulse voltage is less than a predetermined voltage, controller 120 may signal bias generator 115 or RF plasma generator 105 to generate a higher voltage pulse. Also, if the pulse voltage is greater than the predetermined voltage, the first ADC 420 may signal the bias generator 115 or RF plasma generator 105 to generate pulses at a lower voltage. In some embodiments, the signal to the nanosecond pulser to increase the pulse voltage may include a low voltage pulse having a longer pulse width than the previously sent signal, and the signal to decrease the pulse voltage. The signal to the nanosecond pulser may contain a low voltage pulse with a shorter pulse width than the previously sent signal.

As another example, if the pulse repetition frequency is greater than the desired pulse repetition frequency, controller 120 may signal bias generator 115 or RF plasma generator 105 to generate a lower frequency pulse. If the burst repetition frequency is less than the desired burst repetition frequency, controller 120 may signal bias generator 115 or RF plasma generator 105 to generate bursts at a higher burst repetition frequency. If the measured full-width half-width of the pulse differs from the desired burst repetition frequency, controller 120 instructs bias generator 115 or RF plasma generator 105 to generate a pulse having an adjusted pulse width or pulse repetition frequency. You can send a signal.

As another example, if the pulse width of the waveform is longer than the desired pulse width, the first ADC 420 may cause bias generator 115 or RF plasma generator 105 to generate a waveform with a shorter or longer pulse width. You can send a signal to If the waveform duty cycle is shorter or longer than the desired duty cycle, the first ADC 420 signals the bias generator 115 or RF plasma generator 105 to generate pulses with the appropriate duty cycle. good too.

Plasma control system 400 may monitor other waveform characteristics and/or adjust these other characteristics.

In some embodiments, plasma control system 400 may output an optional pulse signal to one or more of bias generators 115 or RF plasma generators 105 via output 435 . For example, the control system can include any RF plasma generator. Output 435 may include, for example, either fiber connections or electrical connections. In some embodiments, plasma control system 400 can include, for example, multiple output pulse channels (eg, 1, 2, 5, 8, 20, 50, 100, etc.) that can be independent of each other. . The multiple output pulse channels may output pulses with sub-nanosecond resolution, for example. In some embodiments, plasma control system 400 may output pulses with a resolution of less than about 0.1 ns. In some embodiments, plasma control system 400 may output pulses with a jitter of less than about 100 ps.

In some embodiments, each output pulse channel of plasma control system 400 may output a pulse to bias generator 115 that triggers bias generator 115 . Plasma control system 400 may, for example, adjust parameters of the output pulses in real time or between pulses. These parameters may include pulse width, pulse repetition frequency, duty cycle, burst repetition frequency, voltage, number of pulses within a burst, number of bursts, and the like. In some embodiments, one or more parameters may be adjusted or changed based on inputs to plasma control system 400 or based on recipes or programs.

For example, a recipe may include alternating high and low bursts from bias generator 115 . A high burst may include, for example, multiple high voltage pulses. A low burst may include, for example, multiple low voltage pulses. The high and low bursts may, for example, contain the same number of pulses within each burst or may contain different numbers of pulses. A low burst may, for example, have a voltage that is 10%, 20%, 30%, 40%, 50%, etc. lower than the voltage of the high burst voltage.

Alternating high and low bursts from the bias generator 115 may include ratios of low to high bursts (low-high ratios) of 5%, 20%, 50%, 100%, 125%, 150%, etc. good. For example, a 20% low-to-high ratio may comprise a train of 10 bursts, each burst comprising approximately 500 pulses (or any number of pulses from 1 to 10,000 pulses). For 10 consecutive bursts with a low high ratio of 10%, 2 bursts may be low voltage bursts and 8 bursts may be high voltage bursts.

In some embodiments, the controller 120 may be implemented in accordance with U.S. patent application Ser. 114,195, a pulse with a longer low voltage pulse is communicated to the nanosecond pulser to generate a high burst, and a pulse with a shorter low voltage pulse is communicated to generate a low burst. may be generated to alternately generate high and low bursts.

In some embodiments, one of sensors 450 may include a DC voltage sensor that may be coupled with a DC power supply within bias generator 115 . For example, if multiple DC power systems are used in bias generator 115 and the voltage fluctuates by more than a set percentage (e.g., 1%, 5%, 10%, 20%, etc.) during operation, or Controller 120 may turn off bias generator 115 if the absolute voltage (eg, 5V, 10V, 50V, 100V, etc.) is varied. As another example, a power system is used in which, during operation, the voltage output exceeds a certain percentage (e.g., 1%, 5%, 10%, 20%, etc.) from the set voltage, or is set to Controller 120 may turn off the pulse if it differs from the voltage by more than an absolute voltage (eg, 5V, 10V, 50V, 100V, etc.).

In some embodiments, controller 120 may send and/or receive communications and/or commands from an external controller 465, such as an industrial controller, for example. In some embodiments, external controller 465 may communicate with controller 120 through an EtherCat module. In some embodiments, an EtherCat module may include any type of communication module. In some embodiments, EtherCat may include one or more components of computing system 2600 .

In some embodiments, the control system controls, for example, pulse width, duty cycle, high voltage setpoint, on/off, return current output voltage, high voltage current setpoint, return current output current, enable high voltage output. , enable state of return high voltage, emergency shutdown, etc., of the pulse system.

FIG. 5 is a process 500 for controlling plasma system 100, according to some embodiments. In some embodiments, process 500 may be performed by controller 120 .

Process 500 begins at block 505 . At block 505, controller 120 may begin driving RF plasma generator 105 to generate a first RF burst. The first RF burst may include a waveform similar to RF waveform 305, for example. The first RF burst may include RF burst parameters such as RF frequency and/or RF voltage, for example. A first burst from RF plasma generator 105 may create a plasma in chamber 110 .

At block 510, process 500 may pause for a first period of time. The first period of time can be, for example, between about 10 μs and about 10 ms. In some embodiments, the first period of time may be 0 seconds. The first time period may be the time between the start of RF waveform 305 (eg, t1 or RF burst turn-on time) and the start of bias burst 310 (eg, t2 or bias burst turn-on time).

At block 515, controller 120 may pulse bias generator 115 to generate a first bias burst. A first bias burst may include a waveform similar to bias burst 310, for example. The first bias burst may include bias burst parameters such as, for example, pulse repetition frequency and/or bias voltage.

At block 520, process 500 may pause for a second period of time. The second time period may be, for example, between about 10 μs and about 10 ms. The second time period may be the time between the start of bias burst 310 (eg, t2 or bias burst turn-on time) and the end of RF waveform 305 (eg, t3 or RF burst turn-off time).

At block 525, the RF plasma generator may stop driving the chamber with the RF waveform. For example, the controller may send a signal to the RF plasma generator 105 to end the burst.

At block 530, process 500 may pause for a third period of time. The third time period may be, for example, between approximately 10 μs and approximately 10 ms. The third time period may be, for example, zero seconds. A third time period may be the time between the end of RF waveform 305 (eg, t3 or RF burst turn-off time) and the end of bias burst 310 (eg, t4 or bias burst turn-off time). In some embodiments, the first time period, the second time period, or the third time period may be the same. In some embodiments, the first period of time, the second period of time, or the third period of time may be different.

At block 535, the bias generator 115 may stop pulsing. For example, the controller may signal the bias generator 115 to end the burst and stop pulsing.

At block 540, process 500 may pause for a fourth period of time. The fourth time period may be, for example, the end of the bias burst 310 (eg, t4 or bias burst turn-off time) and the start of the next RF burst or the start of the next RF waveform 305 (eg, t1 of the next RF waveform or the next (the RF burst turn-on time of the RF waveform). In some embodiments, the fourth period of time may be greater than the first period of time, the second period of time, and/or the fourth period of time. The fourth time period may define the duty cycle of the RF waveform and/or the duty cycle of the bias burst.

At block 545, process parameters may be changed. The process parameters may include RF parameters, bias parameters, first time periods, second time periods, third time periods, fourth time periods, and the like. In some embodiments, RF parameters and/or bias parameters may be changed based on feedback from the chamber, eg, RF voltage, bias voltage, RF frequency, pulse repetition frequency, temperature, pressure, and the like. In some embodiments, RF parameters and/or bias parameters may be changed based on feedback from the chamber via HV signal 405 or sensor 450 .

After block 545, the process may repeat.

FIG. 6 is a circuit diagram of a bias generator 600 according to some embodiments.

In this example, bias generator 600 may include RF driver 605 . RF driver 605 may be, for example, a half-bridge driver or a full-bridge driver, as shown in FIG. RF driver 605 may include an input voltage source V1, which may be a DC voltage source (eg, capacitive source, AC/DC converter, etc.). In some embodiments, RF driver 605 may include four switches S1, S2, S3, and S4. In some embodiments, RF driver 605 may include multiple switches S1, S2, S3, and S4 arranged in series or in parallel. These switches S1, S2, S3 and S4 may comprise any type of solid state switches such as IGBTs, MOSFETs, S1C-MOSFETs, S1C junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc. good. These switches S1, S2, S3, S4 may be switched at a high frequency and generate high voltage pulses. These frequencies may include, for example, frequencies of about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and the like.

Each of switches S1, S2, S3, and S4 may be coupled in parallel with a respective diode D1, D2, D3, and D4 to provide stray inductance represented by inductors L1, L2, L3, and L4. may contain. In some embodiments, the inductances of inductors L1, L2, L3, and L4 may be equal. In some embodiments, the inductance of inductors L1, L2, L3, and L4 may be less than about 50 nH, 100 nH, 150 nH, 500 nH, 1000 nH, and so on. A combination of a switch (S1, S2, S3, or S4) and a respective diode (D1, D2, D3, or D4) may be coupled in series with a respective inductor (L1, L2, L3, or L4). . Inductors L3 and L4 are connected to ground. Inductor L1 is connected to switch S4 and resonant circuit 610 . Inductor L2 is then connected to the opposite side of switch S3 and resonant circuit 610 .

In some embodiments, RF driver 605 may be coupled with resonant circuit 610 . Resonant circuit 610 may include resonant inductor L5 and/or resonant capacitor C2 coupled with transformer T1. Resonant circuit 610 may include, for example, resonant resistor R5, which may include stray resistance in any leads between RF driver 605 and resonant circuit 610, and/or, for example, transformer T1, capacitor C2, and/or /or any component within resonant circuit 610, such as inductor L5. In some embodiments, resonant resistor R5 includes only stray resistance of wires, traces, or circuit elements. Although the inductance and capacitance of other circuit elements can affect the drive frequency, the drive frequency can be generally set by selection of resonant inductor L5 and/or resonant capacitor C2. Further refinement and/or adjustment may be required to achieve an appropriate drive frequency to account for stray inductance and stray capacitance. Furthermore, by changing L5 and/or C2, the rise time of transformer T1 can be adjusted, but the following conditions must be satisfied.

In some embodiments, increasing the inductance value of L5 may slow down or shorten the rise time. These values can also affect the burst envelope. As shown in Figure 7, each burst may include a transient pulse and a stationary pulse. Transient pulses within each burst may be set by L5 and/or Q of the system until full voltage is reached during the steady pulse.

When the switches of RF driver 605 are switched at the _{resonant frequency f - - resonant} , the output voltage at transformer T1 is amplified. In some embodiments, the resonant frequencies may be approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and so on.

In some embodiments, resonant capacitor C2 may include the stray capacitance of transformer T1 and/or a physical capacitor. In some embodiments, resonant capacitor C2 may have a capacitance of approximately 10 μF, 1 μF, 100 nF, 10 nF, and the like. In some embodiments, resonant inductor L5 may include the stray inductance of transformer T1 and/or a physical inductor. In some embodiments, resonant inductor L5 may have an inductance of approximately 50 nH, 100 nH, 150 nH, 500 nH, 1000 nH, etc. In some embodiments, resonant resistor R5 may have a resistance of approximately 10 ohms, 25 ohms, 50 ohms, 100 ohms, 150 ohms, 500 ohms, and the like.

In some embodiments, resonant resistor R5 may represent stray resistance of wires, traces, and/or transformer windings within a physical circuit. In some embodiments, resonant resistor R5 may have a resistance of approximately 10 mOhms, 50 mOhms, 100 mOhms, 200 mOhms, 500 mOhms, and the like.

In some embodiments, transformer T1 is disclosed in US patent application Ser. No. 15/365,094, entitled "High Voltage Transformer," which is incorporated herein for all purposes. It may contain such a transformer. In some embodiments, the output voltage of resonant circuit 610 changes the duty cycle of switches S1, S2, S3, and/or S4 (eg, the "on" time of the switches or the time the switches are conducting). can be changed by For example, a longer duty cycle results in a higher output voltage and a shorter duty cycle results in a lower output voltage. In some embodiments, adjusting the switching duty cycle of RF driver 605 can change or adjust the output voltage of resonant circuit 610 .

For example, changing the duty cycle of signal Sig1 opens and closes switch S1, changing the duty cycle of signal Sig2 opens and closes switch S2, changing the duty cycle of signal Sig3 opens and closes switch S3, Switch S4 may be opened or closed by changing the duty cycle of signal Sig4 to adjust the duty cycle of the switch. By adjusting the duty cycle of switches S1, S2, S3, or S4, for example, the output voltage of resonant circuit 610 can be controlled.

In some embodiments, each switch S1, S2, S3, or S4 of RF driver 605 can be switched independently or in conjunction with one or more other switches. For example, signal Sig1 may be the same signal as signal Sig3. As another example, signal Sig2 may be the same signal as signal Sig4. As another example, each signal may be independent and independently or separately control each switch S1, S2, S3, or S4.

In some embodiments, resonant circuit 610 may be coupled with half-wave rectifier 615, which may include blocking diode D7.

In some embodiments, half-wave rectifier 615 may be coupled with resistive output stage 620 . Resistive output stage 620 may include any resistive output stage known in the art. For example, resistive output stage 620 may be any of the resistive output stages described in U.S. patent application Ser. and this patent application is incorporated in its entirety into this disclosure for all purposes.

For example, resistive output stage 620 may include inductor L11, resistor R3, resistor R1, and capacitor C11. In some embodiments, inductor L11 may include an inductance between about 5 μH and about 25 μH. In some embodiments, resistor R1 may include a resistance of about 50 ohms to about 250 ohms. In some embodiments, resistor R3 may include a floating resistance in resistive output stage 620. FIG.

In some embodiments, resistor R1 may include multiple resistors arranged in series and/or in parallel. Capacitor C11 may represent the stray capacitance of resistor R1, including the capacitance of series and/or parallel resistors arranged. The capacitance of the stray capacitance C11 may be, for example, 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, less than 1 pF, or the like. The capacitance of stray capacitance C11 may be less than the load capacitance, eg, less than the capacitance of C2, C3, and/or C9.

In some embodiments, resistor R1 may discharge a load (eg, the capacitance of the plasma sheath). In some embodiments, resistive output stage 620 may be configured to discharge more than about 1 kilowatt of average power during each pulse cycle and/or less than 1 Joule of energy during each pulse cycle. may be configured to discharge In some embodiments, the resistance of resistor R1 of resistive output stage 620 may be less than 200 ohms. In some embodiments, resistor R1 may include multiple resistors arranged in series or parallel with a combined capacitance of less than about 200 pF (eg, C11).

In some embodiments, resistive output stage 620 may include a collection of circuit elements that can be used to control the shape of the voltage waveform on the load. In some embodiments, resistive output stage 620 may include only passive components (eg, resistors, capacitors, inductors, etc.). In some embodiments, resistive output stage 620 may include active circuit elements (eg, switches) as well as passive circuit elements. In some embodiments, resistive output stage 620 may be used, for example, to control the voltage rise time of the waveform and/or the voltage fall time of the waveform.

In some embodiments, resistive output stage 620 can discharge capacitive loads (eg, wafers and/or plasma). For example, these capacitive loads can have small capacitances (eg, about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

In some embodiments, the resistive output stage is pulsed at high voltages (eg, greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.) and/or high frequency (eg, 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz) and/or frequencies of about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

In some embodiments, a resistive output stage may be selected to handle high average power, high peak power, fast rise time and/or fast fall time. For example, average power ratings may be greater than about 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and/or peak power ratings may be greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.

In some embodiments, resistive output stage 620 may include a series or parallel network of passive components. For example, resistive output stage 620 may include a series of resistors, capacitors, and inductors. As another example, resistive output stage 620 may include a capacitor in parallel with an inductor and a capacitor-inductor combination in series with a resistor. For example, L11 can be chosen large enough so as not to inject too much energy into the resistive output stage when the voltage is out of the rectifier. The values of R3 and R1 can be chosen such that the L/R time can drain a suitable capacitor in the load faster than the RF frequency.

In some embodiments, resistive output stage 620 may be coupled with bias compensation circuit 625 . Bias compensation circuitry 625 may include any bias and/or bias compensation circuitry known in the art. For example, the bias compensation circuit 625 may include any of the bias and/or bias compensation circuits described in US patent application Ser. Well, this patent application is incorporated in its entirety into this disclosure for all purposes.

In some embodiments, bias compensation circuit 625 includes bias capacitor C7, blocking capacitor C12, blocking diode D8, switch S8 (eg, high voltage switch), offset supply voltage V1, resistor R2, and/or resistor R4. It's okay. In some embodiments, switch S8 may be used in the U.S. patent application entitled HIGH VOLTAGE SWITCH FOR NANOSECOND PULS1NG, which is incorporated in its entirety by this disclosure for all purposes. No. 62/717,637, and/or US patent application Ser.

In some embodiments, the offset supply voltage V5 may include a DC voltage source that can bias the output voltage either positively or negatively. In some embodiments, capacitor C12 may isolate/isolate offset supply voltage V5 from resistive output stage 620 and/or other circuit elements. In some embodiments, the bias compensation circuit 625 may allow potential shifts in power from one portion of the circuit to another. In some embodiments, bias compensation circuit 625 may be used to hold the wafer in place when high voltage pulses are active in the chamber. Resistor R2 may protect/isolate the DC bias power supply from the driver.

In some embodiments, switch S8 may be open while RF driver 605 is pulsing and closed when RF driver 605 is not pulsing. While closed, switch S8 may, for example, short-circuit current through blocking diode D8. Shorting this current allows the bias between the wafer and chuck to be less than 2 kV, which may be acceptable.

In some embodiments, plasma and chamber 630 may be coupled with bias compensation circuitry 625 . Plasma and chamber 630 may be represented, for example, by various circuit elements shown in FIG.

FIG. 6 does not include conventional matching networks such as, for example, 50 ohm matching networks, external matching networks, or stand-alone matching networks. In fact, the embodiments described herein do not require a 50 ohm matching network to adjust the switching power applied to the wafer chamber. Further, the embodiments described herein provide variable output impedance RF generators without conventional matching networks. This allows the power drawn by the plasma chamber to be changed quickly. Typically, this adjustment of the matching network can take at least 100-200 μs. In some embodiments, the power change may occur within one or two RF cycles, eg, from 2.5 μs to 5.0 μs at 400 kHz.

FIG. 7 shows the voltage waveforms across transformer T1 (red), pole (green), and wafer (blue) in a time frame of 600 μs. FIG. 8 is a magnified view of the waveforms in a time frame of 10 μs.

FIG. 9 is a circuit diagram of a bias generator 900 according to some embodiments. Bias generator 900 may include, for example, RF driver 605 , resonant circuit 610 , bias compensation circuit 625 , and plasma chamber 630 . Bias generator 900 is similar to bias generator 600 but lacks resistive output stage 620 and includes energy recovery circuit 905 .

In this example, the energy recovery circuit 905 may be located on or electrically coupled to the secondary side of the transformer T1. Energy recovery circuit 905 may include, for example, a diode D9 (eg, a crowbar diode) across the secondary of transformer T1. Energy recovery circuit 905 may include, for example, diode D10 and inductor L12 (placed in series) to draw current from the secondary of transformer T1 to charge power supply C15 and to the plasma and chamber 630. can flow. Diode D12 and inductor L12 are electrically connected to the secondary side of transformer T1 and may be coupled to power source C15. In some embodiments, energy recovery circuit 905 may include diode D13 and/or inductor L13 electrically coupled to the secondary of transformer T1. Inductor L12 may represent and/or include the stray inductance of transformer T1.

When the nanosecond pulser turns on, current may charge the plasma and chamber 630 (eg, charge capacitor C3, capacitor C2, or capacitor C9). Some current may flow through inductor L12, for example, when the voltage on the secondary side of transformer T1 rises above the charging voltage of power supply C15. When the nanosecond pulser is turned off, current may flow from a capacitor in plasma chamber 630 through inductor L12 to charge power source C15 until the voltage across inductor L12 is zero. Diode D9 may prevent capacitors in plasma chamber 630 from ringing with inductance in plasma chamber 630 and bias compensation circuit 625 .

Diode D12 may, for example, prevent charge from flowing from power source C15 to a capacitor in plasma chamber 630 .

The value of inductor L12 may be selected to control the current fall time. In some embodiments, inductor L12 may have an inductance value between 1 μH and 500 μH.

In some embodiments, energy recovery circuit 905 may include a switch that may be used to control current flow through inductor L12. A switch may, for example, be placed in series with inductor L12. In some embodiments, the switch may be closed when switch S1 is open and/or when it is no longer pulsing, allowing current to flow back from plasma and chamber 630 to power source C15.

The switches of energy recovery circuit 905, for example, claim priority from U.S. Provisional Patent Application No. 62/717,637, filed Aug. 10, 2018, both of which are incorporated by reference in their entirety. 16/178,565, filed Nov. 1, entitled HIGH VOLTAGE SWITCH WITH ISOLATED POWER. good. In some embodiments, RF driver 605 may include high voltage switches instead of or in addition to various components shown in RF driver 605 . In some embodiments, using a high voltage switch may allow at least the transformer T1 and switch S1 to be eliminated.

FIG. 10 is a circuit diagram of bias generator 1000 according to some embodiments. Bias generator 1000 may include, for example, RF driver 605 , resonant circuit 610 , resistive output stage 620 , and plasma chamber 630 . Thus, bias generator 1000 is similar to bias generator 600 without bias compensation circuit 625 .

FIG. 11 is a circuit diagram of bias generator 1100 according to some embodiments. Bias generator 1100 may include, for example, RF driver 605 , resonant circuit 610 , energy recovery circuit 905 , and plasma chamber 630 . Thus, bias generator 1100 is similar to bias generator 900 without bias compensation circuit 625 .

FIG. 12 is a circuit diagram of an RF plasma generator 1200 according to some embodiments. RF plasma generator 1200 may include, for example, RF driver 605 , resonant circuit 610 , and inductive discharge plasma 1205 . In this example, inductor L5 may include an antenna coupled to or disposed within inductive discharge plasma 1205 . Transformer T1 may represent how the inductive discharge plasma 1205 couples with the antenna, which is at least partially represented by inductor L5. Capacitor C2 may resonate with inductor L5 to determine the resonant frequency. RF driver 605 may generate pulses driven at this resonant frequency.

FIG. 13 is a circuit diagram of an RF plasma generator 1200 according to some embodiments. RF plasma generator 1200 may include, for example, RF driver 1305 , resonant circuit 1310 which may include a transformer, and chamber 630 . Capacitor C1 may represent a discharge shaped capacitance, stray capacitance in the circuit, or the capacitance of any capacitor in the circuit. L5 may represent any stray inductance in the circuit, or the inductance of any inductance in the circuit. RF driver 1305 may drive resonant circuit 1310 with a pulse frequency substantially equal to the resonant frequency of the resonant circuit.

In some embodiments, each switch S1, S2, S3, or S4 within RF driver 1305 may be switched independently or in conjunction with one or more other switches. For example, signal Sig1 may be the same signal as signal Sig3. As another example, signal Sig2 may be the same signal as signal Sig4. As another example, each signal may be independent and independently or separately control each switch S1, S2, S3, or S4.

In some embodiments, transformer T1 may or may not be included in RF plasma generator 1200 .

14A, 14B, 15A and 15B are circuit diagrams of exemplary resonant circuits that may be used in place of resonant circuit 610 of FIG. These circuits may or may not include the transformers shown in each figure.

FIG. 16 is a circuit diagram of bias generator 1600 including nanosecond pulser stage 101 with energy recovery circuit 1610, transformer T1, read stage 103, DC bias circuit 104, and load stage .

In some embodiments, load stage 106 may represent an idealized or effective circuit of a semiconductor processing chamber such as, for example, a plasma deposition system, semiconductor fabrication system, plasma sputtering system, or the like. Capacitance C2 may represent, for example, the capacitance of an electrostatic chuck on which a semiconductor process wafer may rest. The chuck may include, for example, a dielectric material (eg, aluminum oxide, or other ceramic material, and a conductor encased within the dielectric material). For example, capacitor C1 may have a small capacitance (eg, about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

Capacitor C3 may represent, for example, the plasma-to-wafer sheath capacitance. Resistor R6 may represent, for example, the sheath resistance between the plasma and wafer. Inductor L2 may represent, for example, the sheath inductance between the plasma and the wafer. Current source I2 may represent, for example, the ion current through the sheath. For example, capacitor C1 or capacitor C3 may have a small capacitance (eg, about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

Capacitor C9 may represent, for example, the capacitance of the plasma sheath to the walls of the chamber. Resistor R7 may represent, for example, the resistance between the plasma and the chamber wall. Current source I1 may represent, for example, the ion current in the plasma. For example, capacitor C1 or capacitor C9 may have a small capacitance (eg, about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

In some embodiments, the plasma voltage may be the voltage measured from ground to circuit point 123, and the wafer voltage may be the voltage measured from ground to circuit point 122, the voltage at the surface of the wafer. where chucking voltage is the voltage measured from ground to circuit point 121, electrode voltage is the voltage measured from ground to circuit point label 124 (e.g., on the electrode), and input voltage is the voltage measured from ground to circuit point 125;

In this example, DC bias circuit 104 does not include bias compensation. DC bias circuit 104 includes, for example, an offset supply voltage V5 whose output voltage can be biased either positively or negatively. In some embodiments, the offset supply voltage V5 can be adjusted to change the potential between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V5 may have a voltage of kV, such as about ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV.

In some embodiments, bias capacitor C12 may isolate (or separate) the DC bias voltage from other circuit elements. For example, bias capacitor C12 may allow potential shifts from one part of the circuit to another. In some embodiments, this potential shift ensures that the electrostatic force holding the wafer in place on the chuck remains below a voltage threshold. Resistor R2 may isolate the DC bias power supply from the high voltage pulse output from nanosecond pulser stage 101 .

Bias capacitor C12 may have a capacitance of, for example, less than about 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, 1 μF, and the like. Resistor R2 may have a high resistance such as, for example, about 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm.

Resistor R13 may represent, for example, the resistance of a lead or transmission line connecting the output of the high voltage power supply system to an electrode (eg, load stage 106). Capacitor C1 may also represent stray capacitance in a lead or transmission line, for example.

In some embodiments, the nanosecond pulser stage 101 uses high pulse voltages (eg, greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high frequencies (eg, 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, frequencies greater than 1 MHz), fast rise times (e.g., rise times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), fast fall times (e.g., about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, fall times of less than 1,000 ns) and/or short pulse widths (e.g., pulse widths of less than about 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.). good.

For example, the nanosecond pulser stage 101 may be any of those described in US patent application Ser. No. 14/542,487, entitled "High Voltage Nanosecond Pulser," which is incorporated into this disclosure for all purposes. or U.S. Patent Application No. 14, entitled "Galvanically Isolated Output Variable Pulse Generator Disclosure," which is incorporated into this disclosure for any purpose. 635,991 or "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency" incorporated into this disclosure for any purpose. No. 14/798,154 entitled Pulse Width and Pulse Repetition Frequency).

In some embodiments, nanosecond pulser stage 101 may include one or more nanosecond pulsers coupled together in any manner.

In some embodiments, nanosecond pulser stage 101 may include a DC power supply that is switched by switch S6 to provide a consistent DC voltage that supplies switched power to transformer T1. The DC power supply may include voltage source V5 and energy storage capacitor C7. If the transformer T1 has a turns ratio of 1:10, the transformer can generate 10 kV on the load C1.

In some embodiments, if the capacitance of the load (eg, capacitance C3 and capacitance C9) is small compared to the capacitance of the energy storage capacitor C7, voltage doubling may (or may not) occur at the input of the transformer. may be used). For example, if energy storage capacitor C7 supplies 500V, 1 kV may be measured at the input of transformer T1.

Switch S6 may include one or more solid state switches such as, for example, IGBTs, MOSFETs, SiC-MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, and the like. Switch S6 may be switched based on signals from the controller labeled Sig6+ and Sig6-.

In some embodiments, nanosecond pulser stage 101 may include snubber circuits that may include any type of snubber circuit. In some embodiments, the snubber circuit may include a capacitor. In some embodiments, a snubber circuit may include a capacitor and a resistor. In some embodiments, snubber circuits may include capacitors, inductors, and resistors.

In some embodiments, the snubber circuit may include snubber resistor R3 in parallel with snubber diode D4, and snubber capacitor C5. The snubber circuit may also include stray inductance. In some embodiments, snubber resistor R3 and/or snubber diode D4 may be placed between the collector of switch S6 and the primary winding of transformer T1. Snubber diode D4 may be used to snubb out overvoltages during switching. A large and/or high speed capacitor C5 may be coupled to the emitter side of switch S6. Freewheeling diode D2 may also be coupled to the emitter side of switch S1. Various other components not shown may be included. One or more switches and/or circuits may be arranged in parallel or in series.

In some embodiments, switch S6 may switch very fast so that the switched voltage does not go to full voltage (eg, the voltage of energy storage capacitor C7 and/or voltage source V5). In some embodiments, a gate resistor coupled to switch S6 may be set with a short turn-on pulse.

In some embodiments, nanosecond pulser stage 101 may include freewheeling diode D2. In some embodiments, a freewheeling diode D2 may be used in combination with an inductive load to keep the current flowing in the same direction through the inductor so that the energy is dissipated in the resistive elements of the circuit. This ensures that the energy stored in the inductive load is dissipated after switch S6 is opened. If freewheeling diode D2 were not included, this could lead to a large reverse voltage on switch S6, for example.

In some embodiments, nanosecond pulser stage 101 may include stray inductance L1 and/or stray resistance R1. The stray inductance L1 may be, for example, less than about 10 nH, 100 nH, 1,000 nH, 10,000 nH, or the like. Floating resistance R1 may be, for example, about 1 Ohm, 100 mOhms, less than 10 mOhms, or the like.

In some embodiments, the energy recovery circuit 1610 may be electrically coupled to the transformer secondary and/or the energy storage capacitor C7. Energy recovery circuit 1610 may include, for example, diode 130 (eg, a crowbar diode) across the secondary of transformer T1. The energy recovery circuit 1610 may include, for example, an energy recovery diode 1620 and an energy recovery inductor 1615 (placed in series) to allow current to flow from the secondary of transformer T1 to charge the energy storage capacitor C7. enable. Energy recovery diode 1620 and energy recovery inductor 1615 may be electrically connected to the secondary of transformer T1 and energy storage capacitor C7. In some embodiments, energy recovery circuit 1610 may include diode 130 and/or inductor 140 electrically coupled to the secondary of transformer T1. Inductor 140 may represent and/or include the stray inductance of transformer T1.

In some embodiments, energy recovery inductor 1615 may include any type of inductor such as, for example, ferrite core inductors or air core inductors. In some embodiments, energy recovery inductor 1615 may have any type of geometry, such as, for example, solenoidal windings, toroidal windings, and the like. In some embodiments, the energy recovery inductor 1615 may have an inductance greater than about 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, energy recovery inductor 1615 may have an inductance between about 1 μH and about 100 mH.

In some embodiments, when the nanosecond pulser is turned on, current can charge the load stage 106 (eg, charge capacitor C3, capacitor C2, or capacitor C9). Some current may flow through energy recovery inductor 1615, for example, when the voltage on the secondary of transformer T1 is higher than the charging voltage of energy storage capacitor C7. When the nanosecond pulser is turned off, current flows from a capacitor (eg, capacitor C1) in load stage 106 through energy recovery inductor 1615 until the voltage across energy recovery inductor 1615 is zero, thereby draining energy storage capacitor C7. You can charge. Diode 130 may prevent capacitors in load stage 106 from ringing with inductance in load stage 106 or DC bias circuit 104 .

Energy recovery diode 1620 may, for example, prevent charge from flowing from energy storage capacitor C7 to a capacitor in load stage 106 .

The value of energy recovery inductor 1615 may be selected to control the current fall time. In some embodiments, energy recovery inductor 1615 may have an inductance value between 1 μH and 600 μH. In some embodiments, energy recovery inductor 1615 may have an inductance value greater than 50 μH. In some embodiments, energy recovery inductor 1615 may have an inductance of less than about 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

For example, if energy storage capacitor C7 supplies 500V, 1 kV will be measured at the input of transformer T1 (eg, by voltage doubling as described above). The 1 kV on transformer T1 may be divided among the components of energy recovery circuit 1610 when switch S6 is open. If the values are properly chosen (eg, inductor L3 has an inductance less than that of energy recovery inductor 1615), the voltage across energy recovery diode 1620 and energy recovery inductor 1615 may be greater than 500V. Current may then flow through the energy recovery diode 1620 and/or charge the energy storage capacitor C7. Current may also flow through diode D3 and inductor L6. Once energy storage capacitor C7 is charged, current may no longer flow through diode D3 and energy recovery inductor 1615.

In some embodiments, the energy recovery circuit 1610 extracts energy from the load stage 106, for example, on fast timescales (eg, timescales of 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). You may transfer (or transfer charge). The stray resistance of the energy recovery circuit may be low to ensure that the pulse applied to load stage 106 has a fast fall time _tf . The floating resistance of the energy recovery circuit 1610 may have a resistance value of, for example, less than about 1 Ohm, 100 mOhms, 10 mOhms, or the like. In some embodiments, the energy transfer efficiency from load stage 106 may be high, such as, for example, greater than about 60%, 70%, 80%, or 90%.

Any components shown in FIG. 16 may or may not be required, such as diode 135 or diode 130 or inductor 140, for example.

In some embodiments, a diode may be placed between voltage source V1 and the point where energy recovery circuit 1610 connects with voltage source V1 and/or energy storage capacitor C7. This diode may, for example, be arranged to allow current flow from the voltage source V1 to the energy storage capacitor C7, but not from the energy recovery circuit to the energy storage capacitor C7.

1700 is a circuit diagram of bias generator 1700 including nanosecond pulser stage 101 with active energy recovery circuit 111 having energy recovery switch S5 according to some embodiments. The energy recovery switch S5 may be switched based on signals from the controller labeled Sig5+ and Sig5-.

17, active energy recovery circuit 111 may include energy recovery switch S5 that may be used to control current flow through energy recovery inductor 1615. In FIG. In some embodiments, energy recovery switch S5 may include a freewheeling diode positioned across the energy recovery switch. Energy recovery switch S5 may be placed in series with energy recovery inductor 1615, for example. In some embodiments, energy recovery switch S5 may be opened and closed based on signals from Sig5+ and/or Sig5-. In some embodiments, switching input V5 closes the energy recovery switch when switch S1 is open and/or no longer pulsing, allowing current to flow back from load stage 106 to high voltage load C7. may be enabled. In some embodiments, the switching signals from Sig5+ and/or Sig5− open the energy recovery switch when switch S1 is closed and/or pulsing to provide current to high voltage load C7. may restrict the flow of

Energy recovery switch S5 in FIG. 17 is shown in series with energy recovery diode 1620 and energy recovery inductor 1615 and is placed between the secondary of transformer T1 and both energy recovery diode 1620 and energy recovery inductor 1615. It is In some embodiments, both energy recovery diode 1620 and energy recovery inductor 1615 may be placed between energy recovery switch S5 and the secondary of transformer T1. In some embodiments, energy recovery switch S5 may be positioned between energy recovery diode 1620 and energy recovery inductor 1615 . Energy recovery diode 1620, energy recovery inductor 1615, and energy recovery switch S5 may be arranged in any order.

Energy recovery switch S5 may include a high voltage switch, such as high voltage switch 2300, for example.

In some embodiments, load stage 106 may be charged by nanosecond pulser stage 101 while energy recovery switch S5 is open. For example, it may be beneficial to remove charge from load stage 106 on fast timescales (eg, less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, less than 1,000 ns, etc.). To remove charge from load stage 106, energy recovery switch S5 may be closed.

FIG. 18 is a circuit diagram of a bias generator 1800 including passive bias compensation circuit 114 with energy recovery circuit 1610 according to some embodiments.

In this example, passive bias compensation circuit 114 is a passive bias compensation circuit and may include bias compensation diode 1805 and bias compensation capacitor 1810 . A bias compensation diode 1805 may be placed in series with the offset supply voltage V5. A bias compensation capacitor 1810 may be placed across either or both of the offset supply voltage V5 and resistor R2. Bias compensation capacitor 1810 may have a capacitance of 100 nF to less than 100 μF, such as, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, 200 nF.

In some embodiments, bias compensating diode 1805 may conduct currents between 10 A and 1 kA at frequencies between 10 Hz and 500 kHz.

In some embodiments, bias capacitor C12 provides a voltage between the output of nanosecond pulser stage 101 (eg, position labeled 125) and the voltage on the electrode (eg, position labeled 124). Offsets may be allowed. In operation, the electrodes may be at a DC voltage of, for example, −2 kV during a burst (a burst may include multiple pulses), while the output of the nanosecond pulser is +6 kV during the pulse and alternating with 0 kV in between.

The bias capacitor C12 is, for example, 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, 1 μF, or the like. Resistor R2 may have a high resistance value, such as, for example, approximately 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm.

In some embodiments, the bias compensation capacitor 1810 and the bias compensation diode 1805 are connected between the output of the nanosecond pulser stage 101 (eg, position labeled 125) and the voltage on the electrode (eg, position labeled 124). ) may be established at the beginning of each burst to allow the necessary equilibrium to be reached. For example, charge is transferred from capacitor C12 to bias compensation capacitor 1810 over the course of multiple pulses (eg, on the order of about 5-100 pulses) at the beginning of each burst to establish the correct voltage in the circuit.

In some embodiments, the pulse repetition frequency (eg, the frequency of pulses within a burst) may be, for example, 200 kHz to 800 MHz, such as 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz. In some embodiments, the burst repetition frequency (eg, the frequency of the bursts) may be approximately 10 kHz, 50 Hz, 100 kHz, 500 kHz, 1 MHz, etc., eg, 400 kHz.

Energy recovery circuit 1610 may or may not include an energy recovery switch, as shown in FIG.

FIG. 19 is a circuit diagram of bias generator 1900 including active bias compensation circuit 134 with energy recovery circuit 1610 according to some embodiments.

Active bias compensation circuitry 134 may include any bias and/or bias compensation circuitry known in the art. For example, active bias compensation circuit 134 may include any of the bias and/or bias compensation circuits described in US patent application Ser. and this patent application is incorporated into this disclosure in its entirety for all purposes.

In some embodiments, the active bias compensation circuit 134 of the bias generator 1900 shown in FIG. It may include supply voltage V5, resistor R2, and/or resistor R4. In some embodiments, switch S8 may include a high voltage switch, such as high voltage switch 2300 shown in FIG. 25, for example. The bias compensation switch S8 may be switched based on signals from the controller labeled Sig8+ and Sig8-.

In some embodiments, the offset supply voltage V5 may include a DC voltage source that can bias the output voltage either positively or negatively. In some embodiments, capacitor C12 may isolate/isolate offset supply voltage V5 from other circuit elements. In some embodiments, active bias compensation circuit 134 may allow for potential shifts in power from one portion of the circuit to another. In some embodiments, active bias compensation circuit 134 may be used to maintain a constant chucking force between the process wafer and the electrostatic chuck. Resistor R2 may, for example, protect/isolate the DC bias supply from the driver. As another example, resistor R2 may be used to prevent DC power supply V5 from going into an overcurrent fault.

In some embodiments, bias compensation switch S8 is open while nanosecond pulser stage 101 is not actively producing pulses or providing bursts of pulses above 10 kHz, and nanosecond pulser stage 101 is It may be closed when not generating a pulse. While closed, bias compensation switch S8 may allow current in the direction blocked by blocking diode D8, for example. Shorting this current allows the bias between the wafer and chuck to be less than 2 kV, which may be acceptable.

In some embodiments, load stage 106 may be coupled with active bias compensation circuit 134 . In some embodiments, the energy recovery circuit 1610 may or may not include an energy recovery switch, as shown in FIG.

FIG. 20 is a circuit diagram of bias generator 2000 including active bias compensation circuit 134 with active energy recovery circuit 111, according to some embodiments.

FIG. 21 is a circuit diagram of bias generator 2100 with energy recovery circuit 1610 according to some embodiments. In this example, bias generator 2100 is similar to bias generator 1600 with nanosecond pulser stage 101 switching the other polarity of energy storage capacitor C7. When switch S6 is open, the charge on capacitor C1 may flow through energy recovery circuit 1610 to high voltage energy storage capacitor C7 to charge high voltage energy storage capacitor C7. Current stops flowing through energy recovery circuit 1610 when the charge on capacitor C1 becomes less than the charge on high voltage energy storage capacitor C7. In some embodiments, DC bias circuit 104 may be replaced with passive bias compensation circuit 114 or active bias compensation circuit 134 . In some embodiments, energy recovery circuit 1610 may be replaced with active energy recovery circuit 111 .

Some embodiments include a nanosecond pulser (or switch) to switch between the ground side (see, eg, FIG. 16) or the positive side (see, eg, FIGS. 21 or 22) of power supplies V1 and/or C7. Any arrangement may be used. A diagram showing one arrangement may be replaced with the other arrangement.

FIG. 22 is a circuit diagram of a bias generator 2200 with an energy recovery circuit 1610 driving a capacitive load 2205, according to some embodiments. In this example, bias generator 2200 is similar to bias generator 1600 without DC bias circuit 104 and is driving capacitive load 2205 . Capacitive load 2205 may include any type of load, such as, for example, a plasma load, multiple grids, multiple electrodes, a physical capacitor, the capacitance of a photoconductive switch, and the like.

FIG. 23 is a block diagram of a high voltage switch 2300 with isolated power, according to some embodiments. The high voltage switch 2300 includes a plurality of switch modules 2305 (collectively or individually 2305 and individually 2305A, 2305B, 2305C, 2305D). Each switch module 2305 may include a switch 2310 such as, for example, a solid state switch.

In some embodiments, switch 2310 may be electrically coupled to gate driver circuitry 2330, which may include power supply 2340 and/or insulated fiber trigger 2345 (also called gate trigger or switch trigger). For example, switch 2310 may include a collector, emitter, and gate (or drain, source, and gate), and power supply 2340 may drive the gate of switch 2310 through gate driver circuit 2330 . The gate driver circuit 2330 may be isolated from other components of the high voltage switch 2300, for example.

In some embodiments, power supply 2340 may be isolated using, for example, an isolation transformer. The isolation transformer may include a low capacity transformer. The low capacitance of the isolation transformer may, for example, allow the power supply 2340 to charge on a fast timescale without requiring large currents. The isolation transformer may, for example, have a capacitance of less than about 100 pF. As another example, the isolation transformer may have a capacitance of less than about 30-100 pF. In some embodiments, the isolation transformer may provide voltage isolation up to 1 kV, 5 kV, 10 kV, 23 kV, 50 kV, etc.

In some embodiments, the isolation transformer may have low stray capacitance. For example, an isolation transformer may have a stray capacitance of less than about 1,000 pF, 100 pF, 10 pF, etc. In some embodiments, the low capacitance may minimize electrical coupling to low voltage components (e.g., input controlled power source) and/or reduce EMI generation (e.g., electrical noise generation). You may In some embodiments, transformer stray capacitance of an isolation transformer may include capacitance measured between a primary winding and a secondary winding.

In some embodiments, the isolation transformer may be a DC/DC converter or an AC/DC transformer. In some embodiments, the transformer may include, for example, a 110V AC transformer. In any event, the isolation transformer can provide power isolated from other components within the high voltage switch 2300 . In some embodiments, the isolation may be galvanic such that conductors on the primary side of the isolation transformer do not pass through or touch any conductors on the secondary side of the isolation transformer.

In some embodiments, a transformer may include a primary winding that is tightly wound or wrapped around a transformer core. In some embodiments, the primary winding may include a conductive sheet wrapped around the transformer core. In some embodiments, the primary winding may include one or more windings.

In some embodiments, the secondary winding may be wound around the core as far away from the core as possible. For example, a winding bundle including a secondary winding may be wound through the center of the transformer core opening. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the winding bundle including the secondary winding may include cross-sections that are, for example, circular or square to minimize stray capacitance. In some embodiments, an insulator (eg, oil or air) may be placed between the primary windings, secondary windings, or transformer core.

In some embodiments, keeping the secondary windings away from the transformer core can have several advantages. For example, it can reduce the stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, a high voltage standoff between the isolation transformer primary and the isolation transformer secondary may be enabled to prevent corona and/or breakdown from forming during operation.

In some embodiments, the spacing between the isolation transformer primary (e.g., primary winding) and the isolation transformer secondary (e.g., secondary winding) is about 0.1 inches, 0.5 inches. It can be inches, 1 inch, 5 inches, or 10 inches. In some embodiments, typical spacings between the isolation transformer core and the isolation transformer secondary (e.g., secondary winding) are about 0.1 inch, 0.5 inch, 1 inch, It can be 5 inches or 10 inches. In some embodiments, the gaps between the windings are filled with the lowest possible dielectric material, such as vacuum, air, any insulating gas or liquid, or a solid material with a dielectric constant of less than 3. may

In some embodiments, power supply 2340 may include any type of power supply capable of providing high voltage standoff (isolation) or having low capacitance (eg, less than about 1,000 pF, 100 pF, 10 pF, etc.). . In some embodiments, the controlled voltage power supply may provide 1420 VAC or 240 VAC at 60 Hz.

In some embodiments, each power supply 2340 may be inductively and/or electrically coupled to a single controlled voltage power supply. For example, power source 2340A may be electrically coupled to the power source via a first transformer, power source 2340B may be electrically coupled to the power source via a second transformer, and power source 2340C may be electrically coupled to the power source via a third transformer. It may be electrically coupled to the power supply through a transformer, and power supply 2340D may be electrically coupled to the power supply through a fourth transformer. For example, any type of transformer capable of providing voltage isolation between various power sources may be used.

In some embodiments, the first transformer, the second transformer, the third transformer, and the fourth transformer may include different secondary windings around a single transformer core. For example, a first transformer includes a first secondary winding, a second transformer includes a second secondary winding, a third transformer includes a third secondary winding, and a fourth transformer includes a third secondary winding. The transformer may include a fourth secondary winding. Each of these secondary windings may be wound on a single transformer core. In some embodiments, the first secondary winding, second secondary winding, third secondary winding, fourth secondary winding, or primary winding is a single winding. Or it may include multiple windings wrapped around a transformer core.

In some embodiments, power supply 2340A, power supply 2340B, power supply 2340C, and/or power supply 2340D may not share a return reference ground or local ground.

Isolated fiber trigger 2345 may also be isolated from other components of high voltage switch 2300, for example. The isolated fiber trigger 2345 may allow each switch module 2305 to float relative to other switch modules 2305 and/or other components of the high voltage switch 2300 and/or, for example, A fiber optic receiver may be included to enable active control of the gate of the .

In some embodiments, for example, the return reference ground or local ground or common ground of each switch module 2305 may be isolated from each other using, for example, an isolation transformer.

Electrically isolating each switch module 2305 from a common ground allows, for example, multiple switches to be arranged in a series configuration for cumulative high voltage switching. In some embodiments, some lag in switch module timing may be allowed or designed. For example, each switch module 2305 may be configured or rated to switch 1 kV, each switch module may be electrically isolated from each other, and/or the timing of closing each switch module 2305 may be a snubber. It may not match perfectly for a period of time defined by the capacitance of the capacitor and/or the voltage rating of the switch.

In some embodiments, electrical isolation can provide many advantages. For example, one possible advantage may include minimizing jitter between switches and/or allowing arbitrary switch timing. For example, each switch 2310 may have a switch transition jitter of less than about 500ns, 50ns, 20ns, 5ns, etc.

In some embodiments, electrical isolation between two components (or circuits) can imply a very high resistance between the two components and/or a small capacitance between the two components.

Each switch 2310 may comprise any type of solid-state switch device such as, for example, IGBTs, MOSFETs, SiC-MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, and the like. The switch 2310 may, for example, transmit high voltages (eg, greater than about 1 kV) at high frequencies (eg, greater than 1 kHz), at high speeds (eg, repetition rates greater than about 500 kHz), and/or with fast rise times (eg, about rise times of less than 23 ns) and/or long pulse lengths (eg, greater than about 10 ms). In some embodiments, each switch can individually switch voltages between 1,200 V and 1,700 V, but when used in combination, voltages in excess of 4,800 V to 6,800 V (for 4 switches) can be switched. Other switches with different voltage ratings may be used.

Using a large number of low voltage switches rather than a small number of high voltage switches has several advantages. For example, low voltage switches generally have higher performance, and low voltage switches may switch faster, have faster transition times, and/or have higher switching efficiency than high voltage switches. However, the greater the number of switches, for example, the greater the need for switch timing accuracy.

The high voltage switch 2300 shown in FIG. 23 includes four switch modules 2305 . Although four are shown in this figure, any number of switch modules 2305 may be used, eg, 2, 8, 12, 16, 20, 24, etc. FIG. For example, if each switch in each switch module 2305 is rated at 1200V and 16 switches are used, the high voltage switches can switch up to 19.2 kV. As another example, if each switch in each switch module 2305 is rated at 1700V and 16 switches are used, the high voltage switches can switch up to 27.2 kV.

In some embodiments, the high voltage switch 2300 can switch voltages greater than 5 kV, 10 kV, 14 kV, 20 kV, 23 kV, and the like.

In some embodiments, high voltage switch 2300 may include high speed capacitor 2355 . High speed capacitor 2355 may include, for example, one or more capacitors arranged in series and/or in parallel. These capacitors may include, for example, one or more polypropylene capacitors. A high speed capacitor 2355 may store energy from a high voltage source 2360 .

In some embodiments, high speed capacitor 2355 may have a low capacitance. In some embodiments, high speed capacitor 2355 may have a capacitance value of about 1 μF, about 5 μF, about 1 μF to about 5 μF, about 100 nF to about 1,000 nF, and the like.

In some embodiments, high voltage switch 2300 may or may not include crowbar diode 2350 . The crowbar diode 2350 may include multiple diodes arranged in series or parallel, which are useful, for example, in driving inductive loads. In some embodiments, crowbar diode 2350 may include one or more Schottky diodes, such as, for example, silicon carbide Schottky diodes. A crowbar diode 2350, for example, may sense if the voltage from the switch of the high voltage switch exceeds a certain threshold. If so, the crowbar diode 2350 may short the power from the switch module to ground. A crowbar diode, for example, may allow an alternating current path to dissipate energy stored in an inductive load after switching. This may, for example, prevent large induced voltage spikes. In some embodiments, the crowbar diode 2350 may have a low inductance, eg, 1 nH, 10 nH, 100 nH. In some embodiments, the crowbar diode 2350 may have a low capacitance, eg, 100 pF, 1 nF, 10 nF, 100 nF.

In some embodiments, crowbar diode 2350 may not be used, for example, if load 2365 is primarily resistive.

In some embodiments, each gate driver circuit 2330 may generate less than about 1000 ns, 100 ns, 10.0 ns, 5.0 ns, 3.0 ns, 1.0 ns, etc. jitter. In some embodiments, each switch 2310 has a minimum switch-on time (eg, less than about 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10, 5 ns, etc.) and a maximum switch-on time (eg, 23 s, 10 s, 5 s, 1s, 500ms, etc.).

In some embodiments, during operation each of the high voltage switches may be switched on and/or off within 1 ns of each other.

In some embodiments, each switch module 2305 may have the same or substantially the same (±5%) stray inductance. Stray inductance may include any inductance within switch module 2305 that is not associated with an inductor, such as, for example, the inductance of leads, diodes, resistors, switch 2310, and/or circuit board traces. The stray inductance within each switch module 2305 may include low inductance, such as, for example, less than about 300 nH, 100 nH, 10 nH, 1 nH, and the like. The stray inductance between each switch module 2305 may include low inductance, eg, less than about 300 nH, 100 nH, 10 nH, 1 nH, and the like.

In some embodiments, each switch module 2305 may have the same or substantially the same (±5%) stray capacitance. Stray capacitance may include, for example, any capacitance within switch module 2305 that is not associated with a capacitor, such as capacitance in leads, diodes, resistors, switch 2310 and/or circuit board traces. The stray capacitance within each switch module 2305 may include low capacitance, eg, less than about 1,000 pF, 100 pF, 10 pF, and the like. The stray capacitance between each switch module 2305 may include low capacitance such as, for example, less than about 1,000 pF, 100 pF, 10 pF.

Voltage sharing imperfections can be addressed, for example, with passive snubber circuits (eg, snubber diode 2315, snubber capacitor 2320, and/or freewheeling diode 2325). For example, voltage spikes may occur due to slight differences in the timing at which each switch 2310 is turned on or off, or differences in inductance and capacitance. These spikes can be mitigated by various snubber circuits (eg, snubber diode 2315, snubber capacitor 2320, and/or freewheeling diode 2325).

The snubber circuit may include snubber diode 2315, snubber capacitor 2320, snubber resistor 2316, and/or freewheeling diode 2325, for example. In some embodiments, a snubber circuit may be co-located in parallel with switch 2310 . In some embodiments, snubber capacitor 2320 may have a low capacitance, eg, a capacitance of less than about 100 pF.

In some embodiments, high voltage switch 2300 may be electrically coupled to or include load 2365 (eg, a resistive or capacitive or inductive load). Load 2365 may have a resistance of, for example, 50 ohms to 500 ohms. Alternatively or additionally, load 2365 may be an inductive load or a capacitive load.

In some embodiments, the energy recovery circuit 1610 or the active energy recovery circuit 111 drives a given load with the same energy consumption and/or energy output performance of the high voltage bias generator as a system without the energy recovery circuit. can reduce the voltage required to For example, for the same energy output performance as a system without an energy recovery circuit, the energy consumption is 10%, 15%, 20%, 23%, 30%, 40%, 45%, 50%, etc., or more. can be reduced.

In some embodiments, diode 130, diode 135, and/or energy recovery diode 1620 may include high voltage diodes.

FIG. 24 is a circuit diagram of bias generator 2400 including RF source 2405, active bias compensation circuit 134, and energy recovery circuit 1610, according to some embodiments. In this example, bias generator 2400 is similar to bias generator 900 with RF source 2405 replacing RF driver 605 and resonant circuit 610 . The RF driver 605 shown in FIG. 9 includes a full-wave rectifier and resonant circuit 610 that replaces the RF source 2405 .

In some embodiments, the RF source 2405 may include multiple high frequency solid state switch(es), an RF generator, an amplifier tube-based RF generator, or a tube-based RF generator.

Bias generator 2400 may or may not include a conventional matching network, such as, for example, a 50 ohm matching network, an external matching network, or a standalone matching network. In some embodiments, bias generator 2400 does not require a 50 ohm matching network to optimize switching power applied to the wafer chamber. Conventional RF generators without matching networks can rapidly change the power drawn by the plasma chamber. Typically, optimization of this matching network can take at least 100-200 μs. In some embodiments, the power change may occur within one or two RF cycles, eg, 2.5 μs - 5.0 μs at 400 kHz.

In some embodiments, RF source 2405 may operate at frequencies of approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and the like.

FIG. 25 shows another exemplary bias generator 2500 according to some embodiments. Bias generator 2500 can be generalized to five stages (these stages can be decomposed into other stages or generalized into fewer stages). Bias generator 2500 includes nanosecond pulser stage 101 , resistive output stage 2507 , bias compensation circuit 134 , and load stage 106 .

In this example, load stage 106 may represent the effective circuitry of a plasma deposition system, plasma etch system, or plasma sputtering system. Capacitance C2 may represent the capacitance of the dielectric material on which the wafer may rest. Capacitor C3 may represent the sheath capacitance of the plasma to the wafer. Capacitor C9 may represent the capacitance in the plasma between the walls of the chamber and the top surface of the wafer. Current source I2 and current source I1 may also represent the ion current through the sheath.

In this example, resistive output stage 2507 may include one or more inductive elements represented by inductor L1 and/or inductor L5. Inductor L5 may represent, for example, the stray inductance of the leads in resistive output stage 2507. FIG. Inductor L1 may be set to minimize the power flowing directly from nanosecond pulser stage 101 to resistor R1.

In some embodiments, resistor R1 may, for example, dissipate charge from load stage 2515 on fast timescales (eg, timescales of 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 100 ns, etc.). . The resistance of resistor R1 may be low so that the pulse on load stage 2515 has a fast fall time tf.

In some embodiments, resistor R1 may include multiple resistors arranged in series and/or in parallel. Capacitor C11 may represent the stray capacitance of resistor R1, including the capacitance of resistors in series and/or parallel arrangements. Also, the capacitance of the stray capacitance C11 may be, for example, less than 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, or the like. The capacitance of stray capacitance C11 may be less than the load capacitance, eg, less than the capacitance of C2, C3, and/or C9.

In some embodiments, multiple nanosecond pulser stages 2506 may be ganged up in parallel and coupled with resistive output stage 2507 across inductor L1 and/or resistor R1. Each of the plurality of pulser and transformer stages 906 may also include a diode D1 and/or a diode D6.

In some embodiments, capacitor C8 may represent the stray capacitance of blocking diode D1. In some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

Computing system 2600 shown in FIG. 26 may be used to implement any of the embodiments of the present invention. For example, computing system 2600 can be used to perform process 500 . As another example, computing system 2600 may be used to perform any calculations, identifications and/or determinations described herein. Computing system 2600 includes hardware elements that may be electrically coupled (or may otherwise communicate, as appropriate) via bus 2605 . Hardware elements may include one or more general purpose processors and/or one or more special purpose processors (such as digital signal processing chips, graphics acceleration chips, and/or the like) Processor 2610, one or more input devices 2615, which may include without limitation mice, keyboards and/or the like, and one or more output devices which may include without limitation display devices, printers and/or the like. 2620.

Computing system 2600 may further include (and/or communicate with) one or more storage devices 2625, which may include without limitation local and/or network accessible storage, and/or , disk drives, drive arrays, optical storage devices, random access memory (“RAM”) and/or solid state storage devices such as read only memory (“ROM”), which may be programmable, It may be flash updateable and the like. Computing system 2600 may also include a communications subsystem 2630, which may include modems, network cards (wireless or wired), infrared communications devices, wireless communications devices and/or chipsets (Bluetooth devices, 802.6 devices, Wi-Fi Fi devices, WiMax devices, cellular communication equipment, etc.), and/or the like, without limitation. Communications subsystem 2630 may allow data to be exchanged with a network (such as the networks described below, for example) and/or any other device described in this document. In many embodiments, computing system 2600 will further include working memory 2635, which may include a RAM or ROM device, as described above.

Computing system 2600 may also include software elements shown currently residing in working memory 2635, including other code such as an operating system 2640 and/or one or more application programs 2645, which are described herein. It may include the computer program of the invention and/or may be designed to implement the method of the invention and/or configure the system of the invention as described herein. For example, one or more of the procedures described with respect to the method(s) described above may be implemented as code and/or instructions executable by a computer (and/or a processor within a computer). These instructions and/or sets of code may be stored in a computer-readable storage medium, such as storage device(s) 2625 described above.

In some cases, the storage media may be embedded within or in communication with computing system 2600 . In other embodiments, the storage medium is separate from computing system 2600 (e.g., a compact disk) such that the storage medium can be used to program a general-purpose computer with the instructions/code stored thereon. ), and/or in an installation package. These instructions may take the form of executable code executable by the computing system 2600, and/or may take the form of source code and/or installable code, which may be implemented by the computing system 2600. When compiled and/or installed on the 2600 (eg, using any of a variety of commonly available compilers, installation programs, compression/decompression utilities, etc.), it takes the form of executable code.

Unless otherwise specified, the term "substantially" means within 5% or 10% of the stated value, or within manufacturing tolerances. Unless otherwise specified, "about" means within 5% or 10% of the stated value or within manufacturing tolerances.

The term "or" is inclusive.

In this specification, numerous specific details are set forth in order to provide a full understanding of the claimed subject matter. However, it will be understood by those of ordinary skill in the art that claimed subject matter may be practiced without these specific details. In other instances, methods, devices, or systems that would be known to one of ordinary skill in the art have not been described in detail so as not to obscure claimed subject matter.

Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions and representations are examples of techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent set of operations or similar processes for achieving a desired result. Manipulations and processing in this context encompass physical manipulations of physical quantities. Although not required, such quantities typically take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerical values, or the like. It should be understood, however, that all of these terms and similar terms relate to appropriate physical quantities and are merely convenient labels. Unless otherwise indicated herein, discussion using terms such as "processing", "computing", "calculating", "determining", "identifying", etc., may refer to memory, registers, or other components of the computing platform. One or more computers or similar electronic computing devices or devices that manipulate or transform data represented as physical, electronic or magnetic quantities in an information storage device, transmission device, or display device It should be understood to refer to operations or processes of a computing device.

The systems described herein are not limited to any particular hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide results conditional on one or more inputs. Suitable computing devices are general-purpose microprocessor-based that access stored software to program or configure computing systems from general-purpose computing devices to specialized computing devices that implement one or more embodiments of the present subject matter. computer system. Any suitable programming language, scripting language, or other type of language or combination of languages may be used to implement the material described herein in the software used to program and configure the computer.

Embodiments of the methods disclosed herein may be implemented in operation of such computing devices. The order of the blocks shown in the examples above can be changed, eg, blocks can be permuted, combined, and divided into sub-blocks. Certain blocks or processes may be executed in parallel.

Use of "adapted to" or "configured to" herein does not exclude devices that have been adapted or configured to perform additional tasks or steps. is intended as an umbrella language in Further, use of “based on” means that a process, step, calculation, or other action that is “based on” one or more stated conditions or values is in fact other than the stated conditions or values. It is meant to be open and inclusive in the sense that it may be based on additional terms or values. Headings, lists and numbers provided herein are for ease of description and are not meant to be limiting.

Although the present subject matter has been described in detail with respect to specific embodiments thereof, it is recognized that modifications, variations, and equivalents to such embodiments will readily occur to those skilled in the art, given the foregoing understanding. will be understood. Accordingly, the present disclosure has been presented by way of illustration and not limitation, and is not intended to exclude modifications, variations, and/or additions to the subject matter that would be readily apparent to those skilled in the art. should understand.

100 plasma system 110 plasma chamber 105, 1200, 1300 RF plasma generator 115, 600, 900, 1000, 1100, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2400, 2500 bias generator 120 controller 130 diode 140 Inductor 400 Plasma Control System 410 Voltage Divider 415 Filter 420 First ADC
435 Output 450 Sensor 605, 1305 RF Driver 610 Resonant Circuit 620 Resistive Output Stage 625 Bias Compensation Circuit 630 Chamber 905, 1610 Energy Recovery Circuit 1205 Inductive Discharge Plasma 1610 Energy Recovery Circuit 1615 Energy Recovery Inductor 2205 Capacitive Load 2300 High Voltage Switch 2305 Switch module 2340 power supply 2345 Insulation Fiber Riga 2350 Clover Diode 2355 High -speed capacitors 2360 High -speed capacitors 2360 high -voltage load 2365 Road Road 255 RF Source 2506 Nanoscal Stage 2507 Reflectivity Output Stage 2600 Calculation System 2605 Bus 2625 Storage Device 2625 35 Working Memory 2640 Operating System 2645 Application Program

Although the present subject matter has been described in detail with respect to specific embodiments thereof, it is recognized that modifications, variations, and equivalents to such embodiments will readily occur to those skilled in the art, given the foregoing understanding. will be understood. Accordingly, the present disclosure has been presented by way of illustration and not limitation, and is not intended to exclude modifications, variations, and/or additions to the subject matter that would be readily apparent to those skilled in the art. should understand.
[Appendix 1]
A plasma system,
a plasma chamber;
An RF plasma generator electrically coupled to the plasma chamber for generating a plurality of RF bursts, each of the plurality of RF bursts comprising an RF waveform, each of the plurality of RF bursts having an RF burst turn-on time and an RF burst turn-off time;
A bias generator electrically coupled to the plasma chamber for generating a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst turn-on time and a bias burst turn-on time. a bias generator having a bias burst turn-off time;
a controller in communication with the RF plasma generator and the bias generator to control the timing of the RF burst turn-on time, the RF burst turn-off time, the bias turn-on time, and the bias turn-off time.
[Appendix 2]
Clause 1. The plasma system of Clause 1, wherein the plurality of RF bursts generate and/or drive a plasma within the plasma chamber and the plurality of bias bursts accelerate ions within the plasma.
[Appendix 3]
Clause 1. The plasma system of Clause 1, further comprising an electrode disposed within said plasma chamber, said electrode coupled to said RF plasma generator.
[Appendix 4]
Clause 1. The plasma system of Clause 1, further comprising an inductive antenna disposed within said plasma chamber, said antenna coupled to said RF plasma generator.
[Appendix 5]
Clause 1. The plasma system of Clause 1, further comprising an electrode disposed within said plasma chamber, said electrode coupled to said bias generator.
[Appendix 6]
Clause 1. The plasma system of clause 1, wherein the RF burst turn-on time precedes the bias burst turn-on time by less than about 10 ms.
[Appendix 7]
Clause 1. The plasma system of Clause 1, wherein the bias burst turn-on time occurs approximately 10 cycles of the RF waveform after the RF burst turn-on time.
[Appendix 8]
Clause 1. The plasma system of Clause 1, wherein the bias burst turn-on time precedes the RF burst turn-off time by less than about 10 ms.
[Appendix 9]
Clause 1. The plasma system of Clause 1, wherein the difference between the RF burst turn-on time and the RF burst turn-off time is less than about 1 ms.
[Appendix 10]
Clause 1. The plasma system of Clause 1, wherein a difference between the bias burst turn-on time and the bias burst turn-off time is less than about 10 ms.
[Appendix 11]
Clause 1. The plasma system of Clause 1, wherein the bias pulse has a pulse repetition frequency greater than 1 kHz.
[Appendix 12]
Clause 1. The plasma system of Clause 1, wherein the bias pulse has a voltage greater than 1 kilovolt.
[Appendix 13]
Clause 1. The plasma system of Clause 1, wherein the RF waveform has a frequency between 10 kHz and 100 MHz.
[Appendix 14]
Clause 1. The plasma system of Clause 1, wherein the RF waveform has a frequency of 13.56 MHz.
[Appendix 15]
Clause 1. The plasma system of Clause 1, wherein the controller controls the timing of the RF burst turn-on time, the RF burst turn-off time, the bias turn-on time, and the bias turn-off time based on feedback from the plasma chamber.
[Appendix 16]
Clause 1. The plasma system of Clause 1, wherein the bias generator includes a bias compensation circuit.
[Appendix 17]
Clause 1. The plasma system of Clause 1, wherein the bias generator includes an energy recovery circuit.
[Appendix 18]
Clause 1. The plasma system of Clause 1, wherein the RF plasma generator comprises either a full bridge circuit or a half bridge circuit and a resonant circuit.
[Appendix 19]
Clause 1. The plasma system of Clause 1, wherein the bias generator comprises a nanosecond pulser.
[Appendix 20]
Clause 1. The plasma system of Clause 1, wherein the bias generator comprises an RF generator.
[Appendix 21]
a method,
driving the plasma chamber with an RF plasma generator at a frequency of 10 MHz or higher;
resting for a first period of time;
pulsing the plasma chamber with a bias generator with pulses having a first voltage at a pulse frequency greater than 1 kHz;
resting for a second period of time;
deactivating the RF plasma generator;
resting for a third period of time;
stopping pulsing of the bias generator;
method including.
[Appendix 22]
further resting for a fourth period of time;
driving the RF plasma generator;
resting for the first period of time;
pulsing the bias generator with a pulse having a second voltage;
resting for the second period of time;
deactivating the RF plasma generator;
resting for the third period of time;
stopping pulsing of the bias generator;
22. The method of clause 21, comprising:
[Appendix 23]
23. The method of clause 22, wherein the second voltage is greater than the first voltage.
[Appendix 24]
Furthermore,
resting for a fourth period;
driving the RF plasma generator;
resting for a fifth period of time different from the first period of time;
pulsing the bias generator with a pulse having a second voltage;
resting for a sixth period of time different from the first period of time;
deactivating the RF plasma generator;
resting for a seventh period different from the first period;
stopping pulsing of the bias generator;
22. The method of clause 21, comprising:
[Appendix 25]
the first period of time is less than about 10 ms;
the second period of time is less than about 10 ms;
the third period of time is less than about 10 ms;
21. The method of Appendix 21.
[Appendix 26]
22. The method of clause 21, wherein the first period of time is shorter than the second period of time.

Claims (26)

A plasma system,
a plasma chamber;
An RF plasma generator electrically coupled to the plasma chamber for generating a plurality of RF bursts, each of the plurality of RF bursts comprising an RF waveform, each of the plurality of RF bursts having an RF burst turn-on time and an RF burst turn-off time;
A bias generator electrically coupled to the plasma chamber for generating a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst turn-on time and a bias burst turn-on time. a bias generator having a bias burst turn-off time;
a controller in communication with the RF plasma generator and the bias generator to control the timing of the RF burst turn-on time, the RF burst turn-off time, the bias turn-on time, and the bias turn-off time. 2. The plasma system of claim 1, wherein said plurality of RF bursts generate and/or drive a plasma within said plasma chamber and said plurality of bias bursts accelerate ions within said plasma. 2. The plasma system of claim 1, further comprising an electrode positioned within said plasma chamber, said electrode coupled to said RF plasma generator. 2. The plasma system of claim 1, further comprising an inductive antenna positioned within said plasma chamber, said antenna coupled to said RF plasma generator. 2. The plasma system of claim 1, further comprising an electrode positioned within said plasma chamber, said electrode coupled to said bias generator. 2. The plasma system of claim 1, wherein said RF burst turn-on time precedes said bias burst turn-on time by less than about 10 ms. 2. The plasma system of claim 1, wherein the bias burst turn-on time occurs approximately 10 cycles of the RF waveform after the RF burst turn-on time. 2. The plasma system of claim 1, wherein said bias burst turn-on time precedes said RF burst turn-off time by less than about 10 ms. 2. The plasma system of claim 1, wherein the difference between said RF burst turn-on time and said RF burst turn-off time is less than about 1 ms. 2. The plasma system of claim 1, wherein a difference between said bias burst turn-on time and said bias burst turn-off time is less than about 10 ms. 2. The plasma system of claim 1, wherein said bias pulses have a pulse repetition frequency greater than 1 kHz. 3. The plasma system of claim 1, wherein said bias pulse has a voltage greater than 1 kilovolt. 2. The plasma system of claim 1, wherein said RF waveform has a frequency between 10 kHz and 100 MHz. 2. The plasma system of claim 1, wherein said RF waveform has a frequency of 13.56 MHz. 2. The plasma system of claim 1, wherein the controller controls timing of the RF burst turn-on time, the RF burst turn-off time, the bias turn-on time, and the bias turn-off time based on feedback from the plasma chamber. . 2. The plasma system of claim 1, wherein said bias generator includes bias compensation circuitry. 2. The plasma system of claim 1, wherein said bias generator includes an energy recovery circuit. 2. The plasma system of claim 1, wherein the RF plasma generator comprises either a full-bridge circuit or a half-bridge circuit and a resonant circuit. 2. The plasma system of claim 1, wherein said bias generator comprises a nanosecond pulser. 2. The plasma system of claim 1, wherein said bias generator comprises an RF generator. a method,
driving the plasma chamber with an RF plasma generator at a frequency of 10 MHz or higher;
resting for a first period of time;
pulsing the plasma chamber with a bias generator with pulses having a first voltage at a pulse frequency greater than 1 kHz;
resting for a second period of time;
deactivating the RF plasma generator;
resting for a third period of time;
stopping pulsing of the bias generator;
method including. further resting for a fourth period of time;
driving the RF plasma generator;
resting for the first period of time;
pulsing the bias generator with a pulse having a second voltage;
resting for the second period of time;
deactivating the RF plasma generator;
resting for the third period of time;
stopping pulsing of the bias generator;
22. The method of claim 21, comprising: 23. The method of claim 22, wherein said second voltage is greater than said first voltage. Furthermore,
resting for a fourth period;
driving the RF plasma generator;
resting for a fifth period of time different from the first period of time;
pulsing the bias generator with a pulse having a second voltage;
resting for a sixth period of time different from the first period of time;
deactivating the RF plasma generator;
resting for a seventh period different from the first period;
stopping pulsing of the bias generator;
22. The method of claim 21, comprising: the first period of time is less than about 10 ms;
the second period of time is less than about 10 ms;
the third period of time is less than about 10 ms;
22. The method of claim 21. 22. The method of claim 21, wherein said first period of time is shorter than said second period of time.

Images