JP2023090896A - memory system - Google Patents

Abstract

To provide a memory system capable of simultaneously using a plurality of write destination blocks.SOLUTION: A controller of a memory system acquires first data from a memory of a host in which the first data is stored according to reception of a write command specifying at least position on a memory of the host. The controller reacquires the first data from the memory of the host according to reception of a read command requesting reading of the first data from the host after acquiring the first data from the memory of the host, and returns the reacquired first data to the host.SELECTED DRAWING: Figure 6

Description

Embodiments of the present invention relate to techniques for controlling non-volatile memory.

In recent years, memory systems with nonvolatile memories have become widespread. As one of such memory systems, a solid state drive (SSD) based on NAND flash technology is known.
SSDs are also used as storage devices in servers in data centers.

High I/O performance is required for storage devices used in host computer systems such as servers.
For this reason, recently, new interfaces between hosts and storage devices have begun to be proposed.
Also, modern storage devices may be required to allow different types of data to be written to different destination blocks.

Yiying Zhang, et al., "De-indirection for flash-based SSDs with nameless writes." FAST. 2012, [online], [searched on September 13, 2017], Internet<URL: https://www.usenix. org/system/files/conference/fast12/zhang.pdf >

Therefore, it is required to realize a new technique for making multiple write destination blocks available at the same time.
A problem to be solved by the present invention is to provide a memory system that can simultaneously use a plurality of write destination blocks.

According to an embodiment, a memory system connectable to a host includes a non-volatile memory and a controller electrically connected to the non-volatile memory. The controller acquires the first data from the memory of the host in response to receiving from the host a write command specifying at least a location on the memory of the host where the first data is stored. . The controller transfers the first data to the host in response to receiving from the host a read command requesting reading of the first data after obtaining the first data from the memory of the host. Reacquire from the memory and return the reacquired first data to the host.

3 is a block diagram showing the relationship between a host and a memory system (flash storage device) according to the embodiment; FIG. FIG. 2 is a block diagram showing a configuration example of the memory system of the same embodiment; FIG. 2 is a block diagram showing the relationship between a plurality of channels and a plurality of NAND flash memory chips used in the memory system of the same embodiment; FIG. 2 is a diagram showing a configuration example of a certain super block used in the memory system of the same embodiment; FIG. 2 is a block diagram showing the relationship between a write data buffer and a flash translation unit included in a host and a write control unit, DMAC, and internal buffers included in the memory system of the same embodiment; 4 is a block diagram for explaining I/O command processing executed by the memory system of the embodiment; FIG. FIG. 4 is a diagram for explaining a multistage write operation performed by the memory system of the embodiment; 4 is a diagram for explaining the order in which data is written to a certain write destination block in the memory system of the embodiment; FIG. FIG. 4 is a diagram for explaining the operation of transferring write data from the host to the memory system of the embodiment in units of the same size as data write units of the nonvolatile memory; 4 is a flowchart showing the procedure of data write processing executed by the memory system of the same embodiment; 4 is a flowchart showing the procedure of write data discard processing executed by the host; FIG. 7 is a diagram for explaining dummy data write processing performed by the memory system of the embodiment when the next write command is not received within a threshold period after the last write command is received; 4 is a flowchart showing the procedure of dummy data write processing executed by the memory system of the embodiment; 4 is a block diagram showing data transfer operations performed by the memory system of the embodiment using internal buffers; FIG. FIG. 4 is a diagram for explaining a write process executed by the memory system of the embodiment using an internal buffer and a process of discarding write data in the internal buffer; FIG. 4 is a diagram for explaining processing for discarding write data in the internal buffer, which is executed by the memory system of the embodiment when the internal buffer has no free space; 4 is a flowchart showing the procedure of data write processing executed by the memory system of the embodiment using an internal buffer; 4 is a flowchart showing the procedure of data read processing executed by the memory system of the embodiment; FIG. 4 is a diagram for explaining data write processing in which a host designates a write destination block and the memory system of the same embodiment determines a write destination page, and data read processing in which the host designates a block address and a page address; FIG. 4 is a diagram for explaining a block allocate command (block allocation request) applied to the memory system of the embodiment; FIG. 4 is a diagram for explaining a response to a block allocate command; FIG. FIG. 4 is a diagram for explaining write commands applied to the memory system of the embodiment; FIG. 4 is a diagram for explaining a response indicating command completion of a write command; FIG. 4 is a diagram for explaining a read command applied to the memory system of the same embodiment;

Embodiments will be described below with reference to the drawings.
First, referring to FIG. 1, the relationship between the memory system and the host according to this embodiment will be described.
The memory system is a semiconductor storage device configured to write data to and read data from non-volatile memory. This memory system is implemented as a flash storage device 3 based on NAND flash technology.

A host (host device) 2 is configured to control a plurality of flash storage devices 3 . The host 2 is realized by an information processing device configured to use a flash array composed of a plurality of flash storage devices 3 as storage. This information processing apparatus may be a personal computer or a server computer.

Note that the flash storage device 3 may be used as one of a plurality of storage devices provided within the storage array. A storage array may be connected to an information processing device, such as a server computer, via a cable or network. The storage array includes a controller that controls multiple storages (eg, multiple flash storage devices 3) within the storage array. When the flash storage device 3 is applied to a storage array, the controller of this storage array may serve as the host for the flash storage device 3 .

A case where an information processing apparatus such as a server computer functions as the host 2 will be described below as an example.
A host (server) 2 and multiple flash storage devices 3 are interconnected via an interface 50 (internal interconnect). The interface 50 for this interconnection may be, but is not limited to, PCI Express (PCIe) (registered trademark), NVM Express (NVMe) (registered trademark), Ethernet (registered trademark), NVMe over Fabrics (NVMeOF), etc. can be used.

A typical example of a server computer functioning as the host 2 is a server computer (hereinafter referred to as a server) in a data center.
In the case where the host 2 is implemented by a server in a data center, this host (server) 2 may be connected to multiple end-user terminals (clients) 61 via a network 60 . The host 2 can provide various services to these end user terminals 61 .

Examples of services that can be provided by the host (server) 2 include (1) a platform as a service (PaaS) that provides a system operating platform to each client (each end-user terminal 61), (2) a virtual server and infrastructure as a service (IaaS) that provides each client (each end-user terminal 61) with such an infrastructure.

A plurality of virtual machines may run on the physical server that functions as this host (server) 2 . Each of these virtual machines running on the host (server) 2 can function as a virtual server configured to provide various services to the client (end-user terminal 61) corresponding to this virtual machine. Each virtual machine runs an operating system and user applications used by the corresponding end-user terminal 61 . An operating system corresponding to each virtual machine includes I/O services. The I/O service may be a logical block address (LBA) based block I/O service or a key-value store service. The I/O service may include an address translation table that manages the mapping between each tag for identifying data to be accessed and each physical address of the flash storage device 3 . A tag can be a logical address, such as an LBA, or a key in a key-value store.

In the operating system corresponding to each virtual machine, the I/O service issues I/O commands (write command, read command) in response to write/read requests from user applications. These I/O commands are sent to the flash storage device 3 via the command queue.

The flash storage device 3 includes non-volatile memory such as NAND flash memory. The flash storage device 3 manages multiple write destination blocks allocated from multiple blocks in the nonvolatile memory. A write destination block means a block to which data is to be written. A write command sent from the host 2 to the flash storage device 3 includes a location on the memory of the host 2 where the write data to be written exists, the length of this write data, and an identifier indicating the block to which this write data is to be written. Specify Therefore, the host 2 can specify a particular destination block to which data is to be written. As a result, for example, the host 2 writes data of a user application corresponding to a certain end-user terminal 61 (client) to one or more specific write destination blocks, and writes data to a user corresponding to another end-user terminal 61 (client). It is possible to implement a data arrangement in which application data is written to another one or more specific write destination blocks.

An identifier indicating a block to which write data is to be written may be represented by a block address (block number) that designates a specific write destination block. In the case where the flash storage device 3 includes multiple NAND flash memory chips, this block address may be represented by a combination of block address and chip number.

In the case where the flash storage device 3 supports stream writing, the identifier indicating the block to which the write data should be written may be the identifier of one stream (stream ID) among multiple streams. In stream writing, multiple write destination blocks are associated with multiple streams, respectively. In other words, when the flash storage device 3 receives a write command containing a certain stream ID from the host 2, this flash storage device 3 writes data to the write destination block associated with the stream corresponding to this stream ID. When the flash storage device 3 receives a write command containing another stream ID from the host 2, this flash storage device 3 writes data to another write destination block associated with another stream corresponding to this another stream ID. write. The flash storage device 3 may use a management table for managing the mapping between each stream ID and each block address.

The flash storage device 3 can be implemented as any of the following type #1-storage device, type #2-storage device, type #3-storage device.
Type #1—storage device is a type of storage device in which the host 2 specifies both the block to which data is to be written and the page address to which this data is to be written. Type #1—A write command applied to a storage device contains block address, page address, data pointer, length. The block address specifies a block to which write data received from the host 2 should be written. The page address specifies the page within this block where this write data is to be written. The data pointer indicates the memory location within the host 2 where this write data exists. Length indicates the length of this write data.

Type #2—Storage device is a type of storage device where the host 2 specifies the block to which data is to be written and the storage device specifies the location (page) within this block where this data is to be written. Type #2—A write command applied to a storage device includes a tag (eg, LBA, key) to identify the write data to be written, block address, data pointer, length. Additionally, the write command may include a QoS domain ID. The QoS domain ID designates one of multiple areas obtained by logically dividing the NAND flash memory. Each of the multiple regions includes multiple blocks. Type #2—The storage device can consider bad pages, page write order constraints, and determine the pages to which data should be written.

That is, in the case where the flash storage device 3 is implemented as a type #2-storage device, the flash storage device 3 hides page write order constraints, bad pages, page size, etc. while allowing the host 2 to handle the blocks. can do. As a result, the host 2 can recognize block boundaries and manage which user data exists in which block without being aware of page write order restrictions, bad pages, and page sizes.

Type #3—A storage device is a type of storage device in which the host 2 specifies a tag (eg, LBA) that identifies the data, and the storage device determines both the block and page to which this data should be written. Type #3—A write command applied to a storage device includes a tag (eg, LBA, key) to identify the write data to be written, stream ID, data pointer, length. A stream ID is an identifier of a stream associated with this write data. In the case where the flash storage device 3 is implemented as a type #2-storage device, the flash storage device 3 refers to a management table that manages the mapping between each stream ID and each block address to perform this write. Determine the block to which the data should be written. Furthermore, the flash storage device 3 uses an address translation table called a logical-physical address translation table to manage the mapping between each tag (LBA) and each physical address of the NAND flash memory.

The flash storage device 3 may be either a type #1-storage device, a type #2-storage device, or a type #3-storage device, but the flash storage device 3 includes multiple storage devices included in a NAND flash memory. A plurality of write destination blocks allocated from blocks are managed, and write data associated with a certain write command is written to the write destination block specified by this write command.

For Type #1—storage devices, the page write order within the destination block is specified by the host 2 . Therefore, in the case where the flash storage device 3 is implemented as a type #1-storage device, the flash storage device 3 writes destination blocks in an order corresponding to the page addresses specified by each write command from the host 2. Write data to each page in the

In Type #2—storage devices, the destination block is specified by the block address included in the write command from the host 2, but the destination page within this destination block is determined by the flash storage device 3. Therefore, in the case where the flash storage device 3 is implemented as a type #2-storage device, the flash storage device 3 reads from the first page to the last page of the write destination block specified by the block address included in the write command. The write destination page is determined so that the data is written in the order of

For Type #3—Storage Device, the flash storage device 3 selects the block associated with the stream ID included in the write command as the destination block and determines the destination page within this destination block. Therefore, in the case where the flash storage device 3 is implemented as a type #3-storage device, the flash storage device 3 is configured such that data is written in order from the first page to the last page of this write destination block, for example. determines the write destination page.

A plurality of write destination blocks managed by the flash storage device 3 can be used by a plurality of end users (clients) sharing this flash storage device 3, respectively. In this case, in the flash storage device 3, the same number of write destination blocks as the number of end users sharing the flash storage device 3 or more are opened at the same time.

FIG. 2 shows a configuration example of the flash storage device 3 .
The flash storage device 3 has a controller 4 and a nonvolatile memory (NAND type flash memory) 5 . Flash storage device 3 may also comprise random access memory, eg DRAM 6 .

The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

A memory cell array of the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 includes a plurality of pages (pages P0 to Pn-1 here). Blocks BLK0 to BLKm-1 function as erase units. Blocks may also be referred to as "erase blocks," "physical blocks," or "physical erase blocks." Pages P0 to Pn-1 are units for data write operations and data read operations.

The controller 4 is electrically connected to a NAND flash memory 5, which is a non-volatile memory, via a NAND interface 13 such as a Toggle NAND flash interface or an open NAND flash interface (ONFI). Controller 4 operates as a memory controller configured to control NAND flash memory 5 . This controller 4 may be implemented by a circuit such as a System-on-a-chip (SoC).

The NAND flash memory 5 may include a plurality of NAND flash memory chips (NAND flash memory dies), as shown in FIG. Individual NAND flash memory chips can operate independently. Therefore, the NAND flash memory chip functions as a unit capable of parallel operation. 3, the NAND interface 13 has 16 channels Ch. 1 to Ch. 16 are connected, and 16 channels Ch. 1 to Ch. 16 are connected to two NAND flash memory chips. In this case, channel Ch. 1 to Ch. 16 NAND flash memory chips #1 to #16 connected to channel Ch.16 may be organized as bank #0, and channel Ch. 1 to Ch. The remaining 16 NAND flash memory chips #17-#32 connected to 16 may be organized as bank #1. A bank functions as a unit for operating a plurality of memory modules in parallel by bank interleaving. In the configuration example of FIG. 3, a maximum of 32 NAND flash memory chips can be operated in parallel by 16 channels and bank interleaving using two banks.

The erase operation may be performed in units of one block (physical block), or may be performed in units of parallel units (super blocks) including a set of a plurality of physical blocks capable of parallel operation. One parallel unit, that is, one super block including a set of multiple physical blocks includes, but is not limited to, a total of 32 physical blocks selected one by one from NAND flash memory chips #1 to #32. may contain. Each of the NAND flash memory chips #1 to #32 may have a multiplane configuration. For example, when each of the NAND flash memory chips #1 to #32 has a multiplane configuration including two planes, one super block is 64 superblocks corresponding to the NAND flash memory chips #1 to #32. It may contain a total of 64 physical blocks selected one by one from the planes.

FIG. 4 shows 32 physical blocks (here, physical block BLK2 in NAND flash memory chip #1, physical block BLK3 in NAND flash memory chip #2, physical block BLK3 in NAND flash memory chip #3). One super block including block BLK7, physical block BLK4 in NAND flash memory chip #4, physical block BLK6 in NAND flash memory chip #5, . . . , physical block BLK3 in NAND flash memory chip #32. (SB) is exemplified.

The write destination block may be one physical block or one superblock. A configuration in which one superblock includes only one physical block may be used, in which case one superblock is equivalent to one physical block.

Next, the configuration of the controller 4 shown in FIG. 2 will be described.
The controller 4 includes a host interface 11, a CPU 12, a NAND interface 13, a DRAM interface 14, a direct memory access controller (DMAC) 15, an ECC encode/decode unit 16 and the like. These host interface 11 , CPU 12 , NAND interface 13 , DRAM interface 14 , DMAC 15 and ECC encoding/decoding unit 16 are interconnected via bus 10 .

The host interface 11 is a host interface circuit configured to communicate with the host 2 . This host interface 11 may be, for example, a PCIe controller (NVMe controller). Alternatively, in configurations where the flash storage device 3 is connected to the host 2 via Ethernet (registered trademark), the host interface 11 may be an NVMe over Fabrics (NVMeOF) controller.

Host interface 11 receives various commands from host 2 . These commands include write commands, read commands, and various other commands.
The CPU 12 is a processor configured to control the host interface 11 , NAND interface 13 and DRAM interface 14 . The CPU 12 loads a control program (firmware) from the NAND flash memory 5 or a ROM (not shown) into the DRAM 6 in response to power-on of the flash storage device 3, and executes various processes by executing this firmware. Note that the firmware may be loaded onto an SRAM (not shown) within the controller 4 . This CPU 12 can execute command processing and the like for processing various commands from the host 2 . The operation of CPU 12 is controlled by the aforementioned firmware executed by CPU 12 . Part or all of the command processing may be executed by dedicated hardware within the controller 4 .

The CPU 12 can function as a write controller 21 and a read controller 22 . Part or all of the write control unit 21 and the read control unit 22 may also be implemented by dedicated hardware within the controller 4 .
The write control unit 21 manages multiple write destination blocks allocated from multiple blocks of the NAND flash memory 5 . Many modern NAND flash memories often perform complex write operations to reduce program disturb. Therefore, in many modern NAND flash memories, even if data is written to a certain page in a block, the data written to this page cannot be read normally immediately after the writing. After data has been written to one or more pages following this page, it may be possible to read data from this page.

In addition, in modern NAND flash memories, there are cases where a multi-step write operation is applied, which involves transferring the same write data to the NAND flash memory multiple times. One example of such a multi-step write operation is a foggy-fine write operation.

A multi-phase write operation includes at least a first phase write operation, such as a foggy write operation, and a second phase write operation, such as a fine write operation. The foggy write operation is a write operation that roughly sets the threshold distribution of each memory cell, and the fine write operation is a write operation that adjusts the threshold distribution of each memory cell. Additionally, intermediate write operations may be performed between the foggy write operation and the fine write operation.

The write control unit 21 writes the write data to the write destination block by a write operation (multi-step write operation) that involves transferring the same write data to the NAND flash memory 5 multiple times, such as the foggy fine write operation. Alternatively, the write data may be written to the destination block by a write operation that involves transferring the write data to the NAND flash memory 5 once, such as a full sequence write operation or various other types of write operations. good.

The write control unit 21 receives each write command from the host 2 . Each of these write commands specifies the location on the memory of the host 2 where the write data to be written exists, the length of the write data, and an identifier indicating the block to which the write data is to be written.

The length of write data differs for each individual write command. For example, one write command may request writing of large size write data, such as 1 Mbyte, while another write command may request writing of small size write data, such as 4K bytes. For this reason, if the flash storage device 3 were to simply transfer the write data of the size specified by each write command from the host 2 to the internal buffer of the flash storage device 3, a particular The internal buffer may be occupied for a long time by large write data to be written to the destination block, and data write operations to other destination blocks may not be performed. As a result, it becomes difficult to use multiple write destination blocks at the same time.

Therefore, the write control unit 21 acquires write data from the host 2 in the same data size unit as the data write unit of the NAND flash memory 5 regardless of the size specified by each write command. A data write unit of the NAND flash memory 5 means a data transfer size for writing data to the NAND flash memory 5 . A typical example of the data write unit of the NAND flash memory 5 is the page size (eg, 16 Kbytes). Alternatively, a data size corresponding to multiple pages (several times the page size) may be used as the data write unit.

When the size of the write data associated with the write command specifying a certain write destination block is smaller than the data write unit of the NAND flash memory 5, the write control unit 21 executes the next write command specifying this write destination block. wait for command. When the total size of some write data associated with some write commands specifying this write destination block is greater than or equal to the data write unit of the NAND flash memory 5, the write control unit 21 combines these write data. Data of the same size as the data write unit of the NAND flash memory 5 obtained by the above is obtained from the host 2 . For example, in a case where four write commands specifying the same write destination block each request writing of four pieces of 4K-byte write data, the write control unit 21 combines these four pieces of 4K-byte write data to obtain 16 Kbytes of write data may be obtained from the host 2 . In this case, the write control unit 21 may sequentially acquire these four pieces of 4K-byte write data from the host 2 through four DMA transfers. Then, the write control unit 21 transfers the acquired write data having the same size as the data write unit of the NAND flash memory 5 to the NAND flash memory 5, and transfers this write data to the NAND flash memory 5. Write to the destination block.

On the other hand, when the size of the write data associated with the write command specifying a certain write destination block is larger than the data write unit of the NAND flash memory 5, the write control unit 21 divides this write data into a plurality of write data. One or more pieces of write data having the same size as the data write unit obtained by dividing into (a plurality of data portions) are obtained. Then, the write control unit 21 acquires from the host 2 the obtained write data having the same size as the data write unit. In this case, the write control unit 21 may acquire the write data obtained by one DMA transfer from the host 2 . Then, the write control unit 21 transfers the acquired write data having the same size as the data write unit of the NAND flash memory 5 to the NAND flash memory 5, and transfers this write data to the NAND flash memory 5. Write to the destination block.

In this way, after receiving one or more write commands having an identifier indicating the same write destination block, the write control unit 21 converts the write data associated with one write command in the received write commands into a plurality of write commands. A data write unit of the NAND flash memory 5 obtained by dividing the write data into write data (a plurality of data portions) or combining the write data respectively associated with two or more write commands in the received write command; Write data having the same size is obtained from the host 2 .

Here, dividing/combining write data means that one or more write commands having an identifier indicating the same write destination block are divided based on the data pointers and lengths respectively specified by these write commands. It means an operation of separating a set of write data associated with from the head by boundaries having the same size as the data write unit of the NAND flash memory 5, and specifying positions in the host memory corresponding to each boundary.

Therefore, regardless of the write data size specified by each write command, the write data can be obtained from the host 2 in the same data size unit as the data write unit of the NAND flash memory 5. can be transferred to the NAND flash memory 5 immediately. Therefore, even if a write command requesting writing of large-sized write data to a certain write destination block is received, it is possible to prevent delays in data write operations to other write destination blocks.

In addition, it is possible to apply a bufferless configuration to the flash storage device 3 in which no internal buffer exists in the flash storage device 3 or the capacity of the internal buffer is close to zero.
Note that when a plurality of write destination blocks belong to different NAND flash memory chips, the operation of transferring the write data to the NAND flash memory 5 is performed by transferring the write data to the NAND flash memory including the write destination block to which the write data is to be written. means to transfer this write data to the type flash memory chip.

The above-described process of acquiring write data from the host 2 in units of the same data size as the data write unit of the NAND flash memory 5 is executed in accordance with the progress of the write operation for each write destination block.
That is, the write control unit 21 manages the progress of the write operation for each write destination block. Then, for example, each time data transfer to the next write destination page of a certain write destination block becomes possible, the write control unit 21 advances the position of the write destination page in this write destination block, and transfers the data to the next write destination page. The write data to be written to is acquired from the host memory, and the acquired write data is written to the write destination block.

Furthermore, the write control unit 21 performs a write operation (a write operation of transferring the same data to the NAND flash memory 5 once or multiple times) associated with one write command specifying a certain write destination block. When everything is completed, a response indicating command completion of this write command is returned to the host 2 .

For example, when large-sized write data associated with one write command is divided into a plurality of write data portions, all data transfer and all data required for writing all of these plurality of write data portions When the write operation is completed, a response indicating command completion of this write command is returned to the host 2 . As a result, command completion can be correctly notified to the host 2 in units of write commands. Therefore, even if large-sized write data requested to be written by one write command is divided into a plurality of write data portions and processed, the host 2 indicates command completion of this one write command. Only one response can be correctly received from the flash storage device 3. Therefore, the host 2 only needs to perform a simple process of discarding from the host memory the write data corresponding to the write command for which command completion has been notified.

The write control unit 21 also performs a write operation for all write data associated with one write command that specifies a certain write destination block (a write operation involving transferring the same data to the NAND flash memory 5 once or multiple times). operation) is completed and the entire write data can be read from the NAND flash memory 5, a response indicating command completion of this write command is returned to the host 2. FIG.

For example, assume that data written to a page in a write destination block becomes readable after the data is written to one or more subsequent pages. In this case, the write control unit 21 performs all data transfers and all writes necessary for writing all of the plurality of write data portions obtained by dividing the large size write data associated with one write command. When the operation is finished, it does not return a command completion response to the host 2 . Then, after data is written to one or more succeeding pages, the write control unit 21 returns a response indicating command completion of this write command to the host 2 .

As a result, the host 2 performs a simple process of discarding the write data corresponding to the write command for which command completion has been notified from the host memory. can be maintained in host memory.

The read control unit 22 receives a read command from the host 2 and reads data specified by the received read command from the NAND flash memory 5 or the internal buffer 31 .
The data (first data) specified by the read command is data for which all write operations (write operations involving transferring the same data to the NAND flash memory 5 once or multiple times) have not been completed, or If the data has not yet become readable from the NAND flash memory 5 even though all of the write operations have been completed, the read control unit 22 determines whether or not this first data exists in the internal buffer 31 . judge. If the first data does not exist in the internal buffer 31, the read control unit 22 acquires the first data from the host memory, stores the acquired first data in the internal buffer 31, and stores the acquired first data in the internal buffer 31. 1 data is returned from the internal buffer 31 to the host 2 . As a result, the host 2 can issue a read command designating the data to be read from the flash storage without performing complicated processing for managing whether the data to be read is in a readable state from the NAND flash memory 5. Data to be read can be received from the flash storage device 3 simply by performing a simple process of sending the data to the device 3 .

The NAND interface 13 is a memory control circuit configured to control the NAND flash memory 5 under control of the CPU 12 .
DRAM interface 14 is a DRAM control circuit configured to control DRAM 6 under the control of CPU 12 . A part of the storage area of the DRAM 6 may be used as an internal buffer (shared cache) 31 . This internal buffer (shared cache) 31 is shared by multiple write destination blocks and is used to temporarily store write data associated with any write command received from the host 2 . As described above, the flash storage device 3 has a bufferless configuration in which the internal buffer (shared cache) 31 does not exist in the flash storage device 3 or the capacity of the internal buffer (shared cache) 31 is almost zero. may be applied.

Also, another part of the memory area of the DRAM 6 may be used for storing the block management table 32 and the defect information management table 33 . The block management table 32 includes multiple management tables corresponding to multiple blocks in the NAND flash memory 5 . Each management table includes a plurality of valid/invalid management information corresponding to a plurality of data included in blocks corresponding to this management table. Each valid/invalid management information indicates whether the data corresponding to this valid/invalid management information is valid data or invalid data. The defect information management table 33 manages a list of defect blocks.

These internal buffer (shared cache) 31 , block management table 32 and defect information management table 33 may be stored in an SRAM (not shown) within the controller 4 .
DMAC 15 performs data transfers between host memory and internal buffers (shared cache) 31 under the control of CPU 12 . When write data is to be transferred from the host memory to the internal buffer (shared cache) 31, the CPU 12 indicates the transfer source address indicating the position on the host memory, the data size, and the position on the internal buffer (shared cache) 31. A transfer destination address is specified for the DMAC 15 .

When data is to be written to the NAND flash memory 5, the ECC encoder/decoder 16 encodes the data (data to be written) to add an error correction code (ECC) to the data as a redundant code. do. When data is read from the NAND flash memory 5, the ECC encoder/decoder 16 uses the ECC added to the read data to correct errors in the data (ECC decode).

FIG. 5 shows the relationship between the write data buffer 51 and flash translation unit 52 included in the host 2 and the write control unit 21, DMAC 15 and internal buffer (shared cache) 31 included in the flash storage device 3. FIG.
The host 2 stores write data in the write data buffer 51 on the host memory and issues a write command to the flash storage device 3 . This write command consists of a data pointer indicating the position on the write data buffer 51 where this write data exists, a tag (for example, LBA) identifying this write data, the length of this write data, and the write data to be written. Identifiers (block addresses or stream IDs) indicating blocks may be included.

In the flash storage device 3, under the control of the write control unit 21, data is transferred from the write data buffer 51 to the internal buffer (shared cache) 31 in accordance with the progress of the write operation of the write destination block specified by the block identifier. Data transfer is performed by DMAC 15 . This data transfer is executed in the same data size unit as the data write unit of the NAND flash memory 5, as described above. Under the control of the write control unit 21, the write data to be written is transferred from the internal buffer (shared cache) 31 to the NAND flash memory chip containing the write destination block, and the write control unit 21 transfers the write data to the NAND flash memory chip. A NAND command for a write instruction is sent to the memory chip.

If the flash storage device 3 is implemented as a type #2-storage device, the write control unit 21 responds to a block allocation request received from the host 2 and selects one of the free blocks as the write destination block. It also executes processing for assigning to host 2 . A block allocation request may include a QoS domain ID. The write control unit 21 determines one of the free blocks belonging to this QoS domain ID as a write destination block, and notifies the host 2 of the block address of this write destination block. This allows the host 2 to issue a write command specifying this block address, data pointer, tag (for example, LBA), and length. After the write data is written to the write destination block, the write control unit 21 generates a block address indicating the write destination block to which the write data is written and the page in the write destination block to which the write data is written. and the tag (for example, LBA) of this write data to the host 2 . The flash translation unit 52 of the host 2 creates an LUT 404A, which is an address translation table for managing mapping between each tag (for example, LBA) and each physical address (block address, page address, etc.) of the NAND flash memory 5. include. When the block address, page address, and tag (for example, LBA) are notified from the flash storage device 3, the flash translation unit 52 updates the LUT 404A and assigns the notified tag (for example, LBA) to the notified physical address. Map (block address, page address). By referring to the LUT 404A, the flash translation unit 52 can translate the tag (for example, LBA) included in the read request into a physical address (block address, page address), thereby converting the read command including the physical address. It can be issued to the flash storage device 3.

FIG. 6 shows I/O command processing performed by the flash storage device 3 .
As described above, in this embodiment, the flash storage device 3 may be any of type #1-storage device, type #2-storage device, and type #3-storage device, but in FIG. An example is given where device 3 is a type #1-storage device.

Each write command issued by the host 2 contains block address, page address, data pointer and length. Each issued write command is placed in the I/O command queue 42 . Each read command issued by the host 2 also contains a block address, page address, data pointer and length. Each issued read command is also entered into the I/O command queue 42 .

When the host 2 wishes to request the flash storage device 3 to write write data, the host 2 first stores this write data in the write data buffer 51 on the host memory, and then sends a write command to the flash storage device. 3 issued. This write command consists of a block address indicating a write destination block to which this write data is to be written, a page address indicating a page within this write destination block to which this write data is to be written, and a write data buffer where this write data resides. 51 and the length of this write data.

Flash storage device 3 includes program/read sequencer 41 . The program/read sequencer 41 is realized by the write control section 21 and the read control section 22 described above. The program/read sequencer 41 can execute each command entered in the I/O command queue 42 in any order.

After the program/read sequencer 41 acquires one or more write commands specifying the same write destination block from the I/O command queue 42, the program/read sequencer 41 executes the write operation in accordance with the progress of the write operation for this write destination block. Then, the internal buffer (shared cache) 31 or the write data buffer 51 sends a transfer request to acquire the next write data to be written to this write destination block (for example, write data of one page size) from the internal buffer (shared cache) 31 or the write data buffer 51 . ) 31. This transfer request may include a data pointer and length. The data pointer included in this transfer request is divided by the process of dividing write data associated with one write command or combining two or more write data associated with two or more write commands specifying the same write destination block. Calculated. In other words, the program/read sequencer 41 divides a set of write data associated with one or more write commands having identifiers indicating the same write destination block into the same size as the data write unit of the NAND flash memory 5 from the top. and identify the locations in host memory that correspond to each boundary. This allows the program/read sequencer 41 to acquire write data from the host 2 in units of the same size as the write unit.

The data pointer included in this transfer request indicates the position on the write data buffer 51 where the write data of this one page size exists. This one-page-size write data may be a set of a plurality of small size write data associated with a plurality of write commands specifying this write destination block, or a set of multiple small size write data specifying this write destination block. It may be part of a large size write data associated with the write command.

Further, the program/read sequencer 41 stores the block address of the write destination block to which the write data of one page size is to be written and the page address of the page to which the write data of one page size is to be written into the internal buffer ( shared cache) 31.

Controller 4 of flash storage device 3 may include a cache controller that controls an internal buffer (shared cache) 31 . In this case, this cache controller can operate the internal buffer (shared cache) 31 as if it were control logic. A plurality of flush command queues 43 exist between the internal buffer (shared cache) 31 and the plurality of write destination blocks #0, #1, #2, . . . , #n. These flash command queues 43 are respectively associated with a plurality of NAND flash memory chips.

The internal buffer (shared cache) 31, that is, the cache controller, determines whether or not the write data of this one page size designated by the transfer request exists in the internal buffer (shared cache) 31 or not.
If this 1-page size write data specified by this transfer request exists in the internal buffer (shared cache) 31, the internal buffer (shared cache) 31, that is, the cache controller, transfers this 1-page size write data. to the NAND flash memory chip containing the write destination block to which this write data is to be written. Furthermore, the internal buffer (shared cache) 31, that is, the cache controller, stores the block address of this write destination block and the page to which this write data is to be written in the NAND flash memory chip containing the write destination block to which this write data is to be written. A NAND command (flash write command) for address and write instruction is sent via the flash command queue 43 . A flash command queue 43 is provided for each NAND flash memory chip. Therefore, the internal buffer (shared cache) 31, that is, the cache controller stores the block address of this write destination block, A page address to which this write data is to be written and a NAND command (flash write command) for instructing writing are entered.

The transfer of write data of one page size from the internal buffer (shared cache) 31 to the NAND flash memory chip is the final data transfer required to write the write data to the NAND flash memory chip. If so, the internal buffer (shared cache) 31, that is, the cache controller discards this write data from the internal buffer (shared cache) 31 and secures the area where this write data was stored as a free area. In the case where the write data is written to the write destination block by a write operation (e.g., a full sequence write operation, etc.) that involves transferring the data once to the NAND flash memory chip, the first time to the NAND flash memory chip Data transfer is the final data transfer. On the other hand, in the case of writing write data to a write destination block by a write operation (for example, a foggy fine write operation) that involves transferring data to a NAND flash memory chip multiple times, Data transfer to the NAND flash memory chip is the final data transfer.

Next, a case where the write data of one page size designated by the transfer request does not exist in the internal buffer (shared cache) 31 will be described.
If this 1-page size write data specified by this transfer request does not exist in the internal buffer (shared cache) 31, the internal buffer (shared cache) 31, that is, the cache controller, receives this transfer request (data pointer, length ) is sent to the DMAC 15 . Based on this transfer request (data pointer, length), the DMAC 15 transfers this one page size write data from the write data buffer 51 on the host memory to the internal buffer (shared cache) 31 . When this data transfer is completed, the DMAC 15 notifies the internal buffer (shared cache) 31, that is, the cache controller, of transfer completion (Done), this data pointer, and this length.

If there is an empty area in the internal buffer (shared cache) 31, the internal buffer (shared cache) 31, that is, the cache controller stores the write data acquired from the write data buffer 51 by DMA transfer in this empty area. .
If there is no free space in the internal buffer (shared cache) 31, the internal buffer (shared cache) 31, that is, the cache controller, transfers the oldest write data in the internal buffer (shared cache) 31 to the internal buffer (shared cache) 31. , and secures the area where the oldest write data was stored as a free area. Then, the internal buffer (shared cache) 31, that is, the cache controller stores the write data obtained from the write data buffer 51 by DMA transfer in this free area.

In the case where a multi-stage write operation such as a foggy fine write operation is used, the cache controller reserves the cache in the internal buffer (shared cache) 31 where the first stage write operation such as a foggy write operation has finished. out of the write data, the oldest write data is discarded.

The progress speed of the data write operation to the write destination block to which the data write amount is large tends to be faster than the progress speed of the data write operation to the write destination block to which the data write amount is small. Therefore, write data to be written to a write destination block with a large amount of data written is frequently transferred from the write data buffer 51 to the internal buffer (shared cache) 31 . As a result, there is a high possibility that this oldest write data is write data to a write destination block in which the amount of data written from the host 2 is relatively small. Therefore, by using a method of discarding the oldest write data among the write data in the internal buffer (shared cache) 31 for which the first stage write operation such as the foggy write operation has been completed, the host 2 and the flash storage device 3 can be efficiently reduced.

Note that the algorithm for selecting write data to be discarded from the write data in the internal buffer (shared cache) 31 for which the first stage write operation such as the foggy write operation has been completed is to select the oldest data. The selection is not limited to first in first out, other algorithms such as LRU, random may be used.

The program/read sequencer 41 receives status from each NAND flash memory chip, that is, write completion (Done), write failure (Error), block address, page address. Based on these statuses, for each write command, the program/read sequencer 41 writes the entire write data associated with the write command (transfers the same data to the NAND flash memory chip once or multiple times). write operation) is completed. When all write operations for the entire write data associated with a certain write command are completed, the program/read sequencer 41 transmits a command completion response (Done) of this write command to the host 2 . A response (Done) indicating the completion of this command includes a command ID that uniquely identifies this write command.

Next, read command processing will be described.
A read command consists of a block address indicating a block in which data to be read is stored, a page address indicating a page in which this data is stored, and a read data buffer 53 on the host memory to which this data is to be transferred. and the length of this data.

The program/read sequencer 41 sends the block address and page address specified by the read command to the internal buffer (shared cache) 31 and requests the internal buffer (shared cache) 31 to read the data specified by the read command. .

The internal buffer (shared cache) 31 , that is, the cache controller, sends this block address, this page address, and a NAND command for read instruction (flash read command) to the NAND flash memory chip via the flash command queue 43 . Send out. Data read from the NAND flash memory chip is transferred to the read data buffer 53 by the DMAC 15 .

If the data specified by the read command is data for which the write operation has not been completed, or data for which all the write operations have been completed but is not yet readable from the NAND flash memory 5, the internal Buffer (shared cache) 31 , the cache controller, may determine if this data exists in internal buffer (shared cache) 31 . If this data exists in internal buffer (shared cache) 31 , this data is read from internal buffer (shared cache) 31 and transferred by DMAC 15 to read data buffer 53 .

On the other hand, if the data does not exist in the internal buffer (shared cache) 31 , the data is first transferred from the write data buffer 51 to the internal buffer (shared cache) 31 by the DMAC 15 . This data is then read from the internal buffer (shared cache) 31 and transferred to the read data buffer 53 by the DMAC 15 .

FIG. 7 shows a multi-stage write operation performed by flash storage device 3 .
Here, a foggy-fine write operation is exemplified in the case of round trips over four word lines. Also, here, it is assumed that the NAND flash memory 5 is a QLC-flash that stores 4-bit data per memory cell. A foggy fine write operation for one specific write destination block (here, write destination block BLK#1) in the NAND flash memory 5 is executed as follows.

(1) First, four pages (P0 to P3) of write data are transferred page by page to the NAND flash memory 5, and transferred to a plurality of memory cells connected to the word line WL0 in the write destination block BLK#1. , a foggy write operation is performed to write write data for these four pages (P0 to P3).

(2) Next, write data for the next four pages (P4 to P7) are transferred to the NAND flash memory 5 page by page, and a plurality of write data connected to the word line WL1 in the write destination block BLK#1 are transferred. A foggy write operation is performed to write the write data of these four pages (P4 to P7) to the memory cells.

(3) Next, write data for the next four pages (P8 to P11) are transferred to the NAND flash memory 5 in units of pages, and the plurality of write data connected to the word line WL2 in the write destination block BLK#1 are transferred. A foggy write operation is performed to write the write data of these four pages (P8 to P11) to the memory cells.

(4) Next, write data for the next four pages (P12 to P15) are transferred to the NAND flash memory 5 in units of pages, and the plurality of write data connected to the word line WL3 in the write destination block BLK#1 are transferred. A foggy write operation is performed to write the write data of these four pages (P12 to P15) to the memory cells.

(5) When the foggy write operation to the memory cells connected to the word line WL3 is completed, the word line to be written returns to the word line WL0, and the fine write operation to the memory cells connected to the word line WL0 is started. execution becomes possible. Then, the write data of the same four pages (P0 to P3) as the write data of four pages (P0 to P3) used in the foggy write operation to the word line WL0 are transferred again to the NAND flash memory 5 in units of pages. , a fine write operation is performed to write write data for these four pages (P0 to P3) to a plurality of memory cells connected to the word line WL0 in the write destination block BLK#1. This completes the foggy fine write operation for pages P0-P3.

(6) Next, write data for the next four pages (P16 to P19) are transferred to the NAND flash memory 5 in units of pages, and a plurality of write data connected to the word line WL4 in the write destination block BLK#1 are transferred. A foggy write operation is performed to write the write data of these four pages (P16 to P19) to the memory cells.

(7) When the foggy write operation to the memory cells connected to the word line WL4 is completed, the word line to be written returns to the word line WL1, and the fine write operation to the memory cells connected to the word line WL1 is started. execution becomes possible. Then, the write data of the same four pages (P4 to P7) as the write data of four pages (P4 to P7) used in the foggy write operation to the word line WL1 are transferred again to the NAND flash memory 5 in units of pages. , a fine write operation is performed to write write data for these four pages (P4 to P7) to a plurality of memory cells connected to the word line WL1 in the write destination block BLK#1. This completes the foggy fine write operation for pages P4-P7.

(8) Next, the write data for the next four pages (P20 to P23) are transferred to the NAND flash memory 5 page by page, and the plurality of write data connected to the word line WL5 in the write destination block BLK#1 are transferred. A foggy write operation is performed to write the write data of these four pages (P20 to P23) to the memory cells.

(9) When the foggy write operation to the memory cells connected to the word line WL5 is completed, the word line to be written returns to the word line WL2, and the fine write operation to the memory cells connected to the word line WL2 is started. execution becomes possible. Then, the write data of the same four pages (P8 to P11) as the write data of four pages (P8 to P11) used in the foggy write operation to the word line WL2 are transferred again to the NAND flash memory 5 in units of pages. , a fine write operation is performed to write write data for these four pages (P8 to P11) to a plurality of memory cells connected to the word line WL2 in the write destination block BLK#1. This completes the foggy fine write operation for pages P8-P11.

FIG. 8 shows the order of writing data to the write destination block BLK#1.
Here, as in FIG. 7, it is assumed that a foggy fine write operation is performed in which four word lines are reciprocated.
Data d0, data d1, data d2, data d3, data d4, data d5, data d6, data d7, . A plurality of write data corresponding to each of a plurality of write commands specifying BLK#1 are shown. Here, for the sake of simplification of illustration, it is assumed that all write data have the same size.

The right part of FIG. 8 shows the order of writing data to the write destination block BLK#1. The write operation includes writing data d0 to multiple memory cells connected to word line WL0 (foggy write), writing data d1 to multiple memory cells connected to word line WL1 (foggy write), and writing data d1 to multiple memory cells connected to word line WL1 (foggy write). Writing data d2 to a plurality of memory cells connected to WL2 (foggy writing), writing data d3 to a plurality of memory cells connected to word line WL3 (foggy writing), and writing data d3 to a plurality of memory cells connected to word line WL3 (foggy writing). (fine write), data d4 is written to a plurality of memory cells connected to word line WL4 (foggy write), and data to a plurality of memory cells connected to word line WL1 are written. d1 is written (fine write), data d5 is written to a plurality of memory cells connected to word line WL5 (foggy write), data d2 is written to a plurality of memory cells connected to word line WL2 (fine write). ), and so on.

FIG. 9 shows the operation of transferring write data from the host 2 to the flash storage device 3 in units of the same size as the data write unit of the NAND flash memory 5 .
Data d1, data d2, data d3, data d4, data d5, data d6, data d7, data d8, data d9, data d10, . 10 write data corresponding to 10 write commands are shown. The length (size) of write data differs for each individual write command. In FIG. 9, each of data d1, data d2, data d3, and data d4 has a size of 4K bytes, data d5 has a size of 8K bytes, data d6 has a size of 40K bytes, and data d7 has a size of 40K bytes. has a size of 16K bytes, each of data d8 and data d9 has a size of 8K bytes, and data d10 has a size of 1M bytes.

Since each write command received from the host 2 includes a data pointer, length, and block identifier (e.g., block address), the controller 4 of the flash storage device 3 distributes the write commands received from the host 2 to multiple write destinations. It can be classified into multiple groups, each corresponding to a block. The data d1, data d2, data d3, data d4, data d5, data d6, data d7, data d8, data d9, data d10, . corresponding to each write command. These 10 write commands are write commands including a block identifier (for example, block address) indicating the write destination block BLK#1.

The controller 4 of the flash storage device 3 writes data d1, data d2, data d3, data d4, data d5, data d6, data d1, data d2, data d3, data d4, data d5, data d6, Positions of data d7, data d8, data d9, and data d10 on write data buffer 51, and data d1, data d2, data d3, data d4, data d5, data d6, data d7, data d8, and data d9 , data d10. Then, the controller 4 divides the large size write data associated with one write command into a plurality of write data (a plurality of data portions), or divides the write data into a plurality of small size write data (a plurality of data portions), or divides the write data into two or more small size write data associated with two or more write commands. Write data having the same size as the data write unit of the NAND flash memory 5 obtained by combining the write data is obtained from the host 2 .

In FIG. 9, controller 4 first stores 16 Kbytes of write data obtained by combining data d1, data d2, data d3, and data d4, each having a size of 4 Kbytes, into write data buffer 51 of host 2. In FIG. Get from In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by, for example, four DMA transfers, although not limited to this. In the first DMA transfer, a transfer source address designating the head position of data d1 and a data length of 4 KB may be set in DMAC15. A transfer source address specifying the head position of data d1 is represented by a data pointer in the write command corresponding to data d1. In the second DMA transfer, a transfer source address designating the head position of data d2 and a data length of 4 KB may be set in the DMAC 15 . A transfer source address specifying the head position of data d2 is represented by a data pointer in the write command corresponding to data d2. In the third DMA transfer, the transfer source address designating the head position of data d3 and the data length=4 KB may be set in the DMAC15. A transfer source address specifying the head position of data d3 is represented by a data pointer in the write command corresponding to data d3. In the fourth DMA transfer, the transfer source address specifying the head position of data d4 and the data length=4 KB may be set in the DMAC15. A transfer source address specifying the head position of data d4 is represented by a data pointer in the write command corresponding to data d4.

Then, the controller 4 transfers the 16-Kbyte write data (d1, d2, d3, d4) obtained by DMA transfer to the NAND flash memory 5 as data to be written to page P0 of write destination block BLK#1. do.
The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P1, and combines the data d3 having a size of 8 Kbytes and the leading 8 Kbyte data d6-1 in the data d6 with each other. The 16-Kbyte write data thus obtained is acquired from the write data buffer 51 of the host 2 . In this case, the controller 4 may transfer this 16-Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by, for example, two DMA transfers, although not limited to this. In the first DMA transfer, a transfer source address designating the head position of data d5 and a data length of 8 KB may be set in DMAC15. A transfer source address specifying the head position of data d5 is represented by a data pointer in the write command corresponding to data d5. In the second DMA transfer, a transfer source address designating the start position of data d6-1 and a data length of 8 KB may be set in DMAC15. A transfer source address specifying the head position of data d6-1 is represented by a data pointer in the write command corresponding to data d6.

The controller 4 then transfers this 16-Kbyte write data (d5, d6-1) to the NAND flash memory 5 as data to be written to page P1 of write destination block BLK#1.
The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P2, and transfers the first 16 Kbyte data d6-2 of the remaining 32 Kbyte data of the data d6 to the write data buffer 51 of the host 2. Get from In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by one DMA transfer, for example, although not limited to this. In this DMA transfer, a transfer source address designating the head position of data d6-2 and a data length of 16 KB may be set in DMAC15. The transfer source address specifying the head position of data d6-2 can be obtained by adding an 8 KB offset to the value of the data pointer in the write command corresponding to data d6.

The controller 4 then transfers this 16-Kbyte write data (d6-2) to the NAND flash memory 5 as data to be written to page P2 of write destination block BLK#1.
The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P3, and acquires the remaining 16 Kbyte data d6-3 of the data d6 from the write data buffer 51 of the host 2. FIG. In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by one DMA transfer, for example, although not limited to this. In this DMA transfer, a transfer source address designating the head position of data d6-3 and a data length of 16 KB may be set in DMAC15. The transfer source address specifying the head position of data d6-3 can be obtained by adding an offset of 24 KB to the value of the data pointer in the write command corresponding to data d6.

The controller 4 then transfers this 16-Kbyte write data (d6-3) to the NAND flash memory 5 as data to be written to page P3 of write destination block BLK#1.
Then, the controller 4 writes four pages of data (P0 to P3) to a plurality of memory cells connected to the word line WL0 of the write destination block BLK#1 by the foggy write operation.

The controller 4 changes the next write destination page of the write destination block BLK# 1 to page P 4 and acquires data d 7 having a size of 16 Kbytes from the write data buffer 51 of the host 2 . In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by one DMA transfer, for example, although not limited to this. In this DMA transfer, a transfer source address specifying the head position of data d7 and a data length of 16 KB may be set in DMAC15. A transfer source address specifying the head position of data 7 is represented by a data pointer in the write command corresponding to data d7.

The controller 4 then transfers this 16-Kbyte write data (d7) to the NAND flash memory 5 as data to be written to page P4 of write destination block BLK#1.
The controller 4 changes the next write destination page of the write destination block BLK#1 to page P5, and is obtained by combining data d8 having a size of 8 Kbytes and data d9 having a size of 8 Kbytes with each other. 16 Kbyte write data is obtained from the write data buffer 51 of the host 2 . In this case, the controller 4 may transfer this 16-Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by, for example, two DMA transfers, although not limited to this. In the first DMA transfer, a transfer source address specifying the head position of data d8 and data length=8 KB may be set in DMAC15. A transfer source address specifying the head position of data d8 is represented by a data pointer in the write command corresponding to data d8. In the second DMA transfer, a transfer source address designating the start position of data d9 and a data length of 8 KB may be set in DMAC15. A transfer source address specifying the head position of data d9 is represented by a data pointer in the write command corresponding to data d9.

The controller 4 then transfers the 16-Kbyte write data (d8, d9) to the NAND flash memory 5 as data to be written to page P5 of write destination block BLK#1.
The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P6, and acquires the first 16 Kbyte data d10-1 in the data d10 from the write data buffer 51 of the host 2. FIG. In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by one DMA transfer, for example, although not limited to this. In this DMA transfer, a transfer source address designating the head position of data d10-1 and a data length of 16 KB may be set in DMAC15. A transfer source address specifying the head position of data d10-1 is represented by a data pointer in the write command corresponding to data d10.

The controller 4 then transfers this 16-Kbyte write data (d10-1) to the NAND flash memory 5 as data to be written to page P6 of write destination block BLK#1.
The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P7, and acquires the next 16-Kbyte data d10-2 in the data d10 from the write data buffer 51 of the host 2. FIG. In this case, the controller 4 may transfer the 16 Kbyte write data from the write data buffer 51 of the host 2 to the internal buffer 31 by one DMA transfer, for example, although not limited to this. In this DMA transfer, a transfer source address designating the head position of data d10-2 and a data length of 16 KB may be set in DMAC15. The transfer source address specifying the head position of data d10-2 can be obtained by adding an offset of 16 KB to the value of the data pointer in the write command corresponding to data d10.

The controller 4 then transfers this 16-Kbyte write data (d10-2) to the NAND flash memory 5 as data to be written to page P7 of write destination block BLK#1.
Then, the controller 4 writes four pages worth of data (P4 to P7) to a plurality of memory cells connected to the word line WL1 of the write destination block BLK#1 by the foggy write operation.

In this way, the controller 4 acquires from the host 2 the 16-Kbyte data to be transferred to the write destination page of the write destination block BLK#1 in accordance with the progress of the write operation of the write destination block BLK#1.
When the foggy write operation for the plurality of memory cells connected to the word line WL3 is completed, the fine write operation for the plurality of memory cells connected to the word line WL0 can be executed. The controller 4 changes the next write destination page of the write destination block BLK#1 to the page P1, and transfers the write data (P0 to P3) to the NAND flash memory 5 page by page again in the same procedure as described above. Then, these four pages of write data (P0 to P3) are written to a plurality of memory cells connected to the word line WL0 of the write destination block BLK#1 by the fine write operation.

As a result, the first six write commands, that is, a write command corresponding to data d1, a write command corresponding to data d2, a write command corresponding to data d3, a write command corresponding to data d4, and a write command corresponding to data d5 , for each of the write commands corresponding to the data d6, all of the foggy fine write operations for the entire write data associated with each write command are completed, and each of the data d1 to d6 is read from the NAND flash memory 5. It becomes possible. Therefore, the controller 4 returns to the host 2 six command completion responses respectively corresponding to the first six write commands.

Note that in FIG. 9, the write data associated with each write command specifying the write destination block BLK#1 is transferred from the host 2 to the flash storage in units of 16 Kbytes in accordance with the progress of the write operation of the write destination block BLK#1. Although the operation of transferring data to device 3 has been described, the same operation as the operation described with reference to FIG. 9 is performed for other write destination blocks BLK#.

The flowchart of FIG. 10 shows the procedure of data write processing executed by the flash storage device 3 .
The controller 4 of the flash storage device 3 receives from the host 2 each write command each including a data pointer, length and block identifier (eg block address) (step S11).

Next, the controller 4 divides the large-sized write data corresponding to one write command designating a specific write destination block into two or more data portions, or divides the write data into two or more data portions, or writes two or more write commands designating this specific write destination block. , and the data is transferred from the host 2 to the flash storage device 3 in units of the same size as the write unit (data transfer size) of the NAND flash memory 5 (step S12). In step S12, as described with reference to FIG. 9, for example, one 16 Kbyte data obtained by combining several small-sized write data parts with each other, or by dividing the large-sized write data One of the several 16K bytes of data obtained is transferred from the host 2 to the flash storage device 3 . In the case where the flash storage device 3 is configured to include an internal buffer 31 , each 16-byte write data transferred from the host 2 to the flash storage device 3 is stored in the internal buffer 31 . Also, in step S12, in order to join together several write data portions having small sizes, the controller 4 determines that the size of the write data associated with the preceding write command having an identifier designating a certain write destination block is If it is smaller than the write unit (eg, 16K bytes), wait for receipt of a subsequent write command with an identifier that specifies this destination block.

The controller 4 transfers the 16K-byte data transferred from the host 2 to the NAND flash memory 5, and writes the 16K-byte data to this specific write destination block (step S13).
Then, the controller 4 performs a write operation (a write operation involving transferring the same data to the NAND flash memory 5 once or multiple times) for the entire write data associated with one write command specifying this specific write destination block. operation) has been completed and the entire write data can be read from the NAND flash memory 5 (step S14).

When all write operations for the entire write data associated with one write command designating this specific write destination block have been completed and the entire write data can be read from the NAND flash memory 5, the controller 4 returns a response indicating command completion of this write command to the host 2 (step S15).

Note that in a case where a write operation involving transferring the same data to the NAND flash memory 5 a plurality of times, such as the foggy fine write operation, is used, the controller 4 is configured to specify a specific write destination block. When all the write operations (multi-step write operations) for the entire write data associated with one write command are completed, a response indicating command completion of this write command may be returned to the host 2 . This is because, in the foggy fine write operation, when the fine write operation of certain data is completed, this data can be correctly read from the NAND flash memory 5 .

Also, even if a fine write operation of data to a certain page ends, this data cannot be read, and this data can be read correctly after writing data to one or more subsequent pages. type NAND flash memory may be used. In this case, all of the write operations (multi-step write operations) for the entire write data associated with one write command specifying a specific write destination block are completed, and data to one or more subsequent pages is completed. When the entire write data can be read from the NAND flash memory 5 by writing , a response indicating command completion of this write command may be returned to the host 2 .

As described above, in this embodiment, when write data associated with a certain write command is transferred from the host 2 to the flash storage device 3, a response indicating completion of the write command is not returned to the host 2. , all write operations required to write the entire write data associated with a certain write command are completed, or all write operations for the entire write data are completed and the entire write data can be read from the NAND flash memory 5. Then, a response indicating command completion of this write command is returned to the host 2 .

As a result, the host 2 can read the write data of each write command from the flash storage device 3 simply by discarding from the write data buffer 51 the write data corresponding to the write command for which command completion has been notified. This write data can be maintained in the write data buffer 51 until it becomes available.

The flowchart of FIG. 11 shows the procedure of write data discard processing executed by the host 2 .
The host 2 determines whether or not a response indicating completion of the write command has been received from the flash storage device 3 (step S21). When receiving a command completion response for a certain write command from the flash storage device 3 (step S22), the host 2 discards the write data associated with this write command from the write data buffer 51 (step S22).

FIG. 12 shows dummy data executed by the flash storage device 3 when the next write command specifying a certain write destination block is not received within a threshold period of time after the last write command specifying a certain write destination block was received. Indicates a write process.

Data d1, data d2, data d3, and data d4 shown in the left part of FIG. 12 indicate four write data corresponding to four write commands specifying the write destination block BLK#1. In FIG. 12, it is assumed that each of data d1, data d2, data d3, and data d4 has a size of 4K bytes.

(1) The controller 4 acquires from the write data buffer 51 of the host 2 16 Kbyte write data obtained by combining data d1, data d2, data d3, and data d4. The controller 4 then transfers this 16-Kbyte write data to the NAND flash memory 5 as data to be written to page P0 of write destination block BLK#1. When the subsequent write command designating the write destination block BLK#1 is not received for a threshold period after the last write command designating the write destination block BLK#1, that is, the write command requesting the writing of data d4 is received. , the controller 4 writes dummy data to one or more pages in the write destination block BLK#1 in order to return a command completion response of the last write command to the host 2 within a predetermined time, The position of the write destination page in the write destination block BLK#1 to which the next write data is to be written is advanced. For example, the controller 4 transfers 3 pages of dummy data corresponding to pages P1 to P3 to the NAND flash memory 5 in page units, and performs a foggy write operation to transfer 4 pages of data (P0 to P3) to the write destination block. Write to a plurality of memory cells connected to word line WL0 of BLK#1.

(2) Next, the controller 4 transfers four pages worth of dummy data corresponding to the pages P4 to P7 to the NAND flash memory 5 in units of pages, and performs the foggy write operation to transfer the four pages worth of data (P4 to P7). Write to a plurality of memory cells connected to word line WL1 of write destination block BLK#1.

(3) Next, the controller 4 transfers the four pages worth of dummy data corresponding to the pages P8 to P11 to the NAND flash memory 5 in page units, and performs the foggy write operation to transfer the four pages worth of data (P8 to P11). A plurality of memory cells connected to the word line WL2 of the write destination block BLK#1 are written.

(4) Next, the controller 4 transfers four pages of dummy data corresponding to the pages P12 to P15 to the NAND flash memory 5 in page units, and performs the foggy write operation to transfer the four pages of data (P12 to P15). Write to a plurality of memory cells connected to word line WL3 of write destination block BLK#1.

(5) Next, controller 4 transfers 16 Kbyte write data obtained by combining data d1, data d2, data d3, and data d4 from write data buffer 51 or internal buffer 31 to NAND flash memory 5. Furthermore, the same three pages of dummy data (P0 to P3) as the three pages of dummy data (P0 to P3) used in the foggy write operation of WL0 are transferred to the NAND flash memory 5 in page units. Then, the controller 4 writes four pages of data (P0 to P3) to a plurality of memory cells connected to the word line WL0 of the write destination block BLK#1 by a fine write operation. As a result, the data d1, data d2, data d3, and data d4 are all written in multiple stages, and the data d1, data d2, data d3, and data d4 can be read from the NAND flash memory 5. FIG. The controller 4 requests a command completion response to the first write command requesting the writing of the data d1, a command completion response to the second write command requesting the writing of the data d2, and the writing of the data d3. It returns to the host 2 a response indicating command completion of the third write command and a response indicating command completion of the fourth write command requesting writing of data d4.

In this embodiment, the write data is transferred from the host 2 to the flash storage device 3 in the same data size unit as the data write unit of the NAND flash memory 5, and all the write operations of the entire write data of a certain write command are completed. At this point in time, or at the point in time when the write operation for the entire write data is completed and the entire write data can be read, a response indicating command completion of this write command is returned to the host 2 . For this reason, for example, after the host 2 issues a write command requesting to write small write data to a certain write destination block to the flash storage device 3, for a while, subsequent write commands specifying this write destination block are If it is not issued from the host 2, there is a possibility that this write command timeout error will occur. In this embodiment, the controller 4 assigns dummy data to this block identifier if the next write command with this block identifier is not received for a threshold period after the last write command with this block identifier was received from the host 2 . Write to the next unwritten page or pages in the corresponding write destination block. Therefore, the write operation of this write destination block can be advanced as necessary, so that it is possible to prevent the write command timeout error from occurring.

The flowchart of FIG. 13 shows the procedure of dummy data write processing executed by the flash storage device 3 . Assume that data is written to the destination block in a multi-step write operation, such as a foggy fine write operation.

The controller 4 of the flash storage device 3 writes the write data associated with the last write command specifying a destination block to this destination block by a first phase write operation, such as a foggy write operation. If the next write command specifying this write destination block is not received within the threshold period (Th) from the reception of this last write command (YES in step S31), the controller 4 writes the write data associated with the last write command. writes dummy data in one or more pages following the page in the write destination block to which is written, thereby advancing the position of the write destination page in this write destination block to which the next write data is to be written (step S32 ). By writing the dummy data to the write destination block, the position of the write destination page advances, and when this makes it possible to execute the fine write operation (second stage write operation) of the write data associated with the last write command, the controller 4 transfers the write data associated with the last write command from the write data buffer 51 or the internal buffer (shared cache) 31 to the NAND flash memory 5 again, and executes the fine write operation of this write data (step S33). ).

When the fine write operation of the write data associated with the last write command is completed, that is, when all of the multi-step write operations of the entire write data are completed, the controller 4 sends a response indicating command completion of this last write command. is returned to the host 2 (step S34).

In this way, in the case where write data is written to a write destination block by a multi-stage write operation, the controller 4 performs the second-stage write operation of the write data associated with the last write command. , write dummy data to one or more pages within this destination block, and advance the position of the destination page within this destination block where the next write data is to be written.

FIG. 14 shows data transfer operations performed by controller 4 using internal buffers (shared cache) 31 .
An internal buffer (shared cache) 31 is shared by a plurality of write destination blocks BLK#1, BLK#2, . . . , BLK#n. The controller 4 of the flash storage device 3 executes the following processing for each of the write destination blocks BLK#1, BLK#2, . . . , BLK#n.

The write destination block BLK#1 will be exemplified below.
After the controller 4 receives one or more write commands specifying the write destination block BLK#1, the controller 4 writes a plurality of write data associated with one write command specifying the write destination block BLK#1. Write data having the same size as the write unit of the NAND flash memory 5, obtained by dividing the data or combining the write data respectively associated with two or more write commands specifying the write destination block BLK#1. is obtained from the write data buffer 51 . Then, the controller 4 stores in the internal buffer (shared cache) 31 a plurality of write data each having the same size as the write unit of the NAND flash memory 5 , which is obtained from the write data buffer 51 .

The write data buffer 51 does not necessarily have to consist of one continuous area on the host memory, and as shown in FIG. 14, a plurality of write data buffers 51-1, 51-2, . 51-n.
The controller 4 acquires write data (first write data) to be written next to the write destination block BLK# 1 from the internal buffer (shared cache) 31 and transfers the first write data to the NAND flash memory 5 . , write this write data to the write destination block BLK#1 by a first stage write operation, such as a foggy write operation.

When the internal buffer (shared cache) 31 does not have a free area for storing the write data acquired from the host 2 so that the write data from the host 2 can be stored efficiently in the internal buffer (shared cache) 31 , the controller 4 discards the write data (foggy state write data) in the internal buffer (shared cache) 31 for which the first stage write operation such as the foggy write operation has been completed, and frees up the space. Secured in the internal buffer (shared cache) 31 .

For example, when a new write command specifying an arbitrary write destination block is received from the host 2 while there is no free space in the internal buffer (shared cache) 31, the controller 4 performs a first step such as a foggy write operation. The write data (write data in the foggy state) in the internal buffer (shared cache) 31 for which the write operation has been completed is discarded, and an empty area capable of storing write data corresponding to a new write command is created in the internal buffer ( shared cache) 31.

For example, when a new write command is received from the host 2 while the entire internal buffer (shared cache) 31 is filled with a large number of foggy-state write data, the controller 4 stores these foggy-state write data. Specific write data to be discarded may be selected from among them, and the selected write data may be discarded. As a result, the internal buffer (shared cache) 31 having a limited capacity can be efficiently shared among multiple write destination blocks.

If the first write data does not exist in the internal buffer (shared cache) 31 at the time when the second stage write operation, such as the fine write operation of the first write data, is to be executed, the controller 4 writes the first write data to the first write data. to the host 2 to acquire the write data (transfer request: DMA transfer request) from the write data buffer 51 of the host 2 again. This acquired first write data may be stored in the internal buffer (shared cache) 31 . Then, the controller 4 transfers the obtained first write data to the NAND flash memory 5, and transfers the first write data to the write destination block BLK#1 by a second stage write operation such as a fine write operation. write to

If the first write data is present in the internal buffer (shared cache) 31 at the time a second phase write operation, such as a fine write operation of the first write data, is to be performed, the controller 4 will: The first write data is acquired from this internal buffer (shared cache) 31, the acquired first write data is transferred to the NAND flash memory 5, and a second stage write operation such as a fine write operation is performed. Write the first write data to the write destination block BLK#1.

After performing the final data transfer of the first write data to the NAND flash memory 5 (here, data transfer for fine write operation), the controller 4 transfers the first write data to the internal buffer ( An empty area is secured in the internal buffer (shared cache) 31 by discarding the data from the shared cache) 31 . Alternatively, the controller 4 may discard the first write data from the internal buffer (shared cache) 31 when the fine write operation of the first write data is completed.

Further, the controller 4 may read out the entire write data from the NAND flash memory 5 when the fine write operation of the entire write data associated with a certain write command is completed, or when the fine write operation of the entire write data is completed and the entire write data is read from the NAND flash memory 5. When it becomes possible, it returns a response indicating command completion of this write command to the host 2 .

The internal buffer (shared cache) 31 has a certain limited capacity, but if the number of destination blocks to be written is less than a certain number, the first The probability (hit rate) that write data exists in the internal buffer (shared cache) 31 is relatively high. Therefore, without transferring the same write data from the host 2 to the flash storage device 3 multiple times, a multi-step write operation such as a foggy fine write operation can be performed. As a result, data traffic between the host 2 and the flash storage device 3 can be reduced. 3 I/O performance can be improved.

The number of write destination blocks may be the same as the number of clients using the host 2 . In this case, data corresponding to one client is written to the destination block corresponding to this client, and data corresponding to other clients is written to another destination block. Therefore, as the number of clients using the host 2 increases, the hit rate of the internal buffer (shared cache) 31 decreases. However, if the first write data does not exist in the internal buffer (shared cache) 31 (miss), the controller 4 acquires this first write data from the host 2 . Therefore, multi-stage write operations, such as foggy-fine write operations, can be successfully performed even if the number of clients increases.

Therefore, the flash storage device 3 can flexibly cope with an increase in the number of clients sharing the flash storage device 3 (that is, an increase in the number of write destination blocks that can be used at the same time). can reduce data traffic between

Although the write process for writing data to the write destination block BLK#1 has been described here, the same write process is executed for each of all the other write destination blocks.
FIG. 15 shows the write process performed by the controller 4 using the internal buffer (shared cache) 31 and the process of discarding the write data in the internal buffer (shared cache) 31 .

FIG. 15 illustrates a case where the internal buffer (shared cache) 31 includes areas 101 to 109 for simplification of illustration. Also, in FIG. 15, the NAND flash memory 5 is implemented as a QLC-flash, and the process of discarding write data in units of data size for four pages is illustrated. However, the present embodiment is not limited to this. For example, a process of transferring write data from the write data buffer 51 to the internal buffer (shared cache) 31 in units of data size for one page may be executed. A process of discarding write data in units of data size for one page may be executed. Also, in FIG. 15, it is assumed that the foggy fine write operation is performed while reciprocating the three word lines WL.

Each of the write data D1 and D2 respectively stored in the areas 101 and 102 of the internal buffer (shared cache) 31 is associated with one or more write commands specifying the write destination block BLK#11. Each of the write data D1 and D2 may have a size of, for example, four pages. The controller 4 (1) writes four pages worth of write data D1 to pages P0 to P3 (a plurality of memory cells connected to the word line WL0) of the write destination block BLK#11 by a foggy write operation, and (2) ) Four pages of write data D2 are written to pages P4 to P7 (a plurality of memory cells connected to word line WL1) of write destination block BLK#11 by a foggy write operation.

Each of the write data D11, D12, D13 stored in the areas 103, 104, 105 of the internal buffer (shared cache) 31 is associated with one or more write commands specifying the write destination block BLK#101. Each of the write data D11, D12, and D13 may have a size of, for example, four pages. The controller 4 (3) writes four pages worth of write data D11 to pages P0 to P3 (a plurality of memory cells connected to the word line WL0) of the write destination block BLK#101 by the foggy write operation, and (4) 4 A page worth of write data D12 is written to pages P4 to P7 (a plurality of memory cells connected to word line WL1) of write destination block BLK#101 by a foggy write operation, and (5) four pages worth of write data D13 is written to foggy write data. A write operation writes to pages P8 to P11 (a plurality of memory cells connected to word line WL2) of write destination block BLK#101.

After the foggy write operation of the four pages of write data D13 to the word line WL2 of the write destination block BLK#101 is completed, the controller 4 (6) writes the four pages of write data D11 to the write destination block BLK#101 by performing a fine write operation. Pages P0-P3 of #101 (multiple memory cells connected to word line WL0) are written. When the fine write operation of the write data D11 is completed, or when the transfer (final transfer) for the fine write operation of the write data D11 to the NAND flash memory chip including the write destination block BLK#101 is completed, this write operation is completed. The state of data D11 changes from the foggy state to the fine state. Then, the controller 4 (7) discards the write data D11 (fine state write data) for which the fine write operation has been completed from the internal buffer (shared cache) 31 and makes the area 103 an empty area.

FIG. 16 shows a process of discarding write data in the internal buffer (shared cache) 31 executed by the controller 4 when the internal buffer (shared cache) 31 has no free space.
The upper part of FIG. 16 shows write data (D21 to D23, D31 to D33, D41 to D43) in the foggy state in which the entire internal buffer (shared cache) 31 has completed the foggy write operation (first stage write operation). , indicating that the internal buffer (shared cache) 31 has no free space.

In this state, when it is necessary to transfer write data from the write data buffer 51 to the internal buffer (shared cache) 31, for example, when a new write command is received from the host 2, the controller 4 changes the middle part of FIG. , the write data to be discarded is the oldest write data (here, write data D11) among the write data (write data in the foggy state) for which the foggy write operation (first stage write operation) has been completed. , and this oldest write data (here, write data D11) is discarded from the internal buffer (shared cache) 31 .

Then, as shown in the lower part of FIG. 16, the controller 4 of the flash storage device 3 stores new write data ( Here write data D51) is stored.

Note that instead of discarding the oldest write data among the write data for which the foggy write operation has ended (write data in the foggy state), write data for which the foggy write operation has ended (write data in the foggy state) Among them, write data with the least number of remaining data transfers to the NAND flash memory 5 may be discarded. In this case, for example, in a case where a multi-step write operation involving transferring the same data to the NAND flash memory 5 three times is used, two transfers to the NAND flash memory 5 have already been executed. Data is selected as data to be discarded in preference to data that has been transferred to the NAND flash memory 5 only once.

The flowchart of FIG. 17 shows the data write processing procedure executed by the controller 4 using the internal buffer (shared cache) 31 .
The controller 4 receives from the host 2 one or more write commands each including a data pointer, a write data length, and an identifier (for example, block address) designating one of a plurality of write destination blocks. (Step S101). After receiving one or more write commands having an identifier indicating the same write destination block, the controller 4 divides the write data associated with one write command in these write commands into a plurality of write data or writes the same write data. Write data having the same size as the write unit of the NAND flash memory 5 obtained by combining write data respectively associated with two or more write commands each having an identifier indicating a destination block is transferred from the write data buffer 51. Transfer to the internal buffer (shared cache) 31 (step S102).

The controller 4 acquires the write data to be written next to this write destination block from the internal buffer (shared cache) 31, transfers this write data to the NAND flash memory 5, and converts this first write data by foggy write operation. is written to this write destination block (steps S103 and S104). When the NAND flash memory 5 is realized as a QLC-flash, in step S103, 4 pages of write data are transferred to the NAND flash memory 5 in page units. Data is written by a foggy write operation to a plurality of memory cells connected to a word line to be written in the destination block.

The transfer of write data from the write data buffer 51 to the internal buffer (shared cache) 31 is executed in accordance with the progress of the write operation of each write destination block. For example, when the operation of transferring write data to be written to a certain page of a certain write destination block to the NAND flash memory chip is completed, the write data to be written to the next page of this write destination block is transferred from the write data buffer 51 to the internal memory. It may be transferred to the buffer (shared cache) 31 . Alternatively, when the operation of transferring write data to be written to a certain page of a certain write destination block to the NAND flash memory chip containing this write destination block is completed, and the operation of writing this write data to this write destination block is completed. Then, the write data to be written to the next page of this write destination block may be transferred from the write data buffer 51 to the internal buffer (shared cache) 31 .

At the time when the fine write operation of the write data for which the foggy write operation was performed is to be started, the controller 4 determines whether or not the write data exists in the internal buffer (shared cache) 31 .
If this write data exists in the internal buffer (shared cache) 31 (YES in step S106), the controller 4 acquires this write data from the internal buffer (shared cache) 31 and stores this write data in the NAND flash memory. 5, and this write data is written to this write destination block by a fine write operation (steps S107, S108, S109). As a result, this write data can be read from the NAND flash memory 5 .

For each write command, the controller 4 determines whether or not the foggy/fine write operation for the entire write data has been completed and the entire write data can be read from the NAND flash memory 5 . Then, the controller 4 returns to the host 2 a response indicating the command completion of the write command corresponding to the write data that has become readable from the NAND flash memory 5 after the foggy fine write operation is completed (step S110). If the fine write operation of the entire write data associated with a certain write command is completed by the processing of step S109, a response indicating command completion of this write command may be returned to the host 2 in step S110.

The flowchart of FIG. 18 shows the procedure of data reading processing executed by the controller 4 .
As described above, the controller 4 allows the data specified by the read command received from the host 2 to be transferred to the NAND-type flash memory 5 in all of its write operations (write operations in which the same data is transferred to the NAND flash memory 5 once or multiple times). In the case of unfinished data, or data whose write operations have all been completed but is not yet readable from the NAND flash memory 5, is this data present in the internal buffer (shared cache) 31? determine whether or not If this data does not exist in the internal buffer (shared cache) 31, the controller 4 acquires this data from the write data buffer 51, stores this data in the internal buffer (shared cache) 31, and stores this data in the internal buffer (shared cache) 31. shared cache) 31 to the host 2.

Specifically, the following data read processing is executed.
If the controller 4 receives a read command from the host 2 (YES in step S121), the controller 4 reads the data specified by this read command from the NAND flash memory 5 after all the write operations have been completed. It is determined whether or not the data is possible (step S122).

If this data can be read from the NAND flash memory 5 (YES in step S122), the controller 4 reads this data from the NAND flash memory 5 and returns the read data to the host 2 (step S126). ). At step S126, the controller 4 transfers the read data to a position within the read data buffer 53 designated by the data pointer included in the read command.

If this data cannot be read from the NAND flash memory 5 (NO in step S122), the controller 4 determines whether this data exists in the internal buffer (shared cache) 31 (step S123).
If this data exists in the internal buffer (shared cache) 31 (YES in step S123), the controller 4 reads this data from the internal buffer (shared cache) 31 and returns the read data to the host 2 (step S124).

At step S124, the controller 4 transfers the read data to a position within the read data buffer 53 designated by the data pointer included in the read command.
If this data does not exist in the internal buffer (shared cache) 31 (NO in step S123), the controller 4 acquires this data from the write data buffer 51 and stores it in the internal buffer (shared cache) 31 (step S125). ). At step S 125 , the DMAC 15 transfers this data from the write data buffer 51 to the free area of the internal buffer (shared cache) 31 . If there is no free space in the internal buffer (shared cache) 31, processing for securing free space in the internal buffer (shared cache) 31 is executed. The controller 4 then reads this data from the internal buffer (shared cache) 31 and returns the read data to the host 2 (step S124). At step S124, the controller 4 transfers the read data to a position within the read data buffer 53 designated by the data pointer included in the read command.

FIG. 19 shows data write and data read operations applied to a flash storage device 3 implemented as a type #2-storage device.
In this data write operation, the host 2 specifies the write destination block and the flash storage device 3 determines the write destination page. Also, in this data read operation, the host 2 designates a block address and a page address.

The host 2 includes a storage manager 404 that manages the flash storage device 3 . The storage management unit 404 sends a block allocation command and a write command to the flash storage device 3 .
The controller 4 of the flash storage device 3 includes a block allocator 701 and a page allocator 702 . The block allocation unit 701 and page allocation unit 702 may be included in the write control unit 21 described with reference to FIG.

A data write operation is performed in the following procedure.
(1) When the storage management unit 404 of the host 2 needs to write data (write data) to the flash storage device 3, the storage management unit 404 assigns a usable free block as a write destination block to the flash storage device. Device 3 may be requested. When the block allocation unit 701 receives this request (block allocation command), the block allocation unit 701 allocates one free block in the free block group to the host 2 as the write destination block, and the block address of the allocated write destination block. (BLK#) is notified to the host 2.

(2) The storage management unit 404 of the host 2 sends a write command that includes a block address that specifies the allocated write destination block, a tag that identifies write data, the data length of this write data, and a data pointer. Send to flash storage device 3. Also, the storage management unit 404 stores the write data in the write data buffer 51 .

(3) When the page allocation unit 702 receives a write command, the page allocation unit 702 determines a page address indicating a write destination page within a block (write destination block) having the block address specified by the write command. The controller 4 transfers the write data from the write data buffer 51 to the internal buffer (shared cache) 31 in units of page size, for example, and writes the write data to the determined write destination page in the write destination block.

(4) The controller 4 may notify the host 2 of the page address indicating the write destination page as a response indicating completion of the write command. Alternatively, the controller 4 sends a set of the tag included in this write command, the block address included in this write command, and the determined page address as a response indicating command completion of this write command. 2 may be notified. In the host 2, the LUT 404A is updated so that the physical address (block address, page address) indicating the physical storage location where the write data is written is mapped to the tag of this write data.

A data read operation is executed in the following procedure.
(1) 'When the host 2 needs to read data from the flash storage device 3, the host 2 reads the physical address (block address, page address) corresponding to the tag of the data to be read by referring to the LUT 404A. ) from LUT 404A.

(2)' The host 2 sends to the flash storage device 3 a read command designating the obtained block address and page address. When the controller 4 of the flash storage device 3 receives this read command from the host 2, the controller 4 reads data from the read target physical storage location within the read target block based on the block address and page address. .

FIG. 20 shows the block allocation command applied to a flash storage device 3 implemented as a type #2-storage device.
A block allocation command is a command (block allocation request) that requests the flash storage device 3 to allocate a write destination block (free block). The host 2 requests the flash storage device 3 to allocate a write destination block by sending a block allocate command to the flash storage device 3, thereby obtaining a block address (the block address of the allocated write destination block). can do.

FIG. 21 shows the response to the block allocate command.
Upon receiving a block allocate command from the host 2, the controller 4 of the flash storage device 3 selects a free block to be allocated to the host 2 from the free block list, allocates the selected free block as the write destination block, and performs this write. A response containing the block address of the previous block is returned to the host 2.

FIG. 22 shows write commands applied to a flash storage device 3 implemented as a type #2-storage device.
A write command is a command that requests the flash storage device 3 to write data. This write command may include a command ID, block address, tag, length, and so on.

The command ID is an ID (command code) indicating that this command is a write command, and the write command includes a command ID for write commands.
A block address is a physical address that specifies a destination block to which data is to be written.

A tag is an identifier for identifying write data to be written. This tag can be a logical address, such as an LBA, as described above, or a key in a key-value store. If the tag is a logical address such as LBA, the logical address (starting LBA) included in this write command indicates the logical location (first logical location) within the logical address space where the write data should be written. .

Length indicates the length of write data to be written.
The write command further includes a data pointer that indicates the location within the write data buffer 51 where the write data is stored.
Upon receiving a write command from the host 2, the controller 4 determines the write destination location (write destination page) within the write destination block having the block address specified by the write command. This write destination page is determined in consideration of page write order restrictions, bad pages, and the like. Then, the controller 4 writes the write data associated with this write command to this write destination position (write destination page) in this write destination block.

FIG. 23 shows responses to the write commands of FIG.
This response contains the page address and length. A page address is a physical address that indicates a physical storage location within a destination block to which data has been written. This physical address may be represented by an intra-block offset (ie, a pair of page address and intra-page offset). Length indicates the length of the data written.

Alternatively, this response may include not only the page address (offset within the block) and length, but also the tag and block address. The tag is the tag included in the write command in FIG. The block address is the block address included in the write command in FIG.

FIG. 24 shows read commands applied to a flash storage device 3 implemented as a type #2-storage device.
A read command is a command that requests the flash storage device 3 to read data. This read command includes command ID, tag, block address, page address and length.

The command ID is an ID (command code) indicating that this command is a read command, and the read command includes a command ID for read commands.
A block address designates a block in which data to be read is stored. The page address designates the page in which data to be read is stored. This page address may be represented by an intra-block offset (that is, a pair of page address and intra-page offset) that indicates the physical storage location within the block where the data to be read is stored. Length indicates the length of data to be read.

Further, the read command includes a data pointer that indicates the location within read data buffer 53 to which the data specified by the read command is to be transferred.
As described above, according to the present embodiment, after receiving one or more write commands having the first identifier indicating the same write destination block, the controller 4 receives one write command in the received write command. obtained by dividing write data associated with a command into a plurality of write data (a plurality of data portions), or combining write data associated with two or more write commands in a received write command, Write data having the same size as the data write unit of the NAND flash memory 5 is acquired from the host 2 . Then, the controller 4 writes the obtained write data to the write destination block specified by the first identifier by a first write operation involving transferring the same data once or multiple times.

Therefore, regardless of the write data size specified by each write command, write data can be obtained from the host 2 in units of the same data size as the data write unit of the NAND flash memory 5. It can be transferred to the flash memory 5 . Therefore, even if a write command requesting writing of large-sized write data to a certain write destination block is received, it is possible to prevent delays in data write operations to other write destination blocks. Therefore, it becomes possible to efficiently process each of a plurality of write commands that specify any one of a plurality of write destination blocks, without providing a large-capacity internal buffer 31 on the device side, or Even in a bufferless configuration with a capacity close to zero, multiple write destination blocks can be used simultaneously.

In other words, by using the host memory (write data buffer 51) on the device side in this way, the number of write destination blocks can be increased without providing a large-capacity internal buffer 31 on the device side. It is possible to flexibly cope with an increase in the number of blocks, and it is possible to maximize the upper limit of the number of write destination blocks that can be used simultaneously with the limited resources of the flash storage device 3 .

In addition, the controller 4 performs all write operations for the entire write data associated with one write command specifying a certain write destination block (write operations for transferring the same data to the NAND flash memory 5 once or multiple times). If completed, or if the write operation for the entire write data associated with one write command specifying a certain write destination block (the write operation that involves transferring the same data to the NAND flash memory 5 once or multiple times) When all the write data have been completed and the entire write data can be read from the NAND flash memory 5, a response indicating completion of the write command is returned to the host 2. FIG.

As a result, the host 2 performs a simple process of discarding the write data corresponding to the write command for which the command completion has been notified from the write data buffer 51, until the write data of each write command becomes readable. Write data may be maintained in write data buffer 51 .

Further, the controller 4 stores the write data in the write data buffer of the host 2 only when the data to be written does not exist in the internal buffer 31 at the time when the second stage write operation such as the fine write operation is to be executed. 51 to the internal buffer 31 again. Therefore, it is not necessary to transfer the same data from the write data buffer 51 to the internal buffer 31 a plurality of times each time data is written. In this way, by using the write data buffer 51 of the host 2 on the device side, it is possible to increase the number of write destination blocks, ie, flash storage, without providing a large-capacity internal buffer 31 on the device side for multistage write operations. An increase in the number of clients sharing the device 3 can be flexibly accommodated, and data traffic between the host 2 and the flash storage device 3 can be reduced.

In this embodiment, the write data of the size specified by each write command itself is transferred from the host 2 to the flash storage device 3, and a command completion response is returned to the host 2 when the transfer of this write data is completed. Instead, the configuration is such that write data is transferred from the host 2 to the flash storage device 3 in units of the same size as the flash write unit, and a command completion response is returned to the host 2 for each write command. It is possible to flexibly cope with an increase in the number of write destination blocks, that is, an increase in the number of clients sharing the flash storage device 3, while using the standard.

Note that the write data buffer 51 can be realized as an area accessible from each virtual machine executed on the host 2 . Also, in a case where the host 2 and the flash storage device 3 are connected via a network such as Ethernet, DMA transfer between the write data buffer 51 and the internal buffer 31 may be performed by remote DMA transfer. good.

Moreover, in this embodiment, the NAND flash memory is exemplified as the nonvolatile memory. However, the function of this embodiment is, for example, MRAM (Magnetoresistive
Random Access Memory), PRAM (Phase change
Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

2 Host, 3 Flash Storage Device, 4 Controller, 5 NAND Flash Memory, 21 Write Control Unit, 22 Read Control Unit, 31 Internal Buffer, 51 Write Data Buffer, 53 Read Data Buffer.

Claims (9)

A memory system connectable to a host,
non-volatile memory;
a controller electrically connected to the non-volatile memory;
The controller is
obtaining the first data from the memory of the host in response to receiving from the host a write command specifying at least a location on the memory of the host where the first data is stored;
receiving the first data from the memory of the host in response to receiving from the host a read command requesting reading of the first data after acquiring the first data from the memory of the host; configured to acquire and return said re-acquired first data to said host;
memory system. The controller is
transmitting the first data to the nonvolatile memory after acquiring the first data from the memory of the host in response to receiving the write command from the host;
in response to receiving the read command from the host after transmitting the first data to the nonvolatile memory, obtaining the first data again from the memory of the host; configured to return to said host data of
2. The memory system of claim 1. further equipped with a buffer,
The controller is
acquiring the first data from the memory of the host and storing it in the buffer in response to receiving the write command from the host, transmitting the first data from the buffer to the nonvolatile memory;
determining whether the first data is still stored in the buffer in response to receiving the read command from the host after transmitting the first data to the nonvolatile memory; is not stored in the buffer, the first data is reacquired from the memory of the host, the reacquired first data is stored in the buffer, and the first data is stored in the buffer. configured to return from said buffer to said host;
2. The memory system of claim 1. The controller is
determining whether the first data is still stored in the buffer in response to receiving the read command from the host after transmitting the first data to the nonvolatile memory; is stored in the buffer, the first data is returned from the buffer to the host without retrieving the first data from the memory of the host.
4. The memory system of claim 3. The controller is
transmitting the first data to the nonvolatile memory after acquiring the first data from the memory of the host in response to receiving the write command from the host;
After transmitting the first data to the nonvolatile memory, instructing the nonvolatile memory to write the first data;
After instructing the nonvolatile memory to write the first data, in response to receiving the read command from the host while the first data is not yet readable from the nonvolatile memory, configured to re-acquire the first data from the memory of the host and return the re-acquired first data to the host;
2. The memory system of claim 1. The nonvolatile memory includes a memory cell array,
The nonvolatile memory is
configured to write the first data to the memory cell array by a multi-stage write operation including at least a first-stage write operation and a second-stage write operation;
The controller is
After transmitting the first data to the non-volatile memory and instructing the non-volatile memory to perform the first stage write operation for the first data, In response to receiving the read command from the host before instructing a two-step write operation, the first data is reacquired from the memory of the host, and the reacquired first data is transferred to the read command. configured to return to the host,
6. The memory system of claim 5. The nonvolatile memory includes a memory cell array,
The nonvolatile memory is
configured to write the first data to the memory cell array by a multi-stage write operation including at least a first-stage write operation and a second-stage write operation;
The controller is
After transmitting the first data to the non-volatile memory and instructing the non-volatile memory to perform the first stage write operation on the first data, the non-volatile memory writes the first data on the first data. retrieving the first data from the memory of the host in response to receiving the read command from the host before completing the two-step write operation; configured to return to the host,
6. The memory system of claim 5. The memory cell array includes memory cells that store data in a nonvolatile manner according to threshold voltages,
The second stage write operation is an operation for adjusting the threshold voltage of the memory cell set by the first stage write operation.
8. The memory system according to claim 6 or 7. The non-volatile memory includes a plurality of blocks, each of which is a unit of data erase operation,
the write command further specifies an identifier indicating one of the plurality of blocks to which the first data is to be written;
The controller is configured to write the first data to one of the plurality of blocks indicated by the identifier.
2. The memory system of claim 1.

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