JP2023087987A - Electronic control device - Google Patents

Abstract

To appropriately shorten an execution time of secure boot.SOLUTION: An electronic control device 1 includes a hardware security module 4 for generating a verification value on the basis of an encryption key, and capable of executing verification processing of an area by collating the generated verification value with a collation value, and an arithmetic part 5 capable of executing arithmetic processing. A target area of secure boot is divided so as to include at least a first division area and a second division area. A portion of verification processing of the first division area is executed by the hardware security module, the entire verification processing of the second division area is executed by the arithmetic part, and the portion of the verification processing of the first division area and the entire verification processing of the second division area are executed in parallel.SELECTED DRAWING: Figure 1

Description

The present invention relates to electronic control units.

For example, electronic control units installed in vehicles are equipped with a function to rewrite applications (hereinafter referred to as applications) for the purpose of adding functions and fixing defects, and malicious third parties may modify applications. It also has a tamper detection function. An app is software that implements a specific function. There is a mechanism called secure boot as a method of detecting tampering with the application before starting the application. For example, Patent Literature 1 discloses a method of executing secure boot using a hardware security module (hereinafter referred to as HSM (Hardware Security Module)).

Japanese Unexamined Patent Application Publication No. 2017-33248

The secure boot target area and the verification time required to verify the target area are in a proportional relationship, and the verification time increases as the secure boot target area increases. In a configuration in which an electronic control unit that executes secure boot executes an application in cooperation with another electronic control unit, the electronic control unit that executes secure boot must be secured before starting data communication with the other electronic control unit. Must have finished booting. However, as described above, the verification time increases as the target area of secure boot increases. verification may not be completed.

The present invention has been made in view of the circumstances described above, and an object of the present invention is to provide an electronic control device capable of appropriately shortening the execution time of secure boot.

According to the first aspect of the invention, a hardware security module (4) is capable of generating a verification value based on an encryption key and comparing the generated verification value with a verification value to execute region verification processing. and a calculation unit (5) capable of executing calculation processing. A secure boot target area is divided to include at least a first divided area and a second divided area. Part of verification processing of the first segmented region is performed by the hardware security module, entire verification processing of the second segmented region is performed by the computing unit, and part of verification processing of the first segmented region is performed. and the whole verification process of the second divided area are executed in parallel.

Unlike the conventional method in which a hardware security module executes all areas targeted for secure boot, a part of the verification processing of the first divided area in the hardware security module and the entire verification process of the second divided area in the arithmetic unit are performed. By executing and in parallel, the execution time of secure boot can be appropriately shortened.

Functional block diagram showing one embodiment Flowchart showing processing for the entire secure boot target area Flowchart showing processing on the CPU side in verification processing of area A Flowchart showing HSM-side processing in area A verification processing Diagram for explaining the verification process of the area A Flowchart showing processing on the CPU side in verification processing for region B Flowchart showing processing on the HSM side in verification processing for area B Diagram for explaining the verification process of the area B Flowchart showing processing on the CPU side in verification processing for area C Diagram for explaining the verification process for area C Timing chart

An embodiment will be described below with reference to the drawings. As shown in FIG. 1, an ECU (Electronic Control Unit) 1 is an in-vehicle electronic control unit mounted on a vehicle, for example, and has a function of managing a plurality of ECUs in an integrated manner. The electronic control unit 1 may be, for example, a device that controls a drive system, a device that controls an ADAS (Advanced Driving Assistant System) system, a device that controls a multimedia system, or the like. The electronic control unit 1 is equipped with a secure boot function for detecting tampering with an application by a malicious third party before starting the application.

The electronic control unit 1 has an MPU 2 . The MPU 2 includes a ROM 3 , an HSM 4 , a CPU 5 as an arithmetic unit, and a data flash 6 . The MPU 2 executes a computer program stored in a non-transitional physical storage medium to execute processing corresponding to the computer program, and controls the operation of the electronic control unit 1 . The CPU 5 can execute arithmetic processing.

The ROM 3 includes a secure boot target area 7 as an area for storing data, a boot program area 8 for storing a boot program as an area for storing programs, and a security program area 9 for storing a security program for security authentication. and The secure boot target area 7 is divided into an area A as a third divided area, an area B as a first divided area, and an area C as a second divided area. Region A includes region division information for regions B and C, the MAC value for region B, and the MAC value for region C. FIG. The area division information of area B is address information indicating the storage range of data specified by the start address and end address of area B, and the area division information of area C is data specified by the start address and end address of area C. This is address information indicating the storage range of the . A MAC value corresponds to a matching value. The boot program area 8 contains area division information for the area A. FIG. The area division information of the area A is address information indicating the storage range of the data specified by the top address and the end address of the area A. FIG. The area division information of area A is information that can be written only once, and cannot be updated after writing.

The HSM 4 stores an encryption key required to generate a verification value for verifying the areas A and B, and the MAC value of the area A. FIG. The data flash 6 can be accessed by security by activating the dedicated security program stored in the security program area 9, and the encryption key required to generate the verification value when executing the verification of the area C to store

Next, the operation of the above configuration will be described with reference to FIGS. 2 to 11. FIG.
In the electronic control unit 1, the HSM 4 and the CPU 5 cooperate to execute the verification processes for the areas A and B, and the CPU 5 executes the verification process for the area C independently. As shown in FIG. 2, the electronic control unit 1 executes the verification process of area A (S1), and when the verification process of area A is completed, the verification process of area B and the verification process of area C are executed in parallel. (S2, S3). Each verification process for areas A to C will be described below.

(1) Verification Processing of Region A Verification processing of region A will be described with reference to FIGS. 3 to 5. FIG.
When the CPU 5 starts processing on the CPU side in the verification processing of the area A, the CPU 5 acquires the area division information of the area A stored in the boot program area 8 of the ROM 3 (A1), and stores it in the secure boot target area 7 of the ROM 3. The data of the area A where the data is stored is acquired (A2). The CPU 5 transmits the verification execution permission of the area A to the HSM 4 (A3), transmits the area division information of the area A to the HSM 4 (A4), transmits the data of the area A to the HSM 4 (A5), and Wait to receive A's verification result.

When HSM 4 starts processing on the HSM side in verification processing for region A, it receives verification execution permission for region A transmitted from CPU 5 (B1). When the HSM 4 receives the area division information of the area A transmitted from the CPU 5 (B2), and receives the data of the area A transmitted from the CPU 5 (B3), the HSM 4 uses the encryption key held by itself to (B4). The HSM 4 compares the generated verification value of the area A with the MAC value of the area A held by itself (B5), verifies the area A (B6), and sends the verification result of the area A to the CPU 5. (B7), and the processing on the HSM side ends. That is, if the verification value and the MAC value match, the HSM 4 transmits to the CPU 5 a verification result indicating that the verification value and the MAC value match. A verification result indicating mismatch of values is sent to the CPU 5 .

When the CPU 5 receives the verification result of the area A transmitted from the HSM 4 (A6), it determines whether or not the verification value and the MAC value match based on the received verification result (A7). When the CPU 5 determines that the verification value and the MAC value match (A7: YES), it shifts to verification of the areas B and C (A8), and ends the processing on the CPU side. When the CPU 5 determines that the verification value and the MAC value do not match (A7: NO), the activation is interrupted without moving to the verification of the areas B and C (A9), and the processing on the CPU side ends. FIG. 5 shows a mode of transmitting and receiving various information in the verification process of area A. In FIG.

(2) Verification Processing of Region B Verification processing of region B will be described with reference to FIGS. 6 to 8. FIG.
When the CPU 5 starts processing on the CPU side in the verification processing of the area B by determining that the verification result of the area A matches, the area division information of the area B stored in the secure boot target area 7 of the ROM 3 is acquired (A11), the data storage range is specified based on the acquired area division information of the area B, and the data of the area B is acquired (A12). The CPU 5 transmits verification execution permission of the area B to the HSM 4 (A13), transmits area division information of the area B to the HSM 4 (A14), transmits data of the area B to the HSM 4 (A15), and Wait to receive B's verification value.

When the HSM 4 starts processing on the HSM side in the verification processing of the region B, the HSM 4 receives verification execution permission of the region B transmitted from the CPU 5 (B11). When the HSM 4 receives the area division information of the area B transmitted from the CPU 5 (B12), and receives the data of the area B transmitted from the CPU 5 (B13), the HSM 4 uses the encryption key held by itself to is generated (B14). The HSM 4 transmits the generated verification value of the area B to the CPU 5 (B15), and ends the processing on the HSM side.

When the CPU 5 receives the verification value of the area B transmitted from the HSM 4 (A16), the CPU 5 acquires the MAC value of the area B stored in the secure boot target area 7 of the ROM 3 (A17). The verification value is compared with the obtained MAC value of area B (A18), and area B is verified (A19). When the CPU 5 determines that the verification value and the MAC value match (A20: YES), the processing on the CPU side ends. When the CPU 5 determines that the verification value and the MAC value do not match (A20: NO), it interrupts activation (A21) and terminates the processing on the CPU side. FIG. 8 shows a mode of transmitting and receiving various information in the verification process of area B. FIG.

(3) Verification Processing of Region C Verification processing of region C will be described with reference to FIGS. 9 to 10. FIG.
When the CPU 5 starts processing on the CPU side in the verification processing of the area C by determining that the verification result of the area A matches, the area division information of the area C stored in the secure boot target area 7 of the ROM 3 is obtained (A31), and the data storage range is specified based on the obtained area division information of the area C to obtain the data of the area C (A32). The CPU 5 transmits an instruction to read out the encryption key to the security program (A33), acquires the encryption key stored in the data flash 6 by activating the security program (A34), and uses the acquired encryption key to A verification value for area C is generated (A35).

The CPU 5 acquires the MAC value of the area C stored in the secure boot target area 7 of the ROM 3 (A36), and compares the generated verification value of the area C with the acquired MAC value of the area C (A37 ), and verify area C (A38). When the CPU 5 determines that the verification value and the MAC value match (A39: YES), the processing on the CPU side ends. When the CPU 5 determines that the verification value and the MAC value do not match (A39: NO), it interrupts activation (A40) and terminates the processing on the CPU side. FIG. 10 shows a mode of transmitting and receiving various information in the verification process of area C. In FIG. That is, the HSM 4 is not involved in the verification process of the area C at all.

As shown in FIG. 11, the HSM 4 generates the verification value for the area B, and the CPU 5 generates the verification value for the area C and compares the verification value with the MAC value. The generation, the generation of the verification value for area C, and the comparison between the verification value and the MAC value are executed in parallel. The allocation between the amount of data in the area B where the verification process is performed by the HSM 4 and the amount of data in the area C where the verification process is performed by the CPU 5 can be determined according to the following formula. Specifically, when the capacity of the application area that is the target area of the secure boot is determined, the data allocated to areas B and C based on the startup time of HSM 4, the boot loader time of CPU 5, and the processing speeds of HSM 4 and CPU 5 Determine quantity.

HSM verification speed: Time calculated from the verification amount per second of HSM4 CPU verification speed: Time calculated from the verification amount per second of CPU5 HSM startup time: Time required for HSM4 to start Boot loader time: Boot loader of CPU5 total verification area: sum of area B and area C HSM verification amount: amount of data allocated to area B CPU verification amount: amount of data allocated to area C
HSM activation time + (HSM verification amount/HSM verification speed)
= Boot loader time + (CPU verification amount/CPU verification speed) (A)
HSM verification amount + CPU verification amount = verification total area (a)
holds, the HSM verification amount and the CPU verification amount can be obtained from the above (a) and (b) by the following formulas.
HSM verification amount = ((total verification area + (HSM startup time - boot loader time) x HSM verification speed) x CPU verification speed) / (HSM verification speed + CPU verification speed)
CPU verification amount = ((verification total area + (boot loader time - HSM startup time) x CPU verification speed) x HSM verification speed) / (HSM verification speed + CPU verification speed)

As described above, according to the embodiment, the following effects can be obtained.
In the electronic control device 1, the HSM 4 generates the verification value for the area B, the CPU 5 generates the verification value for the area C and compares the verification value with the MAC value, and generates the verification value for the area B; The generation of the verification value for area C and the comparison between the verification value and the MAC value are executed in parallel. Unlike the conventional method in which the HSM 4 executes all the target areas for secure boot, generation of the verification value of the area B in the HSM 4, generation of the verification value of the area C in the CPU 5, and matching of the verification value and the MAC value are performed in parallel. By executing it, the execution time of secure boot can be shortened appropriately.

An encryption key required for a CPU 5 to generate a verification value of an area C is stored in a data flash 6 which can be accessed by security by activating a dedicated security program. The security of encryption keys can be appropriately ensured.

After completion of the verification process for the area A, generation of the verification value for the area B, generation of the verification value for the area C, and collation between the verification value and the MAC value are executed in parallel. When executing the verification process for the areas B and C, if the MAC values of the areas B and C are tampered with, the verification result becomes meaningless. By executing the verification process of A and executing the verification process of areas B and C on the condition that the verification value of area A and the MAC value match, the verification results of areas B and C are appropriately guaranteed. can do.

Although the present disclosure has been described with reference to examples, it is understood that it is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including single elements, more, or less, are within the scope and spirit of this disclosure.

Although the case where the number of CPUs is one has been exemplified, the number of CPUs may be two or more. When a first CPU and a second CPU are provided as two CPUs, they are divided into areas A, B, C, and D, and first, verification processing of area A in which MAC values of areas B, C, and D are stored is performed. Execute, and on the condition that the verification value of region A and the MAC value match, each verification process of regions B, C, and D is executed, the verification value of region B is generated in HSM 4, and the region in the first CPU The generation of the verification value for C and the comparison between the verification value and the MAC value and the generation of the verification value for the area D and the comparison between the verification value and the MAC value in the second CPU may be executed in parallel.

The controller and techniques described in this disclosure may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by the computer program. can be Alternatively, the controller and techniques described in this disclosure may be implemented by a dedicated computer provided by configuring the processor with one or more dedicated hardware logic circuits. Alternatively, the controller and techniques described in this disclosure can be implemented by a combination of a processor and memory programmed to perform one or more functions and a processor configured with one or more hardware logic circuits. It may also be implemented by one or more dedicated computers configured. The computer program may also be stored as computer-executable instructions on a computer-readable non-transitional tangible storage medium.

In the drawing, 1 is an electronic control unit, 2 is an MPU, 3 is a ROM, 4 is an HSM, 5 is a CPU (arithmetic unit), and 6 is a data flash.

Claims (5)

a hardware security module (4) capable of generating a verification value based on an encryption key and comparing the generated verification value with a verification value to execute region verification processing;
A calculation unit (5) capable of executing calculation processing,
A secure boot target area is divided to include at least a first divided area and a second divided area, a part of verification processing of the first divided area is executed by the hardware security module, and the second divided area is executed. The entire verification process of is executed by the calculation unit,
An electronic control device that executes, in parallel, part of the verification processing of the first segmented region and the entire verification processing of the second segmented region. As part of the verification processing of the first segmented region, the hardware security module generates a verification value based on an encryption key;
2. The electronic control device according to claim 1, wherein, as a remainder of the verification process for the first divided area, the calculation unit executes verification between a verification value and a verification value. Equipped with a data flash (6) that can be accessed by security by activating a dedicated security program,
3. The electronic control device according to claim 1, wherein said data flash stores an encryption key necessary for said calculation unit to generate a verification value. dividing the secure boot target area so as to include at least the first divided area and the second divided area, and further including a third divided area;
The third divided area stores divided area information indicating each area of the first divided area and the second divided area, a matching value of the first divided area, and a matching value of the second divided area. ,
4. The method according to any one of claims 1 to 3, wherein a part of the verification process of the first divided area and the verification of the second divided area are executed in parallel after the verification process of the third divided area is completed. electronic controller. The computing unit is plural,
The electronic control device according to any one of claims 1 to 4, wherein the second divided areas are plural.

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