JP2023086509A - electronic circuit module - Google Patents

Abstract

To improve the immunity of an electronic circuit module.SOLUTION: An electronic circuit module includes a semiconductor device having an unused terminal that is not connected to a power supply potential, is not connected to a reference potential, receives no signal, and outputs no signal, and a resistor or inductance element electrically connected between the unused terminal and the reference potential.SELECTED DRAWING: Figure 1

Description

The present invention relates to electronic circuit modules.

Patent Document 1 describes an integrated circuit noise reduction device in which a bypass capacitor is connected between a pair or a plurality of pairs of empty input/output ports whose outputs are fixed to H level and L level.

Patent Document 2 discloses a semiconductor device in which a first semiconductor chip and a second semiconductor chip formed with an RC filter are stacked, and the RC filter of the second semiconductor chip is connected to a terminal of the first semiconductor chip. A device is described.

In Patent Document 3, when a control device is reset, a first terminal required to be in a floating state and to maintain a signal at a terminal of a connected device to be controlled at High is described as a first terminal. A second terminal required to be pulled up by a pull-up resistor, to float when the control device is reset, and to keep the signal of the terminal of the connected device to be controlled at Low. An information processing device is described that pulls down with a pull down resistor of 1.

In US Pat. No. 5,300,000, in a first mode, a first signal is received at a first terminal and a second signal representing the capacitance of the sensing device is output on a second terminal, and an induction coil and a first capacitor are connected. is coupled in parallel between the first node and ground, and in the second mode receives a third signal at the first terminal and outputs a fourth signal on the second terminal representing the inductance of the sensing device; A sensing device is described.

JP-A-6-175758 JP 2005-252123 A JP 2020-109553 A Japanese Patent Publication No. 2020-512625

The bypass capacitors connected between a pair or a plurality of pairs of empty input/output ports whose outputs are fixed to H level and L level, described in Patent Document 1, are effective in suppressing differential noise, but are effective in suppressing common noise. Suppression has no effect. Common noise propagated to a power supply line or a ground line may propagate to a GPIO (General Purpose Input/Output) terminal. In that case, the bypass capacitor connected to the GPIO terminal cannot induce common noise to the ground. Therefore, the common noise affects the inside of the semiconductor device. Further, in the technique described in Patent Document 1, the integrated circuit requires two terminals for connecting the two terminals of the bypass capacitor, respectively.

Patent Documents 2 to 4 describe GPIO terminals used for signal transmission/reception, but do not describe unused GPIO terminals. If an unused GPIO terminal is left open, noise propagated to the power supply line or ground line may propagate to the unused GPIO terminal. In that case, since the unused GPIO terminals are open, noise affects the inside of the semiconductor device.

The present invention has been made in view of the above, and an object of the present invention is to improve immunity.

An electronic circuit module according to one aspect of the present invention is a semiconductor device having an unused terminal that is not connected to a power supply potential, is not connected to a reference potential, receives no signal, and outputs no signal. , and a resistor or inductance element electrically connected between the unused terminal and a reference potential.

According to the present invention, it is possible to improve immunity.

FIG. 1 is a diagram showing the configuration of an electronic circuit module according to the first embodiment. FIG. 2 is a diagram showing the internal configuration of the semiconductor device of the electronic circuit module according to the first embodiment. FIG. 3 is a diagram showing the configuration of the input buffer of the electronic circuit module according to the first embodiment. FIG. 4 is a diagram showing the configuration of the output buffer of the electronic circuit module according to the first embodiment. FIG. 5 is a diagram showing the configuration of an electronic circuit module according to the second embodiment. FIG. 6 is a diagram showing the configuration of an electronic circuit module according to the third embodiment. FIG. 7 is a diagram showing the configuration of an electronic circuit module according to the fourth embodiment.

DETAILED DESCRIPTION OF THE INVENTION Embodiments of an electronic circuit module according to the present invention will be described in detail below with reference to the drawings. It should be noted that the present invention is not limited by this embodiment. Each embodiment is an example, and it goes without saying that partial substitutions or combinations of configurations shown in different embodiments are possible.

<First Embodiment>
(composition)
FIG. 1 is a diagram showing the configuration of an electronic circuit module according to the first embodiment. The electronic circuit module 1 has a plurality of electronic components mounted on a substrate 10 . The substrate 10 may be composed of a plurality of substrates.

The electronic circuit module 1 is a wireless communication module that performs wireless communication, but the present disclosure is not limited to this. Although the electronic circuit module 1 is exemplified to be mounted on a vehicle, the present disclosure is not limited to this.

The electronic circuit module 1 includes a substrate 10 , a semiconductor device 11 , a matching circuit 21 , an antenna 22 and a resistor 23 .

The semiconductor device 11 may be enclosed in a package or may be a bare chip.

The antenna 22 may be provided outside the substrate 10 .

The substrate 10 has terminals 10a to 10c. The semiconductor device 11 has terminals 11a to 11e.

One end of a matching circuit 21 is electrically connected to the terminal 11a. The other end of matching circuit 21 is electrically connected to antenna 22 . That is, the terminal 11a is a high frequency signal input/output terminal. The matching circuit 21 is a circuit that performs impedance matching between the antenna 22 and the semiconductor device 11 .

Terminal 11b is electrically connected to power supply potential Vcc through terminal 10a. Power supplied from the power supply potential Vcc to the terminal 11 b is supplied to each circuit inside the semiconductor device 11 .

Terminal 11c is electrically connected to a reference potential through terminal 10b. The reference potential is exemplified by a ground potential, but the present disclosure is not limited to this. The terminal 11 c is electrically connected to each circuit inside the semiconductor device 11 .

The terminal 11d is a GPIO (General Purpose Input/Output) terminal, and is electrically connected to the external circuit 2 via the terminal 10c. The external circuit 2 transmits and receives signals to and from circuits inside the semiconductor device 11 via terminals 10c and 11d. The signal is exemplified by a digital signal, but the present disclosure is not limited to this.

A terminal 11e is an unused GPIO terminal. An unused GPIO terminal is a GPIO terminal that is not connected to the power supply potential Vcc, is not connected to the reference potential, receives no signal, and outputs no signal.

The terminal 11e corresponds to an example of the "unused terminal" of the present disclosure.

The electronic circuit module 1 of the first embodiment suppresses noise by using the terminal 11e, which is an unused GPIO terminal.

One end of a resistor 23 is electrically connected to the terminal 11e in order to suppress noise. The other end of resistor 23 is electrically connected to a reference potential through terminal 10b.

FIG. 2 is a diagram showing the internal configuration of the semiconductor device of the electronic circuit module according to the first embodiment. 2, the substrate 10 and the terminals 10a to 10c are omitted.

Semiconductor device 11 includes switch 41 , preamplifier 42 , and power amplifier 43 . The power amplifier 43 is an amplifier that amplifies a high frequency transmission signal. The preamplifier 42 is an amplifier that amplifies a high frequency received signal.

The preamplifier 42 and the power amplifier 43 are electrically connected to the power supply potential Vcc through the power supply potential line 44 and the terminal 11b, and are electrically connected to the reference potential through the reference potential line 45 and the terminal 11c. . The preamplifier 42 and the power amplifier 43 operate using power supplied from the power supply potential Vcc through the terminal 11b and the power supply potential line 44. FIG.

When transmitting a high-frequency transmission signal to the matching circuit 21 , the power amplifier 43 amplifies the high-frequency transmission signal input from the preceding circuit (not shown) and outputs the amplified high-frequency transmission signal to the switch 41 . The switch 41 electrically connects the terminal 11 a and the output terminal of the power amplifier 43 when transmitting the high-frequency transmission signal to the matching circuit 21 .

The switch 41 electrically connects the terminal 11 a and the input terminal of the preamplifier 42 when receiving the high frequency reception signal from the matching circuit 21 . The preamplifier 42 amplifies the high-frequency received signal input from the switch 41 and outputs it to a subsequent circuit (not shown).

The semiconductor device 11 includes general purpose input/output circuits 51 and 52 . General-purpose input/output circuits 51 and 52 are electrically connected to terminals 11d and 11e, respectively.

The general-purpose input/output circuit 51 includes a first protection diode 61, a second protection diode 62, a pull-up resistor 63, a first switch 64, a pull-down resistor 65, a second switch 66, an input buffer 67, and an output a buffer 68;

The input buffer 67 and the output buffer 68 are electrically connected to the power supply potential Vcc through the power supply potential line 44 and the terminal 11b, and electrically connected to the reference potential through the reference potential line 45 and the terminal 11c. there is The input buffer 67 and the output buffer 68 operate using power supplied from the power supply potential Vcc through the terminal 11b and the power supply potential line 44. FIG.

The cathode of the first protection diode 61 is electrically connected to the power supply potential Vcc through the power supply potential line 44 and the terminal 11b. The anode of the first protection diode 61 is electrically connected to the terminal 11d.

A cathode of the second protection diode 62 is electrically connected to the terminal 11d. The anode of the second protection diode 62 is electrically connected to the reference potential via the reference potential line 45 and the terminal 11c.

One end of the pull-up resistor 63 is electrically connected to the terminal 11d. The other end of pull-up resistor 63 is electrically connected to one end of first switch 64 . The other end of the first switch 64 is electrically connected to the power supply potential Vcc through the power supply potential line 44 and the terminal 11b. The pull-up resistor 63 pulls up the terminal 11d when the first switch 64 is on.

The pull-up resistor 63 and the first switch 64 may be implemented by a P-channel MOS transistor having a high on-resistance.

One end of the pull-down resistor 65 is electrically connected to the terminal 11d. The other end of pull-down resistor 65 is electrically connected to one end of second switch 66 . The other end of the second switch 66 is electrically connected to the reference potential via the reference potential line 45 and the terminal 11c. The pull-down resistor 65 pulls down the terminal 11d when the second switch 66 is on.

Note that the pull-down resistor 65 and the second switch 66 may be implemented by an N-channel MOS transistor having a high on-resistance.

An input terminal of the input buffer 67 is electrically connected to the terminal 11d. The input buffer 67 outputs a signal received from the external circuit 2 via the terminal 11d to a subsequent circuit (not shown).

FIG. 3 is a diagram showing the configuration of the input buffer of the electronic circuit module according to the first embodiment.

Input buffer 67 includes a P-channel transistor 81 and an N-channel transistor 82 .

The source of transistor 81 is electrically connected to power supply potential Vcc through terminal 67a. The drain of transistor 81 is electrically connected to the drain of transistor 82 . The source of transistor 82 is electrically connected to a reference potential through terminal 67b.

The gates of transistors 81 and 82 are electrically connected to terminal 67c. A signal 83 is input to the terminal 67c. The drains of transistors 81 and 82 are electrically connected to terminal 67d. A signal 84 is output from the terminal 67d.

When the signal 83 is at high level, the transistor 81 is turned off and the transistor 82 is turned on. Therefore, the signal 84 becomes low level.

When the signal 83 is low level, the transistor 81 is turned on and the transistor 82 is turned off. Therefore, the signal 84 becomes high level.

Referring again to FIG. 2, the output terminal of output buffer 68 is electrically connected to terminal 11d. The output buffer 68 outputs the signal received from the preceding circuit (not shown) to the external circuit 2 via the terminal 11d.

FIG. 4 is a diagram showing the configuration of the output buffer of the electronic circuit module according to the first embodiment.

Output buffer 68 includes an output control circuit 91 , a P-channel transistor 92 and an N-channel transistor 93 .

A signal 94 is input to the input terminal of the output control circuit 91 via the terminal 68c.

The source of transistor 92 is electrically connected to power supply potential Vcc through terminal 68a. The drain of transistor 92 is electrically connected to the drain of transistor 93 . The source of transistor 93 is electrically connected to a reference potential through terminal 68b.

Gates of the transistors 92 and 93 are electrically connected to two output terminals of the output control circuit 91, respectively. The drains of transistors 92 and 93 are electrically connected to terminal 68d. A signal 95 is output from the terminal 68d.

The output control circuit 91 turns on one of the transistor 92 and the transistor 93 according to the signal 94 .

When the transistor 92 is controlled to be off and the transistor 93 is controlled to be on, the signal 95 becomes low level.

When the transistor 92 is controlled to be on and the transistor 93 is controlled to be off, the signal 95 becomes high level.

Referring again to FIG. 2, the general-purpose input/output circuit 52 includes a first protection diode 71, a second protection diode 72, a pull-up resistor 73, a first switch 74, a pull-down resistor 75, and a second switch 76. , an input buffer 77 and an output buffer 78 .

Since the connection relationship of each circuit element in the general-purpose input/output circuit 52 is the same as the connection relationship of each circuit element in the general-purpose input/output circuit 51, description thereof will be omitted.

Since the circuit configuration of the input buffer 77 is the same as the circuit configuration of the input buffer 67 (see FIG. 3), description thereof will be omitted.

Since the circuit configuration of the output buffer 78 is the same as the circuit configuration of the output buffer 68 (see FIG. 4), description thereof will be omitted.

Terminal 11d is the GPIO terminal being used. Therefore, the first switch 64 and the second switch 66 are controlled to be on or off depending on the operating conditions of the semiconductor device 11 .

A terminal 11e is an unused GPIO terminal. Therefore, the first switch 64 and the second switch 66 are always controlled to be off.

(effect)
For example, noise 31 (see FIGS. 1 and 2) may enter the connecting portion between the matching circuit 21 and the antenna 22 . Note that the location where the noise 31 enters is an example, and the present disclosure is not limited to this. Also, the noise 31 is an example of common noise, and the present disclosure is not limited to this.

The noise 31 propagates to the power supply potential line 44 or the reference potential line 45 via the matching circuit 21 , the terminal 11 a , the switch 41 , and the preamplifier 42 or power amplifier 43 . Each transistor inside the semiconductor device 11 is composed of an oxide film of Si (silicon), and acts as a capacitance of several pF (picofarad) against the noise 31 . Therefore, the noise 31 propagated to the power supply potential line 44 or the reference potential line 45 may propagate inside the semiconductor device 11 and cause the semiconductor device 11 to malfunction.

As a countermeasure, it is conceivable to add a capacitor in the matching circuit 21 to electrically connect between the line through which the high frequency transmission signal and the high frequency reception signal pass and the reference potential. However, in that case, the matching circuit 21 loses impedance matching between the antenna 22 and the semiconductor device 11, which is not preferable.

Therefore, in the electronic circuit module 1 of the first embodiment, one end of the resistor 23 is electrically connected to the terminal 11e. The other end of resistor 23 is electrically connected to a reference potential.

For example, the noise 31 propagated to the power supply potential line 44 flows through the first protection diode 71, the terminal 11e, and the resistor 23 to the reference potential. Also, for example, the noise 31 propagated to the reference potential line 45 flows out to the reference potential via the second protection diode 72, the terminal 11e, and the resistor .

Thereby, the electronic circuit module 1 can suppress the propagation of the noise 31 to the elements inside the semiconductor device 11 . As a result, the electronic circuit module 1 can suppress malfunction of the semiconductor device 11 and improve immunity. Also, the electronic circuit module 1 can maintain impedance matching between the antenna 22 and the semiconductor device 11 . Moreover, the electronic circuit module 1 only needs to have one unused GPIO terminal, and a pair of unused GPIO terminals is unnecessary.

<Second Embodiment>
Among the constituent elements of the electronic circuit module of the second embodiment, the constituent elements that are the same as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 5 is a diagram showing the configuration of an electronic circuit module according to the second embodiment.

The electronic circuit module 1A includes an inductance element 24 instead of the resistor 23, unlike the electronic circuit module 1 (see FIG. 1) of the first embodiment.

A ferrite bead is exemplified as the inductance element 24, but the present disclosure is not limited thereto.

One end of the inductance element 24 is electrically connected to the terminal 11e. The other end of inductance element 24 is electrically connected to a reference potential through terminal 10b.

The noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows through the first protection diode 71, the terminal 11e, and the inductance element 24 to the reference potential. Also, for example, the noise 31 propagated to the reference potential line 45 (see FIG. 2) flows through the second protection diode 72, the terminal 11e, and the inductance element 24 to the reference potential.

As a result, the electronic circuit module 1A has the same effect as the electronic circuit module 1 does.

<Third Embodiment>
Among the constituent elements of the electronic circuit module of the third embodiment, the constituent elements that are the same as those of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

FIG. 6 is a diagram showing the configuration of an electronic circuit module according to the third embodiment.

The electronic circuit module 1B further includes an inductance element 24 in addition to the resistor 23, unlike the electronic circuit module 1 (see FIG. 1) of the first embodiment.

One end of the inductance element 24 is electrically connected to the terminal 11e. The other end of inductance element 24 is electrically connected to a reference potential through terminal 10b.

That is, the resistor 23 and the inductance element 24 are connected in parallel.

The noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows through the first protection diode 71, the terminal 11e, the resistor 23, and the inductance element 24 to the reference potential. Also, for example, the noise 31 propagated to the reference potential line 45 (see FIG. 2) flows through the second protection diode 72, the terminal 11e, the resistor 23, and the inductance element 24 to the reference potential.

Accordingly, the electronic circuit module 1B has the same effects as the electronic circuit module 1 does.

<Fourth Embodiment>
Among the constituent elements of the electronic circuit module of the fourth embodiment, the constituent elements that are the same as those of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

FIG. 7 is a diagram showing the configuration of an electronic circuit module according to the fourth embodiment.

The electronic circuit module 1C further includes an inductance element 24 in addition to the resistor 23, unlike the electronic circuit module 1 (see FIG. 1) of the first embodiment.

One end of the inductance element 24 is electrically connected to the other end of the resistor 23 . The other end of inductance element 24 is electrically connected to a reference potential through terminal 10b.

That is, the resistor 23 and the inductance element 24 are connected in series.

The noise 31 propagated to the power supply potential line 44 (see FIG. 2) flows through the first protection diode 71, the terminal 11e, the resistor 23, and the inductance element 24 to the reference potential. Also, for example, the noise 31 propagated to the reference potential line 45 (see FIG. 2) flows through the second protection diode 72, the terminal 11e, the resistor 23, and the inductance element 24 to the reference potential.

Accordingly, the electronic circuit module 1C has the same effect as the electronic circuit module 1 does.

Note that in the fourth embodiment, one end of the resistor 23 is electrically connected to the terminal 11e, the other end of the resistor 23 is electrically connected to one end of the inductance element 24, and the other end of the inductance element 24 is the reference terminal. Although described as being electrically connected to a potential, the present disclosure is not limited to this. One end of the inductance element 24 is electrically connected to the terminal 11e, the other end of the inductance element 24 is electrically connected to one end of the resistor 23, and the other end of the resistor 23 is electrically connected to the reference potential. Also good.

<Appendix>
(1)
Although each embodiment has described a case where there is one unused GPIO terminal (terminal 11e), the present disclosure is not limited to this. There may be two or more unused GPIO terminals. In that case, a resistor, an inductance element, a parallel circuit of a resistor and an inductance element, or a series circuit of a resistor and an inductance element may be connected between each unused GPIO terminal and the reference potential.

(2)
In each embodiment, the resistor 23 and the inductance element 24 are mounted on the substrate 10, but the present disclosure is not limited to this. Each of the resistor 23 and the inductance element 24 may be formed in the substrate 10 using wiring or the like.

In addition, the above-described embodiment is for facilitating the understanding of the present invention, and is not for limiting and interpreting the present invention. The present invention may be modified/improved without departing from its spirit, and the present invention also includes equivalents thereof.

1, 1A, 1B, 1C electronic circuit module 10 substrate 10a, 10b, 10c, 11a, 11b, 11c, 11d, 11e terminal 11 semiconductor device 21 matching circuit 22 antenna 23 resistor 24 inductance element 41 switch 42 preamplifier 43 power amplifier 51, 52 general-purpose input/output circuits 61, 71 first protection diodes 62, 72 second protection diodes 63, 73 pull-up resistors 64, 74 first switches 65, 75 pull-down resistors 66, 76 second switches 67, 77 input buffers 68, 78 Output buffer 81, 82, 92, 93 Transistor 91 Output control circuit

Claims (5)

a semiconductor device having an unused terminal that is not connected to a power supply potential, is not connected to a reference potential, receives no signal, and outputs no signal;
a resistor or inductance element electrically connected between the unused terminal and a reference potential;
including,
Electronic circuit module. The electronic circuit module according to claim 1,
a parallel circuit of a resistor and an inductance element electrically connected between the unused terminal and a reference potential;
Electronic circuit module. The electronic circuit module according to claim 1,
a series circuit of a resistor and an inductance element electrically connected between the unused terminal and a reference potential;
Electronic circuit module. The electronic circuit module according to any one of claims 1 to 3,
The semiconductor device is
Further having a high frequency signal input/output terminal for inputting and outputting a high frequency signal,
Electronic circuit module. The electronic circuit module according to claim 4,
an antenna for transmitting and receiving radio waves;
a matching circuit electrically connected between the antenna and the high-frequency signal input/output terminal and performing impedance matching between the antenna and the semiconductor device;
further comprising
Electronic circuit module.

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