JP2023082869A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of suppressing an increase in reliability.SOLUTION: A semiconductor device comprises: a semiconductor substrate 10 including one surface 10a and the other surface 10b opposite the one surface 10a and formed with a semiconductor element; an interlayer insulation film 18 formed on the one surface 10a of the semiconductor substrate 10 and formed with a contact hole 18a for exposing a part of the semiconductor element; and an electrode 19 including a buried electrode 191 arranged in the contact hole 18a and electrically connected to the semiconductor element and a wiring electrode 192 arranged on the interlayer insulation film 18 and connected to the buried electrode 191. The semiconductor substrate 10 is composed of silicon or a material having higher rigidity than silicon, and a width t1 is greater than or equal to 100 μm. The buried electrode 191 is composed of tungsten and buried only in the contact hole 18a, and a thickness t2 is less than or equal to 1.2 μm.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device having embedded electrodes.

2. Description of the Related Art Conventionally, semiconductor devices having embedded electrodes have been proposed (see Patent Document 1, for example). Specifically, this semiconductor device includes a semiconductor substrate having one surface and the other surface. Semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) having a base layer, a source region, etc. formed on one side and a drain layer etc. on the other side are formed on a semiconductor substrate.

A semiconductor device includes a first electrode connected to a base layer and a source region on one side of a semiconductor substrate, and a second electrode connected to a drain layer on the other side of the semiconductor substrate. .

More specifically, an interlayer insulating film is formed on one surface side of the semiconductor substrate, and contact holes are formed in the interlayer insulating film to expose the base layer and the source region. The upper electrode has an embedded electrode embedded in the contact hole and a wiring electrode arranged on the interlayer insulating film and connected to the embedded electrode. The wiring electrodes are made of a material containing aluminum or the like as a main component, and the buried electrodes are made of tungsten, which is a material having a higher embedding property in contact holes than the wiring electrodes. However, tungsten is a material that causes greater thermal stress than the wiring electrode.

In such a semiconductor device, tungsten forming the embedded electrodes is a material having a larger thermal stress than the wiring electrodes, so that the other surface side of the semiconductor substrate can be warped to be convex. Therefore, compared to the case where the other surface side of the semiconductor substrate is warped to be concave, when the other surface side (that is, the second electrode) of the semiconductor substrate is mounted on the mounted member via solder, the other surface It is possible to suppress air bubbles from being caught in the central portion of the side, and to improve mountability.

JP 2017-143214 A

However, according to studies by the present inventors, in the semiconductor device as described above, if the amount of tungsten forming the embedded electrode is too large, there is a possibility that the other surface of the semiconductor substrate may become too convex. confirmed. In this case, if the other surface of the semiconductor substrate is mounted on the mounted member via solder, the outer edge of the other surface may not be properly connected with the solder, resulting in a decrease in reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of suppressing deterioration in reliability.

In claim 1 for achieving the above object, a semiconductor device having a buried electrode (191) has one surface (10a) and the other surface (10b) opposite to the one surface, in which a semiconductor element is formed. an interlayer insulating film (18) formed on one surface of the semiconductor substrate and having a contact hole (18a) for exposing a part of the semiconductor element; an electrode (19) having a buried electrode (191) electrically connected to an element and a wiring electrode (192) arranged on an interlayer insulating film and connected to the buried electrode; The substrate is made of silicon or a material having higher rigidity than silicon and has a thickness (t1) of 100 μm or more, and the embedded electrodes are made of tungsten and are embedded only in the contact holes, The thickness (t2) is 1.2 μm or less.

According to this, the semiconductor substrate is made of silicon or a material having higher rigidity than silicon, and the embedded electrode has a thickness of 1.2 μm or less. Therefore, it is possible to prevent the semiconductor substrate from being excessively warped in a state where the other surface is convex. Therefore, when connecting the other surface side of the semiconductor substrate to the mounted member via solder, it is possible to prevent the outer edge portion of the other surface from being properly connected to the solder, thereby suppressing a decrease in reliability.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

1 is a plan view showing a semiconductor device according to a first embodiment; FIG. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1; 3 is a plan view of the semiconductor device shown in FIG. 2; FIG. 4 is a diagram showing the relationship between the thickness of embedded electrodes and the amount of warpage of a semiconductor device; FIG. It is a top view of the semiconductor device in 2nd Embodiment. It is a top view of the semiconductor device in 3rd Embodiment. It is a top view which shows the semiconductor device in other embodiment.

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is preferably mounted on a vehicle such as an automobile and applied as a device for driving various electronic devices for the vehicle.

As shown in FIG. 1, the semiconductor device of this embodiment has a rectangular plane shape, and has a cell region 1 and an outer peripheral region 2 surrounding the cell region 1 . In this embodiment, an IGBT (abbreviation of Insulated Gate Bipolar Transistor) is formed as a semiconductor element in the cell region 1 . A pad portion 3 connected to a gate electrode 15 and the like, which will be described later, is formed in the outer peripheral region 2 . In this embodiment, two cell regions 1 are provided, and each cell region 1 has the same configuration. In FIG. 1, embedded electrodes 191, which will be described later, are indicated by solid lines for easy understanding.

The semiconductor device is constructed using a semiconductor substrate 10 as shown in FIG. The semiconductor substrate 10 of this embodiment is made of a silicon substrate and has a thickness t1 of 100 μm or more. The semiconductor substrate 10 has an N ⁻ -type drift layer 11, and on the drift layer 11 is arranged a P-type base layer 12 having a relatively low impurity concentration. Hereinafter, the surface of the semiconductor substrate 10 on the side of the base layer 12 is defined as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 on the side of the drift layer 11 is defined as the other surface 10b.

A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 from the one surface 10a side and reach the drift layer 11. The trenches 13 divide the base layer 12 into a plurality of pieces. The plurality of trenches 13 extend so that the trenches 13 form stripes at equal intervals, with one of the surface directions of the surface 10a of the semiconductor substrate 10 (that is, the depth direction of the paper surface of FIG. 2) being the longitudinal direction. is set.

Each trench 13 is filled with a gate insulating film 14 formed to cover the wall surface of each trench 13 and a gate electrode 15 made of polysilicon or the like formed on the gate insulating film 14 . there is A trench gate structure is thus formed. The gate electrode 15 is electrically connected to the pad portion 3 formed in the peripheral region 2 through a gate wiring (not shown). Further, in the present embodiment, the portion of the wall surface of the trench 13 where the base layer 12 is exposed corresponds to the surface of the base layer 12 arranged between the emitter region 16 and the drift layer 11, which will be described later.

As shown in FIGS. 2 and 3, an N ⁺ -type emitter region 16 and a P ⁺ -type contact region 17 are formed in the surface layer portion of the base layer 12 . Specifically, the emitter region 16 has an impurity concentration higher than that of the drift layer 11 , and the contact region 17 has an impurity concentration higher than that of the base layer 12 . In this embodiment, the emitter regions 16 and the contact regions 17 are alternately formed along the longitudinal direction of the trenches 13 .

In FIG. 3, an interlayer insulating film 18, which will be described later, is omitted, and embedded electrodes 191 and contact holes 18a, which will be described later, are indicated by dotted lines. Although FIG. 3 is not a plan view, the gate insulating film 14 and the gate electrode 15 are hatched for easy understanding. In this embodiment, the emitter region 16 and the contact region 17 can also be said to be impurity regions.

An interlayer insulating film 18 made of BPSG (abbreviation for Borophosphosilicate Glass) or the like is formed on the base layer 12 (that is, one surface 10a of the semiconductor substrate 10). A contact hole 18 a is formed in the interlayer insulating film 18 to expose the emitter region 16 and the contact region 17 . In the present embodiment, the contact hole 18a is formed in a portion located between the adjacent trenches 13 in the normal direction to the one surface 10a (hereinafter also simply referred to as the normal direction). In addition, the contact hole 18a extends continuously along one surface direction of the semiconductor substrate 10 in the normal direction. Specifically, contact hole 18 a extends continuously along the longitudinal direction of trench 13 . The direction normal to the surface 10a can also be said to be the direction along the stacking direction of the drift layer 11 and the base layer 12 . Further, the normal direction to the one surface 10a can also be said to be when viewed from the normal direction to the one surface 10a.

An upper electrode 19 is formed on the interlayer insulating film 18 . Specifically, the upper electrode 19 of the present embodiment has an embedded electrode 191 arranged in the contact hole 18a and a wiring electrode 192 arranged on the interlayer insulating film 18 and connected to the embedded electrode 191. are doing. The wiring electrode 192 is made of aluminum, Al—Si containing aluminum as a main component, or the like, and the embedded electrode 191 is made of tungsten, which is a material having a higher embedding property in the contact hole 18a than the wiring electrode 192. there is Note that tungsten is a material that has a larger thermal stress than the wiring electrode 192 . In addition, since the embedded electrodes 191 of the present embodiment are arranged in the contact holes 18a, they are formed continuously along one surface direction of the semiconductor substrate 10. As shown in FIG. In other words, the embedded electrode 191 extends continuously along the longitudinal direction of the trench 13 .

Here, the buried electrode 191 of this embodiment is arranged only in the contact hole 18a and is not arranged on the interlayer insulating film 18. As shown in FIG. That is, the thickness t2 of the embedded electrode 191 is equal to the thickness of the interlayer insulating film 18. As shown in FIG. Such interlayer insulating film 18 and embedded electrode 191 are formed, for example, as follows. First, an interlayer insulating film 18 is formed to form a contact hole 18a. Next, a buried electrode 191 is formed by forming a tungsten film by a CVD (abbreviation of Chemical Vapor Deposition) method or the like so as to fill the contact hole 18a. At this time, tungsten is arranged also on the interlayer insulating film 18 . After that, by removing the tungsten arranged on the interlayer insulating film 18 by CMP (abbreviation of Chemical Mechanical Polishing) method or the like, it is arranged only in the contact hole 18a and the thickness t2 is the same as that of the interlayer insulating film 18. A recessed embedded electrode 191 is formed.

An N-type field stop layer (hereinafter simply referred to as an FS layer) 20 is formed on the side of the drift layer 11 opposite to the side of the base layer 12 (that is, the side of the other surface 10b of the semiconductor substrate 10). Although the FS layer 20 is not necessarily required, it prevents the spread of the depletion layer to improve the breakdown voltage and the steady-state loss performance, and also reduces the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10. is provided to control

A P-type collector layer 21 is formed on the opposite side of the drift layer 11 with the FS layer 20 interposed therebetween. A lower electrode 22 is formed on the collector layer 21 (that is, the other surface 10b of the semiconductor substrate 10). Incidentally, in this embodiment, the collector layer 21 corresponds to the impurity region.

The above is the configuration of the semiconductor device according to the present embodiment. In this embodiment, N-type, N ⁻ type, and N ⁺ type correspond to the first conductivity type, and P-type and P 2 ⁺ type correspond to the second conductivity type. In such a semiconductor device, the semiconductor substrate 10 includes the collector layer 21, the FS layer 20, the drift layer 11, the base layer 12, the emitter region 16, the contact region 17, etc., as described above. Also, although not shown in this embodiment, a plated film of nickel or the like is arranged on the upper electrode 19 when the semiconductor device is mounted. The plated film is arranged with a thickness of, for example, about 3 to 6 μm.

Next, the thickness t2 of the embedded electrode 191 will be described. In the semiconductor device as described above, according to studies by the present inventors, the thermal stress generated in the embedded electrode 191 increases as the thickness t2 of the embedded electrode 191 increases. It was confirmed that the surface 10b side is likely to be warped in a convex state. Specifically, as shown in FIG. 4, it was confirmed that the warpage of the semiconductor device increased steeply when the thickness t2 of the embedded electrode 191 was greater than 1.2 μm. FIG. 4 shows the results when the semiconductor substrate 10 is composed of a silicon substrate and the thickness of the semiconductor substrate 10 is 100 μm. Further, the amount of warp in FIG. 4 is the amount of warp when the ambient temperature is 230.degree.

As the thickness t1 of the semiconductor substrate 10 increases, the semiconductor substrate 10 becomes less likely to warp due to its rigidity. Therefore, in this embodiment, the thickness of the semiconductor substrate 10 is set to 100 μm or more, and the thickness of the embedded electrode 191 is set to 1.2 μm or less.

According to the present embodiment described above, the semiconductor substrate 10 is made of a silicon substrate and has a thickness t1 of 100 μm or more, and the embedded electrode 191 has a thickness t2 of 1.2 μm or less. Therefore, it is possible to prevent the semiconductor substrate 10 from being excessively warped in a state where the other surface 10b side is convex. Therefore, when the other surface 10b side of the semiconductor substrate 10 is connected to a mounted member via solder, it is possible to prevent the outer edge portion of the other surface 10b side from being properly connected to the solder, thereby preventing deterioration in reliability. can be suppressed.

(Second embodiment)
A second embodiment will be described. In this embodiment, the planar shape of the embedded electrode 191 is changed from that of the first embodiment. Others are the same as those of the first embodiment, so description thereof is omitted here.

In the semiconductor device of the present embodiment, as shown in FIG. 5, the contact holes 18a are divided into a plurality of pieces in the longitudinal direction of the trench 13 . The embedded electrode 191 is arranged in the contact hole 18a, and is divided into a plurality of parts in the longitudinal direction. 5 is a plan view corresponding to FIG. 3, and the emitter region 16 and the contact region 17 are omitted for easy understanding.

According to the present embodiment described above, the semiconductor substrate 10 is made of a silicon substrate, the thickness t1 is set to 100 μm or more, and the thickness t2 of the embedded electrode 191 is set to 1.2 μm or less. Therefore, the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, the embedded electrode 191 is divided into a plurality of parts in the longitudinal direction. Therefore, compared to the case where the embedded electrodes 191 are continuously extended in the longitudinal direction, the influence of the thermal stress of the embedded electrodes 191 can be reduced, and the semiconductor substrate 10 is made convex on the other surface 10b side. Excessive warping in the state can be further suppressed.

(Third embodiment)
A third embodiment will be described. In this embodiment, the planar shape of the embedded electrode 191 is changed from that of the first embodiment. Others are the same as those of the first embodiment, so description thereof is omitted here.

In the semiconductor device of the present embodiment, as shown in FIG. 6, contact hole 18a is formed to have a bent portion that is bent in the longitudinal direction of trench 13 . The bent portion is formed so as to form an acute angle with the longitudinal direction. 6 is a plan view corresponding to FIG. 3, and the emitter region 16 and the contact region 17 are omitted for easy understanding.

The buried electrode 191 is arranged in such a contact hole 18a. Therefore, the embedded electrode 191 has an extension portion 191a extending in one direction as a longitudinal direction, and a bent portion 191b connected to the extension portion 191a and forming an acute angle θ with the longitudinal direction. It becomes the structure to have. In other words, the embedded electrode 191 has a configuration in which the extending portions 191a connected to the same bent portion 191b overlap in the crossing direction, when the direction crossing the longitudinal direction of the trench 13 is defined as the crossing direction. In addition, in FIG. 6, the intersecting direction is the horizontal direction of the paper surface.

According to the present embodiment described above, the semiconductor substrate 10 is made of a silicon substrate and has a thickness t1 of 100 μm or more, and the embedded electrode 191 has a thickness t2 of 1.2 μm or less. Therefore, it is possible to prevent the semiconductor substrate 10 from being excessively warped in a state where the other surface 10b side is convex.

(1) In this embodiment, the embedded electrode 191 has an extension portion 191a and a bent portion 191b, and the extension portion 191a has a portion that overlaps in the cross direction. For this reason, mutual thermal stresses are likely to cancel each other out in the overlapping portions in the crossing direction. Therefore, the influence of the thermal stress of the embedded electrode 191 can be reduced, and the excessive warping of the semiconductor substrate 10 in a state where the other surface 10b side is convex can be further suppressed.

(Other embodiments)
Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

For example, in the first embodiment, an N-channel type trench gate structure IGBT in which the first conductivity type is the N type and the second conductivity type is the P type has been described as an example. However, the semiconductor device may be configured by forming, for example, a P-channel type trench gate structure IGBT in which the conductivity type of each component is inverted with respect to the N-channel type. Furthermore, the semiconductor device may have a configuration in which a MOSFET having a similar structure is formed in addition to the IGBT. The MOSFET is the same as the IGBT described in the first embodiment, except that the P ⁺ -type collector layer 21 in each of the above embodiments is changed to an N ⁺ -type drain layer.

Further, in each of the above embodiments, the semiconductor device in which the IGBT having the trench gate structure is formed has been taken as an example, but the semiconductor device may be configured by forming a semiconductor device having a planar gate structure. .

Furthermore, in each of the above-described embodiments, an example in which the semiconductor substrate 10 is configured by a silicon substrate has been described. However, if the semiconductor substrate 10 is made of a material having higher rigidity than the silicon substrate, it is difficult to warp. can be suppressed.

Further, in each of the above embodiments, the semiconductor device provided with two cell regions 1 and each cell region 1 has the same configuration has been described. However, the number of cell regions 1 and the configuration of each cell region 1 can be changed as appropriate. For example, as shown in FIG. 7, the semiconductor device may have four cell regions 1. FIG. Further, each cell region 1 may be arranged in the circumferential direction around a predetermined reference position RP on the semiconductor substrate 10 . Specifically, the four cell regions 1 may be arranged such that two cell regions 1 face each other across the reference position RP. The four cell regions 1 are formed such that the longitudinal direction of the embedded electrodes 191 in two cell regions 1 intersects with the longitudinal direction of the embedded electrodes 191 in the remaining two cell regions 1. good. For example, as shown in FIG. 7, in two cell regions 1 on one side and two cell regions 1 on the other side facing each other across the reference position RP, the embedded electrodes 191 are formed so that their longitudinal directions intersect each other. may have been Note that the trench 13 formed in each cell region 1 extends along the longitudinal direction of the embedded electrode 191 in each cell region 1 . According to this, since the direction in which the buried electrode 191 is likely to warp changes when the longitudinal direction of the embedded electrode 191 differs, excessive warping of the semiconductor device as a whole is suppressed by providing the cell regions 1 in which the buried electrode 191 has a different longitudinal direction. can.

REFERENCE SIGNS LIST 10 semiconductor substrate 10a one surface 10b other surface 18 interlayer insulating film 19 electrode 191 embedded electrode 192 wiring electrode t1, t2 thickness

Claims (3)

A semiconductor device having a buried electrode (191),
a semiconductor substrate (10) having one surface (10a) and the other surface (10b) opposite to the one surface and having a semiconductor element formed thereon;
an interlayer insulating film (18) formed on one surface of the semiconductor substrate and having a contact hole (18a) exposing a portion of the semiconductor element;
The embedded electrode arranged in the contact hole and electrically connected to the semiconductor element, and a wiring electrode (192) arranged on the interlayer insulating film and connected to the embedded electrode. an electrode (19);
The semiconductor substrate is made of silicon or a material having higher rigidity than silicon, and has a thickness (t1) of 100 μm or more,
The semiconductor device according to claim 1, wherein the embedded electrode is made of tungsten, is embedded only in the contact hole, and has a thickness (t2) of 1.2 μm or less. 2. The semiconductor device according to claim 1, wherein said embedded electrode extends in one direction in the surface direction of said semiconductor substrate as a longitudinal direction, and is divided into a plurality of parts in said longitudinal direction. The embedded electrode is connected to an extension portion (191a) extending with one direction in the surface direction of the semiconductor substrate as a longitudinal direction, and is connected to the extension portion, and forms an acute angle (θ) with the longitudinal direction. and a bent portion (191b) that is bent in a state of
2. The semiconductor device according to claim 1, wherein the extending portions connected to the same bent portion are overlapped in a crossing direction crossing the longitudinal direction.

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