JP2023082459A - Model creation method and program - Google Patents

Abstract

To provide a model creation method for modeling a relationship between an internal voltage and a drain current of a transistor.SOLUTION: A model creation process includes an internal voltage calculation step S106 of calculating internal voltages Vgsi and Vdsi by using a gate voltage measurement value for expressing a measurement value of a gate voltage VG of a transistor, a drain voltage measurement value for expressing a measurement value of a drain voltage VD of a transistor, and a middle value ID_middle of a drain current calculation value for expressing a drain current calculated by a current source model, a current calculation step S107 of calculating a drain current calculation value by the current source model by using an internal voltage, and an update step S109 for updating a parameter of the current source model by using an error between the drain current calculation value, and a drain current measurement value for expressing a measurement value of a drain current ID(n) of a transistor. Until parameters of the current source model converge, a first loop process including the current calculation step and the update step is repeated.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a model creation method and program.

Transistors are modeled for circuit design and the like. For example, Non-Patent Document 1 discloses a technique for creating a model of a GaN (gallium nitride) FET (Field Effect Transistor).

GaN FET transistor model extraction / IVCAD, Internet <URL: https://www.youtube.com/watch?v=Ihbg60DqRlU&t=300s>

In order to create a transistor model, it is necessary to model the relationship between the built-in voltage and the drain current.

An object of the present disclosure is to provide a model creation and a program capable of modeling the relationship between the built-in voltage and the drain current of a transistor.

A model creation method of the present disclosure is a model creation method for creating a current source model representing a relationship between a built-in voltage and a drain current of a transistor, comprising: a gate voltage measurement value representing a measured value of the gate voltage of the transistor; a built-in voltage calculation step of calculating the built-in voltage using a measured drain voltage representing the measured drain voltage of the transistor and an intermediate value of the calculated drain current representing the drain current calculated by the current source model; , a current calculation step of calculating a drain current calculated value by the current source model using the built-in voltage; an updating step of updating the parameters of the current source model using the The computer does that.

The present disclosure can be implemented not only as a model generation method that executes such characteristic steps, but also as a model generation device that includes a processing unit that executes such characteristic steps, or as a model generation device that includes a processing unit that executes such characteristic steps. It can be realized as a program for causing a computer to execute the steps. Moreover, all or part of the model generation device can be realized as a semiconductor integrated circuit, or a model generation system including the model generation device can be realized.

According to the present disclosure, it is possible to model the relationship between the built-in voltage and the drain current of a transistor.

FIG. 1 is a diagram showing an example of an equivalent circuit of a transistor used for a large signal model. FIG. 2 is a diagram schematically showing a conventional example of a method of creating a current source model. FIG. 3 is a diagram showing an example of the hardware configuration of the model creation device according to the first embodiment. FIG. 4 is a diagram showing an example of the functional configuration of the model creation device according to the first embodiment. FIG. 5 is a flowchart showing an example of current source model creation processing according to the first embodiment. FIG. 6 is a diagram schematically showing how the drain current calculated by the current source model converges. FIG. 7 is a diagram illustrating an example of current collapse. FIG. 8 is a diagram showing an example of the functional configuration of a model creating device according to the second embodiment. FIG. 9 is a flowchart showing an example of current source model creation processing according to the second embodiment. FIG. 10 is a flowchart showing an example of weight calculation processing according to the second embodiment. FIG. 11 is a diagram illustrating an example of load line calculation. FIG. 12 is a diagram showing an example of area definition. FIG. 13 is a diagram illustrating an example of distance calculation for calculating weights.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure will be listed and described.

[1] A model creation method according to one aspect of the present disclosure is a model creation method for creating a current source model that represents a relationship between a built-in voltage and a drain current of a transistor, and represents a measured value of a gate voltage of the transistor. Calculating the built-in voltage using a measured gate voltage, a measured drain voltage representing the measured drain voltage of the transistor, and a calculated drain current representing the drain current calculated by the current source model. a current calculation step of calculating a calculated drain current by the current source model using the built-in voltage; and a drain representing the calculated drain current and a measured value of the drain current of the transistor. an updating step of updating the parameters of the current source model using the error from the current measurement, the current calculating step and the updating step until the parameters of the current source model converge. The computer executes repeating the first loop process.

After calculating the built-in voltage, the calculation of the drain current calculation value and the updating of the parameters are repeated until the parameters of the current source model converge. Therefore, the built-in voltage does not change while the calculation of the drain current calculated value and the update of the parameters are repeated. This allows the parameters of the current source model to converge.

[2] In [1], the computer repeats a second loop process including the built-in voltage calculation step and the first loop process until the drain current calculated value converges. This allows the parameters of the current source model to be updated to fit the drain voltage measurements.

[3] In [2], the intermediate value is the drain current calculated value calculated in the second loop processing in the nth iteration and the drain current calculated in the second loop processing in the n−1th iteration. This is an intermediate value between the calculated drain current value and the calculated drain current value. This ensures the convergence of the calculated drain current.

[4] In [1] to [3], including a weight calculation step of calculating a weight for the drain current measurement value using the drain voltage measurement value and the drain current measurement value, and multiplying the weight by The error is used to determine whether the parameters of the current source model have converged.

[5] In [4], the weight calculation step uses the operating point of the large-signal operation of the transistor, the drain voltage measurement value, and the drain current measurement value to calculate the load line of the large-signal model. and weighting the drain current measurements such that the drain current measurements closer to the load line are weighted higher and the drain current measurements further away from the load line are weighted lower. calculate.

[6] A program according to one aspect of the present disclosure stores a gate voltage measurement value representing a measured value of the gate voltage of the transistor in a computer for creating a current source model representing the relationship between the built-in voltage and the drain current of the transistor. and an intermediate value of the measured drain voltage representing the measured drain voltage of the transistor and the calculated drain current representing the drain current calculated by the current source model to calculate the built-in voltage. a current calculation step of calculating a drain current calculated value by the current source model using the built-in voltage; the drain current calculated value; and a drain current measured value representing a measured drain current of the transistor. A first loop including the current calculation step and the update step until the parameters of the current source model converge, and an update step of updating the parameters of the current source model using the error of Repeat the process.

After calculating the built-in voltage, the calculation of the drain current calculation value and the updating of the parameters are repeated until the parameters of the current source model converge. Therefore, the built-in voltage does not change while the calculation of the drain current calculated value and the update of the parameters are repeated. This allows the parameters of the current source model to converge.

[Details of the embodiment of the present disclosure]
A first embodiment and a second embodiment of the present disclosure will be described in detail below, but the present disclosure is not limited to these. In addition, in this specification and the drawings, substantially the same components may be denoted by the same reference numerals, thereby omitting duplicate descriptions.

The first and second embodiments of the present disclosure are a modeling device that models the relationship between built-in voltage and drain current in order to create a transistor model (also called a large-signal model). Regarding. At least part of each embodiment described below may be combined arbitrarily.

(transistor model)
A transistor model (large signal model of a transistor) is a model of a circuit as shown in FIG. FIG. 1 shows an equivalent circuit of a transistor used for the large signal model.

In FIG. 1, G is gate, D is drain, S is source, R is resistance, L is inductance, I is current, V is voltage, and C is capacitance. Regarding the subscripts given to R, L, I, V and C, G and g represent gate, D and d represent drain, s represents source, and i represents intrinsic.

It is necessary to accurately model the relationship between the built-in voltages V _gsi and V _dsi and the drain current _ID . This is because the drain current I _D is determined by the built-in voltages V _gsi and V _dsi , as indicated by the dashed line 1000 in FIG.

That is, it is necessary to accurately obtain the function f that satisfies I _D =f(V _gsi , V _dsi ). Hereinafter, the model represented by this function f will be called a current source model.

(Conventional example of current source model creation method)
It is known that the built-in voltages V _gsi and V _dsi can be calculated as follows.

V _gsi =V _G -I _D ×R _s
V _dsi = V _D −I _D ×(R _s +R _d )
It should be noted that R _s , R _s and R _d are generally known or readily measurable.

In a conventional method for _{creating a current source model, ID = f(V gsi , V dsi )} and _{V gsi} and _Vdsi are calculated and iterative parameter updates of the function f to minimize the error with the _ID measurements. FIG. 2 schematically shows this. FIG. 2 shows parameter update in a certain n-th iteration number of the conventional example of the current source model creation method.

As shown in _{FIG. 2, in the conventional example, the drain current I D ( n} ^{) =} f(V _gsi ^{( n)} , V _dsi ⁽ⁿ⁾ ) and the built-in voltages V _gsi ⁽ⁿ⁺¹⁾ and V _dsi ⁽ⁿ⁺¹⁾ to be used in the next iteration. Also, the error between I _D ⁽ⁿ⁾ and the I _D measurement is used to update the parameters of the function f to minimize this error.

Here, when calculating the built-in voltage V _gsi ⁽ⁿ⁺¹⁾ , using the V _G measurement value and the drain current I _D ⁽ⁿ⁾ , the above formula V _gsi =V _G −I _D ×R _s calculate. Similarly, in calculating V _dsi ⁽ⁿ⁺¹⁾ , the V _D measurement and the drain current I _D ⁽ⁿ⁾ are used to calculate V _dsi =V _D −I _D ×(R _s +R _d ). Therefore, in the conventional example, the values of the built-in voltages V _gsi ⁽ⁿ⁺¹⁾ and V _dsi ⁽ⁿ⁺¹⁾ also change whenever the value of the drain current I _D ⁽ⁿ⁾ changes. Therefore, depending on the transistor to be modeled (for example, a gallium nitride high electron mobility transistor (GaN HEMT (High Electron Mobility Transistor)), etc.), the parameters of the function f do not converge, making modeling impossible, Manual parameter adjustment may be required for modeling.

(First embodiment)
A model creating apparatus 10 capable of creating a current source model f with higher accuracy than the conventional example described above will be described below. Note that the model generation device 10 may be configured as one element of a model generation system including the model generation device 10, for example.

First, the hardware configuration of the model creation device 10 according to this embodiment will be described with reference to FIG. As shown in FIG. 3, the model generating apparatus 10 according to the present embodiment has the hardware configuration of a general computer or computer system. , a communication I/F 104 , a processor 105 and a memory device 106 . Also, each of these pieces of hardware is connected via a bus 107 so as to be able to communicate with each other.

The input device 101 is, for example, a keyboard, mouse, touch panel, physical button, or the like. The display device 102 is, for example, a display, a display panel, or the like. Note that the model creation device 10 does not have to include at least one of the input device 101 and the display device 102 .

The external I/F 103 is an interface with the recording medium 103a. The model creation device 10 can perform reading and writing of the recording medium 103a via the external I/F 103. FIG. Examples of the recording medium 103a include a CD (Compact Disc), a DVD (Digital Versatile Disk), an SD memory card (Secure Digital memory card), a USB (Universal Serial Bus) memory card, and the like.

A communication I/F 104 is an interface for connecting the model generating device 10 to a communication network. The processor 105 is, for example, various arithmetic units such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). The memory device 106 is, for example, various storage devices such as HDD (Hard Disk Drive), SSD (Solid State Drive), RAM (Random Access Memory), ROM (Read Only Memory), and flash memory.

The model generating apparatus 10 according to the present embodiment, having the hardware configuration shown in FIG. 3, can implement various processes including a current source model generating process, which will be described later. Note that the hardware configuration shown in FIG. 3 is an example, and the model generating device 10 may include, for example, a plurality of processors 105, a plurality of memory devices 106, or other Various hardware not shown (for example, semiconductor integrated circuits other than CPU and GPU) may be provided.

Next, the functional configuration of the model generation device 10 according to this embodiment will be described with reference to FIG. As shown in FIG. 4, the model creation device 10 according to this embodiment has a model creation processing unit 201 and a storage unit 202 . The model generation processing unit 201 is implemented by, for example, processing that causes the processor 105 to execute one or more computer programs stored in the memory device 106 . Also, the storage unit 202 is realized by a memory device 106 such as an HDD or an SSD, for example. One or more computer programs that implement the model generation processing unit 201 may be stored in the recording medium 103a, or may be downloaded from a predetermined server device or the like via the communication I/F 104, for example.

The model creation processing unit 201 creates a current source model f using the _VG measurement value, _VD measurement value and _ID measurement value stored in the storage unit 202 . That is, the model generation processing unit 201 learns the parameters of the current source model f using the _VG measured value, _{the VD} measured value, and the _ID measured value as learning data. Here, the model generation processing unit 201 includes a current calculation unit 211 that calculates the drain current _ID , an internal voltage calculation unit 212 that calculates the internal voltages V _gsi and V _dsi , and a current source model f parameter updater. A parameter updating unit 213 is included. Any function having parameters to be learned can be used as the function f representing the current source model.

The storage unit 202 stores the _VG measured value, the _VD measured value and the _ID measured value given to the model generating device 10 . The storage unit 202 also stores the parameters of the current source model f.

Here, _VG measurement, _VD measurement, and _ID measurement are pre-measured gate voltage _VG measurement, drain voltage _VD measurement, and drain current _ID measurement, respectively. In the following, where t is an index representing the measurement time, V _G measured value V _G '(t), V _D measured value V _D '(t) and ID measured value _ID at t = 1, ..., _T '(t) is given to the model generating device 10 . _At this time _{, V G ' =} (V _{G '} (1), . Define. _{Similarly, V D ' = (} V _{D '} (1), . defined as _{Similarly ,} ID _' =( _{ID '} (1), _. defined as If there is no misunderstanding, the T-dimensional vectors V _G ', V _D ', and I _D ' may also be referred to as the V _G measurement value, the V _D measurement value, and the _ID measurement value, respectively.

Next, the current source model creating process according to this embodiment will be described with reference to FIG. This current source model creation process includes a small loop (loop from step S107 to step S109) for fixing the built-in voltage and updating the parameters, and a large loop for changing the drain current and recalculating the built-in voltage by the bisection method ( loop from step S105 to step S111). In the following, it is assumed that the parameters of the current source model f have been initialized by a known method or the like.

The built-in voltage calculation unit 212 of the model generation processing unit 201 calculates _the built-in voltages V _gsi and V _dsi using the V _G measurement value, V _D measurement value, and ID measurement value stored in the storage unit 202 ( step S101). Specifically, the built-in voltage calculator 212 calculates the built-in voltages V _gsi and V _dsi as follows.

V _gsi =V _G '-R _s I _D '
V _dsi =V _D '-(R _s +R _d )I _D '
Both V _gsi and V _dsi are T-dimensional vectors, V _gsi =(V _gsi (1), . . . , V _gsi (T)), V _dsi =(V _dsi (1), . , V _dsi (T)). Also note that both R _s and R _d are scalars. _That is, for _{each t} = _{1 , .} −(R _s +R _d )I _D ′(t).

The parameter updating unit 213 of the model creation processing unit 201 initializes n, which is an index that increases by 1 each time the large loop is executed, to 1 (step S102).

The current calculation unit 211 of the model creation processing unit 201 calculates the drain current I _D ⁽¹⁾ when n=1 using the built-in voltages V _gsi and V _dsi calculated in step S101 (step S103 ). Specifically, the current calculator 211 calculates the drain _current I D ⁽¹⁾ by I _D (1) = f(V _gsi , V _dsi ⁾ . Note that _ID ⁽¹⁾ is a T-dimensional vector, _ID ⁽¹⁾ = ( _ID ⁽¹⁾ (1), ..., _ID ⁽¹⁾ (T)) = (f(V _gsi ( 1), V _dsi (1)), . . . , f(V _gsi (T), V _dsi (T))). That is, for each t=1, . . . , T, I _D ⁽¹⁾ (t)=f(V _gsi (t), V _dsi (t)).

The current calculation unit 211 of the model creation processing unit 201 sets _ID ⁽¹⁾ /2 to the variable _{ID_middle} in which the intermediate value of the drain current is stored (step S104). Specifically, the current calculation unit 211 calculates _{ID_middle} =( _{ID_middle} (1), . . . , _{ID_middle} (T))=( _ID ⁽¹⁾ (1)/2, . . . , _ID ⁽¹⁾ Set (T)/2).

The parameter updating unit 213 of the model creation processing unit 201 adds 1 to n (step S105).

The built-in voltage calculation unit 212 of the model generation processing unit 201 calculates the built-in voltages V _gsi and V _dsi using _{ID_middle} , the V _G measurement value, and the V _D measurement value (step S106). Specifically, the built-in voltage calculator 212 calculates the built-in voltages V _gsi and V _dsi as follows.

V _gsi = V _G ′−R _s I _{D_middle}
V _dsi =V _D ′−(R _s +R _d )I _{D_middle
That is} , for _each t ₌ 1 _{, .} Let (R _s +R _d ) _{ID_middle} (t).

The current calculator 211 of the model creation processor 201 calculates the drain current I _D ⁽ⁿ⁾ using the built-in voltages V _gsi and V _dsi calculated in step S106 (step S107). Specifically, the current calculator 211 calculates the drain current I _D (n) by I _D ⁽ⁿ⁾ = f(V _gsi , V _dsi ⁾ . _ID ⁽ⁿ⁾ = ( _ID ⁽ⁿ⁾ (1), ..., _ID ⁽ⁿ⁾ (T)) = (f (V _gsi (1), V _dsi (1)), ... , f(V _gsi (T), V _dsi (T))). That is, for each t=1, . . . , T, I _D ⁽ⁿ⁾ (t)=f(V _gsi (t), V _dsi (t)).

The parameter updating unit 213 of the model creation processing unit 201 determines whether or not the parameters of the current source model f have converged (step S108). For example, the parameter update unit 213 determines that the parameters have converged when the error between I _D ⁽ⁿ⁾ and I _D ' is equal to or less than a predetermined threshold value _th1 . It is sufficient to determine that it has not converged. Here, various errors (error functions) E between I _D ⁽ⁿ⁾ and I _D ′ can be used. For example, the following mean square error can be used.

ただし、これは一例であって、平均二乗誤差以外にも、例えば、平均絶対誤差等といった他の誤差（誤差関数）を用いることも可能である。

However, this is only an example, and other errors (error functions) such as mean absolute error can be used other than the mean squared error.

When it is determined in step S108 that the parameters of the current source model f have not converged, the parameter updating unit 213 of the model creation processing unit 201 uses the error between I _D ⁽ⁿ⁾ and I _D ' to , the parameters of the current source model f are updated so as to minimize the error (step S109). Various optimization methods can be used to update the parameters of the current source model f. For example, the Newton method or the like can be used to update the parameters of the current source model f.

Note that when step S109 is executed, the model creation processing unit 201 returns to step S107. As a result, with the internal voltages V _gsi and V _dsi fixed, the small loop (steps S107 to S109) is repeatedly executed until the parameters of the current source model f converge.

On the other hand, if it is determined in step S108 that the parameters of the current source model f have converged, the parameter updating unit 213 of the model generation processing unit 201 determines whether or not I _D ⁽ⁿ⁾ has converged. (Step S110). The parameter updating unit 213 determines that I D (n) has converged when, _for example, the difference between I _D ⁽ⁿ⁾ and I _D ^{( n−1)} is equal to or less than a predetermined threshold th ₂ . If not, it should be determined that I _D ⁽ⁿ⁾ has not converged. Here, various values can be used as the difference between I _D ⁽ⁿ⁾ and I _D ⁽ⁿ⁻¹⁾ . For example, the following mean absolute error can be used.

ただし、これは一例であって、平均絶対誤差以外にも、例えば、Ｉ_Ｄ ^（ｎ）とＩ_Ｄ ^{（ｎ－１）}とのＬ１ノルムやユークリッド距離、その他の任意の距離等を、Ｉ_Ｄ ^（ｎ）とＩ_Ｄ ^{（ｎ－１）}との差として用いることも可能である。

However, this is only an example, and other than the mean absolute error, for example, the L1 norm or Euclidean distance between I _D ⁽ⁿ⁾ and I _D ⁽ⁿ⁻¹⁾ , other arbitrary distances, etc. can be used as I _D ^{( n)} and I _D ⁽ⁿ⁻¹⁾ .

If it is determined in step S110 above that I _D ⁽ⁿ⁾ has not converged, the current calculation unit 211 of the model generation processing unit 201 _calculates (I _D ⁽ⁿ⁾ + I _D ^{(n− 1)} )/2 is set (step S111). That is, the current calculator 211 sets the intermediate value between I _D ⁽ⁿ⁾ and I _D ⁽ⁿ⁻¹⁾ as I _{D_middle} . Specifically, the current calculation unit 211 calculates _{ID_middle} = ( _{ID_middle} (1), ..., _{ID_middle} (T)) = (( _ID ⁽ⁿ⁾ (1) + _ID ^(n-1) ( 1))/2, . . . , ( _ID ⁽ⁿ⁾ (T)+ _ID ⁽ⁿ⁻¹⁾ (T))/2). Note that _{ID_middle} is set to an intermediate value between _ID ^{( n)} _{and ID} ^{( n-1)} following the dichotomy, but is not limited to _this . ^-1) may be proportionally divided by a certain predetermined ratio.

Note that when step S111 is executed, the model creation processing unit 201 returns to step S105. This causes the built-in voltages V _gsi and V _dsi to be recalculated using _{ID_middle} , and then the small loop is executed again.

On the other hand, if it is determined in step S110 that I _D ⁽ⁿ⁾ has converged, the model generation processing unit 201 terminates the current source model generation processing. As a result, a current source model f having learned parameters is created.

As described above, the model generation device 10 according to the present embodiment includes a small loop that fixes the built-in voltage and updates parameters, and a large loop that changes the drain current and recalculates the built-in voltage by the bisection method. A current source model f is created by the algorithm described. In this algorithm, since the built-in voltage is fixed without changing during execution of the small loop, it is possible to prevent the parameters of the current source model f from converging and diverging.

In addition, in the large loop, the drain current value _{ID_middle} is calculated by _the bisection method (or a similar method), and the internal voltages V _gsi and V _dsi are recalculated using the drain current value _{ID_middle} . Convergence of ⁽ⁿ⁾ = f(V _gsi , V _dsi ) is also guaranteed. For example, on an ID- _{VD plane with ID on} the vertical axis and _VD on the horizontal _axis , the _ID measured value _ID ' and the calculated value _ID ⁽ⁿ⁾ calculated by the current source model f are shown. Then, it becomes like FIG. As shown in FIG. 6, as n increases, the bisection method reduces the difference between I _D ⁽ⁿ⁾ and I _D ⁽ⁿ⁻¹⁾ , thus ensuring the convergence of I _D ⁽ⁿ⁾ and It can be seen that the convergence value accurately fits the _ID measurement value _ID '.

Therefore, according to the model generating apparatus 10 of the present embodiment, it is possible to generate a highly accurate current source model f without requiring, for example, manual parameter adjustment.

(Second embodiment)
A problem called current collapse can occur in gallium nitride high electron mobility transistors (GaN HEMTs). Current collapse is the I _D -V _D waveform on the I _D -V _D plane when the drain current and the drain voltage are measured immediately after applying a relatively large drain voltage V _D (this is called stress) to the GaN HEMT. It is a phenomenon that the is distorted. FIG. 7 shows the I _D -V _D waveform of the GaN HEMT without stress and the I _D -V _D waveform of the GaN HEMT immediately after stress application. As shown in FIG. 7, it can be seen that current collapse occurs immediately after stress application, and the I _D -V _D waveform is distorted.

When a transistor such as a GaN HEMT in which current collapse can occur is targeted for modeling, if the I _D -V _D waveform is distorted due to the influence of the current collapse, the parameters of the function f do not converge and the model cannot be modeled ( Or, even if it can be modeled, the accuracy is low). For this reason, in the conventional examples, it was often necessary to manually adjust the parameters for modeling. On the other hand, in modeling, it is often not necessary to create a current source model that fits all measured values. is often sufficient for purposes such as circuit design.

Therefore, in the following, a current source model f can be created with high accuracy by weighting a transistor in which a current collapse can occur and weighting it so as to fit the measured values on and around the load line. The model generating device 10 will be described.

In addition, in this embodiment, differences from the first embodiment will be mainly described, and the description of the same components as in the first embodiment will be omitted (that is, the The first embodiment can be applied as it is to matters not specified.).

First, the functional configuration of the model generation device 10 according to this embodiment will be described with reference to FIG. As shown in FIG. 8, the model creation processing unit 201 of the model creation device 10 according to the present embodiment includes a weight ω _t (where 0≦ω _t ≦100) for each _ID measurement value _ID′ (t). Further included is a weight calculator 214 that calculates . Further, the parameter updating unit 213 according to the present embodiment calculates the error in consideration of the weight ω _t when calculating the error for determining whether the parameters of the current source model f have converged.

Next, the current source model creating process according to this embodiment will be described with reference to FIG. Steps S202 to S208 of this current source model creation process are the same as steps S101 to S107 of the current source model creation process according to the first embodiment, respectively, and steps S210 to S212 are the same as steps S109 to S111. are the same as, respectively, the description thereof will be omitted.

The weight calculation unit 214 of the model generation processing unit 201 uses the V _D measurement value and the _ID measurement value to calculate the weight ω _t (where 0≦ω _t ≦100) for each _ID measurement value I _{D ′} (t). is calculated (step S201). The details of the processing of this step will be described later, and the following description will continue on the assumption that these weights ω _t have been calculated. As will be described later, these weights ω _t are high for measurements in the area on and around the load line, and for measurements in areas away from the load line, close to the operating point and low output. Or it will be a low value for the measured value in the low efficiency region.

Following step S208, the parameter updating unit 213 of the model generation processing unit 201 determines whether or not the parameters of the current source model f have converged (step S209). At this time, the parameter updating unit 213 according to the present embodiment uses the error E considering the weight ω _t as the error between I _D ⁽ⁿ⁾ and I _D ′, for example, the error E is a predetermined is equal to or less than the threshold th ₃ , it is determined that the parameters have converged; otherwise, it is determined that the parameters have not converged. Here, as the error E considering the weight _ωt , for example, the following error may be used.

この数３に示す誤差は、重みω_ｔを係数として持つ平均二乗誤差である。ただし、これは一例であって、これ以外にも、例えば、重みω_ｔを係数として持つ平均絶対誤差等を用いることも可能である。

The error shown in Equation 3 is the mean square error with the weight _ωt as a coefficient. However, this is only an example, and it is also possible to use, for example, an average absolute error having the weight _ωt as a coefficient.

As a result, among the differences between I _D ⁽ⁿ⁾ (t) and I _D ′(t), the influence of the difference corresponding to t with a low weight ω _t on the parameter update can be reduced. Therefore, even when a transistor in which current collapse can occur is modeled, it is possible to prevent the parameter from diverging without convergence, and the accuracy of the measured values on and around the load line can be improved. A well-fitting current source model f can be created.

Next, the weight calculation process in step S201 will be described with reference to FIG.

First, the weight calculator 214 calculates the load line on the I D -V _D plane using the given operating point and the V _D measurements V _{D ′} and I _D measurements I _{D ′} (step S301). Here, the operating point is the value of _VD and _ID determined by a person who designs circuits using a transistor model (for example, a person who designs and manufactures circuits after receiving delivery of transistors). An example of load line calculation will be described below with reference to FIG. 11, with the operating point set to _Q0 =( _{ID_set} , _{VD_set} ). In addition, each measurement point in FIG. 11 is a point obtained by plotting the _ID measured value _ID '(t) and the _VD measured value VD'(t) ( _ID '(t) _{, VD} '(t) ).

The weight calculator 214 calculates the load line by the following Steps 1-1 to 1-5.

Step 1-1: First, the weight calculator 214 calculates θ=arccos(1-I _D '/(I _D '-I _{D_set} )). Note that θ is a T-dimensional vector and is expressed as θ=(θ(1), . . . , θ(T)). Also note that _{ID_set} is a scalar. That _is , for _each t=1 _, .

Step 1-2: Next, the weight calculator 214 calculates the following output power _Pout or efficiency Eff.

P _out =( _ID' - _{ID_set} )*( _{VD_set} - _VD ')*(θ-sin θ*cos θ)/2π
Eff=0.5×(1−V _D ′/V _{D_set} )×(θ−sin θ×cos θ)/sin θ
Both P _out and Eff are T-dimensional vectors, P _out =(P _out (1), ..., P _out (T)), Eff = (Eff (1), ..., Eff ( Note that it is denoted as T)). That is, for _{each t =} 1 _{, .} )−sin θ(t)×cos θ(t))/2π, Eff(t)=0.5×(1−V _D ′(t)/V _{D_set} )×(θ(t)−sin θ(t)×cos θ (t))/sin θ(t).

Step 1-3: Next, when the output power P _out is calculated in Step 1-2 above, the weight calculator 214 calculates the measurement point corresponding to the element with the maximum value among the elements of P _out . That is, when t _max =argmax(P _out (t)), (I _D '(t _max ), V _D '(t _max )) is calculated. Note that this measurement point (I _D '(t _max ), V _D '(t _max )) is also called an output matching point.

On the other hand, when the efficiency Eff is calculated in Step 1-2 above, the weight calculator 214 calculates the measurement point corresponding to the element with the maximum value among the elements of Eff. That is, when t _max =argmax(Eff(t)), (I _D '(t _max ), V _D '(t _max )) is calculated. Note that this measurement point (I _D '(t _max ), V _D '(t _max )) is also called an efficiency matching point.

In the following, let the output matching point or the efficiency matching point be Q ₁ =(I _D '(t _max ), V _D '(t _max )). It should be noted that which of the output matching point and the efficiency matching point is to be calculated is determined in advance by, for example, a circuit designer using a transistor model.

Step 1-4: Next, the weight calculator 214 calculates the following points Q ₂ , Q ₃ , Q ₄ and Q ₅ .

Intersection point Q ₂ of a straight line passing through Q ₀ and Q ₁ and the V _D axis (that is, a straight line of I _D =0)
A perpendicular drawn from _Q1 to the _VD axis and the intersection point _Q3 with the _VD axis
A perpendicular drawn from _Q0 to the _VD axis and the intersection point _Q4 with the _VD axis
Assuming that the distance between _Q3 and _Q4 is H, a point _Q5 on the _VD axis located at a distance H from _Q4 and different from _Q3
Note that the above point _Q5 is also called the off-side maximum operating point.

Step 1-5: Then, the weight calculator 214 calculates a line composed of a line segment passing through Q ₁ , Q ₀ and Q ₂ and a line segment passing through Q ₂ and Q ₅ (in the example shown in FIG. line) is the load line. A line segment passing through Q ₁ , Q ₀ and Q ₂ is also called an on-state load line because the value of _ID is 0 or more. On the other hand, the line segment through _Q2 and _Q5 is also called the off-state load line because the value of _ID is always zero.

Following step S301, the weight calculator 214 calculates the weight ω _t for each measurement point (I _{D ′} (t), V _D ′(t)), and applies the weight ω _t to the _ID measurement value I _D ′. (t) is weighted (step S302). Here, the weight calculator 214 defines a region on the I _D -V _D plane, and then calculates the weight of each measurement point according to the region to which each measurement point belongs and the distance to the load line.

First, definition of regions on the I _D -V _D plane will be described with reference to FIG. The weight calculator 214 defines a region on the I _D -V _D plane by the following Steps 2-1 to 2-7. Here, below, in the I _D -V _D plane, the smallest area containing all measurement points {(I _D '(t), V _D '(t)) | t = 1, ..., T} Let W be For example, the area W corresponds to the area including all the measurement points {(I _D '(t), V _D '(t))|t=1, . . . , T} and having the smallest area. do. Note that the power match point or efficiency match point is a point on the boundary of region W. FIG.

Step 2-1: The weight calculator 214 calculates a straight line a ₁ parallel to the on-state load line and passing through the origin O of the I _D -V _D plane.

Step 2-2: The weight calculator 214 calculates a straight line _a2 which is parallel to the on-state load line and passes between the straight line _a1 and the on-state load line. In other words, the weight calculator 214 calculates a straight line _a2 that is parallel to the on-state load line and passes through the midpoint of a perpendicular drawn from the on-state load line to the straight line _a1 .

Step 2-3: The weight calculator 214 calculates a straight line a ₃ parallel to the _ID axis and passing through the operating point Q ₀ .

Step 2-4: The weight calculator 214 calculates a straight line _a4 parallel to the _VD axis and passing through the operating point _Q0 .

Step 2-5: The weight calculator 214 calculates a straight line _a5 which is parallel to the _VD axis and which passes through the middle of the straight line _a4 and the _VD axis. In other words, the weight calculator 214 calculates a straight line _a5 that is parallel to the _VD axis and passes through the midpoint of the perpendicular drawn from the straight line _a4 to the _VD axis.

Step 2-6: The weight calculator 214 calculates a straight line a ₆ parallel to the _ID axis and passing through Q ₂ .

Step 2-7: The weight calculator 214 defines regions W ₁ , W ₂ , W ₃ and W ₄ as follows.

_W1 is the area surrounded by the boundary of the area W, the straight line _a2 , the _VD axis, the straight line _a3 , and the load line.
_W2 is the area surrounded by the boundary of area W, the load line, and straight line _a3
The area surrounded by the boundary of the area W, the straight lines _a5 , the straight lines _a6 , and the _VD axis is _{W3
W 4 _ _}
Next, according to the area to which each measurement point (I _D '(t), V _D '(t)) belongs and the distance to the load line, the measurement point (I _D '(t), V _D '(t ))) will be described with reference to _FIG . The weight calculator 214 calculates the weight ω _t of each measurement point (I _D '(t), V _D '(t)) by the following Steps 3-1 to 3-7.

Step 3-1: The weight calculator 214 calculates the distance _Δ1 representing the length of the perpendicular drawn from the on-state load line to the straight line _a2 .

Step 3-2: For each measurement point (I _D '(t), V _D '(t))εW ₁ , the weight calculator 214 determines the length of the perpendicular drawn from the measurement point to the on-state load line. Δ ₂ (t) representing , respectively.

Step 3-3: For each measurement point (I _D '(t), V _D '(t))εW ₂ , the weight calculation unit 214 calculates a straight line a Calculate the distance Δ ₃ (t) representing the length of the perpendicular dropped to ₃ respectively.

Step 3-4: The weight calculator 214 calculates the length of the perpendicular drawn from each measurement point (I _D '(t), V _D '(t))εW ₂ to the straight line a ₃ Calculate the respective distance Δ ₄ (t) to represent.

Step 3-5: The weight calculator 214 calculates the distance _Δ5 representing the length of the perpendicular drawn from the _VD axis to the straight line _a5 .

Step 3-6: The weight calculation unit 214 calculates the length of the perpendicular drawn from each measurement point (I _D '(t), V _D '(t)) ∈ W ₃ to the straight line a ₅ from the measurement point. Calculate the respective distance Δ ₆ (t) to represent.

Step 3-7: The weight calculator 214 calculates the weight ω _t of each measurement point (I _D '(t), V _D '(t)) as follows.

If (I _D '(t), V _D '(t))εW ₁ then ω t = 100 _x cos as c ₁ (t) = (Δ ₂ (t)/Δ ₁ ) x π/2 ( _c1 (t))
_If (I _D '(t) _, V _D '(t)) _{εW 2} then ω _t = 100×cos(c ₂ (t))
If (I _D '(t), V _D '(t))εW ₃ , then ω _t = 100 x cos as c ₃ (t) = (Δ ₆ (t)/Δ ₅ ) x π/2 ( _c3 (t))
ω _t = 0 if (I _D '(t), V _D '(t)) ∈ W ₄
This gives for each measurement point (I _D '(t), V _D '(t))εW its weight ω _t . In the above calculation method, a weight with a large value is obtained for the measured values on and around the load line, and the weight value decreases as the distance from the load line increases. The weight value is set to 0. Therefore, it becomes possible to update the parameters of the current source model f so as to fit the measured values on and around the load line.

The first embodiment and the second embodiment of the present disclosure have been described in detail above, but the present disclosure is not limited to these specific embodiments, and within the scope described in the claims, Various modifications and alterations are possible.

10: model creation device 101: input device 102: display device 103: external I/F
103a: Recording medium 104: Communication I/F
105: Processor 106: Memory Device 107: Bus 201: Model Creation Processing Unit 202: Storage Unit 211: Current Calculation Unit 212: Internal Voltage Calculation Unit 213: Parameter Update Unit 214: Weight Calculation Unit

Claims (6)

A model creation method for creating a current source model representing a relationship between a built-in voltage and a drain current of a transistor, comprising:
intermediate between a measured gate voltage representing the measured gate voltage of the transistor, a measured drain voltage representing the measured drain voltage of the transistor, and a calculated drain current representing the drain current calculated by the current source model. a built-in voltage calculation step of calculating the built-in voltage using
a current calculation step of calculating a drain current calculated value by the current source model using the built-in voltage;
updating parameters of the current source model using the error between the calculated drain current and a measured drain current representing the measured drain current of the transistor;
includes
A model creation method in which a computer executes repeating a first loop process including the current calculation step and the update step until the parameters of the current source model converge. 2. The model creation method according to claim 1, wherein said computer repeats a second loop process including said built-in voltage calculation step and said first loop process until said drain current calculated value converges. . The intermediate value is
An intermediate value between the drain current calculated value calculated in the second loop process in the n-th iteration and the drain current calculated value calculated in the second loop process in the n-1th iteration, The method of creating a model according to claim 2. a weight calculation step of calculating a weight for the drain current measurement using the drain voltage measurement and the drain current measurement;
4. The model creation method according to any one of claims 1 to 3, wherein the error multiplied by the weight is used to determine whether the parameters of the current source model have converged. The weight calculation step includes:
calculating a load line for the large-signal model using the operating point for large-signal operation of the transistor, the measured drain voltage, and the measured drain current;
calculating weights for the drain current measurements such that the drain current measurements closer to the load line are weighted higher and the drain current measurements further away from the load line are weighted lower; 5. The model creation method according to claim 4. A computer for creating a current source model that expresses the relationship between the transistor's built-in voltage and drain current,
intermediate between a measured gate voltage representing the measured gate voltage of the transistor, a measured drain voltage representing the measured drain voltage of the transistor, and a calculated drain current representing the drain current calculated by the current source model. a built-in voltage calculation step of calculating the built-in voltage using
a current calculation step of calculating a drain current calculated value by the current source model using the built-in voltage;
updating parameters of the current source model using the error between the calculated drain current and a measured drain current representing the measured drain current of the transistor;
and
A program for repeating a first loop process including the current calculation step and the update step until the parameters of the current source model converge.

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