JP2023075428A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of increasing reliability while reducing inductance.SOLUTION: A semiconductor device 11 includes a circuit pattern 17, a semiconductor chip, a first electrode plate 31, and a second electrode plate 32. The first electrode plate 31 includes a first part 41a, a second part 42a, and a third part 43. The second electrode plate 32 includes a fourth part 44a, a fifth part 45a, and a sixth part 46. The second part 42a and the fifth part 45a are placed with a space in a first direction. The third part 43 and the sixth part 46 are placed in parallel, with a space in a second direction. The third part 43 includes a projection region projecting to the side of the fifth part 45a with respect to the second end part 62a in the first direction.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to semiconductor devices.

A semiconductor module in which two electrode plates are arranged in parallel is known (see, for example, Patent Document 1). The semiconductor module disclosed in Patent Document 1 includes a positive electrode pad, a first electrode plate electrically connected to the positive electrode pad and having a flat plate portion, a negative electrode pad, and a negative electrode pad. A second electrode plate is provided which is electrically connected and has a flat plate portion. According to Patent Document 1, the first electrode plate and the second electrode plate are arranged in parallel plates.

WO2020/035931

According to Patent Document 1, the electrode plate is formed by bending one plate-like member. A bent portion of the electrode plate is attached to an electrode pad on the circuit board. At this time, in order to reduce the inductance, the two parallel plates are attached close to each other.

Here, if the two electrode plates are brought closer together, the distance between the electrode plates becomes too small, and there is a risk that the electrode plates will come into contact with each other and cause a short circuit. Such a semiconductor device cannot be improved in reliability. In particular, when forming an electrode plate by bending a plate-like member, the accuracy of bending is low, so there is a high possibility that the slanted portions will come into contact with each other. Also, when attaching the electrode plate, ultrasonic bonding may be used. Then, since the direction of vibration during ultrasonic bonding becomes perpendicular to the thickness direction of the electrode plate, the electrode plate tends to tilt and deform. This further increases the risk of short-circuiting due to contact between the electrode plates.

Therefore, it is an object to provide a semiconductor device whose reliability can be improved while reducing inductance.

A semiconductor device according to the present disclosure includes a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board in a first direction; arranged on the circuit pattern; It comprises a semiconductor chip electrically connected to the circuit pattern, a first electrode plate electrically connected to the first circuit board, and a second electrode plate electrically connected to the second circuit board. The first electrode plate is arranged so as to be continuous with a first portion joined to the first circuit board and a first end on one side of the first portion in a first direction, and is arranged in the thickness direction of the circuit pattern. a second portion extending in two directions; a third portion continuous with a second end on one side of the second portion in the second direction and spaced apart from the first portion in the second direction; including. The second electrode plate has a fourth portion joined to the second circuit board, and a fifth portion arranged in series with a third end on one side of the fourth portion in the first direction and extending in the second direction. and a sixth portion continuous with a fourth end on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction. The second portion and the fifth portion are spaced apart in the first direction. The third portion and the sixth portion are spaced apart and parallel in the second direction. The third portion includes a protruding region protruding toward the fifth portion from the second end in the first direction.

According to the above semiconductor device, reliability can be improved while reducing inductance.

FIG. 1 is a schematic plan view of a semiconductor device according to Embodiment 1. FIG. FIG. 2 is a schematic side view of the semiconductor device shown in FIG. 1 when illustration of a frame is omitted. FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. 1 when illustration of the second electrode plate is omitted. FIG. 4 is a schematic plan view of the semiconductor device shown in FIG. 1 when illustration of the first electrode plate, the second electrode plate, and the third electrode plate is omitted. FIG. 5 is a schematic perspective view showing an enlarged part of a first electrode plate and a part of a second electrode plate included in the semiconductor device shown in FIG. FIG. 6 is a schematic plan view of the second electrode plate. FIG. 7 is a schematic side view of the second electrode plate. FIG. 8 is a schematic side view of the second electrode plate. FIG. 9 is a schematic plan view of the second electrode plate before being folded. FIG. 10 is a schematic plan view of the first electrode plate. FIG. 11 is a schematic side view of the first electrode plate. FIG. 12 is a schematic side view of the first electrode plate. FIG. 13 is a schematic plan view of the first electrode plate before being folded. FIG. 14 is a schematic side view showing part of the semiconductor device before ultrasonic bonding. FIG. 15 is a schematic side view showing part of the semiconductor device after ultrasonic bonding.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described. A semiconductor device according to the present disclosure includes: a circuit pattern including a first circuit board; a second circuit board arranged apart from the first circuit board in a first direction; It comprises a semiconductor chip electrically connected to the pattern, a first electrode plate electrically connected to the first circuit board, and a second electrode plate electrically connected to the second circuit board. The first electrode plate is arranged so as to be continuous with a first portion joined to the first circuit board and a first end on one side of the first portion in a first direction, and is arranged in the thickness direction of the circuit pattern. a second portion extending in two directions; a third portion continuous with a second end on one side of the second portion in the second direction and spaced apart from the first portion in the second direction; including. The second electrode plate has a fourth portion joined to the second circuit board, and a fifth portion arranged in series with a third end on one side of the fourth portion in the first direction and extending in the second direction. and a sixth portion continuous with a fourth end on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction. The second portion and the fifth portion are spaced apart in the first direction. The third portion and the sixth portion are spaced apart and parallel in the second direction. The third portion includes a protruding region protruding toward the fifth portion from the second end in the first direction.

In a semiconductor device including the first electrode plate and the second electrode plate, they are arranged to form parallel plates within the semiconductor device in order to reduce inductance. Here, each of the first electrode plate and the second electrode plate may be formed by bending a plate-like member. In this case, a portion that is joined to the circuit pattern, a portion that rises in the thickness direction of the circuit pattern, and a portion that is arranged parallel to the circuit pattern in the frame and constitutes a parallel plate are formed. Here, in order to obtain the effect of reducing the inductance more efficiently, it is necessary to secure as large a region as possible for forming the parallel plates and to reduce the interval. Here, if the bent portions are close to each other, the first electrode plate and the second electrode plate may come into contact with each other during bonding to the circuit pattern, causing a short circuit. In particular, when bonding by ultrasonic bonding, there is a high risk of short-circuiting due to the direction of ultrasonic vibration. If the jointed portions are separated in the first direction in order to reduce the possibility of short-circuiting, the area forming the parallel plates becomes smaller, and the effect of reducing the inductance becomes smaller.

According to the semiconductor device of the present disclosure, since the third portion includes the protruding region that protrudes toward the fifth portion from the second end, a large region forming the parallel plate is secured, and the effect of reducing the inductance is greatly increased. can do. In this case, since the protruding region that protrudes further toward the fifth portion than the second end portion is included, it is possible to reduce the risk that the second end portion will come close to the fifth portion. Therefore, it is possible to reduce the risk of short-circuiting due to contact with the second electrode plate in the region including the second end. As described above, according to such a semiconductor device, reliability can be improved while reducing inductance.

In the semiconductor device described above, the first electrode plate may be a P-type bus bar. The second electrode plate may be an N-type busbar. In such a semiconductor device, the direction of the current flowing through the third portion of the first electrode plate is opposite to the direction of the current flowing through the sixth portion of the second electrode plate, so that a large reduction in inductance can be obtained.

In the above semiconductor device, the first portion and the first circuit board may be ultrasonically bonded. The fourth portion and the second circuit board may be ultrasonically bonded. By doing so, the first part and the first circuit board and the fourth part and the second circuit board can be joined without using a joining material. In this case, since the thickness direction of the projecting region is perpendicular to the vibrating direction during ultrasonic bonding, it is difficult to mechanically deform in the vibrating direction. Therefore, even if the first electrode plate and the second electrode plate are ultrasonically welded, the risk of short-circuiting due to contact with each other is reduced. Therefore, reliability can be improved.

In the above semiconductor device, the first electrode plate may be formed by bending a plate-like member. By doing so, it is possible to manufacture the first electrode plate by punching out a plate-like member as a raw material into a predetermined shape and bending it, so that productivity can be improved.

In the above semiconductor device, the end face of the projecting region facing the fifth portion in the first direction may correspond to the side surface of the first electrode plate. By doing so, it is possible to reduce the possibility that the second end corresponding to the bent portion comes close to the second electrode plate when the plate-like member is bent to form the first electrode plate. Therefore, even if the bending accuracy is low, it is possible to reduce the risk of short-circuiting due to contact due to inclination during bonding.

In the above semiconductor device, the distance between the end surface of the projecting region and the fifth portion may be 1 mm or less. By doing so, it is possible to secure a large area for forming the parallel plates and to further reduce the inductance.

In the above semiconductor device, a pair of first portions may be provided symmetrically with a gap in a third direction orthogonal to the first direction when viewed in the second direction. By doing so, it is possible to efficiently flow a current from the first portion to the third portion through the second portion, thereby further reducing the inductance.

In the above semiconductor device, the distance between the projecting region and the fifth portion may be 80% or less of the distance between the third portion and the sixth portion. By doing so, it is possible to secure a large area for forming the parallel plates and to further reduce the inductance.

[Details of the embodiment of the present disclosure]
Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

(Embodiment 1)
A configuration of the semiconductor device according to the first embodiment of the present disclosure will be described. FIG. 1 is a schematic plan view of a semiconductor device according to Embodiment 1. FIG. From the viewpoint of facilitating understanding, illustration of the sealing resin included in the semiconductor device is omitted in the drawings shown in FIG. 1 and subsequent figures. FIG. 2 is a schematic side view of the semiconductor device shown in FIG. 1 when illustration of a later-described frame body is omitted. FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. 1 when illustration of a second electrode plate, which will be described later, is omitted. FIG. 4 is a schematic plan view of the semiconductor device shown in FIG. 1, omitting a first electrode plate, a second electrode plate, and a third electrode plate, which will be described later. FIG. 5 is a schematic perspective view showing an enlarged part of a first electrode plate and a part of a second electrode plate included in the semiconductor device shown in FIG.

1, 2, 3, 4 and 5, semiconductor device 11 according to the first embodiment includes base plate 12, frame 13, substrate 14, semiconductor chips 21a, 21b and 21c. , 21d, 22a, 22b, 22c, 22d, wires 23a, 23b, 23c, 23d, 24a, 24b, 24c, 24d, 25a, 25b, 25c, 25d, 26a, 26b, 26c, 26d, and press-fit pin 27a. , 27b, 27c, 27d, a first electrode plate 31, a second electrode plate 32, and a third electrode plate 33. As shown in FIG. The first electrode plate 31 is a P terminal and is also called a P-type busbar. The second electrode plate 32 is an N terminal and is also called an N-type busbar. The third electrode plate 33 is an O-terminal and is also called an O-shaped busbar. Each of the first electrode plate 31, the second electrode plate 32 and the third electrode plate 33 is made of a conductive member such as a copper plate. When the semiconductor device 11 is driven, the direction of the current flowing through the first electrode plate 31 and the direction of the current flowing through the second electrode plate 32 are opposite to each other.

The base plate 12 has a rectangular plate shape when viewed in the thickness direction. In this embodiment, the longitudinal direction of the base plate 12 is the X direction, the lateral direction of the base plate 12 is the Y direction, and the thickness direction of the base plate 12 is the Z direction. In this embodiment, the X direction is the first direction, the Z direction is the second direction, and the Y direction is the third direction. The base plate 12 includes a main surface 12a positioned on one side in the thickness direction and a main surface 12b positioned on the other side in the thickness direction. Four through holes 12c, 12d, 12e, and 12f are formed through the four corner regions of the base plate 12 in the thickness direction. That is, the through holes 12c, 12d, 12e, and 12f extend from one main surface 12a of the base plate 12 to the other main surface 12b. The through holes 12c, 12d, 12e, and 12f are used when mounting the semiconductor device 11 at a predetermined location.

The frame 13 is arranged on the base plate 12 . The frame 13 is arranged on the base plate 12 so as to surround the substrate 14 . The frame 13 includes a first wall portion 13a and a second wall portion 13b facing each other in the Y direction, and a third wall portion 13c and a fourth wall portion 13d facing each other in the X direction. A space 19 surrounded by the base plate 12 and the frame 13 is filled with a sealing resin (not shown). For example, epoxy resin, silicone gel, or urethane resin is selected as the type of sealing resin.

A substrate 14 is arranged on one main surface 12 a of the base plate 12 . The substrate 14 includes a metal plate 15 , an insulating plate 16 and circuit patterns 17 . The insulating plate 16 is sandwiched between the metal plate 15 and the circuit pattern 17 . The substrate 14 has a structure in which a metal plate 15, an insulating plate 16, and a circuit pattern 17 are laminated. A metal plate 15 is joined to one main surface 12 a of the base plate 12 . In this manner, substrate 14 is attached to base plate 12 .

The circuit pattern 17 includes a first circuit board 18a, a second circuit board 18b, a third circuit board 18c, a fourth circuit board 18d, a fifth circuit board 18e, a sixth circuit board 18f and a seventh circuit board 18g. The first circuit board 18a, the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f, and the seventh circuit board 18g each have a strip shape extending in the Y direction. The widths in the X direction of the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f and the seventh circuit board 18g are equal. The X-direction width of the first circuit board 18a is wider than the X-direction width of the fourth circuit board 18d. The third circuit board 18c has a band-like region extending in the Y direction. In the X direction, the fourth circuit board 18d, the fifth circuit board 18e, the first circuit board 18a, the second circuit board 18b, the sixth circuit board 18f, and the seventh circuit board 18g are arranged from the order of proximity to the third wall portion 13c. be done. A pair of second circuit boards 18b are formed with an interval in the Y direction. The pair of second circuit boards 18b are arranged adjacent to each other in the Y direction in the region of the third circuit board 18c where the width in the Y direction is narrow. The fourth circuit board 18d and the seventh circuit board 18g respectively constitute so-called auxiliary source wiring patterns. The fifth circuit board 18e and the sixth circuit board 18f respectively constitute a so-called gate wiring pattern.

The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are vertical semiconductor chips in which current flows in the thickness direction. The semiconductor chips 21a, 21b, 21c, and 21d are arranged on the first circuit board 18a at intervals in the Y direction. The semiconductor chips 22a, 22b, 22c, and 22d are arranged on a band-shaped region of the third circuit board 18c with a space in the Y direction. The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are wide bandgap semiconductor chips. A wide bandgap semiconductor chip refers to a semiconductor chip having, as an operating layer, a semiconductor layer made of a material having a bandgap larger than that of silicon. A wide bandgap semiconductor chip has, as an operating layer, a semiconductor layer made of, for example, silicon carbide, gallium nitride, or gallium oxide. Such a wide bandgap semiconductor chip has a high dielectric breakdown voltage and can reduce the resistance of the drift layer, so that the on-resistance can be reduced. The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, 22d are, for example, metal-oxide-semiconductor field effect transistors (MOSFETs). The semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d may have a semiconductor layer made of silicon as an operating layer.

The source pads of the semiconductor chips 21a, 21b, 21c and 21d and the fourth circuit board 18d are connected by wires 23a, 23b, 23c and 23d, respectively. The gate pads of the semiconductor chips 21a, 21b, 21c and 21d and the fifth circuit board 18e are connected by wires 24a, 24b, 24c and 24d, respectively. The source pads of the semiconductor chips 21a, 21b, 21c, 21d and the third circuit board 18c are connected by wires 25a, 25b, 25c, 25d, 26a, 26b, 26c, 26d, respectively. Source pads of the semiconductor chips 22a, 22b, 22c, 22d and the seventh circuit board 18g are connected by wires 23e, 23f, 23g, 23h, respectively. The gate pads of the semiconductor chips 22a, 22b, 22c, 22d and the sixth circuit board 18f are connected by wires 24e, 24f, 24g, 24h, respectively. The source pads of the semiconductor chips 22a, 22b and one second circuit board 18b are connected by wires 25e, 25f, 26e, 26f. The source pads of the semiconductor chips 22c, 22d and the other second circuit board 18b are connected by wires 25g, 25h, 26g, 26h.

The press-fit pins 27a, 27b, 27c, 27d are respectively arranged on the fourth circuit board 18d, the fifth circuit board 18e, the sixth circuit board 18f and the seventh circuit board 18g so as to extend in the Z direction. One end of the press-fit pin 27a in the Z direction is connected to the end on the second wall portion 13b side on the fourth circuit board 18d. One end of the press-fit pin 27b in the Z direction is connected to the end on the second wall portion 13b side on the fifth circuit board 18e. One end of the press-fit pin 27c in the Z direction is connected to the end of the sixth circuit board 18f on the side of the first wall 13a. One end of the press-fit pin 27d in the Z direction is connected to the end of the seventh circuit board 18g on the side of the first wall 13a. The other ends of the press-fit pins 27 a , 27 b , 27 c and 27 d in the Z direction each protrude outside the semiconductor device 11 . Electrical connections between the outside of the semiconductor device 11 and the semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, 22d are secured through the press-fit pins 27a, 27b, 27c, 27d.

Next, first, the configuration of the third electrode plate 33 will be described. The O-terminal, that is, the third electrode plate 33, which is an O-shaped bus bar, is formed by bending a single plate-like member. The third electrode plate 33 includes seventh portions 47 a and 47 b, an eighth portion 48 and a ninth portion 49 .

The seventh portions 47a and 47b are portions electrically connected to the circuit pattern 17, and two of them are formed with an interval in the Y direction. Each of the seventh portions 47 a and 47 b is formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12 . Each of the seventh portions 47a, 47b is parallel to the XY plane. The seventh portions 47a and 47b are joined to the third circuit board 18c at positions avoiding the semiconductor chips 22a, 22b, 22c and 22d when viewed in the Z direction. In this embodiment, the seventh portions 47a, 47b are bonded to the third circuit board 18c by ultrasonic bonding.

The eighth portion 48 is formed so as to extend from each of the seventh portions 47a and 47b and rise from the third circuit board 18c. The eighth portion 48 is formed in a rectangular shape when viewed in the X direction. The eighth portion 48 is parallel to the YZ plane.

The ninth portion 49 is formed continuously from the eighth portion 48 . The ninth portion 49 is parallel to the XY plane. That is, each of the seventh portions 47a and 47b and the ninth portion 49 are parallel. The ninth portion 49 is arranged so as to pass through the fourth wall portion 13d in the X direction. The ninth portion 49 is continuous from the eighth portion 48 and has a rectangular seventh region 57 when viewed in the thickness direction (Z direction) and an eighth region formed so as to protrude from the seventh region 57 in the X direction. 58 and . A through hole 36 is formed through the eighth region 58 in the thickness direction. Third electrode plate 33 is arranged such that parts of seventh region 57 and eighth region 58 are located within space 19 , and the remainder of eighth region 58 and through hole 36 are located outside semiconductor device 11 . Using the eighth region 58 of the third portion 43 and the through hole 36, electrical connection of the third electrode plate 33 to the outside is ensured.

Next, the configuration of the second electrode plate 32 will be described. The N terminal, that is, the second electrode plate 32, which is an N-type bus bar, is formed by bending a single plate-like member. 6 is a schematic plan view of the second electrode plate 32. FIG. 7 and 8 are schematic side views of the second electrode plate 32. FIG. 7 shows the second electrode plate 32 viewed in the Y direction, and FIG. 8 shows the second electrode plate 32 viewed in the X direction. FIG. 9 is a schematic plan view of the second electrode plate 32 before being folded.

6 to 9, the second electrode plate 32 includes fourth portions 44a and 44b, fifth portions 45a and 45b, and a sixth portion . Referring particularly to FIG. 9, the second electrode plate 32 is bent at 90 degrees along dashed lines 37a and 37b and bent 90 degrees along dashed lines 38a and 38b to form the shape shown in FIGS. It is formed.

The fourth portions 44a and 44b are portions that are electrically connected to the circuit pattern 17, and two are formed with an interval in the Y direction. Specifically, the fourth portions 44a and 44b are spaced apart and symmetrical in a third direction (Y direction) perpendicular to the first direction (X direction) when viewed in the second direction (Z direction). A pair is provided so that Each of the fourth portions 44a and 44b is formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12 . Each of the fourth portions 44a, 44b is parallel to the XY plane. The fourth portion 44a is joined to one second circuit board 18b. The fourth portion 44b is joined to the other second circuit board 18b. In this embodiment, the fourth portion 44a is bonded to one of the second circuit boards 18b by ultrasonic bonding. Also, the fourth portion 44b is joined to the other second circuit board 18b by ultrasonic joining.

Two fifth portions 45a and 45b are formed with an interval in the Y direction. Each of the fifth portions 45a and 45b is formed in a rectangular shape when viewed in the X direction. The fifth portions 45a and 45b are arranged continuously with the third end portion 63a on one side of the fourth portions 44a and 44b in the first direction (X direction). Specifically, the fifth portion 45a is formed so as to extend from the fourth portion 44a and rise from one of the second circuit boards 18b. The fifth portion 45b is formed so as to continue from the fourth portion 44b and rise from the other second circuit board 18b. Each of the fifth portions 45a, 45b is parallel to the YZ plane. The fifth portions 45a and 45b are shaped to extend in the second direction.

The sixth portion 46 is formed continuously from each of the fifth portions 45a and 45b. Specifically, the sixth portion 46 continues to the fourth end portion 64a on one side of the fifth portions 45a and 45b in the second direction (Z direction). The sixth portion 46 is spaced apart from the fourth portions 44a, 44b in the second direction. A sixth portion 46 is parallel to the XY plane. That is, each of the fourth portions 44a and 44b and the sixth portion 46 are parallel. The sixth portion 46 is arranged so as to pass through the third wall portion 13c in the X direction. The sixth portion 46 includes a fourth region 54 continuous from the fifth portions 45a and 45b, a fifth region 55 having a rectangular shape when viewed in the thickness direction (Z direction), and a fifth region 55 projecting from the fifth region 55 in the X direction. and a sixth region 56 formed in the . Boundaries of the fourth area 54, the fifth area 55 and the sixth area 56 are indicated by dashed lines in FIG. A through hole 35 is formed through the sixth region 56 in the thickness direction. Part of the fourth region 54 , the fifth region 55 and the sixth region 56 of the second electrode plate 32 are located within the space 19 , and the remainder of the sixth region 56 and the through hole 35 are located outside the semiconductor device 11 . are arranged as follows. The sixth portion 46 of the second electrode plate 32 is mainly a region forming a parallel plate with the first electrode plate 31 . Using the sixth region 56 of the sixth portion 46 and the through hole 35, the electrical connection of the second electrode plate 32 to the outside is ensured.

Next, the configuration of the first electrode plate 31 will be described. The P terminal, that is, the first electrode plate 31, which is a P-shaped bus bar, is formed by bending a single plate-like member. FIG. 10 is a schematic plan view of the first electrode plate 31. FIG. 11 and 12 are schematic side views of the first electrode plate 31. FIG. 11 shows the first electrode plate 31 viewed in the Y direction, and FIG. 12 shows the first electrode plate 31 viewed in the X direction. FIG. 13 is a schematic plan view of the first electrode plate 31 before being folded.

10 to 13, the first electrode plate 31 includes first portions 41a and 41b, second portions 42a and 42b, and a third portion 43. As shown in FIG. Referring particularly to FIG. 13, first electrode plate 31 is formed by bending dashed lines 39a and 39b at 90 degrees and bending dashed lines 40a and 40b at 90 degrees to form the shape shown in FIGS. It is formed.

The first portions 41a and 41b are portions that are electrically connected to the circuit pattern 17, and two are formed with an interval in the Y direction. Specifically, the first portions 41a and 41b are spaced apart and symmetrical in a third direction (Y direction) perpendicular to the first direction (X direction) when viewed in the second direction (Z direction). A pair is provided so that Each of the first portions 41 a and 41 b is formed in a rectangular shape when viewed in the thickness direction (Z direction) of the base plate 12 . Each of the first portions 41a, 41b is parallel to the XY plane. The first portions 41a and 41b are joined to the first circuit board 18a at positions avoiding the semiconductor chips 21a, 21b, 21c and 21d when viewed in the Z direction. In this embodiment, the first portions 41a, 41b are bonded to the first circuit board 18a by ultrasonic bonding. This will be described later.

Two second portions 42a and 42b are formed with an interval in the Y direction. Each of the second portions 42a and 42b is formed in a rectangular shape when viewed in the X direction. The second portions 42a, 42b. It is arranged continuously with the first end 61a on one side of the first portions 41a and 41b in the first direction. Specifically, the second portions 42a and 42b are formed so as to extend from the first portions 41a and 41b and rise from the third circuit board 18c. The second portions 42a, 42b are each parallel to the YZ plane. The second portions 42 a and 42 b are shaped to extend in the second direction (Z direction), which is the thickness direction of the circuit pattern 17 .

The third portion 43 is formed continuously from each of the second portions 42a and 42b. Specifically, the third portion 43 is continuous with the second end portion 62a on one side of the second portions 42a and 42b in the second direction. The third portion 43 is spaced apart from the first portions 41a and 41b in the second direction (Z direction). The third portion 43 is parallel to the XY plane. That is, each of the first portions 41a and 41b and the third portion 43 are parallel. The third portion 43 is arranged so as to pass through the third wall portion 13c in the X direction. The third portion 43 includes a first region 51 continuous from the second portions 42a and 42b, a rectangular second region 52 viewed in the thickness direction (Z direction), and a second region 52 projecting from the second region 52 in the X direction. and a third region 53 formed in the . Boundaries of the first area 51, the second area 52 and the third area 53 are indicated by dashed lines in FIG. A through hole 34 is formed through the third region 53 in the thickness direction. The first electrode plate 31 has the first region 51 , the second region 52 and part of the third region 53 located within the space 19 , and the remainder of the third region 53 and the through hole 34 located outside the semiconductor device 11 . are arranged as follows. Note that the third portion 43 is arranged at a position closer to the substrate 14 than the sixth portion 46 in the Z direction. That is, in the Z direction, the third portion 43 of the first electrode plate 31 is arranged between the substrate 14 and the sixth portion 46 of the second electrode plate 32 with a gap therebetween. The third portion 43 of the first electrode plate 31 is mainly a region forming a parallel plate with the second electrode plate 32 . Using the third region 53 of the third portion 43 and the through hole 34, the electrical connection of the first electrode plate 31 with the outside is ensured. Also, the third region 53 of the third portion 43 and the sixth region 56 of the sixth portion 46 are arranged with their positions shifted in the Y direction. Specifically, the third region 53 is arranged at a position near the first wall portion 13a in the Y direction, and the sixth region 56 is arranged at a position near the second wall portion 13b in the Y direction.

Here, the first region 51 included in the third portion 43 is a protruding region that protrudes toward the fifth portions 45a and 45b from the second end portion 62a in the X direction, which is the first direction. That is, the first region 51, which is a protruding region, also constitutes a parallel plate in the region indicated by the space 29 surrounded by the dashed line in FIG. An end surface 65 of the first region 51 , which is a projecting region facing the fifth portions 45 a and 45 b in the first direction, corresponds to the side surface of the first electrode plate 31 . 2, the distance between the first region ₅₁ , which is a projecting region, and the fifth portions 45a and 45b indicated by the interval _D1 in FIG. is 80% or less of the interval of

Next, an example of a method for manufacturing the semiconductor device 11 having the above configuration will be briefly described. First, the substrate 14 is bonded onto the base plate 12, and the semiconductor chips 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are bonded to the circuit pattern 17. As shown in FIG. At this time, for example, they are joined by reflow soldering using solder. Then, the members are connected by wires 23a to 23h, 24a to 24h, 25a to 25h, and 26a to 26h using stitch bonding, for example. The first electrode plate 31, the second electrode plate 32, and the third electrode plate 33 are formed by punching out a plate-like member into a predetermined shape and then bending it. Then, it is integrated with the frame 13 by insert molding. After that, the frame 13 integrated with the first electrode plate 31 , the second electrode plate 32 and the third electrode plate 33 is adhered and mounted on the base plate 12 .

After that, the first portions 41a and 41b, the fourth portions 44a and 44b and the seventh portions 47a and 47b are joined to the circuit pattern 17 by ultrasonic joining. FIG. 14 is a schematic side view showing part of the semiconductor device 11 before ultrasonic bonding. FIG. 15 is a schematic side view showing part of the semiconductor device 11 after ultrasonic bonding. In addition, in FIG. 15, the second portion 42a and the fifth portion 45a are exaggerated and greatly inclined for easy understanding.

14 and 15, if the bending accuracy is low and the angle formed by the first portion 41a and the second portion 42a does not reach 90 degrees, the second portion 42a approaches. However, since the second end portion 62a, which is the bent portion, is located farther from the fifth portion 45a than the first region 51, which is the protruding region, it is possible to reduce the risk of short-circuiting due to contact. Thus, the first electrode plate 31 and the second electrode plate 32 are joined by ultrasonic joining.

Then, the space 19 is filled with a sealing resin. After that, a lid (not shown) is attached to manufacture the semiconductor device 11 .

According to the semiconductor device 11 as described above, since the third portion 43 includes the first region 51 which is a protruding region protruding toward the fifth portion 45a from the second end portion 62a, a wide region constituting the parallel plate is secured. By doing so, the effect of reducing the inductance can be increased. In this case, since the first region 51, which is a protruding region protruding toward the fifth portion 45a from the second end portion 62a, is included, the risk of the second end portion 62a approaching the fifth portion 45a can be reduced. . Therefore, it is possible to reduce the possibility of contact with the second electrode plate 32 and causing a short circuit in the region including the second end 62a. As described above, according to the semiconductor device 11, it is possible to improve the reliability while reducing the inductance.

In this embodiment, the first electrode plate 31 is a P-type busbar and the second electrode plate 32 is an N-type busbar. In such a semiconductor device 11, the direction of the current flowing through the third portion 43 of the first electrode plate 31 and the direction of the current flowing through the sixth portion 46 of the second electrode plate 32 are reversed to greatly reduce the inductance. Obtainable.

In this embodiment, the first portions 41a, 41b and the first circuit board 18a are ultrasonically bonded, and the fourth portions 44a, 44b and the second circuit board 18b are ultrasonically bonded. Therefore, the first parts 41a, 41b and the first circuit board 18a and the fourth parts 44a, 44b and the second circuit board 18b can be joined without using a joining material. In this case, since the thickness direction of the first region 51, which is the projecting region, is perpendicular to the vibrating direction during ultrasonic bonding, it is difficult to mechanically deform in the vibrating direction. Therefore, even if the first electrode plate 31 and the second electrode plate 32 are ultrasonically welded, the risk of short-circuiting due to contact with each other is reduced. Therefore, reliability can be improved.

In this embodiment, the first electrode plate 31 is formed by bending a plate-like member. Therefore, the first electrode plate 31 can be manufactured by punching out a plate-shaped member as a raw material into a predetermined shape and bending it, so that productivity can be improved.

In this embodiment, the end surface 65 of the first region 51 , which is a projecting region facing the fifth portions 45 a and 45 b in the first direction, corresponds to the side surface of the first electrode plate 31 . By doing so, it is possible to reduce the possibility that the second end portion 62a corresponding to the bent portion comes close to the second electrode plate 32 when the first electrode plate 31 is formed by bending the plate-shaped member. . Therefore, even if the bending accuracy is low, it is possible to reduce the risk of short-circuiting due to contact due to inclination during bonding.

In the present embodiment, the distance between the end face 65 of the first region 51, which is the projecting region, and the fifth portions 45a, 45b is 1 mm or less. Therefore, it is possible to secure a large area for forming the parallel plates and further reduce the inductance.

In the present embodiment, the first portions 41a and 41b are provided as a pair so as to be symmetrically spaced apart in a third direction orthogonal to the first direction when viewed in the second direction. Therefore, it is possible to efficiently flow a current from the first portion to the third portion through the second portion, thereby further reducing the inductance.

In the present embodiment, the distance between the first region 51, which is the projecting region, and the fifth portions 45a and 45b is 80% or less of the distance between the third portion 43 and the sixth portion 46. As shown in FIG. Therefore, it is possible to secure a large area for forming the parallel plates and further reduce the inductance.

(Other embodiments)
In the above embodiment, the first electrode plate is formed by bending one plate-like member, but this is not restrictive, and the first electrode plate may be formed, for example, at the first portion. A plurality of plate-shaped members may be joined together, such as a corresponding plate-shaped member, a plate-shaped member corresponding to the second portion, and a plate-shaped member corresponding to the third portion. The same applies to the second electrode plate and the third electrode plate.

Further, in the above embodiment, the first electrode plate is joined to the first circuit board by ultrasonic joining, but the present invention is not limited to this. It may be bonded to the first circuit board with a adhesive. The same applies to the second electrode plate and the third electrode plate.

In the above embodiments, the semiconductor device includes the first electrode plate that is the P-type bus bar, the second electrode plate that is the N-type bus bar, and the third electrode plate that is the O-type bus bar. However, the present invention is not limited to this, and a semiconductor device may be provided with two electrode plates without the third electrode plate, and the semiconductor device may have parallel flat plates.

It should be understood that the embodiments disclosed this time are illustrative in all respects and not restrictive in any aspect. The scope of the present invention is defined by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and range of equivalents of the scope of the claims.

The semiconductor device of the present disclosure can be particularly advantageously applied when reduction in inductance and improvement in reliability are required.

11 semiconductor device 12 base plates 12a, 12b main surfaces 12c, 12d, 12e, 12f, 34, 35, 36 through hole 13 frame 13a first wall 13b second wall 13c third wall 13d fourth wall 14 Substrate 15 Metal plate 16 Insulating plate 17 Circuit pattern 18a First circuit board 18b Second circuit board 18c Third circuit board 18d Fourth circuit board 18e Fifth circuit board 18f Sixth circuit board 18g Seventh circuit board 19 Spaces 21a, 21b , 21c, 21d, 22a, 22b, 22c, 22d Semiconductor chips 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h, 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 25a, 25b, 25c, 25d, 25e, 25f, 25g, 25h, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h Wires 27a, 27b, 27c, 27d Press-fit pin 31 First electrode plate 32 Second electrode plate 33 3 electrode plates 37a, 37b, 38a, 38b, 39a, 39b, 40a, 40b dashed lines 41a, 41b first portions 42a, 42b second portion 43 third portions 44a, 44b fourth portions 45a, 45b fifth portion 46 sixth Portions 47a, 47b Seventh portion 48 Eighth portion 49 Ninth portion 51 First region (projection region)
52 Second region 53 Third region 54 Fourth region 55 Fifth region 56 Sixth region 57 Seventh region 58 Eighth region 61a First end 62a Second end 63a Third end 64a Fourth end 65 End surface 66
D ₁ , D ₂ intervals

Claims (8)

a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board in a first direction;
a semiconductor chip arranged on the circuit pattern and electrically connected to the circuit pattern;
a first electrode plate electrically connected to the first circuit board;
a second electrode plate electrically connected to the second circuit board;
The first electrode plate is
a first portion joined to the first circuit board;
a second portion arranged contiguously with a first end on one side of the first portion in the first direction and extending in a second direction that is a thickness direction of the circuit pattern;
a third portion connected to a second end on one side of the second portion in the second direction and spaced apart from the first portion in the second direction;
The second electrode plate is
a fourth portion bonded to the second circuit board;
a fifth portion arranged contiguously with a third end on one side of the fourth portion in the first direction and extending in the second direction;
a sixth portion connected to a fourth end on one side of the fifth portion in the second direction and spaced apart from the fourth portion in the second direction;
The second portion and the fifth portion are spaced apart in the first direction,
the third portion and the sixth portion are arranged in parallel with a gap in the second direction;
The semiconductor device, wherein the third portion includes a projecting region that projects toward the fifth portion from the second end in the first direction. The first electrode plate is a P-type busbar,
2. The semiconductor device according to claim 1, wherein said second electrode plate is an N-type bus bar. The first portion and the first circuit board are ultrasonically bonded,
3. The semiconductor device according to claim 1, wherein said fourth portion and said second circuit board are ultrasonically bonded. 4. The semiconductor device according to claim 1, wherein said first electrode plate is formed by bending a plate-like member. 5. The semiconductor device according to claim 1, wherein an end surface of said projecting region facing said fifth portion in said first direction corresponds to a side surface of said first electrode plate. 6. The semiconductor device according to claim 1, wherein the distance between the end surface of said projecting region and the fifth portion is 1 mm or less. A pair of said first portions are provided so as to be symmetrically spaced apart in a third direction perpendicular to said first direction when viewed in said second direction. The semiconductor device according to any one of items 1 and 2. 8. The semiconductor device according to claim 1, wherein the distance between said projecting region and said fifth portion is 80% or less of the distance between said third portion and said sixth portion.

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