JP2023073952A - current source circuit - Google Patents

Abstract

To provide a current source circuit which can shorten start-up time.SOLUTION: A current source circuit (10) comprises a constant current circuit (4) and a current supply unit (3). The constant current circuit includes: a first MOS transistor (4A) including a source connectable to a fixed voltage (GND) application end, a drain, and a gate short-circuited to the drain; a second MOS transistor (4B) having lower Vth than the first MOS transistor and including a gate connected to the gate of the first MOS transistor; and a first resistance (4C) connected between a source of the second MOS transistor and a source of the first MOS transistor. The current supply unit supplies current to the gate of the first MOS transistor.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to current source circuits.

Conventionally, a current source circuit capable of supplying current to another circuit block is known. A known current source circuit includes a constant current circuit and an activation circuit for activating the constant current circuit (see Patent Document 1, for example).

Japanese Patent Application Laid-Open No. 2021-124742

However, in the current source circuit including the start-up circuit as described above, there is a problem that the start-up time is long until the rising current becomes steady after the power supply voltage is turned on.

In view of the above situation, an object of the present disclosure is to provide a current source circuit capable of shortening the start-up time.

For example, a current source circuit according to the present disclosure
a first MOS transistor having a source connectable to a fixed voltage application terminal, a drain, and a gate short-circuited with the drain;
a second MOS transistor having a lower Vth than the first MOS transistor and having a gate connected to the gate of the first MOS transistor;
a first resistor connected between the source of the second MOS transistor and the source of the first MOS transistor;
a constant current circuit having
a current supply unit that supplies a current to the gate of the first MOS transistor;
It is configured to have

According to the current source circuit according to the present disclosure, it is possible to shorten the start-up time.

FIG. 1 is a diagram showing the configuration of a current source circuit according to an exemplary embodiment of the present disclosure; FIG. FIG. 2 is a diagram showing the current source circuit in a power-down state. FIG. 3 is a diagram showing the current source circuit in the power-on state. FIG. 4 is a diagram showing an example of a vertical structure of an NMOS transistor in a constant current circuit. FIG. 5 is a diagram showing the configuration of a current source circuit according to a modification. FIG. 6 is a diagram showing the configuration of a constant current circuit according to a modification. FIG. 7 is a diagram showing a first configuration example of a current source circuit capable of compensating temperature characteristics. FIG. 8 is a diagram showing a second configuration example of a current source circuit capable of compensating for temperature characteristics.

Exemplary embodiments of the present disclosure are described below with reference to the drawings.

<1. Configuration of Current Source Circuit>
FIG. 1 is a diagram showing the configuration of a current source circuit 10 according to an exemplary embodiment of the present disclosure. The current source circuit 10 shown in FIG. 1 includes inverters 1 and 2, a current supply section 3, a constant current circuit 4, an output current mirror 5, a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor) 6 and a boost circuit 7, and is a semiconductor integrated circuit in which these components are integrated.

The inverter 1 has a PMOS transistor 1A and an NMOS transistor (N-channel MOSFET) 1B. The source of the PMOS transistor 1 is connected to the application terminal of the power supply voltage VCC. The drain of PMOS transistor 1A is connected to the drain of NMOS transistor 1B at node ND1. The source of the NMOS transistor 1B is connected to the ground potential application terminal. A power down signal PDB is applied to the gate of the PMOS transistor 1A and the gate of the NMOS transistor 1B. The power down signal PDB is a signal that goes high or low.

The inverter 2 has a PMOS transistor 2A and an NMOS transistor 2B. The source of the PMOS transistor 2A is connected to the application terminal of the power supply voltage VCC. The drain of PMOS transistor 2A is connected to the drain of NMOS transistor 2B at node ND2. The source of the NMOS transistor 2B is connected to the ground potential application terminal. The gates of PMOS transistor 2A and NMOS transistor 2B are commonly connected to node ND1.

As a result, the power-down signal PDB is level-inverted by the inverter 1 and further level-inverted by the inverter 2 .

The current supply unit 3 is a circuit that supplies current to the gate of the NMOS transistor 4A in the constant current circuit 4, which will be described later, and has a PMOS transistor 3A and a current supply resistor 3B.

The PMOS transistor 3A is a switch that switches ON/OFF of current supply to the gate of the NMOS transistor 4A. The source of the PMOS transistor 3A is connected to the application terminal of the power supply voltage VCC. The drain of PMOS transistor 3A is connected to the first end of current supply resistor 3B. The gate of PMOS transistor 3A is connected to node ND1. As a result, the PMOS transistor 3A is switched on and off based on the level-inverted signal of the power-down signal PDB by the inverter 1. FIG.

The constant current circuit 4 has an NMOS transistor 4A, an NMOS transistor 4B, and a constant current resistor 4C. The drain of NMOS transistor 4A is connected to the second end of current supply resistor 3B. The gate of NMOS transistor 4A and the drain of NMOS transistor 4A are short-circuited. The source of the NMOS transistor 4A is connected to the ground potential application terminal. Gates of the NMOS transistors 4A and 4B are connected to each other. The source of NMOS transistor 4B is connected to the first end of constant current resistor 4C. A second end of the constant current resistor 4C is connected to the ground potential application end.

When a current is supplied from the current supply unit 3 to the gate of the NMOS transistor 4A, a constant current is generated in the constant current resistor 4C. Generation of the constant current will be described in detail later.

The output current mirror 5 is a circuit that mirrors and outputs the constant current generated in the constant current circuit 4, and has PMOS transistors 5A and 5B. The source of the PMOS transistor 5A on the input side is connected to the application terminal of the power supply voltage VCC. The gate of PMOS transistor 5A and the drain of PMOS transistor 5A are short-circuited. The drain of PMOS transistor 5A is connected to the drain of NMOS transistor 4B. Gates of the PMOS transistors 5A and 5B are connected to each other. The source of the PMOS transistor 5B is connected to the application terminal of the power supply voltage VCC. A drain of the PMOS transistor 5B is connected to an output terminal Tout for outputting an output current.

The PMOS transistor 6 is a switch that switches between enabling and disabling the PMOS transistors 5A and 5B in the output current mirror 5 . The source of the PMOS transistor 6 is connected to the application terminal of the power supply voltage VCC. The drain of PMOS transistor 6 is connected to the drain of PMOS transistor 5A. The gate of PMOS transistor 6 is connected to node ND2. As a result, the PMOS transistor 6 is switched on and off based on the level-inverted signals of the power-down signal PDB by the inverters 1 and 2, respectively.

The boost circuit 7 is a circuit for speeding up the activation of the output current mirror 5, and has a capacitor 7A and a boost resistor 7B. A first end of capacitor 7A is connected to node ND1. A second end of capacitor 7A is connected to a first end of boost resistor 7B. A second end of the boost resistor 7B is connected to the drain of the PMOS transistor 5A. That is, the capacitor 7A and the boost resistor 7B are connected in series.

<2. Operation of Current Source Circuit>
The operation of the current source circuit 10 configured as described above will be described with reference to FIGS. 2 and 3. FIG.

FIG. 2 is a diagram showing the power-down state of the current source circuit 10. As shown in FIG. In the power-down state, the power-down signal PDB is at low level. As a result, the power-down PDB is level-inverted by the inverter 1, and the signal generated at the node ND1 is at a high level. Therefore, the PMOS transistor 3A is turned off, and no current is supplied from the current supply section 3 to the gate of the NMOS transistor 4A. At this time, the level of the signal generated at the node ND1 is inverted by the inverter 2, and the signal generated at the node ND2 is at the low level. As a result, the PMOS transistor 6 is turned on. Therefore, the gates of the PMOS transistors 5A and 5B are set to high level, and the PMOS transistors 5A and 5B are turned off (disabled).

FIG. 3 is a diagram showing the power-on state of the current source circuit 10. As shown in FIG. In the power-on state, the power-down signal PDB is at high level. As a result, the power-down PDB is level-inverted by the inverter 1, and the signal generated at the node ND1 is at a low level. Therefore, the PMOS transistor 3A is turned on, and the current supply section 3 supplies current to the gate of the NMOS transistor 4A.

Here, Vth (threshold voltage) of the NMOS transistor 4B is set lower than Vth of the NMOS transistor 4A. The potentials of the gates of the NMOS transistors 4A and 4B are common, and the constant current resistor 4C is connected between the source of the NMOS transistor 4B and the source of the NMOS transistor 4A. Assuming ΔVth, a constant current Ic=ΔVth/R (R: resistance value of the constant current resistor 4C) is generated in the constant current resistor 4C.

At this time, the signal generated at the node ND1 is level-inverted by the inverter 2, and the signal generated at the node ND2 is at a high level. As a result, the PMOS transistor 6 is turned off. Therefore, the PMOS transistors 5A and 5B in the output current mirror 5 are enabled. Here, the gate voltages of the PMOS transistors 5A and 5B are lowered by the boost circuit 7 because the low level signal generated at the node ND1 is applied to the first end of the capacitor 7A in the boost circuit 7A. That is, the boost circuit 7 changes the gate voltages of the PMOS transistors 5A and 5B in the output current mirror 5 in the direction of turning on the PMOS transistors 5A and 5B. As a result, the constant current Ic generated in the constant current circuit 4 is mirrored by the output current mirror 5 and output from the output terminal Tout as the output current Iout. In the boost circuit 7, a boost resistor 7B buffers changes in the gate voltages of the PMOS transistors 5A and 5B.

As described above, in the present embodiment, the configuration of the constant current circuit 4 eliminates the need for a start-up circuit, and the start-up time from when the power-down signal PDB is switched from low level to high level until the output current Iout rises and becomes steady is can be shortened. Furthermore, by providing the boost circuit 7, the output current mirror 5 can be activated at a higher speed, thereby further shortening the activation time. Moreover, a starter circuit is not required, and the circuit area can be reduced.

<3. Configuration of NMOS Transistor>
A configuration example of the NMOS transistors 4A and 4B in the constant current circuit 4 will now be described. FIG. 4 is a diagram showing an example of the vertical structure of the NMOS transistors 4A and 4B.

In the structure shown in FIG. 4, buried layer (BL) 42 is formed on P-type substrate 41 . A P-well layer (HVPW) 43 is formed over the buried layer 42 . In the surface portion of the P well layer 43, an N+ type region 431 is formed on one side in the lateral direction and an N+ type region 432 is formed on the other side. The N+ type region 431 corresponds to the source region, and the N+ type region 432 corresponds to the drain region. A channel region 433 is formed between N+ type regions 431 and 432 in the surface portion of P well layer 43 . A gate oxide layer 44 is formed on the channel region 433 . A gate electrode 45 is formed on the gate oxide film 44 .

In both NMOS transistors 4A and 4B, gate electrode 45 is formed of P-type polysilicon or N-type polysilicon. By varying the Fermi level of the gate due to the difference in the doping amount of impurities in the gate electrode 45, the Vth of the NMOS transistors 4A and 4B are differentiated.

Alternatively, by forming the gate electrode 45 of the NMOS transistor 4A from P-type polysilicon and forming the gate electrode 45 of the NMOS transistor 4B from N-type polysilicon, the Vth of the NMOS transistor 4B is made lower than the Vth of the NMOS transistor 4A. You may

<4. Modified Example of Current Source Circuit>
FIG. 5 is a diagram showing a modification of the current source circuit 10. As shown in FIG. In the current source circuit 10 shown in FIG. 5, a power-down switch 8 is provided as compared with the above-described embodiment (FIG. 1). It should be noted that the PMOS transistor 3A is removed from the current supply section 3 as the power-down switch 8 is provided.

The power-down switch 8 is composed of an NMOS transistor. The source of the NMOS transistor 4A and the second end of the constant current resistor 4C are commonly connected to the drain of the power down switch 8. The source of the power-down switch 8 is connected to the ground potential application terminal. The gate of power down switch 8 is connected to node ND2.

With such a configuration, as shown in FIG. 5, in the power-down state (power-down signal PDB=low level), the node ND2 becomes low level and the power-down switch 8 is turned off. In the above-described embodiment (FIG. 1), since the Vth of the NMOS transistor 4B is low, a leak current may flow through the NMOS transistor 4B in the power-down state. In contrast, in the present embodiment, the power-down switch 8 is turned off, so that leakage current can be prevented from flowing through the NMOS transistor 4B.

<5. Modified Example of Constant Current Circuit>
In the current source circuit, the constant current circuit 4 may be configured as shown in FIG. The constant current circuit 4 shown in FIG. 6 has PMOS transistors 4D and 4E. The source of the PMOS transistor 4D is connected to the application terminal of the power supply voltage VCC (fixed voltage). The gate of PMOS transistor 4D and the drain of PMOS transistor 4D are shorted. Gates of the PMOS transistors 4D and 4E are connected to each other. The source of PMOS transistor 4E is connected to the first end of constant current resistor 4C. A second end of the constant current resistor 4C is connected to the application end of the power supply voltage VCC.

Vth of the PMOS transistor 4E is set lower than Vth of the PMOS transistor 4D. As a result, a constant current Ic=ΔVth/R is generated in the constant current resistor 4C, where ΔVth is the difference between the Vths of the PMOS transistors 4D and 4E.

<6. Temperature characteristic compensation>
Here, a current source circuit capable of compensating temperature characteristics will be described. FIG. 7 is a diagram showing a first configuration example of a current source circuit 10 capable of compensating for temperature characteristics.

In the current source circuit 10 shown in FIG. 7, the NMOS transistor 4A is composed of an enhancement-type MOSFET, and the NMOS transistor 4B is composed of a depletion-type MOSFET.

The current supply unit 3 is a constant current source having an NMOS transistor 31 composed of a depletion type MOSFET and a bias resistor 32 . The source of NMOS transistor 31 is connected to the first end of bias resistor 32 . A second end of the bias resistor 32 is connected to the gate of the NMOS transistor 31 . A second end of the bias resistor 32 is connected to the drain of the NMOS transistor 4A.

The drain of PMOS transistor 5B in output current mirror 5 is connected to current source 9 . Current source 9 has an NMOS transistor 91 . The drain of NMOS transistor 91 is connected to the drain of PMOS transistor 5B. The gate of NMOS transistor 91 is connected to the gate of NMOS transistor 4A. The NMOS transistor 4A and the NMOS transistor 91 form a current mirror.

Here, it is assumed that the reference current Iref generated by the current supply unit 3 has a positive temperature characteristic that increases as the temperature increases. In this case, current IB flowing through PMOS transistor 5B based on reference current Iref has a positive temperature characteristic. Here, since the current I9 flowing through the current source 9 is based on the reference current Iref, it has a positive temperature characteristic. Therefore, the output current IoutB output from the node NB where the drain of the PMOS transistor 5B and the current source 9 are connected is generated by subtracting the current I9 from the current IB. A corresponding current change can be suppressed.

In the configuration shown in FIG. 7, PMOS transistors 5C and 5D can be provided in addition to PMOS transistor 5B as PMOS transistors whose gates are connected to PMOS transistor 5A. In the example shown in FIG. 7, the current source 9 is connected to the drain of the PMOS transistor 5C, and the current source 9 is not provided for the PMOS transistor 5D. As a result, it is possible to select whether to perform temperature compensation for each output, such as performing temperature compensation for the PMOS transistor 5C (output current IoutC) and not performing temperature compensation for the PMOS transistor 5D (output current IoutD).

FIG. 8 is a diagram showing a second configuration example of the current source circuit 10 capable of compensating temperature characteristics. The difference between the configuration shown in FIG. 8 and the configuration shown in FIG. 7 is that the current source 9 is connected to the node N4 where the source of the NMOS transistor 4B and the constant current resistor 4C are connected, and the drain of the PMOS transistor 5B. is not connected to the NMOS transistor 91 of FIG. In this configuration, the current source 9 has the same configuration as the current supply section 3 and has an NMOS transistor 92 configured by a depletion type MOSFET and a bias resistor 93 . However, for example, the resistance value of the bias resistor 93 is adjusted to be different from the resistance value of the bias resistor 32 .

Here, it is assumed that the reference current Iref generated by the current supply unit 3 has a positive temperature characteristic that increases as the temperature increases. In this case, current I9 generated by current source 9 is injected into node N4, and current I9 has a positive temperature characteristic. As a result, the gate-source voltage Vgs of the NMOS transistor 4B is reduced as the temperature increases, canceling the temperature characteristics of the current flowing through the NMOS transistor 4B. Therefore, the output current Iout flowing through the PMOS transistor 5B can be suppressed from changing with temperature.

In addition, in the first configuration example (FIG. 7), the amount of current IB increased due to the temperature is discarded, so the current consumption is relatively large. Since the increase is suppressed, the consumption current becomes relatively small.

In both the first configuration example and the second configuration example, if the reference current Iref has a negative temperature characteristic, the current I9 generated by the current source 9 may have a negative temperature characteristic. .

<7. Others>
In addition to the above-described embodiments, the various technical features of the present disclosure can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments, and the claims is to be understood to include all changes that fall within the meaning and range of equivalents of the range.

<8. Note>
As described above, for example, the current source circuit (10) according to the present disclosure is
a first MOS transistor (4A) having a source connectable to an application terminal of a fixed voltage (GND), a drain, and a gate short-circuited with the drain;
a second MOS transistor (4B) having a lower Vth than the first MOS transistor and having a gate connected to the gate of the first MOS transistor;
a first resistor (4C) connected between the source of the second MOS transistor and the source of the first MOS transistor;
a constant current circuit (4) having
a current supply unit (3) that supplies a current to the gate of the first MOS transistor;
(first configuration).

In the first configuration, the output current mirror (5) whose input side is connected to the drain of the second MOS transistor (4B), and the gate voltages of the MOS transistors (5A, 5B) in the output current mirror are A boost circuit (7) that changes the direction to turn on the MOS transistor may be further provided (second configuration).

In the second configuration, the boost circuit (7) may have a configuration in which a capacitor (7A) and a second resistor (3B) are connected in series (third configuration).

In any one of the first to third configurations, a first terminal commonly connected to the source of the first MOS transistor (4A) and the first resistor (4C); (fourth configuration).

In any one of the first to fourth configurations, the first MOS transistor (4A) and the second MOS transistor (4B) are both NMOS transistors, and the fixed voltage is ground. A potential configuration may be employed (fifth configuration).

In the fifth configuration, the current supply section (3) includes a switch element ( 3A) and a third resistor (3B) (sixth configuration).

In any one of the first to sixth configurations, the gate electrode of the first MOS transistor (4A) and the gate electrode of the second MOS transistor (4B) are both P-type polysilicon or N-type. The first MOS transistor and the second MOS transistor may be formed of polysilicon and may have a difference in Vth between the first MOS transistor and the second MOS transistor by providing a difference in the doping amount of impurities in the gate electrode (7th MOS transistor). configuration).

In any one of the first to sixth configurations, the gate electrode of the first MOS transistor (4A) is made of P-type polysilicon, and the gate electrode of the second MOS transistor (4B) is made of P-type polysilicon. The electrodes may be configured to be formed of N-type polysilicon (eighth configuration).

In the first configuration, an output current mirror (5) having an input side connected to the drain of the second MOS transistor (4B);
a current source (9) configured to generate a current having temperature characteristics of the same polarity as the temperature characteristics of the current of the current supply (3);
An output current may be generated by subtracting the current generated by the current source from the output of the output current mirror (ninth configuration).

Further, in the ninth configuration, a plurality of output side transistors (5B, 5C, 5D) having gates connected to the gates of the input side transistors (5A) in the output current mirror (5),
The current source (9) is provided corresponding to one of the plurality of output side transistors (5B, 5C), and the current source is provided corresponding to one of the plurality of output side transistors (5D). It may be configured without (tenth configuration).

In the ninth or tenth configuration, the current source (9) may have a MOS transistor (91) including a gate connected to the gate of the first MOS transistor (4A) ( 11th configuration).

In the first configuration, an output current mirror (5) having an input side connected to the drain of the second MOS transistor (4B);
a current source (9) configured to generate a current having temperature characteristics of the same polarity as the temperature characteristics of the current of the current supply (3);
The current generated by the current source may be injected into a node (N4) connecting the source of the second MOS transistor and the first resistor (4C) (12th configuration).

In the twelfth configuration, the current source (9)
an NMOS transistor (92) composed of a depletion type MOSFET;
A configuration having a bias resistor (93) having a first end connected to the source of the NMOS transistor and a second end connected to the gate of the NMOS transistor may be provided (a thirteenth configuration).

In any one of the first to thirteenth configurations, the first MOS transistor may be an enhancement type MOSFET, and the second MOS transistor may be a depletion type MOSFET ( 14th configuration).

The present disclosure can be used as a current source for supplying current to various circuits.

1 inverter 1A PMOS transistor 1B NMOS transistor 2 inverter 2A PMOS transistor 2B NMOS transistor 3 current supply unit 3A PMOS transistor 3B current supply resistor 4 constant current circuit 4A, 4B NMOS transistor 4C constant current resistor 4D, 4E PMOS transistor 5 output current mirror 5A , 5B PMOS transistor 5C, 5D PMOS transistor 6 PMOS transistor 7 boost circuit 7A capacitor 7B boost resistor 8 power-down switch 9 current source 10 current source circuit 31 NMOS transistor 32 bias resistor 41 P-type substrate 42 buried layer 43 P-well layer 44 gate Oxide film 45 Gate electrode 91 NMOS transistor 92 NMOS transistor 93 Bias resistor 431, 432 N+ type region 433 Channel region Tout Output terminal

Claims (14)

a first MOS transistor having a source connectable to a fixed voltage application terminal, a drain, and a gate short-circuited with the drain;
a second MOS transistor having a lower Vth than the first MOS transistor and having a gate connected to the gate of the first MOS transistor;
a first resistor connected between the source of the second MOS transistor and the source of the first MOS transistor;
a constant current circuit having
a current supply unit that supplies a current to the gate of the first MOS transistor;
a current source circuit. an output current mirror whose input side is connected to the drain of the second MOS transistor;
a boost circuit that changes the gate voltage of the MOS transistor in the output current mirror in a direction to turn on the MOS transistor;
2. The current source circuit of claim 1, further comprising: 3. The current source circuit according to claim 2, wherein said boost circuit has a configuration in which a capacitor and a second resistor are connected in series. 3. A power-down switch having a first end commonly connected to the source of said first MOS transistor and said first resistor, and a second end connectable to said fixed voltage application end. 2. The current source circuit according to 1. both the first MOS transistor and the second MOS transistor are NMOS transistors,
2. The current source circuit according to claim 1, wherein said fixed voltage is ground potential. 6. The current source circuit according to claim 5, wherein said current supply unit has a switch element and a third resistor which can be connected in series between a power supply voltage application terminal and the drain of said first MOS transistor. Both the gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor are formed of P-type polysilicon or N-type polysilicon,
2. The current source circuit according to claim 1, wherein a difference in Vth is provided between said first MOS transistor and said second MOS transistor by providing a difference in impurity doping amount in said gate electrode. the gate electrode of the first MOS transistor is formed of P-type polysilicon,
2. The current source circuit according to claim 1, wherein said gate electrode of said second MOS transistor is made of N-type polysilicon. an output current mirror whose input side is connected to the drain of the second MOS transistor;
a current source configured to generate a current having a temperature characteristic of the same polarity as the temperature characteristic of the current of the current supply,
2. The current source circuit of claim 1, wherein the current generated by said current source is subtracted from the output of said output current mirror to generate an output current. a plurality of output-side transistors having gates connected to the gates of the input-side transistors in the output current mirror;
10. The current source circuit according to claim 9, wherein said current source is provided corresponding to any of said plurality of output side transistors and said current source is not provided corresponding to any of said plurality of output side transistors. . 11. A current source circuit according to claim 9 or 10, wherein said current source comprises a MOS transistor having a gate connected to the gate of said first MOS transistor. an output current mirror whose input side is connected to the drain of the second MOS transistor;
a current source configured to generate a current having a temperature characteristic of the same polarity as the temperature characteristic of the current of the current supply,
2. The current source circuit according to claim 1, wherein the current generated by said current source is injected into a node connecting said source of said second MOS transistor and said first resistor. The current source is
an NMOS transistor configured by a depletion type MOSFET;
a bias resistor having a first end connected to the source of the NMOS transistor and a second end connected to the gate of the NMOS transistor;
13. The current source circuit of claim 12, comprising: 2. The current source circuit according to claim 1, wherein said first MOS transistor comprises an enhancement-mode MOSFET, and said second MOS transistor comprises a depletion-mode MOSFET.

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