JP2023065093A - DC/DC converter and high side regulator - Google Patents

Abstract

To provide: a DC/DC converter capable of reducing current consumption without reducing drivability of a high-side MOS transistor; and high side regulator.SOLUTION: A DC/DC converter 1 comprises a high side regulator 9 for turning on and turning off a high-side power MOS transistor MPW1. The high side regulator 9 includes an output capacitor C1 and a Zener diode DZ1 which are connected in parallel with each other. When a voltage across the output capacitor C1 exceeds a Zener voltage, a current flows to a Zener diode DZ2, and a current detection unit 172 detects this and outputs a detection signal to a delay circuit 181. The delay circuit 181 turns on a transistor Mn3 just for a fixed delay time from input of the detection signal and cuts off a current to be supplied to the output capacitor C1 and the Zener diode DZ2.SELECTED DRAWING: Figure 2

Description

The present invention relates to DC/DC converters and high side regulators.

Conventionally, a circuit shown in FIG. 10 has been proposed as a high-side regulator used in a DC/DC converter. A high-side regulator 100 shown in FIG. 10 is a power supply circuit for turning on and off a high-side MOS transistor provided between an input voltage source and a coil of a DC/DC converter. The high-side regulator 100 comprises a Zener diode _DZ1 , an output capacitor _C1 , and a current mirror circuit 16 consisting of transistors _Mn1 and _Mn2 .

When bias current I _BIAS is provided to output capacitor _C1 by current mirror circuit 16, the voltage across output capacitor _C1 , ie, voltage V _HREG , increases. When the voltage V _HREG exceeds the Zener voltage V _DZ of the Zener diode D _Z1 , the Zener diode D _Z1 conducts and the voltage V _HREG is clamped to the Zener voltage V _DZ to produce a constant voltage.

JP 2007-151323 A

However, the above-described high-side regulator 100 has a problem of large current consumption because current is constantly supplied from the current mirror circuit 16 to the Zener diode _DZ1 and the output capacitor _C1 for voltage stabilization.

SUMMARY OF THE INVENTION The present invention has been made in view of the circumstances described above, and an object of the present invention is to provide a DC/DC converter and a high-side regulator capable of reducing current consumption without lowering the drive capability of a high-side MOS transistor. is to provide

In order to achieve the above object, a DC/DC converter and a high-side regulator according to the present invention are characterized by the following [1] to [6].
[1]
a coil;
a high-side MOS transistor provided between an input voltage source and the coil for supplying an input voltage of the input voltage source to the coil;
a control circuit for controlling on/off of the high-side MOS transistor to convert the input voltage;
In a DC/DC converter in which the control circuit includes a high-side regulator, which is a power supply circuit for turning on and off the high-side MOS transistor,
The high side regulator is
an output capacitor;
a first Zener diode connected in parallel with the output capacitor;
a current supply circuit provided on the low side of the output capacitor and the first Zener diode and supplying current to the output capacitor and the first Zener diode;
a current detection circuit that detects that a current has flowed through the first Zener diode;
a cutoff circuit that cuts off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that the current has flowed through the first Zener diode. ,
Must be a DC/DC converter.
[2]
In the DC/DC converter according to [1],
The cutoff circuit cuts off the current for a certain period from the timing when the current detection circuit detects that the current has flowed through the first Zener diode.
Must be a DC/DC converter.
[3]
In the DC/DC converter according to [1],
The control circuit
an oscillator that outputs a clock;
a PWM control unit that outputs a PWM signal having a duty based on a comparison between the slope signal synchronized with the clock and an error signal indicating the difference between the output voltage or current of the DC/DC converter and a reference value,
ON/OFF of the high-side MOS transistor is controlled according to the PWM signal,
The cutoff circuit cuts off the current only until the clock rises or falls after the current detection circuit detects that the current has flowed through the first Zener diode.
Must be a DC/DC converter.
[4]
In the DC/DC converter according to [1],
The cutoff circuit cuts off the current only until the high-side MOS transistor is switched from off to on after the current detection circuit detects that the current has flowed through the first Zener diode.
Must be a DC/DC converter.
[5]
In the DC/DC converter according to any one of [1] to [4],
The current detection circuit includes a second Zener diode whose cathode is connected to the cathode of the first Zener diode;
a current mirror circuit that copies the current flowing through the output capacitor and the first Zener diode and flows it through the second Zener diode;
a current detection unit that detects that the second Zener diode is conductive and the current mirror circuit causes the current to flow through the second Zener diode;
Must be a DC/DC converter.
[6]
A high-side regulator, which is a power supply circuit for turning on and off a high-side MOS transistor provided between an input voltage source and a coil of a DC/DC converter,
an output capacitor;
a first Zener diode connected in parallel with the output capacitor;
a current supply circuit provided on the low side of the output capacitor and the first Zener diode and supplying current to the output capacitor and the first Zener diode;
a current detection circuit that detects that a current has flowed through the first Zener diode;
a cutoff circuit that cuts off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that the current has flowed through the first Zener diode. rice field,
Be a high-side regulator.

ADVANTAGE OF THE INVENTION According to this invention, the DC/DC converter and high side regulator which can reduce a consumption current can be provided, suppressing the fall of the drive capability of the MOS transistor of a high side.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing a DC/DC converter in the first embodiment. FIG. 2 is a circuit diagram showing the high-side regulator shown in FIG. 1; FIG. 3 is a time chart of the voltage V _HREG , the drain current of transistor Mp ₁ , the drain current of transistor Mp ₂ , and the gate voltage of transistor Mn ₃ shown in FIG. FIG. 4 is a circuit diagram showing a DC/DC converter in the second embodiment. 5 is a circuit diagram showing the high side regulator shown in FIG. 4. FIG. FIG. 6 is a time chart of the voltage V _HREG , the drain current of transistor Mp ₁ , the drain current of transistor Mp ₂ , the clock of the oscillator, and the gate voltage of transistor Mn ₃ shown in FIG. FIG. 7 is a circuit diagram showing a DC/DC converter in the third embodiment. 8 is a circuit diagram showing the high-side regulator shown in FIG. 7. FIG. FIG. 9 is a time chart of the voltage V _HREG , the drain current of transistor Mp ₁ , the drain current of transistor Mp ₂ , the PWM signal, and the gate voltage of transistor Mn ₃ shown in FIG. FIG. 10 is a circuit diagram showing an example of a conventional high side regulator.

(First embodiment)
A specific first embodiment of the present invention will be described below with reference to each drawing.

The DC/DC converter 1 shown in FIG. 1 steps down the DC input voltage V _IN supplied from the input voltage source by turning on/off the power MOS transistors M _PWH and M _PWL and outputs it as the output voltage V _OUT from the output terminal OUT. . The DC/DC converter 1 controls on/off of the power MOS transistors M _PWH and M _PWL , the coil L _OUT1 , the capacitor C _OUT1 , the voltage detection resistors R _B1 and R _B2 , and the power MOS transistors M _PWH and M _PWL . and a control IC 2 (control circuit) that

A power MOS transistor _MPWH as a high-side MOS transistor is composed of a P-channel field effect transistor. The power MOS transistor _MPWH has a source connected to the positive electrode of the input voltage source, a drain connected to one end of the coil _LOUT1 and the drain of the power MOS transistor _MPWL , and a gate connected to a control resistor _RH , which will be described later. It is connected to IC2.

The power MOS transistor _MPWL is composed of an N-channel field effect transistor. The power MOS transistor _MPWL has a drain connected to the drain of the power MOS transistor _MPWH and one end of the coil _LOUT1 , a source connected to ground, and a gate connected to a control IC2 described later via a resistor _RL .

The coil L _OUT1 has one end connected to the drains of the power MOS transistors M _PWH and M _PWL and the other end connected to the positive electrode side of the output terminal OUT. A capacitor C _OUT1 and voltage detection resistors R _B1 and R _B2 are connected in parallel between a pair of output terminals OUT. Specifically, the capacitor C _OUT1 has one end connected to the other end of the coil L _OUT1 and the positive electrode side of the output end OUT, and the other end connected to the ground.

The voltage detection resistors R _B1 and R _B2 are connected in series with each other. The voltage detection resistor _RB1 has one end connected to the other end of the coil L _OUT1 and the positive electrode side of the output terminal OUT, and the other end connected to the voltage detection resistor _RB2 . The voltage detection resistor _RB2 has one end connected to the voltage detection resistor _RB1 and the other end connected to the ground. A detection voltage V _OUTS obtained by dividing the output voltage V _OUT by the voltage detection resistors R _B1 and R _B2 is supplied to the control IC2.

When the power MOS transistor _MPWH is turned on and the power MOS transistor _MPWL is turned off, energy from the input voltage _VIN is accumulated in the coil _LOUT1 . On the other hand, when the power MOS transistor _MPWH is turned off and the power MOS transistor _MPWL is turned on, the current corresponding to the energy accumulated in the coil _LOUT1 is sent from the ground to the coil _LOUT1 , and the output smoothed by the capacitor _COUT1 . A voltage V _OUT is output.

The control IC 2 turns on and off the power MOS transistors M _PWH and M _PWL so that the detected voltage V _OUTS becomes the reference value. The control IC 2 has a PWM control section 3 , an oscillator 4 , a dead time control section 5 , a high side drive section 6 , a low side drive section 7 and a regulator 8 .

The PWM control unit 3 outputs a PWM signal having a duty corresponding to a comparison between an error signal, which is the difference between the detected voltage V _OUTS and the reference value, and a slope signal synchronized with the clock output from the oscillator 4, to the dead time control unit 5. Output for The dead time control section 5 outputs PWM signals with dead time provided so that the power MOS transistors M _PWH and M _PWL are not turned on at the same time to the high side driving section 6 and the low side driving section 7 respectively.

The high side driving section 6 outputs a driving voltage to the gate of the high side power MOS transistor _MPWH according to the PWM signal output from the dead time control section 5 .

The high side driver 6 has transistors M _1H and M _2H , a high side regulator 9 , a level shifter 10 and a pre-driver 11 . Transistor _M1H consists of a P-channel field effect transistor. The transistor _M1H has a source connected to the positive terminal of the input voltage source, a drain connected to the gate of the power MOS transistor _MPWH via the resistor _RH , and a gate connected to the predriver 11 described later. Transistor _M2H consists of an N-channel field effect transistor. The transistor _M2H has a source connected to the output end of the high-side regulator 9, a drain connected to the gate of the power MOS transistor _MPWH via the resistor _RH , and a gate connected to the predriver 11 which will be described later.

A high-side regulator 9 generates an output voltage (V _IN −V _HREG ). The high side regulator 9 will be described later. The level shifter 10 level-shifts the PWM signal output from the dead time control unit 5 so that the H level becomes V _IN and the L level becomes V _IN −V _HREG , and supplies the PWM signal to the predriver 11 . The pre-driver 11 outputs level-shifted PWM signals to the gates of transistors M _1H and M _2H .

As a result, when an L-level PWM signal is output, the transistor _{M1H is} turned on, the transistor _M2H is turned off, and the input voltage V _IN is supplied to the gate of the power MOS transistor M _PWH . turn off. On the other hand, when an H-level PWM signal is output, the transistor _M1H is turned off, the transistor _M2H is turned on, and the output voltage (V _IN −V _HREG ) is supplied to the gate of the power MOS transistor M _PWH . Transistor _{M_PWH} turns on.

The low-side drive section 7 outputs a drive voltage to the gate of the low-side power MOS transistor _MPWL according to the PWM signal output from the dead time control section 5 .

The low-side driver 7 has transistors M _1L and M _2L , a low-side regulator 12 , a level shifter 13 and a pre-driver 14 . Transistor _M1L consists of a P-channel field effect transistor. The transistor _M1L has a source connected to the output terminal of the low-side regulator 12, a drain connected to the gate of the power MOS transistor _MPWL via a resistor _RL , and a gate connected to the predriver 14, which will be described later. Transistor _M2L consists of an N-channel field effect transistor. The transistor _M2L has a source connected to the ground, a drain connected to the gate of the power MOS transistor _MPWL via a resistor _RL , and a gate connected to the predriver 14 which will be described later.

Low-side regulator 12 produces an output voltage _VLREG . The level shifter 13 level-shifts the PWM signal output from the dead time control unit 5 so that the H level becomes V _LREG and the L level becomes ground (0 V), and supplies the PWM signal to the pre-driver 14 . The pre-driver 14 outputs level-shifted PWM signals to the gates of the transistors M _1L and M _2L .

As a result, when the L level PWM signal is output, the transistor _M1L is turned on, the transistor _M2L is turned off, the voltage V _LREG is supplied to the gate of the power MOS transistor M _PWL , and the power MOS transistor M _PWL is turned on. do. On the other hand, when the H level PWM signal is output, the transistor _M1L is turned off, the transistor _M2L is turned on, 0V is supplied to the gate of the power MOS transistor _{M_PWL} , and the power MOS transistor _{M_PWL} is turned off.

The regulator 8 generates an output voltage V _REG to be supplied to the PWM control section 3, the oscillator 4, the dead time control section 5, the high side regulator 9 and the level shifter 13 described above.

Next, details of the high-side regulator 9 described above will be described with reference to FIG. The high-side regulator 9 includes a Zener diode _DZ1 as a first Zener diode, an output capacitor _C1 , a bias current source 15, a current mirror circuit 16 as a current supply circuit, a current detection circuit 17, and a cutoff circuit. 18.

Zener diode _DZ1 and output capacitor _C1 are connected in parallel between output terminals VH and VL. Bias current source 15 outputs a bias current I _BIAS . A bias current source 15 is connected between the output voltage _VREG of the regulator 8 and a current mirror circuit 16 which will be described later.

A current mirror circuit 16 is provided on the low side of the output capacitor _C1 and the Zener diode _DZ1 (between the output terminal VL and ground) to copy the bias current I _BIAS to the output capacitor _C1 and the Zener diode _DZ1 . is the circuit that supplies the The current mirror circuit 16 has transistors _Mn1 and _Mn2 . Transistors _Mn1 and _Mn2 are constructed from N-channel field effect transistors. Transistor _Mn1 has a drain connected to bias current source 15, a source connected to ground, and a gate connected to the drain.

The drain of the transistor _Mn2 is connected to the anode of the Zener diode _DZ1 and one end of the output capacitor _C1 via the transistor _Mp1 , which will be described later. Transistor _Mn2 has a source connected to the source of transistor _Mn1 and a gate connected to the gate of transistor _Mn1 .

When bias current I _BIAS is provided to output capacitor _C1 by current mirror circuit 16, the voltage across output capacitor _C1 , ie, voltage V _HREG , increases. When the voltage V _HREG exceeds the Zener voltage V _DZ of the Zener diode D _Z1 , the Zener diode D _Z1 conducts and the voltage V _HREG is clamped to the Zener voltage V _DZ to produce a constant voltage. The high-side regulator 9 outputs an output voltage (V _IN −V _HREG ) from the output terminal VL by supplying the input voltage V _IN to the output terminal VH.

The current detection circuit 17 is a circuit that detects that a current has flowed through the Zener diode _DZ1 . The current detection circuit 17 has a Zener diode _DZ2 as a second Zener diode, a current mirror circuit 171, and a current detection section 172. FIG. Zener diode _DZ2 is of the same type as Zener diode _DZ1 and has the same characteristics (same Zener voltage _VDZ ). The Zener diode _DZ2 has a cathode connected to the cathode of the Zener diode _DZ1 and an anode connected to the source of the transistor _Mp2 which will be described later.

The current mirror circuit 171 copies the bias current I _BIAS that flows through the output capacitor _C1 and the Zener diode _DZ1 when the Zener diode _DZ1 conducts and flows it through the Zener diode _DZ2 . When the current mirror circuit 171 causes a current to flow through the Zener diode _DZ1 , a current also flows through the Zener diode _DZ2 . The current mirror circuit 171 is composed of transistors Mp ₁ and Mp ₂ . Transistors Mp ₁ and Mp ₂ are composed of P-channel field effect transistors. The transistor _Mp1 has a drain connected to the drain of the transistor _Mn2 , a source connected to one end of the output capacitor _C1 and the anode of the Zener diode _DZ1 , and a gate connected to the drain.

The transistor _Mp2 has a drain connected to the ground via a current detection unit 172, which will be described later, a source connected to the anode of the Zener diode _DZ2 , and a gate connected to the gate of the transistor _Mp1 . The current detection unit 172 is provided between the drain of the transistor _Mp2 and the ground, and when it detects that a current has flowed through the Zener diode _DZ2 and the drain of the transistor _Mp2 , the delay circuit 181 outputs a detection signal to that effect. output to

When the current detection circuit 17 detects that a current has flowed through the Zener diode _DZ2 and the transistor _Mp2 , the blocking circuit 18 supplies the bias current I from the current mirror circuit 16 to the output capacitor _C1 and the Zener diode _DZ1 . Shut off _BIAS . The blocking circuit 18 has a delay circuit 181 and a transistor _Mn3 . A delay circuit 181 is provided between the output terminal of the current detection section 172 and the gate of the transistor _Mn3 . When the detection signal is input from the current detection unit 172, the delay circuit 181 applies an H level signal to the gate of the transistor _Mn3 until a predetermined delay time (fixed period) elapses from the timing when the detection signal is input. output to turn on transistor _Mn3 .

Transistor _Mn3 consists of an N-channel field effect transistor. The transistor Mn ₃ has a drain connected to the drain of the transistor Mn ₁ , a source connected to the source of the transistor Mn ₁ , and a gate connected to the output end of the delay circuit 181 .

Next, the operation of the high-side regulator 9 described above will be described with reference to the time chart of FIG. When the current mirror circuit 16 supplies the bias current I _BIAS to the output capacitor _C1 , the voltage across the output capacitor _C1 , that is, the voltage V _HREG increases (FIG. 3(A)). While the bias current I _BIAS is being supplied to the output capacitor _C1 , a drain current flows through the transistor _Mp1 (FIG. 3(B)). When voltage V _HREG exceeds the Zener voltage V _DZ of Zener diode D _Z1 , Zener diode D _Z1 conducts and voltage V _HREG is clamped to Zener voltage V _DZ . At this time, since the voltage _VHREG clamped to the Zener voltage _VDZ is also applied to both ends of the Zener diode _DZ2 , the Zener diode _DZ2 conducts and the drain current flows through the transistor _Mp2 (Fig. 3 (C )).

When the current detection unit 172 detects that a current has flowed through the Zener diode D _Z2 and the transistor Mp ₂ , it outputs a detection signal to the delay circuit 181 . When the detection signal is input from the current detection unit 172, the delay circuit 181 outputs an H level gate signal to the gate of the transistor _Mn3 until a predetermined delay time elapses from the timing at which the detection signal is input (FIG. 3 ( D)). Transistor _Mn3 is turned on when it receives the H level gate signal from delay circuit 181, and short-circuits the gate and source of transistor _Mn1 . As a result, the bias current I _BIAS supplied to the output capacitor _C1 is cut off, and the drain currents of the transistors _Mp1 and _Mp2 become 0 A (FIGS. 3(B) and 3(C)).

Even if the bias current I _BIAS supplied to the output capacitor _C1 is cut off, the charge stored in the output capacitor _C1 keeps the voltage V _HREG constant (=Zener voltage V _DZ ). When the delay time elapses and the H level gate signal output from the delay circuit 181 is cut off and the L level signal is output to the transistor _Mn3 , the transistor _Mn3 is turned off and the current mirror circuit 16 The bias current I _BIAS is again applied to the output capacitor _C1 and the drain current flows through the transistor _Mp1 . At this time, if the voltage _VHREG is maintained at the Zener voltage _VDZ , when the transistor _Mn3 is turned off, currents flow through the Zener diodes _DZ1 and _DZ2 again, a detection signal is output from the current detection unit 172, and a delay occurs. A gate signal of H level is supplied from the circuit 181, and the bias current I _BIAS supplied to the output capacitor _C1 is cut off again.

According to the first embodiment described above, when the voltage across the output capacitor _C1 reaches the Zener voltage _VDZ and current flows through the Zener diode _DZ1 , the current mirror circuit 16 outputs the output capacitor _C1 and the Zener diode _DZ1 . The bias current I _BIAS supplied to is cut off. Therefore, since the bias current I _BIAS is not always supplied to the output capacitor _C1 and the Zener diode _DZ1 , it is possible to reduce current consumption. In addition, when the voltage across the output capacitor _C1 does not reach the Zener voltage _VDZ , the bias current _IBIAS is not cut off, thus suppressing the deterioration of the drive capability of the high-side power MOS transistor _MPW1 . can be done.

According to the first embodiment described above, the delay circuit 181 causes the bias current supplied to the output capacitor _C1 and the Zener diode _DZ1 only until the delay time elapses after the current flows through the Zener diode _DZ1 . I _BIAS outputs a blocking gate signal to transistor _Mn3 . As a result, the interruption and supply of the bias current I _BIAS to the output capacitor _C1 and the Zener diode _DZ1 are not repeated at high speed, and the current consumption can be further reduced.

(Second embodiment)
Next, a second embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 and 5, parts equivalent to those of the DC/DC converter 1 and the high-side regulator 9 shown in FIGS. 1 and 2, which have already been explained in the first embodiment, are denoted by the same reference numerals, and a detailed explanation thereof will be given. omitted.

A major difference between the DC/DC converter 1 of the first embodiment and the DC/DC converter 1B of the second embodiment is that, as shown in FIG. This is the point.

A major difference between the high-side regulator 9 of the first embodiment and the high-side regulator 9B of the second embodiment is the configuration of a cutoff circuit 18B, as shown in FIG. The blocking circuit 18B of the second embodiment is provided with a flip-flop circuit 182 in place of the delay circuit 181. FIG.

A flip-flop circuit 182 is provided between the output terminal of the current detection section 172 and the gate of the transistor _Mn3 . A clock output from the oscillator 4 is input to the flip-flop circuit 182 . The flip-flop circuit 182 outputs an H level signal to the gate of the transistor _Mn3 from the time the detection signal is input from the current detection section 172 until the clock rises.

Next, the operation of the high side regulator 9B described above will be described below with reference to the time chart of FIG. As in the first embodiment, when the current mirror circuit 16 supplies the bias current I _BIAS to the output capacitor C1, the voltage across the output capacitor _C1 , that is, the voltage V _HREG increases (FIG _. 6A). . While the bias current I _BIAS is being supplied to the output capacitor _C1 , a drain current flows through the transistor _Mp1 (FIG. 6(B)). When voltage V _HREG exceeds the Zener voltage V _DZ of Zener diode D _Z1 , Zener diode D _Z1 conducts and voltage V _HREG is clamped to Zener voltage V _DZ . At this time, since the voltage _VHREG clamped to the Zener voltage _VDZ is also applied to both ends of the Zener diode _DZ2 , the Zener diode _DZ2 becomes conductive and the drain current flows through the transistor _Mp2 (Fig. 6 (C )).

When the current detection unit 172 detects that a current has flowed through the Zener diode D _Z2 and the transistor Mp ₂ , it outputs a detection signal to the flip-flop circuit 182 . When the detection signal is input from the current detection unit 172, the flip-flop circuit 182 outputs an H level gate signal to the transistor _Mn3 (FIGS. 6C and 6E) to turn on the transistor _Mn3 . . As a result, the bias current I _BIAS supplied to the output capacitor _C1 is cut off, and the drain currents of the transistors _Mp1 and _Mp2 become 0 A (FIGS. 6B and 6C).

After outputting the H level gate signal, the flip-flop circuit 182 cuts off the H level gate signal at the timing when the clock rises to H level, and outputs an L level signal to the transistor _Mn3 (Fig. 6 (D ), (E)). As a result, the transistor _Mn3 is turned off, and the current mirror circuit 16 supplies the bias current I _BIAS to the output capacitor _C1 again.

At this time, if the voltage _VHREG is maintained at the Zener voltage _VDZ , when the transistor _Mn3 is turned off, currents flow through the Zener diodes _DZ1 and _DZ2 again, the current detection unit 172 outputs a detection signal, and the flip-flop circuit A gate signal of H level is supplied from the amplifier circuit 182, and the bias current I _BIAS supplied to the output capacitor _C1 again by the transistor _Mn3 is cut off.

According to the _second embodiment described above, the flip-flop circuit ₁₈₂ supplies the bias current _{I BIAS} is shut off. Since the cycle of the clock is the ON/OFF cycle of the power MOS transistor _MPWH , the bias current I _BIAS to the output capacitor _C1 and the Zener diode _DZ1 can be _interrupted in accordance with the ON/OFF cycle of the power MOS transistor MPW1. can. As a result, it is possible to further reduce current consumption while suppressing deterioration in the drive capability of the high-side power MOS transistor _MPWH .

Note that, according to the second embodiment described above, the flip-flop circuit 182 turns on the transistor _Mn3 during the period from when the detection signal is input until the clock rises, and the output capacitor _C1 and the Zener diode _DZ1 are connected. Although the supplied bias current I _BIAS is cut off, it is not limited to this. The flip-flop circuit 182 can be configured to turn on the transistor _Mn3 from the time the detection signal is input until the _clock falls. effect can be obtained.

(Third Embodiment)
Next, a third embodiment will be described with reference to FIGS. 7 and 8. FIG. 7 and 8, parts equivalent to those of the DC/DC converter 1 and the high-side regulator 9 shown in FIGS. 1 and 2, which have already been explained in the first embodiment, are denoted by the same reference numerals, and a detailed explanation thereof will be given. omitted.

A major difference between the DC/DC converter 1 of the first embodiment and the DC/DC converter 1C of the third embodiment is that, as shown in FIG. This is the input point.

A major difference between the high-side regulator 9 of the first embodiment and the high-side regulator 9C of the third embodiment is the configuration of a cutoff circuit 18C, as shown in FIG. The breaker circuit 18C is provided with a flip-flop circuit 183 in place of the delay circuit 181. FIG.

A flip-flop circuit 183 is provided between the output terminal of the current detection section 172 and the gate of the transistor _Mn3 . A PWM signal output from the PWM control section 3 is input to the flip-flop circuit 183 . The flip-flop circuit 183 outputs an H level signal to the gate of the transistor _M3 from the time when the detection signal is input from the current detection section 172 until the PWM signal rises.

Next, the operation of the high-side regulator 9C described above will be described below with reference to the time chart of FIG. As in the first embodiment, when the current mirror circuit 16 supplies the bias current I _BIAS to the output capacitor C1, the voltage across the output capacitor _C1 , that is, the voltage V _HREG increases (FIG _. 9A). . While the bias current I _BIAS is being supplied to the output capacitor _C1 , a drain current flows through the transistor _Mp1 (FIG. 9(B)). When voltage V _HREG exceeds the Zener voltage V _DZ of Zener diode D _Z1 , Zener diode D _Z1 conducts and voltage V _HREG is clamped to Zener voltage V _DZ . At this time, since the voltage _VHREG clamped to the Zener voltage _VDZ is also applied to both ends of the Zener diode _DZ2 , the Zener diode _DZ2 becomes conductive and the drain current flows through the transistor _Mp2 (FIG. 9 (C )).

When the current detection unit 172 detects that a current has flowed through the Zener diode D _Z2 and the transistor Mp ₂ , it outputs a detection signal to the flip-flop circuit 183 . When the detection signal is input from the current detection unit 172, the flip-flop circuit 183 outputs an H-level gate signal to the transistor _Mn3 at the timing when the detection signal is input (FIGS. 9(C) and 9(E)). , turn on transistor _Mn3 . As a result, the bias current I _BIAS supplied to the output capacitor _C1 is cut off, and the drain currents of the transistors _Mp1 and _Mp2 become 0 A (FIGS. 9B and 9C).

After outputting the H level gate signal, the flip-flop circuit 183 cuts off the H level gate signal at the timing when the PWM signal falls to the L level, and outputs the L level signal to the transistor _Mn3 (FIG. 9). (D), (E)). As a result, the transistor _Mn3 is turned off, the bias current I _BIAS is supplied again to the output capacitor _C1 by the current mirror circuit 16, and the drain current flows through the transistor _Mp1 .

While the PWM signal is at L level, the power MOS transistor _{M_PWH} is turned on to supply current to the coil _{L_OUT1} , so that the voltage _{V_HREG} decreases. At this time, when the voltage _VHREG becomes less than the Zener voltage _VDZ , no current flows through the Zener diodes _DZ1 and _DZ2 while the PWM signal is at L level, and the bias current _IBIAS supplied to the output capacitor _C1 is reduced to never be blocked. On the other hand, while the PWM signal is at H level, the power MOS transistor _{M_PWH} is turned off and the power MOS transistor _{M_PWL} is turned on, so that the voltage _{V_HREG} increases. After that, when the voltage V _HREG reaches the Zener voltage V _DZ , current flows through the Zener diodes D _Z1 and D _Z2 , turning on the transistor Mn ₃ again, and the bias current I _BIAS supplied to the output capacitor C ₁ becomes Cut off and repeat.

According to the third embodiment described above, the flip-flop circuit 183 maintains the output capacitor C1 and the Zener diode D only during the period from when the current flows through the Zener diode _DZ1 to when the power MOS transistor _MPWH is switched from off to on _. A gate signal is output to transistor _Mn3 that cuts off the bias current I _BIAS that supplies _Z1 . Therefore, when the power MOS transistor _{M_PWH} is turned on to supply current to the coil _LOUT1 , the bias current _{I_BIAS} is not cut off, and when the power MOS transistor _{M_PWH} is turned off, the bias current _{I_BIAS} can be cut off. . As a result, it is possible to further suppress the deterioration of the drive capability of the high-side power MOS transistor _MPWH .
In the DC/DC converter, when the load connected to the output terminal OUT is light, the PWM signal output by the PWM control unit 3 is such that the time during which the power MOS transistor _MPWH turns on is and the off time becomes longer. Therefore, in the DC/DC converter 1C of the third embodiment, when the load connected to the output terminal OUT is light, the time during which the bias current I _BIAS is interrupted becomes longer, and It is possible to suppress the current consumption of the high side regulator 9C. In other words, the high-side regulator 9C can operate with an appropriate consumption current for the driving capability of the power MOS transistor _MPWH .

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

According to the above-described embodiment, the delay circuit 181 and the flip-flop circuits 182 and 183 are provided between the current detection section and the transistor _Mn3 , but the present invention is not limited to this. The current detection unit 172 and the transistor _Mn3 are directly connected so that the transistor _Mn3 is turned on when current flows through the Zener diode _DZ1 , and the bias current I _BIAS is supplied to the output capacitor _C1 and the Zener diode _DZ1 . may be blocked.

According to the above-described embodiment, the error signal used in the PWM controller 3 is the difference between the detected voltage V _{OUTS corresponding to the output voltage V OUT and} the reference value, but it is not limited to this. The error signal may be the difference between the output current flowing from the output terminal OUT to the load and the reference value.

1, 1B, 1C DC/DC converter 2 Control IC (control circuit)
3 PWM control unit 4 oscillator 9, 9B, 9C high side regulator 16 current mirror circuit (current supply circuit)
17 current detection circuit 18 cutoff circuit 171 current mirror circuit 172 current detection unit C ₁ output capacitor D _Z1 Zener diode (first Zener diode)
D _Z2 Zener Diode (Second Zener Diode)
L _OUT1 coil M _PWH high-side power MOS transistor V _IN input voltage

Claims (6)

a coil;
a high-side MOS transistor provided between an input voltage source and the coil for supplying an input voltage of the input voltage source to the coil;
a control circuit for controlling on/off of the high-side MOS transistor to convert the input voltage;
In a DC/DC converter in which the control circuit includes a high-side regulator, which is a power supply circuit for turning on and off the high-side MOS transistor,
The high side regulator is
an output capacitor;
a first Zener diode connected in parallel with the output capacitor;
a current supply circuit provided on the low side of the output capacitor and the first Zener diode and supplying current to the output capacitor and the first Zener diode;
a current detection circuit that detects that a current has flowed through the first Zener diode;
a cutoff circuit that cuts off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that the current has flowed through the first Zener diode. ,
DC/DC converter. The DC/DC converter according to claim 1,
The cutoff circuit cuts off the current for a certain period from the timing when the current detection circuit detects that the current has flowed through the first Zener diode.
DC/DC converter. The DC/DC converter according to claim 1,
The control circuit
an oscillator that outputs a clock;
a PWM control unit that outputs a PWM signal having a duty based on a comparison between the slope signal synchronized with the clock and an error signal indicating the difference between the output voltage or current of the DC/DC converter and a reference value,
ON/OFF of the high-side MOS transistor is controlled according to the PWM signal,
The cutoff circuit cuts off the current only until the clock rises or falls after the current detection circuit detects that the current has flowed through the first Zener diode.
DC/DC converter. The DC/DC converter according to claim 1,
The cutoff circuit cuts off the current only until the high-side MOS transistor is switched from off to on after the current detection circuit detects that the current has flowed through the first Zener diode.
DC/DC converter. In the DC/DC converter according to any one of claims 1 to 4,
The current detection circuit includes a second Zener diode whose cathode is connected to the cathode of the first Zener diode;
a current mirror circuit that copies the current flowing through the output capacitor and the first Zener diode and flows it through the second Zener diode;
a current detection unit that detects that the second Zener diode is conductive and the current mirror circuit causes the current to flow through the second Zener diode;
DC/DC converter. A high-side regulator that is a power supply circuit for turning on and off a high-side MOS transistor provided between an input voltage source and a coil of a DC/DC converter,
an output capacitor;
a first Zener diode connected in parallel with the output capacitor;
a current supply circuit provided on the low side of the output capacitor and the first Zener diode and supplying current to the output capacitor and the first Zener diode;
a current detection circuit that detects that a current has flowed through the first Zener diode;
a cutoff circuit that cuts off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that the current has flowed through the first Zener diode. rice field,
high side regulator.

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