JP2023061066A - game machine - Google Patents

Abstract

To provide a game machine capable of appropriately managing a storage area.SOLUTION: The total storage capacity of a special storage area storing unused data indicating 0 in a restart area to which a restart address is assigned is 7 bytes. The total storage capacity of the special storage area storing unused data indicating 0 in an area storing table data included in an interrupt vector table XTBL_INTR is 12 bytes. The total storage capacity of these special storage areas is less than 1069 bytes, which is the total storage capacity of unused areas that become unused storage areas. Discontinuous addresses are assigned to storage addresses of unused data as special addresses in the special storage area. The discontinuous addresses are assigned to storage addresses of used data, including areas where data indicating 0 is stored.SELECTED DRAWING: Figure 11- 2

Description

The present invention relates to a game machine capable of playing games.

A gaming machine has been proposed in which an unused area can be easily identified when referring to a dump list (for example, Patent Document 1).

Japanese Patent No. 6034903

The technology described in Patent Document 1 has room for improvement in the management of storage areas.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of appropriately managing storage areas.

In order to achieve the above object, a gaming machine according to the present invention is a gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by a program stored in the storage means;
The memory means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
a third storage area different from the first storage area and the second storage area;
an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area;
Unused data indicating all 0 is stored in the unused storage area,
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
the second storage area includes a normal storage area storing use data indicating 0 at a normal address;
The total storage capacity of regular storage is less than the total storage capacity of unused storage, and
The normal storage area may include a plurality of areas assigned normal addresses in which use data indicating 0 is stored.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The storage means may be, for example, the ROM 101 or the like. The control means may be, for example, the CPU 103 or the like. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The third storage area may be, for example, a non-game program area and a non-game data area. The unused storage area may be, for example, an unused area of addresses 0BD3[H] to 11FF[H] and an unused area of addresses 1D34[H] to 1FFF[H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of unused storage areas may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area for zero data, which is used data in setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes.
According to such a configuration, discontinuous addresses are assigned as normal addresses in which used data are stored in the normal storage area, and since the normal storage area has a smaller total storage capacity than the unused storage area, Appropriate storage area management becomes possible so as to prevent erroneous recognition of an area as an unused storage area.

It is a front view of the pachinko game machine. 3 is a configuration diagram showing various control boards and the like; FIG. It is a figure which shows an example of the random number for a game. It is a flow chart which shows the main processing for game control. It is a flow chart showing an example of timer interrupt processing for game control. It is a flow chart which shows an example of special design process processing. It is a figure which shows the structural example of a special design process processing jump table. It is a flow chart which shows the main processing for production control. It is a flowchart etc. which show an example of production|presentation control process processing. It is a figure which shows the structural example of the microcomputer for game control. It is a figure which shows an example of an address map. FIG. 4 is a diagram showing a main setting example of addresses included in a function setting register area; FIG. 4 is a diagram showing a main setting example of addresses included in a function control register area; It is a figure for demonstrating the example of a setting about the random number for a game. FIG. 4 is a diagram for explaining a random number update cycle; 6 is a flowchart showing an example of power supply start handling processing; FIG. 10 is a diagram showing a configuration example of a function setting register stored value table; FIG. 4 is a diagram showing a configuration example of an RWM access protect register; 7 is a flowchart illustrating an example of power-off processing; It is a figure for demonstrating the usage example of a data structure. 6 is a flowchart illustrating an example of random number update processing; It is a figure for demonstrating the usage example of a data structure. 9 is a flowchart showing an example of initial value change random number update processing; 9 is a flowchart showing an example of initial value determination random number update processing; It is a flowchart which shows an example of a starting opening switch passage process. It is a figure for demonstrating the usage example of a data structure. It is a flow chart which shows an example of special design normal processing. It is a figure for demonstrating the usage example of a data structure. It is a flowchart which shows an example of special design determination processing. It is a figure for demonstrating the usage example of a data structure. It is a flow chart which shows an example of special design information setting processing. It is a flow chart which shows an example of jackpot information data selection processing. It is a figure for demonstrating the usage example of a data structure. It is a figure for demonstrating the usage example of a data structure. It is a flowchart which shows an example of a fluctuation pattern setting process. It is a flowchart etc. which show an example of a variation pattern classification table selection process at the time of a hit. It is a flowchart etc. which show an example of a change pattern classification table selection process at the time of a failure. FIG. 11 is a diagram for explaining a configuration example of a variation pattern type sorting table; FIG. 11 is a diagram for explaining a configuration example of a variation pattern sorting table; FIG. FIG. 11 is a diagram for explaining a configuration example of a variation pattern sorting table; FIG. FIG. 11 is a diagram for explaining a configuration example of a variation pattern sorting table; FIG. It is a flowchart etc. which show an example of design process processing normally. It is a figure for demonstrating the usage example of a data structure. It is a flow chart which shows an example of gate switch passage processing. It is a flowchart which shows an example of normal design normal processing. It is a figure for demonstrating the usage example of a data structure. FIG. 4 is a diagram showing memory areas of a ROM; It is a figure which shows the setting example of unused data. FIG. 4 is a diagram showing a configuration example of an RST instruction; FIG. 3 is a diagram showing a description example of a program module; It is a figure which shows the storage example of table data. It is a figure which shows the setting example of zero data. It is a figure which shows the storage example of table data. FIG. 10 is a diagram showing an output example of a dump list;

(Basic explanation)
First, the basic configuration and control of the pachinko game machine 1 will be described.

(Structure of pachinko machine 1, etc.)
FIG. 1 is a front view of the pachinko game machine 1, showing the arrangement layout of the main members. A pachinko game machine (game machine) 1 is roughly composed of a game board (gauge board) 2 forming a game board surface and a game machine frame (underframe) 3 supporting and fixing the game board 2 . A game area is formed in the game board 2, and a game ball as a game medium is shot from a predetermined ball shooting device and hit into the game area.

At predetermined positions of the game board 2, a first special symbol display device 4A and a second special symbol display device 4B are provided. In the example shown in FIG. 1, it is provided on the right side of the game area. Each of the first special symbol display device 4A and the second special symbol display device 4B can variably display special symbols as a plurality of types of special identification information. A special design is also called a "special design." The variable display of special symbols is also called a "special symbol game". Both the first special symbol display device 4A and the second special symbol display device 4B are configured using a 7-segment LED or the like. The special symbols are represented by numbers representing "0" to "9", symbols representing "-", and other arbitrary lighting patterns. The special symbol may include a pattern in which all LEDs are turned off.

"Variable display" of special symbols means, for example, to display a plurality of types of special symbols in a variable manner. "Variable display" also means that a plurality of types of symbols are displayed in a variable manner with respect to other symbols such as effect symbols, small symbols, and normal symbols. The production design is also called a decoration design or a decoration design. Variable display is also referred to as variable display or simply variation. Variations include updating display of a plurality of patterns, scrolling display of a plurality of patterns, deformation, enlargement, and reduction of one or more patterns. Variation may include a mode of blinking a certain symbol. In the variable display of special symbols and normal symbols, a plurality of types of special symbols or normal symbols are displayed in an updatable manner. In the variable display of performance symbols, a plurality of types of performance symbols are scrolled or updated, or one or more performance symbols are deformed, enlarged, or reduced. In the variable display of arbitrary patterns, a predetermined pattern is stopped and displayed at the end as a display result. A stop display is also referred to as a derivation display, or simply a derivation. The symbol that is finally stopped and displayed in the variable display is also called a final stop symbol or a fixed symbol. The final stop symbol in the special symbol game is also called a fixed special symbol. The display result of the variable display includes the display result of the special symbol, and is also referred to as the variable display result. The display result of a special design is also called a special figure display result. The execution time of the variable display includes the special symbol variation time, which is the variation time of the special symbol, and is also called variable display time. Different times can be set for the special figure variation time corresponding to the variation pattern of the special symbols in which a plurality of patterns are prepared in advance.

The special symbol variably displayed on the first special symbol display device 4A is also called "first special symbol". The special symbol variably displayed on the second special symbol display device 4B is also called a "second special symbol". A special game using the first special game is also called a "first special game". A special game using the second special game is also called a "second special game". There may be one type of special symbol display device that variably displays the special symbols.

A normal symbol display device 20 is provided at a predetermined position on the game board 2 . In the example shown in FIG. 1, it is provided on the left side of the game area. The normal symbol display device 20 can variably display normal symbols as a plurality of types of normal identification information different from special symbols. Ordinary design is also called 'Fu-zu'. The variable display of normal symbols is also called a “normal game”. The normal symbol display 20 is configured using a 7-segment LED or the like. The normal symbols are represented by numbers representing "0" to "9", symbols representing "-", and other arbitrary lighting patterns. The normal pattern may include a pattern in which some or all of the plurality of LEDs are turned on, or a pattern in which all of the plurality of LEDs are turned off. The final stop pattern in the general pattern game is also called a fixed normal pattern. The normal pattern display result is also called a normal pattern display result. The execution time during which the normal pattern is variably displayed in the general pattern game is also referred to as general pattern fluctuation time. The normal pattern fluctuation time can be set to different times corresponding to the normal pattern fluctuation patterns in which a plurality of patterns are prepared in advance.

An image display device 5 is provided near the center of the game area on the game board 2 . The image display device 5 may be, for example, an LCD (liquid crystal display device), an organic EL (Electro Luminescence), a dot matrix LED, a projector and a screen, a stereoscopic image projection device, or any other mechanism that can form any image. Just do it. The image display device 5 can display various effect images. In addition, the image display device 5 can display any control-related image, such as an inspection image or a setting image, without being limited to the effect image.

For example, on the screen of the image display device 5, it is possible to perform variable display of the effect symbols in synchronization with the first special game and the second special game. The production pattern is a display pattern showing numbers and the like, and serves as a plurality of types of decoration identification information different from special patterns and normal patterns. On the screen of the image display device 5 shown in FIG. 1, "left", "middle", and "right" effect symbol display areas 5L, 5C, and 5R are provided for the first special symbol game or the second special symbol. In synchronism with the game, for example, the performance symbols are displayed by scrolling in the vertical direction or being updated, thereby performing variable display of the performance symbols. Synchronization of the variable display may be such that the timing at which pattern variation is started and the timing at which the pattern is finally stopped and displayed after the variation is completed are common timings for different types of symbols. . The final stop pattern in the variable display of the production pattern is also called a fixed production pattern, a fixed decorative pattern, or a fixed decorative pattern. Since the variable display of the performance symbols is synchronized with the first special symbol game and the second special symbol game, the variable display time of the performance symbols is the same as the special symbol fluctuation time.

The screen of the image display device 5 may be provided with a display area capable of displaying effect images corresponding to the suspension display and the active display. A pending display is a display corresponding to a variable display that has not yet been executed and is on hold. An active display is a display that corresponds to a running variable display. Suspended presentations and active presentations are also collectively referred to as variable presentation-enabled presentations that correspond to variable presentations. A display area for holding display is also called a holding display area. A display area for active display is also called an active display area. The number of variable representations that are reserved is also referred to as the number of reserved memories. The reserved memory number corresponding to the first special game is also referred to as the first reserved memory number. The reserved memory number corresponding to the second special game is also referred to as the second reserved memory number. The total value of the first reserved memory count and the second reserved memory count is also referred to as the total reserved memory count.

Above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. 1, a first suspension display 25A and a second suspension display 25B each including a plurality of LEDs are provided. . The first pending display 25A displays the first pending memory number by the number of lit LEDs. The second pending display 25B displays the number of second pending memories according to the number of lit LEDs. Above the normal design display 20 shown in FIG. 1, a normal design suspension display 25C including a plurality of LEDs is provided. 25 C of normal-map reservation|holding indicators display the number of normal-map reservation|holding memory|storages by the lighting number of LEDs. The number of reserved memory for the normal pattern is the number of reserved memory corresponding to the normal pattern game.

Below the image display device 5, a winning ball device 6A and a variable winning ball device 6B are provided. Winning ball device 6A, for example, by a predetermined ball receiving member, forms a first starting winning opening that is always kept in a constant open state in which game balls can enter. The variable winning ball device 6B forms a second starting prize opening that can be changed between a closed state and an open state by a normal electric accessory solenoid 81 shown in FIG. 2 as a normal electric accessory. The variable winning ball device 6B is provided with, for example, an electric tulip-shaped accessory having a pair of movable wing pieces, and when the normal electric accessory solenoid 81 is in an OFF state, the movable wing pieces are in a vertical position, whereby the second start-up is performed. A closed state in which game balls do not enter the winning opening or a normal open state in which game balls hardly enter the second starting winning opening. The variable winning ball device 6B is in an open state in which the game ball can enter the second starting winning opening or the second starting winning opening by moving the movable wing to the tilting position when the normal electric accessory solenoid 81 is in the ON state. The mouth is in an enlarged open state in which game balls can easily enter. The open state in which the game ball can enter the second start winning opening or the enlarged open state in which it is easy to enter is also called the first variable state. The closed state in which the game ball does not enter the second starting winning hole or the normal open state in which it is difficult to enter is also called the second variable state. Note that the variable winning ball device 6B may be any device that can be changed between the first variable state and the second variable state, and is not limited to the one provided with the electric tulip-shaped accessory.

The entry of the game ball into the first starting winning hole formed by the winning ball device 6A is also referred to as the first starting winning. The entry of the game ball into the second starting winning hole formed by the variable winning ball device 6B is also referred to as second starting winning. A game ball that has entered the first starting winning opening is detected by the first starting opening switch 22A shown in FIG. A game ball that has entered the second starting winning opening is detected by the second starting opening switch 22B shown in FIG. Based on the occurrence of the first start winning, a predetermined number of prize balls, such as three, are paid out, and the first reserved storage number can be updated to be incremented by one. However, when the first reserved memory number has reached the upper limit number, the first reserved memory number is not updated even if the first start winning is generated. Corresponding to the case where 1 is added to the first reserved memory number, the first starting condition is established, and the first special symbol game in which the special symbols are variably displayed by the first special symbol display device 4A can be executed. Based on the occurrence of the second start winning, a predetermined number of prize balls, such as three, are paid out, and the second reserved storage number can be updated so as to be incremented by one. However, when the second reserved memory number has reached the upper limit number, the second reserved memory number is not updated even if the second start winning is generated. Corresponding to the case where 1 is added to the second reserved memory number, the second starting condition is established, and the second special symbol game in which the special symbols are variably displayed by the second special symbol display device 4B can be executed.

At a predetermined position of the game board 2, a general prize winning opening 10 is provided which is always kept in a constant open state by a predetermined ball receiving member. In the example shown in FIG. 1, two general winning openings 10 are provided at the lower left corner of the game area. When a game ball enters one of the general winning holes 10, a predetermined number of prize balls, such as ten, are paid out.

In the game area formed by the game board 2, a first path and a second path are provided as flow paths along which game balls flow. The first path is mainly provided in an area on the left side of the image display device 5 when viewed from the front. The second path is mainly provided in a region on the right side of the image display device 5 when viewed from the front. The left area of the image display device 5 is also called a left game area or a left game area. The right area of the image display device 5 is also called a right game area or a right game area. The left game area and the right game area may be separated by, for example, the end face of the image display device 5 in the game area, the arrangement of the game nails, or the like. Shooting a game ball toward the left game area in order to make the game ball flow down the first path is also called left hitting. Shooting a game ball toward the right game area in order to make the game ball flow down the second path is also called right hitting. The first path is also referred to as a left-handed path. The second path is also called a right-handed path. The first route and the second route may be composed of different routes, or may be a route in which a part is shared.

A game ball is shot from the ball shooting device and struck into the game area in response to the operation of a ball operating handle provided on the ball shooting device. When the game ball hit into the game area is guided to the left game area and flows down the first path, for example, it is guided along the arrangement of the game nails, so that it is guided to the second path in the right game area. It becomes impossible or difficult to induce. When the game ball hit into the game area is guided to the right game area and flows down the second path, for example, it is guided along the arrangement of the game nails, so that it is guided to the first path in the left game area. It becomes impossible or difficult to induce.

The winning ball device 6A is provided on the first path in the left game area, and allows game balls flowing down the first path to enter. The variable winning ball device 6B is provided on the second path in the right game area, and allows game balls flowing down the second path to enter. In addition, the variable winning ball device 6B may be able to enter the game ball flowing down the first path in the left game area. The variable winning ball device 6B may be arranged such that a game ball flowing down the second path in the right side gaming area is easier to enter than a game ball flowing down the first path in the left side gaming area.

A passage gate 41 and a special variable winning ball device 50 are provided on the second path in the right game area. The passage gate 41 forms a passage area through which game balls can pass. A game ball that has passed through the passage gate 41 is detected by the gate switch 21 shown in FIG. Based on the passage of the game ball through the passage gate 41, the normal reserved memory number can be added and updated, and the variable display of the normal pattern by the normal pattern display device 20 can be executed as the normal pattern game. The passage gate 41 can be configured as a normal symbol operation opening into which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol operation port switch capable of detecting a game ball that has entered the normal symbol operation port.

The special variable winning ball device 50 forms a large winning opening that can be changed between a closed state and an open state by a large winning opening solenoid 82 as a special electric accessory. An upper portion of the special variable winning ball device 50 is formed with a guide passage having a passage width in the front-rear direction to the extent that game balls can pass therethrough. This guide path slopes down from the right side to the left side, and walls are provided on both sides of the extended passage, the front side and the back side. At the center of the guide path, there is formed an accessory entrance that serves as a big winning entrance. In the special variable winning ball device 50, a movable member 52 that can move in the front-rear direction is provided as a member for opening and closing the large winning opening at a position where the large winning opening can be opened and closed. In the special variable prize winning ball device 50, a fixing member 53 forming a fixed passage is provided in a portion of the guide passage where the large winning opening is not formed.

The movable member 52 is driven by a large winning prize opening solenoid 82, and can move forward and backward to open and close the accessory entrance that serves as a large winning prize opening. In the special variable winning ball device 50, a game ball that enters from the big winning opening is detected by the count switch 23. - 特許庁Inside the special variable winning ball device 50, a V winning area 51, which is a specific area, is provided as a winning area through which game balls can pass. Also, inside the special variable winning ball device 50, a normal area different from the V winning area 51 is provided. Above the V winning area 51, a plate-shaped distribution member is provided as a V winning opening opening/closing member that can switch the V winning area 51 between an open state and a closed state. The distribution member is driven by a specific area solenoid 83 and is capable of advancing and retreating to open and close the V winning area 51 . A game ball can pass through the V winning area 51 when it is in an open state, and a game ball cannot pass through it when it is in a closed state. A game ball that has passed through the V winning area 51 is detected by the specific area switch 24 . A game ball that has not passed through the V winning area 51 passes through the normal area. A game ball that has passed through the V winning area 51 and a game ball that has passed through the normal area without passing through the V winning area 51 are detected by the discharge port switch 26, and then released outside the special variable winning ball device 50. is discharged to

The surface of the game board 2 is provided with, in addition to the above configuration, a windmill for changing the flowing direction and speed of the game ball and a large number of obstacle nails. At the bottom of the game area, an out port is provided for taking in game balls that have not entered any of the winning ports. Speakers 8L and 8R for reproducing and outputting sound effects and the like are provided at the upper left and right positions of the frame 3 for the game machine, and a game effect lamp 9 for lighting effects is provided at the periphery of the game area. there is The game effect lamp 9 includes an LED. At a predetermined position on the game board 2, a movable body 32 that operates according to the performance is provided.

At the lower right position of the frame 3 for the gaming machine, there is provided a ball-hitting operation handle operated by a player or the like to shoot a game ball toward the game area by the ball-hitting device. The hitting operation handle is also called an operation knob. At a predetermined position of the game machine frame 3 below the game area, a game ball paid out as a prize ball or a game ball lent by a predetermined ball lending machine is held so as to be supplied to the ball launching device. A serving tray is provided. The hitting ball supply plate is also called an upper plate. Below the upper plate, there is provided a prize ball storage plate in which the awarded balls flow down and are stored when the upper plate is full. The prize ball storage plate is also called a lower plate.

A stick controller 31A and a push button 31B are provided at predetermined positions of the gaming machine frame 3 below the game area. The stick controller 31A can be gripped and tilted by the player, and is provided with a trigger button that can be pushed and pulled by the player. An operation on the stick controller 31A is detected by the controller sensor unit 35A shown in FIG. The push button 31B can be pressed by the player. An operation on the push button 31B is detected by the push sensor 35B shown in FIG. In the pachinko game machine 1, the stick controller 31A and the push button 31B are used as detection means for detecting actions such as player's operations, but detection means other than these may be used.

(Overview of Game Progress)
A game ball is shot toward a game area by a player's rotation operation of a ball-hitting operation handle provided in the pachinko game machine 1.例文帳に追加When the game ball passes through the passage gate 41, the normal pattern display device 20 starts the normal pattern game. In addition, when the previous normal game is being executed, even if the game ball passes through the passage gate 41, the normal game based on the passage cannot be immediately executed, so the normal game based on the passage cannot be performed. , for example, up to a predetermined upper limit number, such as "4". In the general pattern game, when a specific normal pattern such as a general pattern winning pattern is stopped and displayed as a fixed normal pattern, the display result of the normal pattern becomes "normal pattern winning". On the other hand, when a normal pattern other than the normal per pattern, such as a normal pattern losing pattern, is stop-displayed as the fixed normal pattern, the display result of the normal pattern becomes "normal pattern losing". In the case of the "normal game", the variable winning ball device 6B is controlled to be in an open state or an enlarged open state for a predetermined period of time. At this time, the second start winning opening becomes an open state or an enlarged open state.

When a game ball enters through a first starting winning hole formed in the winning ball device 6A, the first special symbol game by the first special symbol display device 4A can be started. When a game ball enters through a second starting winning hole formed in the variable winning ball device 6B, the second special symbol game by the second special symbol display device 4B can be started. In addition, during the period during which the special game is being executed, or during the period during which the game ball is controlled to the big win game state or the small win game state, even if the game ball enters the start prize opening and the start prize is generated, Since the special game based on the starting prize cannot be executed immediately, the special game based on the starting prize is suspended up to a predetermined upper limit number such as "4". In the special symbol game, when a specific special symbol such as a big hit symbol is stopped and displayed as a fixed special symbol, the display result of the special symbol becomes a "big hit". On the other hand, when a predetermined special symbol different from the big win symbol, such as a small winning symbol, is stop-displayed as the fixed special symbol, the display result of the special symbol becomes "small winning". Further, when a special symbol different from the big win symbol or the small win symbol such as a lost symbol is stop-displayed as the fixed special symbol, the display result of the special symbol becomes "loss". Furthermore, when a special pattern different from a big hit pattern, a small hit pattern, and a losing pattern, such as a time saving pattern, is stopped and displayed as a fixed special pattern, the display result of the special pattern may be "time saving". . The special pattern may not include the time saving pattern. That is, the display result of the special symbol may not include "time saving".

In the special symbol game, after the display result of the special symbol becomes "big win", the game is controlled to a big win game state as an advantageous state for the player. In the jackpot game state, the jackpot opening formed in the special variable winning ball device 50 can be opened in a predetermined manner. The open state at this time is, for example, 29 seconds or 1.8 seconds, until the timing when a predetermined period of time elapses, or the timing when the number of game balls entering the big winning opening reaches a predetermined number, whichever is earlier. Continued. The predetermined period during which the large winning opening can be controlled to be open is an upper limit period during which the large winning opening can be opened in one round, and is also referred to as an upper limit opening period. One cycle in which the big winning opening is open in the big winning game state is called a round or a round game. In the jackpot game state, such rounds can be repeated until a predetermined upper limit number of times, such as 15 times or 2 times, is reached. In the jackpot game state, the player can get a prize ball by entering the game ball into the big winning hole. Therefore, the jackpot game state is an advantageous state for the player. The larger the number of rounds in the jackpot game state and the longer the upper limit period of opening, the more advantageous the player is.

When the display result of the special symbol becomes "big win", it includes a plurality of big win types. For example, the game state after the end of the big win game state such as the opening mode of the big winning mouth such as the number of rounds and the upper limit of the opening period, the normal state, the time saving state, and the probability variable state is set to a plurality of different settings, and the big win is set according to each setting. A type is specified. A plurality of jackpot types may include a part or all of a jackpot type with which many prize balls can be obtained, a jackpot type with few prize balls, or a jackpot type with which few prize balls can be obtained. Alternatively, the prize balls that can be obtained may include the same level of jackpot types. The control to the big win game state based on the display result of the special pattern being a "big win" is also called a big win in the pattern, a big win by the special pattern, a big win in the variable display, or a direct hit.

In the special symbol game, after the display result of the special symbols becomes "small hit", the game is controlled to the small win game state. In the small winning game state, the big winning opening formed in the special variable winning ball device 50 can be opened in a predetermined opening mode. For example, in the small winning game state, the big winning opening may be opened in the same opening mode as the big winning game state at the time of some jackpot types. It is sufficient that the big winning openings can be opened in a similar manner by sharing the number of times of opening and the opening period. Alternatively, in the small winning game state, the big winning opening may be opened in an opening mode different from the big winning game state. Similar to the big hit type, even when the display result of the special symbol is "small hit", a plurality of small hit types may be included. The big hit type and the small hit type are also collectively referred to as the hit type. The operation of opening and closing the big winning opening in the small winning game state is also called starting operation. When the game ball is in the small winning game state, the special variable winning ball device 50 is opened to become the big winning opening, and the game ball passes through the V winning area 51 and is detected by the specific area switch 24. A condition for generating a big win is established, and control to a big win game state becomes possible. Controlling to the big win game state based on the occurrence of the V prize by the game ball passing through the V winning area 51 in the small win game state is also called a big win via a small win.

After the jackpot game state is finished, the game state can be controlled to a time-saving state or a variable probability state corresponding to the jackpot type. Further, in the special symbol game, after the display result of the special symbols becomes "time saving", the game state is controlled to the time saving state without being controlled to the jackpot game state. The time saving state is a gaming state in which the second special symbol game by the second special symbol display device 4B is more likely to be executed than in the normal state. The game state in which the second special figure game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to enter through the second start winning opening than in the normal state. The control of whether or not the game ball is likely to pass through the second start winning opening is also called base control. Base control in the normal state is also called normal base control or low base control. Base control in the time saving state includes high base control. In addition to high-based control, the time-saving state may include mid-based control. Medium base control is base control in which a game ball is more likely to pass through the second start winning opening than in low base control, but more difficult to pass through the second start winning opening than in high base control. The game state in which the middle base control is performed is also called a middle base state. A game state in which high base control is performed is also referred to as a high base state. High base control is also called high opening control.

In the case of the normal state, the medium base state, and the high base state, the time-saving design can be stopped and displayed as a display result of the special design. However, in the medium base state and the high base state, even if the time saving pattern is stopped and displayed as a result of the display of the special pattern, the base control based on the time saving pattern is not performed, and the medium base state or the high base state is not performed. A new control transition to the high base state is not initiated. In the time-saving state, time-saving control that shortens the average variable display time compared to the normal state is possible. Accordingly, the time saving state is also referred to as a time shortening state.

Since the time saving state is a state in which the variation efficiency of the special symbols such as the second special symbol is improved, it is included in the special state advantageous to the player, which is different from the jackpot game state. When the game state is the variable probability state, in addition to the time saving control, the variable probability control is possible in which the probability that the display result of the special symbol is a "jackpot" is higher than in the normal state. Accordingly, the probability variable state is also referred to as the probability variable state. The probability variable state is included in the special state advantageous to the player, which is different from the jackpot game state, because the variable probability state is a state in which the special symbol variation efficiency is improved and the "big win" is likely to occur. The time-saving state and probability variable state are continued until any one of the predetermined end conditions such as execution of the special figure game for a predetermined number of times and control to the next jackpot game state is established first. The end condition that the special figure game has been executed a predetermined number of times is also called a number cut. The time-saving state of cutting the number of times is also called the time-saving state of cutting the number of times. The probability-variable state of the number-of-times cutting is also called a number-of-times-cutting probability variation.

The normal game state is an advantageous state such as a big win game state that is advantageous to the player, a predetermined state such as a small win game state, and a game state that is not included in special states such as a time saving state and a variable probability state. In the normal state, the probability that the display result in the normal game is "normal game", the probability that the display result in the special game is "big hit", etc. are controlled to be the same as the initial setting state of the pachinko game machine 1. It is in play state. The initial setting state of the pachinko gaming machine 1 is a control state after executing the initial setting process without executing a predetermined recovery process after power-on, such as when the system is reset.

The state in which probability variable control is executed is also called a high probability state, and the state in which probability variable control is not executed is also called a low probability state. A state in which time-saving control is performed is also referred to as a high-based state, and a state in which time-saving control is not performed is also referred to as a low-based state. Combining these, the short-time state is also called a low-probability-high base state, the probability-variable state is a high-probability-high base state, and the normal state is a low-probability-low base state. The high probability state and the low base state are also referred to as the high probability low base state. In addition, the pachinko gaming machine 1 may not include the variable probability state as the game state.

After the small winning game state is finished, there are two cases: a case where the game state is controlled to the big winning game state based on the occurrence of the V winning prize, and a case where the game state before entering the small winning game state is not changed without the occurrence of the V winning prize. be. However, when the display result of the special game is "small hit" and the special game is executed a predetermined number of times in the cut, the control of the time saving state and the variable probability state ends and the normal state may occur. . In addition, the pachinko gaming machine 1 may not include the small winning game state as the game state. That is, the display result of the special symbols may not include the "minor hit".

It may be possible to control the game state to the time saving state when the time saving condition based on the number of execution times of the variable display is satisfied. Such a time-saving state is also called relief time-saving. The time-saving condition is that after the power is turned on to the pachinko gaming machine 1, after the occurrence of a big hit, or after the display result of the special figure game becomes "time-saving", even if the variable display is executed for a specific number of times, a new big-hit game state or When control to a time saving state is not performed, what is necessary is just to be the conditions which can be established.

(Progress of production, etc.)
In the pachinko game machine 1, various effects can be executed in accordance with the progress of the game. This effect includes an effect for notifying the progress of the game and an effect for exciting the game. These effects include displaying various effects images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, and operating the stick controller. Vibration of 31A or push button 31B, or a combination of some or all of these, as long as it can be executed using any production device.

The effects that can be executed in accordance with the progress of the game include variable display of the effect symbols. In response to the start of the first special game or the second special game, the "left", "middle", and "right" effect pattern display areas 5L provided on the screen of the image display device 5, At 5C and 5R, the variable display of the effect symbols is started. When the finalized special symbols that are the display result in the first special symbol game and the second special symbol game are stop-displayed, the finalized performance symbols that are the display result are stop-displayed in the variable display of the performance symbols. The fixed effect pattern is composed of a combination of three effect patterns corresponding to the "left", "middle" and "right" effect pattern display areas 5L, 5C and 5R. During the period from the start of the variable display of the performance symbols to the end thereof, the display mode in the variable display of the performance symbols may be the ready-to-win mode. The ready-to-win mode is a mode in which, when the performance symbols stopped on the screen of the image display device 5 constitute a part of the jackpot combination, the performance symbols that have not yet stopped continue to fluctuate. . The fact that the display mode in the variable display of the production pattern is the ready-to-win mode is also said to be the ready-to-win.

The ready-to-win effect can be executed in response to the variable display of the effect pattern becoming the ready-to-win mode. The pachinko game machine 1 can execute a plurality of types of ready-to-win effects so that the ratio of the display result of the variable display to be a "jackpot" differs when the effect modes are different. The ratio of "big win" corresponding to the effect mode is also called "big win reliability" and "big win expectation". The ready-to-win performance includes, for example, normal ready-to-win and super ready-to-win with higher reliability of big win than normal ready-to-win. In addition, a short reach and a long reach whose execution time is longer than the short reach may be included in correspondence with the execution time of the reach effect.

When the display result of the special pattern becomes a ``big hit'', the determined performance pattern that becomes a predetermined big win combination is stopped and displayed on the screen of the image display device 5 as the display result of the performance pattern. As an example, in the "left", "middle", and "right" production pattern display areas 5L, 5C, 5R, the same production pattern, for example, a production pattern showing the number "7", is aligned and on a predetermined effective line. displayed to stop. In the case of a ``variable probability big win'' controlled to a variable probability state after the end of the big winning game state, odd-numbered performance symbols such as a performance symbol showing the number ``7'', for example, may be stop-displayed together. In the case of a ``non-probability variable big win'' which is not controlled to a probability variable state after the end of the big win game state, even-numbered performance symbols such as a performance symbol showing the number ``6'', for example, may be stop-displayed together. The "non-probable variable jackpot" is also referred to as the "normal jackpot". In this case, the odd production design is also referred to as a probability variable design. The even-numbered production pattern is also called a non-variable pattern or a normal pattern. After becoming a ready-to-win mode with non-probability variation symbols, a promotion performance may be executed to finally become a "probability variation big hit".

When the display result of the special pattern becomes a ``small hit'', the fixed performance pattern that becomes a predetermined small win combination is displayed on the screen of the image display device 5 in a stopped manner as the display result of the performance pattern. As an example, in the "left", "middle", and "right" performance symbol display areas 5L, 5C, 5R, the same performance symbols, such as a performance symbol indicating a number other than "7", are aligned and a predetermined effective line is displayed. May be paused on top. A common fixed performance symbol may be stop-displayed depending on whether the display result of the special symbol is a "big hit" or a "small hit".

When the display result of the special design becomes "losing", there is a case where the display result is not displayed in the ready-to-win state in the variable display of the production design, and the display result is stopped. In this case, as a result of displaying the performance symbols, the fixed performance symbols of the non-reach combination are stopped and displayed. The display result in which the fixed effect symbol of the non-reach combination is stopped and displayed without being in the reach mode is also called non-reach loss. When the display result of the special symbol becomes "losing", the variable display of the effect symbol becomes a ready-to-win mode, and the display result may be stopped after the ready-to-win effect is executed. In this case, as a result of the display of the performance symbols, the determined performance symbols of the ready-to-win combinations other than the big winning combination and the small winning combination are stopped and displayed. The display result in which the fixed effect pattern of the ready-to-win combination is stopped and displayed after the ready-to-win state is reached is also called a ready-to-win failure.

The effects that can be executed by the pachinko game machine 1 include display corresponding to variable display such as pending display and active display. In addition, for example, it is possible to execute a notice effect for notifying the reliability of the big hit during the variable display of the effect symbols. The notice effect includes the variable notice effect for notifying the reliability of the big hit corresponding to the variable display during execution, and the pre-reading notice effect for notifying the reliability of the big hit corresponding to the variable display before the execution of which the execution is suspended. may contain. The pre-reading advance notice effect may be capable of executing a change effect that changes the display mode of variable display compatible display such as suspended display and active display to a mode different from usual.

On the screen of the image display device 5, once the performance symbols are temporarily stopped during the variable display of the performance symbols, and then the variable display is restarted, one variable display is simulated as a plurality of variable displays. It may be possible to execute a pseudo-continuous effect that makes it look like. The pseudo-continuous performance may be set so that the reliability of the big win is higher when the number of times of re-fluctuation for restarting the variable display after temporarily stopping the performance pattern is larger than when the number of times of re-fluctuation is small. . The variable display of the performance symbols may include a case where the pseudo-continuous performance is executed before the ready-to-win state is established and a case where the pseudo-continuous performance is executed after the ready-to-win state is established. In addition, in the variable display of the performance symbols, the pseudo-continuous performance may be executed at a plurality of timings.

During the control of the big-hit game state, it is possible to execute the performance during the big-hit game for notifying the big-hit game state. The effect during the big win may include the effect of notifying the number of rounds and the promotion effect of suggesting or notifying that the advantage of the big win game state is improved. During the control of the small-hit game state, it is possible to execute a performance during the small-hit game for notifying the small-hit game state. By executing a common performance during the control of the big win game state and during the control of the small win game state, the player can determine whether the current game state is the big win game state or the small win game state. It may be made unrecognizable or difficult to recognize.

In a non-game state in which no special game or the like is executed and the game is not progressing, an effect image for demonstration can be displayed on the screen of the image display device 5.例文帳に追加The effect image for demonstration is also called a demo image. The display of the demonstration image is also called demonstration display. The production by the demonstration display is also called a customer waiting demonstration production.

(Substrate configuration)
The pachinko game machine 1 includes, for example, a main board 11, an effect control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17 and the like as shown in FIG. In addition, various boards such as a payout control board, an information terminal board, and a launch control board are arranged on the back surface of the pachinko game machine 1 .

The main board 11 is a control board on the main side, and has the function of controlling the progress of the game in the pachinko gaming machine 1 . The progress of the game is the execution of various games and game states such as execution of special game with management of suspension, execution of general game with management of suspension, big hit game state, small hit game state, time saving state, probability variable state, etc. including the migration of The main board 11 includes a game control microcomputer 100 , a switch circuit 110 and a solenoid circuit 111 .

The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number It can be configured to include a circuit 104 and an I/O (Input/Output port) 105 . A part or all of the ROM 101, the RAM 102, and the random number circuit 104 may be externally attached to the game control microcomputer 100, or may be built in the game control microcomputer 100. good. The switch circuit 110 takes in detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100 . Various switches for game ball detection include, for example, a gate switch 21, starter switches such as a first starter switch 22A and a second starter switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a game ball has passed or entered and the switch has been turned on. The transmission of the detection signal means that the passage or entry of the game ball has been detected. The solenoid circuit 111 can supply the solenoid drive signal from the game control microcomputer 100 to the normal electric accessory solenoid 81, the big winning opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

The ROM 101 provided in the game control microcomputer 100 is a non-volatile storage device that stores computer programs and data used for game control. The data which ROM101 memorize|stores includes the table data etc. which comprise the table used for a variation pattern, production|presentation control command, other various setting, determination, and determination. The RAM 102 provided in the game control microcomputer 100 is a temporary storage device that provides a work area used for game control and a stack for saving data. The RAM 102 may be a backup RAM that stores the contents stored in part or all of the storage area so as to be recoverable within a predetermined period of time even when the power supply to the pachinko game machine 1 is stopped. The RAM 102 is also called RWM (Read/Write Memory). The work area of the RAM 102 includes storage areas capable of storing various data used for game control, such as counters, timers, buffers, and storage areas for various codes and numerical values. The CPU 103 provided in the game control microcomputer 100 can control the progress of the game in the pachinko gaming machine 1 by executing processing corresponding to programs stored in the ROM 101 .

A random number circuit 104 provided in the game control microcomputer 100 counts updatably numerical data representing various random numbers used to control the progress of the game. A random number used to control the progress of a game is also called a game random number. Part or all of the game random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by CPU 103 .

FIG. 3 shows an example of game random numbers. The game random numbers are a random number MR1-1 for special symbol determination, a random number MR1-2 for winning symbols, a random number MR1-3 as an initial value for winning symbols, and a random number MR2-1 for normal symbols per symbol. , a random number MR2-2 as an initial value for the normal per-symbol pattern, a random number MR3-1 for the normal pattern variation pattern, a random number MR3-2 for selecting the losing effect, and a random number MR3-3 for selecting the type of variation pattern. , and random numbers MR3-4 for variation patterns.

The random number MR1-1 for determining the special design determines the display result of the special design, such as whether the display result of the special design is a "big hit" or whether the display result of the special design is a "small hit". Used for judgment. The random number MR1-2 for the winning pattern is a fixed special pattern such as a big hit pattern when the display result of the special pattern is set to "big hit" or a small hit pattern when the display result of the special pattern is set to "small hit". Used to select from multiple special symbols. The random number MR1-3, which is the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The normal symbol hit random number MR2-1 is used to select a fixed normal symbol to be displayed when the display result is "general hit" in the variable display of normal symbols from a plurality of normal symbols. The random number MR2-2, which is the initial value for the normal per-symbol pattern, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the normal symbol variation pattern to one of a plurality of patterns prepared in advance. The random number MR3-2 for selecting the loss effect is used to select whether or not the ready-to-win mode is set in the variable display of the effect symbols when the display result of the special symbol is "loss". The random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbol. The variation pattern type of the special symbol is a group in which the variation pattern of the special symbol is classified in advance based on, for example, the effect mode during the variable display of the effect symbol, and is configured to include one or more variation patterns. Just do it. The random number MR3-4 for the variation pattern is used to select a special symbol variation pattern.

The CPU 103 reads various tables from the ROM 101 and refers to them when performing various judgments and decisions based on random numbers, such as numerical data indicating game random numbers. Even when random numbers are not used, a necessary table may be read out from the ROM 101 and referenced to perform various determinations, decisions, settings, and the like.

The I/O 105 provided in the game control microcomputer 100 includes an input port to which various signals are input and an output port to which various signals are output. Various signals input to the input port of the I/O 105 may include detection signals from various switches transmitted via the switch circuit 110 . Various signals output from the output port of the I/O 105 are the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first reservation display device 25A, the second reservation display device 25B, A signal for controlling the normal figure holding display 25C, etc., and a solenoid drive signal for driving the normal electric accessory solenoid 81, the big winning opening solenoid 82, the specific area solenoid 83, etc., may be included.

The main board 11 outputs an effect control command corresponding to the progress of the game to the effect control board 12 as part of the operation of controlling the progress of the game by the game control microcomputer 100 . The effect control command is a command that designates or notifies the progress of the game or the like. The effect control command output from the main board 11 is relayed by the relay board 15 and supplied to the effect control board 12. - 特許庁The effect control commands include commands for specifying various determination results on the main board 11, such as the display result of the special game, the winning type, and the variation pattern, for example, the start and end of the variable display, the opening status of the big winning opening, and winning. , the number of pending memories, the game state, and a command specifying the occurrence of an error.

The performance control board 12 is a sub side control board independent of the main board 11, and has a function capable of receiving a performance control command and controlling the performance based on the received performance control command. The effects that can be controlled by the effect control board 12 are various effects according to the progress of the game, such as driving the movable body 32, and also include various notifications such as error notification and power failure recovery notification. The performance control board 12 includes a performance control CPU 120, a ROM 121, a RAM 122, a display control section 123, a random number circuit 124, and an I/O 125.

The effect control CPU 120 executes a program stored in the ROM 121 to perform processing for controlling the execution of the effect together with the display control unit 123 . This process is a process for realizing various functions of the effect control board 12, and includes determination of the effect to be executed. The effect control CPU 120 uses various data stored in the ROM 121, such as data of various tables, and uses the RAM 122 as a main memory. The effect control CPU 120 may instruct the display control unit 123 to execute the effect based on detection signals from the controller sensor unit 35A and the push sensor 35B. The detection signal here is a signal that is output when an operation by a player is detected, and may be a signal that appropriately indicates the content of the operation.

The display control unit 123 includes a VDP (Video Display Processor), a CGROM (Character Generator ROM), a VRAM (Video RAM), etc., and executes mainly display-related effects based on the effect execution instruction from the effect control CPU 120. control possible. The display control unit 123 displays the effect image on the screen of the image display device 5 by supplying a video signal corresponding to the effect to be executed to the image display device 5 . The display control unit 123 also supplies a sound designation signal to the audio control board 13 and a lamp signal to the lamp control board 14 . The sound designation signal designates sounds to be output from the speakers 8L and 8R. The lamp signal designates a lighting mode or an extinguishing mode of the game effect lamp 9 . By supplying the sound designation signal and the lamp signal, it becomes possible to output sounds from the speakers 8L and 8R and turn on/off the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be capable of supplying a signal for operating the movable body 32 to the motor or solenoid of the movable body 32 or to a driver circuit that drives the movable body 32 . A driver board for driving the movable body 32 may be provided separately from the effect control board 12 .

The random number circuit 124 counts updatably numerical data indicating various random numbers used when controlling the execution of various effects. A random number used to control the execution of a performance is also called a random number for performance. The effect random number may be updated by software such as a computer program executed by the effect control CPU 120 . The effect control CPU 120 reads various tables from the ROM 121 and refers to them when performing various determinations and determinations based on random numbers, such as numerical data indicating the value of random numbers for effect. Even if a random number value is not used, the effect control CPU 120 may read a necessary table from the ROM 121 and refer to it to perform various determinations, determinations, settings, and the like.

The I/O 125 includes, for example, an input port for receiving effect control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I/O 125 may include an input terminal for the detection signal supplied from the controller sensor unit 35A and an input terminal for the detection signal supplied from the push sensor 35B. The output ports of the I/O 125 are an output terminal for a video signal supplied to the image display device 5, an output terminal for an audio designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14. and an output terminal.

The audio control board 13 is equipped with various circuits for driving the speakers 8L and 8R, drives the speakers 8L and 8R based on the sound designation signal from the display control unit 123, and outputs the sound designated by the sound designation signal to the speaker. Output from 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamp 9, drives the game effect lamp 9 based on the lamp signal from the display control unit 123, and controls the game effect lamp in a manner specified by the lamp signal. 9 is turned on or off. In this manner, the sound output from the speakers 8L and 8R and the lighting and extinguishing of the game effect lamp 9 can be controlled based on the signal from the display control section 123. FIG. It should be noted that control of sound output and lamp lighting and extinguishing, such as supply of sound designation signals and lamp signals, and control of the movable bodies 32, such as supply of signals for operating the movable bodies 32, are partly performed by the effect control CPU 120. Or you may make it run all. Boards other than the main board 11, such as the effect control board 12, the sound control board 13, and the lamp control board 14, are also called sub-boards. As in the configuration example shown in FIG. 2, a plurality of sub-boards may be provided for each function, or unlike the configuration example shown in FIG. 2, one sub-board may be configured to have a plurality of functions. good.

The power supply board 17 can supply electric power from an AC power supply such as AC 100V in an external power supply such as a commercial power supply to electrical components including various control boards such as the main board 11 and the performance control board 12 . The power supply board 17 includes, for example, a rectifier circuit for converting alternating current (AC) into direct current (DC), a power circuit for converting a predetermined DC voltage into a specific DC voltage (eg, 12 V DC or 5 V DC), and the like. I have it. The pachinko game machine 1 can switch between starting and ending power-on by operating the power switch 91 . A switch circuit 110 on the main board 11 receives a reset signal, a power-off signal, and a clear signal from the power supply board 17 and transmits them to the game control microcomputer 100 . The reset signal is an operation stop signal for stopping the operation of the control circuit such as the game control microcomputer 100, and can be output using either the power supply monitoring circuit, the IC with built-in watchdog timer, or the system reset IC. I wish I had. The power-off signal turns off when a predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and turns on when the period in which the predetermined power supply voltage is equal to or less than the predetermined value continues for a power-off reference time or longer. Become. The clear signal is turned on, for example, when a clear switch 92 provided on the power supply board 17 is pressed.

(motion)
Next, the operation (action) of the pachinko game machine 1 will be described.

(Major operations of the main substrate 11)
First, main operations in the main board 11 will be described. When power supply to the pachinko game machine 1 is started, the game control microcomputer 100 is activated, and the CPU 103 executes main processing for game control.

FIG. 4 is a flow chart showing main processing P_MAIN for game control executed by the CPU 103 on the main board 11 . When the main process P_MAIN for game control shown in FIG. 4 is started, the CPU 103 executes power supply start corresponding process P_POWER_ON (step S1), and then executes RWM check process P_RWM_CHK (step S2). In the power supply start corresponding process P_POWER_ON of step S1, initial setting of the game control microcomputer 100 and the like can be executed in response to the start of power supply in the pachinko game machine 1. FIG. The initial setting of the game control microcomputer 100 may include output port initialization, interrupt vector setting, built-in device register setting, and specific register setting. The RWM check processing P_RWM_CHK in step S2 includes checksum calculation processing, and compares the checksum data obtained as a processing result with the data stored in the checksum buffer. Judge that the content is normal.

Subsequently, it is determined whether or not a predetermined restoration condition is satisfied (step S3). The recovery condition can be established when the clear signal corresponding to the operation of the clear switch 92 is in the OFF state, the checksum buffer has normal stored data, and the stored contents in the RAM 102 as a backup RAM are normal. . When the power of the pachinko game machine 1 is turned on, for example, if the clear switch 92 provided on the power supply board 17 is pressed, a clear signal in the on state is input to the game control microcomputer 100 . If such an on-state clear signal is input, it may be determined in step S3 that the restoration condition is not satisfied. The checksum buffer stores the checksum data calculated by the checksum calculation process when the backup judgment time is measured by the backup monitoring timer at the time of the previous power failure. If the measured value of the backup monitoring timer does not match the specific value corresponding to the backup determination time, it may be determined in step S3 that the recovery condition is not satisfied. The backup data may be data stored in the game work area in the RAM 102 which serves as a backup RAM for game control. In step S3, whether or not the recovery condition can be satisfied may be determined based on the result of confirming or inspecting the presence or absence of backup data and the presence or absence of data errors by the RWM check process P_RWM_CHK of step S2.

If the recovery condition is satisfied (step S3; Yes), the backup setting process P_BACKUP_SET is executed (step S4). The setting process P_BACKUP_SET at the time of backup makes it possible to transmit the effect control command corresponding to the time of backup from the main board 11 to the effect control board 12 using the command transmission table at the time of backup. The backup setting process P_BACKUP_SET enables initialization by clearing the process code, timer, counter, and flag specified by the backup setting table.

If the recovery condition is not satisfied (step S3; No), the initialization setting process P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET makes it possible to transfer clear data to a game work area, which is a work area in the RAM 102 . Thereby, the game work area in the RAM 102 is initialized. Then, the initialization setting process P_INIT_SET enables transmission of the effect control command corresponding to the initialization from the main board 11 to the effect control board 12 using the command transmission table at the time of initialization. The initialization setting process P_INIT_SET enables initialization by clearing the buffers, timers, pointers, and counters specified by the initialization setting table.

Thereafter, a control start setting process P_STACON is executed (step S6). The control start setting processing P_STACON may include wait processing. The wait process executes a loop process and waits until a set waiting time elapses, so that the sub-board such as the performance control board 12 can be reliably activated. Also, the control start setting process P_STACON may include a specific number of times command transmission process or a chip individual number information command transmission process. The specified number of times command transmission processing enables transmission of a performance control command designating the count value of the specified number of times counter from the main board 11 to the performance control board 12 when the power is turned on. The specific number counter is provided at a predetermined address in the RAM 102, and may be capable of counting the remaining number of times until the number of executions of the variable display reaches the specific number corresponding to the time saving condition. The command transmission processing for chip individual number information makes it possible to transmit an effect control command designating the stored value of the chip individual number register from the main board 11 to the effect control board 12 . The individual chip number register is included in the built-in register of the game control microcomputer 100, and may store different values assigned to each chip as an individual chip number.

The control start setting process P_STACON may include an out-of-area process at startup. The start-time outside area processing is a process executed by reading out a program stored in the non-game program area of the ROM 101 corresponding to start-up due to the start of power supply in the pachinko gaming machine 1 . The start-up outside area processing may be, for example, performance display RWM initial value setting processing. The performance display RWM initial value setting process makes it possible to set initial values for initial display by the 7-segment LEDs constituting the performance display monitor. The performance display monitor may be mounted on the main board 11, for example, and may display the contents of the set values and the contents of the base. The setting value can be changed to any one of a plurality of stages such as 6 stages when the setting of the pachinko game machine 1 is changeable, and the probability that the display result of the special symbol will be a "big hit". be configurable. The base is divided by the number of game balls launched into the game area by the number of prize balls paid out when the game balls pass through each of the winning openings, such as the start winning opening, the general winning opening, and the big winning opening. Calculated.

After the control start setting process P_STACON in step S6, timer interrupt counter setting is performed (step S7). In step S7, the PTC counter output value is set so that a periodic timer interrupt occurs at predetermined time intervals, such as 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop process. In this loop processing, interrupt prohibition is set (step S8), random number update processing P_TFINIT for initial value determination is executed (step S9), and after loop outside region processing P_REGOUT is executed (step S10), interrupt permission is executed. is set (step S11), and the process returns to step S8. The CPU 103 is enabled to execute timer interrupt processing each time an interrupt request signal is input to the CPU 103 from the PTC when the interrupt is enabled. As a result, the CPU 103 can execute timer interrupt processing each time a predetermined period of time, such as 4 [ms], elapses.

FIG. 5 is a flowchart showing an example of timer interrupt processing P_PCT for game control. In the timer interrupt process P_PCT shown in FIG. 5, a power-off process P_POWER_OFF is executed (step S51). Subsequently, it is determined whether or not the illegal activity monitoring flag is "0" (step S52). The illegal activity monitoring flag is set to "1" corresponding to the ON state when magnetism is detected by the magnet sensor or radio waves are detected by the frame radio wave sensor. Otherwise, the fraud monitor flag is set to '0', which corresponds to an off state.

If the fraudulent activity monitoring flag is "1" (step S52; No), game stop processing P_GAME_STOP is executed (step S53). The game stop processing P_GAME_STOP may be processing that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and when it is in the OFF state, execution of the payout process in the payout control board is stopped.

If the illegality monitoring flag is "0" (step S52; Yes), the switch process P_SW is executed (step S54), the switch error notification process P_CON_CHK is executed (step S55), and the random number update process P_RANDOM is executed. (Step S56), a random number update process P_TFINIT for initial value determination is executed (Step S57). In addition, special symbol process processing P_TPROC is executed (step S58), normal symbol process processing P_FPROC is executed (step S59), information output processing P_JYOUHOU is executed (step S60), prize ball processing P_PAY is executed (step S61 ), and the display process P_HYOUZI is executed (step S62). Further, other timer interrupt handling processing is executed (step S63). Thereafter, after the interrupt permission is set (step S64), the timer interrupt process P_PCT ends.

In the power-off process P_POWER_OFF in step S51, the power confirmation signal transmitted from the power supply board 17 is determined, and the checksum calculation process and the like at the time of power-off can be executed. The switch processing P_SW in step S54 determines the state of the input port and enables update of the switch-on buffer and the like. The switch error notification process P_CON_CHK in step S55 can update the count value of the sensor ON counter specified by the switch error notification determination table, for example, and when the count value reaches the sensor abnormality error determination value, the error notification display be executable. The random number update process P_RANDOM in step S56 allows software random numbers among game random numbers to be updated by software. The random number update process P_TFINIT for initial value determination in step S57 makes it possible to update the random number used as the random number initial value among the game random numbers by software.

The special symbol process processing P_TPROC in step S58 includes processing related to the variable display of special symbols and the game state, such as management of execution and suspension of the special symbol game, control of the big win game state and small win game state, and control of the game state. be The normal symbol process processing P_FPROC of step S59 includes normal symbol processing such as management of execution and suspension of the normal pattern game based on the detection signal from the gate switch 21, opening and closing control of the variable winning ball device 6B based on "normal pattern hit", etc. It includes processing related to variable display and state control of the second start winning opening. Information output processing P_JYOUHOU in step S60 sets an information output signal. The information output signal is a signal corresponding to information supplied to a hall management computer installed outside the pachinko gaming machine 1, such as jackpot information, starting information, and probability variation information. The jackpot information indicates the number of occurrences of jackpots and the like. The starting information indicates the number of starting winnings and the like. The probability variation information indicates, for example, the number of times the probability variation state has occurred. The prize ball processing P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. In the prize ball command output counter addition process, a prize ball number table is used to determine whether the switch is turned on, and when the switch is detected to be on, the prize ball command output counter and the winning information output counter are updated. The prize ball control process selects the process corresponding to the prize ball process code, and controls the payout of the prize balls based on the detection of the game balls. The display processing P_HYOUZI in step S62 sets the display related to the first suspension indicator 25A, the second suspension indicator 25B, the normal diagram suspension indicator 25C, and various other status indicator lamps.

FIG. 6 is a flow chart showing an example of a process that can be executed in step S58 shown in FIG. 5 as the special symbol process process P_TPROC. The CPU 103 sets the flag corresponding to the first start winning prize in the special symbol process process P_TPROC (step S101). The setting of the flag corresponding to the first starting winning a prize reflects the state of the first starting opening switch 22A included in the switch-on buffer in the flag register of the CPU 103 by executing a logic operation instruction or the like. At this time, the ON state of the zero flag in the flag register indicates that the first start winning corresponding flag is OFF state. On the other hand, the fact that the zero flag is off indicates that the first start winning correspondence flag is on. Subsequently, a first start winning prize table is set by a transfer command for setting a table pointer (step S102). After that, it is determined whether or not the flag corresponding to the first starting prize is ON (step S103). When the first starting winning corresponding flag is ON (step S103; Yes), the starting opening switch passing process P_TZU_ON is executed (step S104).

When the first start winning correspondence flag is OFF corresponding to step S103 (step S103; No), or after the starting opening switch passage processing P_TZU_ON in step S104, the second start winning correspondence flag is set (step S105). . The setting of the flag corresponding to the second starting winning a prize reflects the state of the second starting opening switch 22B included in the switch-on buffer in the flag register of the CPU 103 by executing a logic operation instruction or the like. At this time, the ON state of the zero flag in the flag register indicates that the second start winning corresponding flag is OFF state. On the other hand, the fact that the zero flag is off indicates that the second start winning correspondence flag is on. Subsequently, a second start winning prize table is set by a transfer command for setting a table pointer (step S106). After that, it is determined whether or not the flag corresponding to the second starting prize is ON (step S107). When the second starting winning corresponding flag is ON (step S107; Yes), the starting opening switch passing process P_TZU_ON is executed (step S108).

The starting opening switch passing process P_TZU_ON of step 104 uses the first starting opening winning prize table set in step S102, and when the first reserved memory number is less than the upper limit number, the first reserved memory number and the total reserved The memory number is updated by adding 1, and the random number MR1-1 for special symbol determination, the random number MR3-2 for selecting the losing effect, the random number MR3-3 for selecting the variation pattern type, and the random number MR3 for the variation pattern. After extracting -4 and storing them in the respective random number buffers, they are transferred to the first special symbol holding buffer. In addition, using the first reserved memory information designation command transmission table, the first reserved memory information designation command designating the number of first reserved memories can be transmitted from the main board 11 to the effect control board 12.例文帳に追加Then, a value indicating "1" is stored in the start-up winning buffer as the start-up winning specified value.

The starting opening switch passing process P_TZU_ON in step S108 uses the second starting opening winning table set in step S106, and if the second reserved memory number is less than the upper limit number, the second reserved memory number or the total reserved The memory number is updated by adding 1, and the random number MR1-1 for special symbol determination, the random number MR3-2 for selecting the losing effect, the random number MR3-3 for selecting the variation pattern type, and the random number MR3 for the variation pattern. After extracting -4 and storing them in the respective random number buffers, they are transferred to the second special symbol holding buffer. In addition, using the second reserved memory information designation command transmission table, the second reserved memory information designation command designating the number of second reserved memories can be transmitted from the main board 11 to the effect control board 12. - 特許庁Then, a value indicating "2" is stored in the start-up winning buffer as the start-up winning designation value.

In step S104 and step S108, it is possible to execute a common starting port switch passage process P_TZU_ON. On the other hand, the starting opening switch passing process P_TZU_ON in step S104 uses the first starting opening winning table set in step S102, while the starting opening switch passing process P_TZU_ON in step S108 uses the first starting opening winning table set in step S106. 2 Use the start-up prize table. In this way, the common starting opening switch passing process P_TZU_ON is executed using different starting opening winning tables. Therefore, when the game ball enters the first starting winning hole and when entering the second starting winning hole, different data setting and control can be performed by common processing. In addition, the starting opening switch passage process P_TZU_ON may include a win effect process using the extracted game random number.

If the second start winning correspondence flag is off corresponding to step S107 (step S107; No), after the start opening switch passage processing P_TZU_ON in step S108, a special symbol process processing jump by a transfer command to set a pointer A table is set (step S109). The special symbol process processing jump table is an address management table that enables selection and execution of processing corresponding to the read value of the special symbol process code. The special symbol process code can be updated to any one of 00 [H] to 0B [H] corresponding to the progress of game control in the pachinko gaming machine 1, and is also called a special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] may indicate a binary number.

Following step S109, a special symbol process code is loaded by a transfer command for reading stored data (step S110). Next, by executing the 2-byte data selection process P_ABXEXEC (step S111), the address of the process selected corresponding to the special design process code is acquired. The address acquired at this time is set in the pointer. After that, by executing the process pointed to by the pointer according to the subroutine call command (step S112), the process selected corresponding to the special symbol process code can be executed. When the selected process ends and returns to the special symbol process process P_TPROC by the return command, this special symbol process process P_TPROC also ends and returns to the timer interrupt process P_PCT for game control by the return command.

FIG. 7 shows a configuration example TT01 of a special symbol process processing jump table used in the special symbol process processing P_TPROC. The special symbol process processing jump table includes table data that can set the address of the process selected in correspondence with the special symbol process code to the internal register of the CPU 103 used as a pointer. The special symbol process processing jump table of configuration example TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H] and special symbol variation processing P_TSTART when the special symbol process code is 01 [H]. And, special symbol stop processing P_TSTOP when the special symbol process code is 02 [H], small hit opening pre-processing P_TLFAN when the special symbol process code is 03 [H], and special symbol process code is 04 [ H] during small hit opening process P_TLOPEN, small hit post-opening process P_TLCLSF when special symbol process code is 05 [H], and small hit when special symbol process code is 06 [H] Eject ball waiting processing P_TLOUT, small winning end processing P_TLEND when the special symbol process code is 07 [H], large winning opening pre-processing P_TINT when the special symbol process code is 08 [H], special Large winning opening opening process P_TOPEN when the symbol process code is 09 [H], large winning opening post-opening process P_TCLSF when the special symbol process code is 0A [H], and special symbol process code 0B [ H] and the table data that can set the address value corresponding to the jackpot end process P_TEND in the pointer.

The special symbol normal process P_TNORMAL includes determining whether or not to start the special symbol game based on the presence or absence of stored reservation information, determining the special symbol display result using the random number MR1-1 for special symbol determination, To determine fixed special symbols to be stopped and displayed in variable display of special symbols, and to determine variation patterns of special symbols. The special figure display result includes ``big win'', ``small win'', ``losing'', etc., and when it is determined to be ``big win'', control is made to a big win game state as an advantageous state for the player. is determined. Further, when the display result of the special pattern is "big win", any one of a plurality of types of jackpot game states with different degrees of advantage for the player can be selected in correspondence with the jackpot pattern to be a confirmed special pattern. It is determined whether the state is controlled. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether or not to control to an advantageous state advantageous to the player. It is possible to decide which one to control. Furthermore, the CPU 103 can determine any one of a plurality of types of variation patterns by executing the special symbol normal process P_TNORMAL.

The special symbol variation process P_TSTART measures the elapsed time after the special symbol starts to vary in the first special symbol display device 4A and the second special symbol display device 4B, and the special symbol variation time corresponding to the variation pattern has elapsed. It is possible to determine whether or not The special symbol stop processing P_TSTOP measures the elapsed time after the special symbol stops changing in the first special symbol display device 4A or the second special symbol display device 4B, and determines whether or not the symbol stop time has elapsed. enable The symbol stop time may be set as the time to stop and display the special symbol when it is determined that the special symbol variation time has elapsed in the special symbol variation process P_TSTART. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are performed in accordance with the special symbol display result. For example, when the special figure display result is "big hit", the special symbol process code can be updated to 08 [H], and when the special figure display result is "small hit", the special symbol process code can be changed to 03 [H]. It is possible to update, and if the special symbol process code can be updated to 00 [H] when the special figure display result is "loss".

Small hit opening pre-processing P_TLFAN, small hit opening middle processing P_TLOPEN, small hit opening post-processing P_TLCLSF, small hit discharge ball standby processing P_TLOUT, small hit end processing P_TLEND are processes for controlling the progress of the game in the small hit game state is. The big winning hole opening pre-processing P_TINT, the big winning hole opening process P_TOPEN, the big winning hole opening post-processing P_TCLSF, and the jackpot ending process P_TEND are processes for controlling the progress of the game in the jackpot game state.

(Major operations of production control board 12)
Next, main operations in the effect control board 12 will be described. In the effect control board 12, when power supply voltage is supplied from the power supply board 17 or the like, the effect control CPU 120 is activated to execute the effect control main process.

FIG. 8 is a flow chart showing main processing S_MAIN for effect control executed by the effect control CPU 120 in the effect control board 12 . When the main process S_MAIN for effect control shown in FIG. 8 is started, the effect control CPU 120 executes effect control initialization process S_INIT (step S71). The effect control initialization process S_INIT includes clearing of the RAM 122, setting of various initial values, register setting for the timer circuit mounted on the effect control board 12, and the like. Subsequently, an initial operation control process S_SYOKI is executed (step S72). The initial motion control process S_SYOKI makes it possible to control the initial motion of the movable body 32, such as control for driving the movable body 32 to return it to the initial position, control for confirming a predetermined motion, and the like. After that, it is determined whether or not the timer interrupt flag is on (step S73). The timer interrupt flag is set to an ON state every time a predetermined time such as 2 [ms (milliseconds)] elapses based on the register setting for the timer circuit. When the timer interrupt flag is turned off (step S73; No), step S73 is repeated to wait.

When the timer interrupt flag is turned on (step S73; Yes), the timer interrupt flag is cleared and turned off (step S74), the command analysis process S_COMMAND is executed (step S75), and the effect control process process S_CPROC is executed (step S76), the effect random number update process S_RANDOM is executed (step S77), and the effect output process S_OUT is executed (step S78). After executing another timer interrupt handling process (step S79), the process returns to step S73.

Command analysis processing S_COMMAND of step S75 enables reading of the production control command stored in the production control command reception buffer, and setting and control corresponding to the read production control command. By executing the command analysis process S_COMMAND, the effect control CPU 120 responds to the effect control command transmitted from the main board 11 by storing data indicating the state of the flag, data stored in the register, and other work areas of the RAM 122. Any stored data in , etc., can be updated. The effect control process processing S_CPROC in step S76 includes, for example, the display of effect images on the screen of the image display device 5, the sound output from the speakers 8L and 8R, and the lighting or To control the execution of performance using various performance devices including turning off and driving control of a movable body 32.例文帳に追加Control contents of effects using various effects devices can be judged, determined, set, etc., based on effects control commands transmitted from the main board 11, execution results of processes by the effects control CPU 120, and the like. good. The effect random number update process S_RANDOM in step S77 enables at least part of the effect random numbers used on the side of the effect control board 12 to be updated by executing a program as software.

FIG. 9(A) is a flow chart showing an example of a process that can be executed in step S76 shown in FIG. 8 as the effect control process process S_CPROC. The effect control CPU 120 executes a look-ahead effect setting process S_SAKI_SET in the effect control process (step S151). The look-ahead effect setting process S_SAKI_SET enables determination, determination, setting, etc. regarding the execution of the look-ahead prediction effect based on the effect control command at the time of starting winning, which is transmitted from the main substrate 11, for example. Also, the look-ahead effect setting process S_SAKI_SET makes it possible to update the pending display based on the number of pending memories specified from the effect control command.

After the look-ahead effect setting process S_SAKI_SET in step S151, the effect control process process jump table is set by the transfer command for setting the pointer (step S152). The performance control process processing jump table is an address management table that enables selection and execution of processing corresponding to the read value of the performance control process code. The effect control process code can be updated to any one of 00 [H] to 0A [H] corresponding to the progress of the effect control in the pachinko game machine 1, and is also called the effect process code. The performance control process code is loaded by a transfer command for reading stored data (step S153). Corresponding to the effect control process code acquired in this way, the address of the selected process is set to the effect control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected corresponding to the effect control process code can be executed.

FIG. 9(B) shows a configuration example TT02 of the effect control process processing jump table used in the effect control process processing S_CPROC. The performance control process processing jump table includes table data capable of setting the address of the process selected in correspondence with the performance control process code to a register used as a performance control pointer. The effect control process processing jump table of the configuration example TT02 includes the variation pattern command waiting process when the effect control process code is 00 [H], and the effect symbol variation start process when the effect control process code is 01 [H]. , production design change processing when the production control process code is 02 [H], production design fluctuation stop processing when the production control process code is 03 [H], and production control process code 04 [H ], a small hit open process when the effect control process code is 05 [H], and a small hit end effect process when the effect control process code is 06 [H]. , jackpot display processing when the production control process code is 07 [H], round processing when the production control process code is 08 [H], and production control process code when the production control process code is 09 [H] Table data that can set an address value corresponding to the post-round process and the jackpot end effect process when the effect control process code is 0A[H] is included in the effect control pointer.

Variation pattern command reception wait processing makes it possible to determine whether or not a variation pattern designation command transmitted from the game control microcomputer 100 of the main board 11 is received. When it is determined that the variation pattern designation command is received, the effect control process code is updated to 01 [H] corresponding to the effect symbol variation start process, and when it is determined that the variation pattern designation command is not received, the demonstration Make the display controllable. The performance symbol variation start processing enables the start of the performance at the time of variation corresponding to the special symbol game. For example, corresponding to the variation pattern command transmitted from the main board 11, it is possible to select the performance pattern used for controlling the performance at the time of variation and to start updating the performance process timer for measuring the performance execution time. The performance symbol change process makes it possible to control the switching timing of each performance element constituting the performance pattern, and to determine whether or not the performance execution time has elapsed based on the measured value of the performance process timer. When it is determined that the performance execution time has passed, the performance control process code is updated to 03 [H] corresponding to the performance symbol variation stop processing. The production design fluctuation stop processing is based on the fact that the production execution time has elapsed or the production design confirmation command has been received, and the end condition of the production at the time of fluctuation is satisfied. To enable display control of a performance result corresponding to a pattern. At this time, the production control process code is updated and various settings are performed according to the display result of the variable display. For example, when the display result of the variable display is "big hit", the effect control process code can be updated to 07 [H], and when the display result of the variable display is "small hit", the effect control process code can be updated to 04 [H]. ], and the effect control process code can be updated to 00 [H] when the display result of the variable display is "loss".

The small-hit display process, the small-hit opening process, and the small-hit end production process are processes for controlling the progress of the production corresponding to the small-hit game state. The big hit display process, the mid-round process, the post-round process, and the big hit end effect process are processes for controlling the progress of the effect corresponding to the big win game state.

(Modified example of basic explanation, etc.)
The pachinko game machine 1 is not limited to the configuration, functions, processing, and operations in the basic explanation and other explanations, and various modifications and applications are possible. For example, the pachinko game machine 1 does not have to have all the technical features shown in the embodiment, and some of the technical features described in the embodiment can solve at least one problem in the prior art. It may be provided with the configuration of. In the embodiment, when a matter that is a more specific concept is described, an invention of a generic concept using a matter of the same family or a similar kind, or an invention of a generic concept using a common property is regarded as the claimed invention. It may have some of the structures and characteristics described in the embodiments so as to be included and solve at least one problem in the prior art.

The pachinko game machine 1 may be a payout type game machine that pays out a predetermined number of game media as prizes based on the occurrence of winning, or an enclosed type game that encloses game media and gives points when winning occurs. machine.

Only one type of pattern such as a sign indicating "-" may be displayed during the variable display of the special pattern, and variable display may be performed by repeating the display and extinguishing of this pattern. One type of pattern may be displayed during the variable display, and this pattern may not be displayed when the variable display is stopped. For example, as a display result, the sign indicating "-" may not be displayed, and a non-display state may be set in which no special symbol is displayed.

The pachinko game machine 1 may be provided with a configuration in which the probability of winning a big hit and the rate of winning balls are changed in accordance with a plurality of set values. For example, in the special symbol normal processing of the special symbol process processing, by using a different jackpot determination value for each set value that is set, it may be possible to change the probability of winning the jackpot and the ball output rate. As a specific example, the set value consists of 6 stages from 1 to 6, with 6 having the highest probability of winning the jackpot, and the smaller the value in the order of 6, 5, 4, 3, 2, and 1, the higher the probability of winning the jackpot. lower. In this case, if 6 is set as the setting value, the advantage for the player is the highest, and the lower the value is in the order of 6, 5, 4, 3, 2, and 1, the lower the advantage is. If the winning probability of the big win changes according to the set value, the ball payout rate may also change according to the set value. While the winning probability of the big win is constant regardless of the set value, the number of rounds in the big win game state may change according to the set value. The pachinko game machine 1 may be configured so as to be able to set one of a plurality of set values with different degrees of advantage for the player. The set value set in the pachinko game machine 1 may be notified by transmitting a set value designation command from the main board 11 side to the effect control board 12 side. During execution of the variable display, it may be possible to execute a setting suggestion effect that suggests the setting value in the pachinko game machine 1 at a predetermined rate. The suggestion about the setting value of the pachinko gaming machine 1 is not limited to suggesting the setting value of the pachinko gaming machine 1, and may be, for example, suggesting whether or not the setting value of the pachinko gaming machine 1 has been changed. . The setting suggesting effect may suggest the degree of expectation for a big hit by an arbitrary effect, and may suggest the setting value of the pachinko game machine 1.例文帳に追加

In place of part or all of the suggestion about the control of the big win game state, or together with part or all of the suggestion about the control of the big win game state, a suggestion about control of a state advantageous to the player different from the big win game state is provided. can be anything. For example, it may be one that suggests a variable probability state to be controlled after the end of the jackpot gaming state. In addition, as the advantageous state, a suggestion may be made according to whether or not control is to be performed regarding a state in which an arbitrary game value that is advantageous to the player is awarded.

The invention relating to the game machine is not limited to the pachinko game machine 1, and can be applied to slot machines as appropriate. In the slot machine, medals are inserted and a predetermined number of bets is set, a plurality of types of symbols are rotated according to the operation of the operation lever by the player, and the symbols are stopped according to the operation of the stop button by the player. It is possible to execute a game in which a predetermined number of medals are paid out to the player when the combination of stop symbols becomes a combination of specific symbols. In a slot machine, an advantageous state advantageous to a player may include one or more of so-called bonuses such as big bonus, regular bonus, RT, AT, ART, and CZ.

Programs and data for realizing various controls including the progress of a game and the execution of effects can be distributed and provided to a computer device included in a game machine such as the pachinko game machine 1 via a detachable recording medium. It may be something that can be distributed and provided by being installed in advance in a storage device such as a computer device. Further, it may be provided with a communication processing unit connectable to an external device on a network via a communication line or the like, and may be distributed or provided by downloading the program or data from the external device. The mode of execution of games and presentations may be executable by installing a detachable recording medium, or programs and data downloaded via a communication line etc. may be temporarily stored in an internal memory or the like. or can be directly executed using hardware resources in an external device on a network connected via a communication line, or another computer device A game or performance may be executed by exchanging data via a network.

Expressions such as "high", "low", and "different" when comparing various ratios such as the determination ratio of processing and data, the execution ratio of effects, etc. are the ratio of "0%" or "100%" may include being For example, one decision result or execution content may include a case where there is no decision or execution at a rate of "0%", or a case where there is always a decision or execution at a rate of "100%".

(Description of Characteristic Portion 01AK)
FIG. 10-1 shows a configuration example of the game control microcomputer 100 with respect to the characteristic portion 01AK. Characteristic part 01AK game control microcomputer 100 includes ROM 101, RAM 102, CPU 103, external bus interface 131, clock circuit 132, unique information storage circuit 133, reset controller 134, interrupt controller 135, timer circuit 136, address decoding It comprises a circuit 137 , a free-running counter 138 and a serial communication circuit 139 . The random number circuit 104 shown in FIG. 2 includes a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I/O 105 shown in FIG. 2 includes a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

The external bus interface 131 is a bus interface having an interface function between the external bus and the internal bus of the chip that constitutes the game control microcomputer 100, an address bus, a data bus, a direction control function for each control signal, and the like. For example, the external bus interface 131 is connected to an external memory or an external input/output device externally attached to the game control microcomputer 100, and exchanges address signals, data signals, various control signals, etc. with these external devices. can be sent and received. The external bus interface 131 may include an internal resource access control circuit that controls access to internal data of the game control microcomputer 100 from an external device.

The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the control external clock terminal EXC. A control clock generated by a control clock generation circuit provided in the game control microcomputer 100 may be input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, 16-bit random number circuit 104A, and 8-bit random number circuit 104B. Further, the internal system clock SCLK can be output to the outside of the game control microcomputer 100 from the system clock output terminal CLKO. Alternatively, the internal system clock SCLK is restricted so as not to be output to the outside of the game control microcomputer 100, thereby making it difficult to specify the operating state of the game control microcomputer 100 from the outside. good.

The unique information storage circuit 133 can store, for example, multiple types of unique information that are internal information of the game control microcomputer 100 . For example, the unique information storage circuit 133 may store ROM codes, individual chip numbers, and ID numbers as unique information that differs for each chip of the game control microcomputer 100 . A ROM code is numerical data that can be generated from data stored in a predetermined area of the ROM 101 . The individual chip number and the ID number are numbers given when the game control microcomputer 100 is manufactured, and show different numerical values for each chip. The individual chip number may be set so that it can be read by a user program such as a game program, while the ID number cannot be read by the user program. The unique information storage circuit 133 may be included in a predetermined area of the ROM 101 or may be included in a built-in register of the game control microcomputer 100 .

The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100 . Resets controllable by reset controller 134 include system resets and user resets. A system reset occurs when the input signal of the external system reset terminal XSRST is at low level for a certain period of time. A user reset is caused by a predetermined factor such as occurrence of a time-out signal of the watchdog timer 134A, occurrence of an out-of-designated-area travel prohibition (IAT), or the like. Reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to the monitoring time, enables countdown to update the timer value by periodically subtracting 1, and when the timer value becomes "0" and a timeout occurs, , It is possible to output a timeout signal for resetting the game control microcomputer 100 and restarting it. Thereby, the watchdog timer 134A can reset the game control microcomputer 100 when measuring the monitoring time and measuring that the monitoring time has passed. The watchdog timer 134A can be set to enable or disable operation according to, for example, a game program.

The interrupt controller 135 can control various interrupt requests generated inside or outside the game control microcomputer 100 . Interrupts controllable by interrupt controller 135 include non-maskable interrupt NMI and maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 103 is in an interrupt disabled state, and is generated when the input signal of the external non-maskable interrupt terminal XNMI (also used as the input port PI6) is at low level for a certain period of time. The maskable interrupt INT is an interrupt that can permit or prohibit acceptance of an interrupt request by a setting command of the CPU 103, and multiple interrupts can be executed by priority setting. The factors of the maskable interrupt INT are that the input signal of the external maskable interrupt terminal XINT (also used as the input port PI5) is low level for a certain period of time, that the timer circuit 136 has timed out, and that the 16-bit random number circuit 104A It is only necessary to be able to set some or all of a plurality of types of interrupt factors including the fact that the 8-bit random number circuit 104B has stored the numerical data representing the random number in the random number register.

The timer circuit 136 includes a PTC (Programmable Timer Counter) as a timer counter corresponding to the three channels PTC0 to PTC2, and enables real-time interrupt generation and time measurement. Each channel PTC0 to PTC2 of the timer circuit 136 uses a count clock generated based on the internal system clock SCLK, and responds to changes in the signal of the count clock such as falling timing when the clock signal changes from high level to low level. It suffices if the timer value can be updated corresponding to .

The address decoding circuit 137 can decode various signals obtained from each functional block inside the game control microcomputer 100, and can output a chip select signal which is a decoding signal for an external device. The chip select signal selectively activates an internal circuit of the game control microcomputer 100 or an external device serving as a peripheral device, enabling access from the CPU 103 . Output terminals that can be used by the address decode circuit 137 are a parallel output signal from the POP 105B, a serial transmission signal from the serial communication circuit 139, a clock output signal from the clock circuit 132, and a chip select signal generated by the address decode circuit 137. , can be used as long as it can selectively output .

The free-running counter 138 includes counter circuits corresponding to four channels FRC0 to FRC3, and can update the count value independently of the operation of the CPU 103. FIG. Each channel FRC0 to FRC3 of the free-running counter 138 can be activated by an independent update clock, and can be set to stop or change its operation according to, for example, a game program. The count value by the free-running counter 138 can be stored in a hard latch register corresponding to the latch signal transmitted from the input terminal serving as the latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program.

The serial communication circuit 139 includes serial communication units corresponding to three channels SCU0, SCU1, and STU2, and enables communication with external devices by a serial communication method. Each channel SCU0, SCU1, STU2 of serial communication circuit 139 is capable of processing communication data, for example, in full-duplex, asynchronous, standard NRZ (Non Return to Zero) format. Channels SCU0 and SCU1 of serial communication circuit 139 are included in a first channel transmitting/receiving circuit capable of bidirectionally transmitting/receiving serial data to/from an external circuit. Channel STU2 of serial communication circuit 139 is included in a second channel transmission circuit capable of transmitting only unidirectional serial data to and from an external circuit. For example, the channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. Also, the channel SCU1 of the serial communication circuit 139 is used for data communication with the effect control board 12 . Instead of the channel SCU1 of the serial communication circuit 139, the channel STU2 of the serial communication circuit 139 may be used for data communication with the effect control board 12.

The 16-bit random number circuit 104A includes random number generation units corresponding to four channels RL0 to RL3, each of which independently operates to generate 16-bit pseudo-random number values from "0" to "65535." ” can be generated. The maximum value of the random number generated by each channel RL0 to RL3 in the 16-bit random number circuit 104A can be set to any value within the range from "256" to "65535". By setting such a maximum value, it is possible to perform an initial setting for selecting a method for starting the random number so that updating of the numerical data indicating the random number is started. Alternatively, each channel RL0 to RL3 in the 16-bit random number circuit 104A selects the random number activation method so that the operation mode of the game control microcomputer 100 is automatically activated by shifting from the security mode to the user mode. Initial setting is possible. The 16-bit random number circuit 104A can update the random number MR1-1 for special symbol determination through the channel RL0, and can update the random number MR3-2 for selecting the losing effect through the channel RL2.

The 8-bit random number circuit 104B includes random number generation units corresponding to four channels RS0 to RS3, each of which independently operates to generate an 8-bit pseudo-random number from "0" to "255". ” can be generated. The maximum value of the random number generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value within the range from "16" to "255". By setting such a maximum value, it is possible to perform an initial setting for selecting a method for starting the random number so that updating of the numerical data indicating the random number is started. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B selects a random number activation method so that the operation mode of the game control microcomputer 100 is automatically activated by shifting from the security mode to the user mode. Initial setting may be possible. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the variation pattern type by the channel RS1, can update the random number MR3-4 for the variation pattern by the channel RS2, and can change the normal symbol by the channel RS3. The random number MR3-1 for the pattern can be updated.

The PIP 105A incorporates, for example, an 8-bit width input-only port, and enables input of various signals from the outside of the game control microcomputer 100. FIG. The PIP 105A can use input terminals corresponding to input ports PI0 to PI7. The input port PI5 uses a function-shared terminal that can also be used as an external maskable interrupt terminal XINT. The input port PI6 uses a function shared terminal that can be shared with the external non-maskable interrupt terminal XNMI. Input port PI7 uses a function-shared terminal that can also be used as a receiving terminal of channel SCU0 in serial communication circuit 139. FIG. The POP 105B incorporates, for example, an 11-bit width output-only port, and enables various signals to be output to the outside of the game control microcomputer 100. FIG. The POP 105B can supply the address decode circuit 137 with parallel output signals corresponding to the output ports PO0 to PO7 and PO10 to PO12.

FIG. 10-2 shows an example of an address map in the game control microcomputer 100. FIG. In the example shown in FIG. 10-2, the area of addresses 0000 [H] to 3FFF [H] is allocated to the ROM 101, and includes a game program area, game data area, non-game program area, non-game data area, ROM comment area, Includes program management area and other unused areas. An area of addresses F000[H] to F3FF[H] is allocated to the RAM 102 and includes a game work area, a game stack area, a non-game work area, a non-game stack area, and other unused areas. The area of address FE00 [H] to FEBF [H] is a function setting register area assigned to the built-in register of the microcomputer 100 for game control. The area of address FF00 [H] to FFFF [H] is a function control register area assigned to the built-in register of the microcomputer 100 for game control.

In the ROM 101, a game program area can store a game program, which is a computer program relating to the progress of a game. The game data area can store game data used by the game program. The non-game program area can store a non-game program, which is a computer program related to control and processing different from progress of the game. The non-game data area can store non-game data used by the non-game program. These programs and data stored in the ROM 101 are designed and created in advance by the manufacturer of the pachinko gaming machine 1 who is the user of the game control microcomputer 100 . Therefore, the game program and the non-game program are included in the user program. Game data and non-game data are included in user data.

In the storage area of the ROM 101, a game program area capable of storing a game program relating to the progress of the game and a non-game program area relating to control and processing different from the progress of the game are separately provided. Among the game program areas, the area before the non-game program area to which the rear address is assigned becomes an unused area of a storage area equal to or larger than the boundary byte number, such as 16 bytes. As a result, it is possible to easily specify a game program area capable of storing a game program relating to the progress of a game and a non-game program area capable of storing a non-game program relating to control and processing different from the progress of the game. The design and management of the programs and data stored in the ROM 101 are facilitated.

In the storage area of the ROM 101, a game program area capable of storing a game program relating to progress of a game and a game data area capable of storing game data used by the game program are separately provided. Of the areas, the area before the game data area to which the rear address is assigned becomes an unused area of a storage area equal to or larger than the boundary byte number, such as 16 bytes. As a result, it is possible to easily specify a game program area capable of storing a game program relating to the progress of a game and a game data area capable of storing game data used by the game program. Easier data design and management.

In the storage area of the ROM 101, a non-game program area capable of storing non-game programs related to control and processing different from the progress of the game, and a non-game data area capable of listening to the non-game data used by the non-game program are connected to each other. Of the non-game program area and the non-game data area provided adjacently, the area behind the non-game program area to which the front address is assigned becomes the non-game data area, and the non-game data to which the rear address is assigned. The area before the area is a non-game program area. As a result, a non-game program area capable of storing a non-game program relating to control and processing different from the progress of a game and a non-game data area capable of storing non-game data used by the non-game program are provided at consecutive addresses. It can be provided in the assigned storage area to improve integration, and the design and management of the programs and data stored in the ROM 101 can be facilitated. By providing an unused area with a storage area equal to or larger than the boundary byte number between the non-game program area and the non-game data area, the non-game program area and the non-game data area can be easily identified. You may do so.

In the storage area of the ROM 101 , data indicating a value of “0” may be stored in all unused storage areas. This makes it possible to easily distinguish between the game program area and game data area, the non-game program area and non-game data area, and the unused area. Also, if unauthorized data is stored in the unused area, the data can be easily found. Note that data indicating a value of "1" may be stored in all of the unused storage areas. In other words, data indicating the same value may be stored in all the unused storage areas. As a result, it is possible to easily distinguish between multiple types of storage areas, and to easily find illegal stored data.

A game work area in the RAM 102 can be used as a work area when the CPU 103 executes a game program. The game stack area can be used as a stack area when the CPU 103 executes a game program. The non-game work area can be used as a work area when the CPU 103 executes a non-game program. The non-game stack area can be used as a stack area when the CPU 103 executes a non-game program.

A game program area and a game data area provided in the storage area of the ROM 101, and a game work area and a game stack area provided in the storage area of the RAM 102 are included in the storage area for game control. A non-game program and non-game data area provided in the storage area of the ROM 101 and a non-game work area and a non-game stack area provided in the storage area of the RAM 102 are included in the non-game control storage area.

A ROM comment area provided in the storage area of the ROM 101 stores data indicating arbitrary program specific information such as program title and version. A program management area provided in the storage area of the ROM 101 can store setting information necessary for internal setting of the game control microcomputer 100 in order for the CPU 103 to execute game programs and non-game programs.

FIG. 10-3 shows a main setting example AKA01 of the addresses included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. FIG. Function setting register area, for example watchdog timer 134A of reset controller 134, interrupt controller 135, timer circuit 136, serial communication circuit 139, etc., for function setting using various circuits included in game control microcomputer 100 1 region.

In setting example AKA01, the set values of the WDT start register at address FE1A[H] and the WDT clear registers at addresses FE1B[H] to FE1C[H] are invalid values corresponding to unused. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. Since the set value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to enable the maskable interrupt IR0. Since the set values of the registers relating to channel PTC0 of timer circuit 136 at addresses FE01[H] to FE03[H] are valid, the timer function using channel PTC0 of timer circuit 136 is enabled. be. At addresses FE04[H] to FE09[H], the set values of the registers related to the channels PTC1 and PTC2 of the timer circuit 136 are invalid values corresponding to non-use. Features are set to an unused state.

Since the set values of the registers for the channels SCU0 and SCU1 of the serial communication circuit 139 at addresses FE0A[H] to FE11[H] are valid values, the serial communication function using the channels SCU0 and SCU1 of the serial communication circuit 139 is disabled. , is set to the enabled state. At addresses FE12[H] to FE14[H], the set value of the register related to channel STU2 of serial communication circuit 139 is an invalid value corresponding to non-use, so that the serial communication function using channel STU2 of serial communication circuit 139 is disabled. are set to the unused state.

Since the set values of the registers relating to the input ports of the PIP 105A at the addresses FE2C[H] to FE2E[H] are valid, the signal input function using each input port is enabled. Since the set values of the registers relating to the random number circuit 104 at the addresses FE36[H] to FE4A[H] include valid values and invalid values, the random number generation function using the random number circuit 104 has channels corresponding to valid values. Channels that are set to the enabled state and that correspond to invalid values are set to the unused state. For example, among the four channels RL0 to RL3 in the 16-bit random number circuit 104A, the channels RL0 and RL2 for which the set values of the corresponding maximum value setting registers are valid are enabled for the random number generation function. , and channels RL1 and RL3 for which the set values of the corresponding maximum value setting registers are invalid values, the random number generation function is set to an unused state. In addition, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, the channels RS1 to RS3 for which the set values of the corresponding maximum value setting registers are effective are enabled for the random number generation function. The random number generation function is set to an unused state for the channel RS0 for which the setting value of the maximum value setting register is an invalid value.

In this way, the various circuits included in the game control microcomputer 100 correspond to the set values in the function setting register area, and the various functions using each circuit are set to either a usable state or an unused state. If possible. The function setting register area is not limited to various circuits included in the game control microcomputer 100, and may be the first area for any function setting.

FIG. 10-4 shows a main setting example AKA02 of the addresses included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. FIG. Function control register area, for example RAM102, random number circuit 104, PIP105A, serial communication circuit 139 and the like, becomes the 2nd territory for function control which uses the various circuits which are included in microcomputer 100 for game control.

In setting example AKA02, the RWM access protect register at address FF00[H] can perform function control to prohibit or permit access to RAM 102, which is RWM, corresponding to the set value 00[H] or 01[H]. to The internal information register of address FF01[H] is set to an invalid value corresponding to unused state, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as random number update status abnormality, random number update clock frequency abnormality, system reset occurrence, WDT time-out occurrence, IAT occurrence, etc. However, in this embodiment, it is in an unused state. not used as

Registers of addresses FF25[H] to FF28[H] are used to control the serial communication function using channel SCU0 of serial communication circuit 139 in response to the availability of the serial communication function. It is possible to store set values that are Each register of addresses FF29[H] to FF2C[H] is used to control the serial communication function using the channel SCU1 of the serial communication circuit 139 in response to the availability of the serial communication function. It is possible to store the configured delay.

Each register of addresses FF60[H] to FF67[H] can store a random value that can be obtained using the soft latch random value obtaining function of the 16-bit random number circuit 104A. Of these, the RL0 soft-latch random number registers of addresses FF60[H] to FF61[H] soft-latch numeric data indicating the value of random numbers that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A. can be stored when obtained by The RL1 soft-latch random number registers at addresses FF62[H] to FF63[H] acquire numeric data indicating the value of random numbers that can be generated by the channel RL1 provided in the 16-bit random number circuit 104A. can be stored if The RL2 soft-latch random number registers at addresses FF64[H] to FF65[H] acquire numeric data indicating the value of random numbers that can be generated by the channel RL2 provided in the 16-bit random number circuit 104A. can be stored if The RL3 soft-latch random number registers at addresses FF66[H] to FF67[H] acquire numeric data indicating the value of random numbers that can be generated by the channel RL3 provided in the 16-bit random number circuit 104A. can be stored if

Each register of addresses FF68[H] to FF6B[H] can store a random value that can be obtained using the soft latch random value obtaining function of the 8-bit random number circuit 104B. Among them, the RS0 soft-latch random value register at address FF68[H] is used when numeric data indicating the value of a random number that can be generated by the channel RS0 provided in the 8-bit random number circuit 104B is acquired by the soft latch. can be stored in The RS1 soft-latch random value register at address FF69[H] can store random numbers that can be generated by the channel RS1 provided in the 8-bit random number circuit 104B when numeric data indicating the value is acquired by the soft latch. is. The RS2 soft-latch random value register at address FF6A[H] can store a random number that can be generated by the channel RS2 provided in the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. is. The RS3 soft-latch random value register at address FF6B[H] can store a random number that can be generated by the channel RS3 provided in the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. is.

The RL0 hard latch random value register number "0" at addresses FF88[H] to FF89[H] and the RL0 hard latch random value register number "1" at addresses FF98[H] to FF99[H] are 16-bit random number circuits. A random number that can be generated by the channel RL0 provided in 104A can be stored when numerical data indicating the value is acquired by a hard latch. Here, the RL0 hard latch random value register includes a plurality of storage areas corresponding to a plurality of register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random value register number "0", which is the RL0 hard latch random value register corresponding to the register number "0", will A hard latch condition can be met. On the other hand, the RL0 hard latch random value register number "1", which is the RL0 hard latch random value register corresponding to the register number "1", is set when the game ball detection signal by the second starting port switch 22B is in the ON state. , a hard latch condition can be satisfied. As a result, the RL0 hard latch random number register number "0" acquires numerical data indicating the value of the special symbol determination random number MR1-1 acquired in response to the occurrence of the first start winning by hard latching. can be stored if RL0 hard latch random value register number "1" is for the random number MR1-1 for special symbol determination acquired corresponding to the occurrence of the second start winning, when numerical data indicating the value is acquired by hard latch can be stored in

Each register of addresses FFF0[H] to FFF2[H] and FF35[H] corresponds to the signal input function using the input port of PIP105A being in a usable state. Can store signal values. Among them, the input port number "0" register of the address FFF0[H] can store the input signal value for the input port of the port number "0" provided in the PIP 105A. The input port number "1" register of address FFF1[H] can store the input signal value for the input port of port number "1" provided in PIP 105A. The input port number "2" register of address FFF2[H] can store the input signal value for the input port of port number "2" provided in PIP 105A. The input port number "3" register of address FF35[H] can store the input signal value for the input port of port number "3" provided in PIP 105A.

In this way, the various circuits included in the game control microcomputer 100 need only be able to control their operating states in accordance with the values stored in the function control register area. In addition, various circuits included in the game control microcomputer 100 may be able to update the stored values in the function control register area in accordance with their operating states. The function control register area is not limited to various circuits included in the game control microcomputer 100, and may be a second area for arbitrary function control.

FIG. 10-5 is a diagram for explaining a setting example of the game random numbers shown in FIG. 3 in this embodiment. The game random numbers shown in FIG. 3 correspond to their respective uses, and are random numbers used to determine the display results in the variable display of special symbols and random numbers used to determine the display results in the variable display of normal symbols. , and a random number used to determine the display mode in the variable display of special symbols and normal symbols.

FIG. 10-5(A) shows a setting example AKA11 of game random numbers used for determining the display result in variable display of special symbols. The game random numbers in the setting example AKA11 include a special symbol determination random number MR1-1, a winning symbol random number MR1-2, and a winning symbol initial value MR1-3. For example, the random number MR1-1 for special symbol determination can be used to determine whether or not the special symbol display result is a "big hit" or "small hit". The random numbers MR1-2 for the winning design can be used to determine the designated value of the big winning design or the designated value of the small winning design corresponding to the fixed special design when the special design result is "big hit" or "small hit". be. The random number MR1-3, which is the initial value for the winning symbol, can be used when setting the initial value of the random number MR1-2.

The range of the random number MR1-1 is the range of numerical values that can update the random number MR1-1, and is "0" to "65535". The magnitude of the random number MR1-1 is the total number of random numbers included in the update range of the random number MR1-1, and is "65536" corresponding to the range of the random number MR1-1 from "0" to "65535". Since the random number MR1-1 has a magnitude of "65536", the total number of random numbers included in the update range is not a prime number. The random number MR1-1 has "2" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random number MR1-1 is based on initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The random number MR1-1 is updated by hardware update using the 16-bit random number circuit 104A. The update condition for the random number MR1-1 is the system clock input in the 16-bit random number circuit 104A. The conditions for obtaining the random number MR1-1 include a hardware latch corresponding to the starting winning and reading to the random number buffer by software corresponding to the starting winning. The period of the random number MR1-1 is 4.369 [ms].

The range of the random numbers MR1-2 is the range of numerical values that can update the random numbers MR1-2, and is "0" to "199". The magnitude of the random number MR1-2 is the total number of random numbers included in the update range of the random number MR1-2, and is "200" corresponding to the range of the random number MR1-2 from "0" to "199". Since the random numbers MR1-2 have a magnitude of "200", the total number of random numbers included in the update range is not a prime number. The random number MR1-2 has "1" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random numbers MR1-2 is based on the immediate value setting of the program code. The method for updating the random numbers MR1-2 is software update SA1. The condition for updating the random numbers MR1-2 is a timer interrupt due to the elapse of a predetermined period of time. The acquisition condition for the random numbers MR1-2 is reading by software corresponding to the start winning. The period of the random numbers MR1-2 is 800 [ms].

The range of the random numbers MR1-3 is the range of numerical values in which the random numbers MR1-3 can be updated, and is "0" to "199", which is the same as the random numbers MR1-2. The magnitude of the random numbers MR1-3 is the total number of random numbers included in the update range of the random numbers MR1-3. is the same "200" as Since the random numbers MR1-3 have a magnitude of "200", the total number of random numbers included in the update range is not a prime number. The random numbers MR1-3 have "1" as the number of bytes of numerical data used to update the values. The method of setting the maximum value of the random numbers MR1-3 is based on the immediate value setting of the program code. The method for updating the random numbers MR1-3 is software update SA2. The update conditions for the random numbers MR1-3 include timer interruption due to the lapse of a predetermined period of time, and loop processing that is standby processing in the main processing P_MAIN for game control. The condition for obtaining the random numbers MR1-3 is that the random numbers MR1-2 have completed one cycle. The period of the random numbers MR1-3 is indefinite due to the update conditions.

FIG. 10-5(B) shows a setting example AKA12 of the game random number used for determining the display result in the variable display of normal symbols. The game random numbers in the setting example AKA12 include the random number MR2-1 for the normal per-symbol pattern and the random number MR2-2 as the initial value for the normal per-symbol pattern. For example, the normal symbol per symbol random number MR2-1 can be used to determine the normal symbol designation value corresponding to the determined normal symbol as the normal symbol display result. The random number MR2-2, which is the initial value for the normal per symbol pattern, can be used when setting the initial value of the random number MR1-2.

The range of the random number MR2-1 is the range of numerical values that can update the random number MR2-1, and is "0" to "198". The magnitude of the random number MR2-1 is the total number of random numbers included in the update range of the random number MR2-1, and is "199" corresponding to the range of the random number MR2-1 from "0" to "198". Since the random number MR2-1 has a magnitude of "199", the total number of random numbers included in the update range is a prime number. The random number MR2-1 has "1" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random number MR2-1 is based on the immediate value setting of the program code. The update method for the random number MR2-1 is software update SA1. A condition for updating the random number MR2-1 is a timer interrupt due to the elapse of a predetermined time. The acquisition condition of the random number MR2-1 is reading by software corresponding to the passage of the game ball through the passage gate 41 which can be configured as a normal symbol activation port. The period of the random number MR2-1 is 796 [ms].

The range of the random number MR2-2 is the range of numerical values in which the random number MR2-2 can be updated, and is "0" to "198", which is the same as the random number MR2-1. The magnitude of the random number MR2-2 is the total number of random numbers included in the update range of the random number MR2-2. is the same "199" as Since the random number MR2-2 has a magnitude of "199", the total number of random numbers included in the update range is a prime number. The random number MR2-2 has "1" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random number MR2-2 is based on the immediate value setting of the program code. The update method for random number MR2-2 is software update SA2. The update condition of the random number MR2-2 includes timer interruption due to the lapse of a predetermined time, and during loop processing which is standby processing in the main processing P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is indefinite due to the update conditions.

FIG. 10-5(C) shows a setting example AKA13 of game random numbers used for determining the display mode in the variable display of special symbols and normal symbols. The game random numbers in the setting example AKA13 are the random number MR3-1 for the normal symbol variation pattern, the random number MR3-2 for selecting the losing effect, the random number MR3-3 for selecting the variation pattern type, and the random number MR3 for the variation pattern. -4 and . For example, the random number MR3-1 for the normal symbol variation pattern can be used to determine the normal symbol variation pattern corresponding to the variable display of the normal symbols. The random number MR3-2 for selecting the loss effect can be used for determining the variable display mode corresponding to the variable display of the special symbol whose special symbol display result is "loss". The random number MR3-3 for selecting the variation pattern type can be used for selecting the variation pattern type corresponding to the variable display of the special symbols. The random numbers MR3-4 for variation patterns can be used to determine variation patterns corresponding to variable display of special symbols.

The range of the random number MR3-1 is the range of numerical values that can update the random number MR3-1, and is "0" to "232". The magnitude of the random number MR3-1 is the total number of random numbers included in the update range of the random number MR3-1, and is "233" corresponding to the range of the random number MR3-1 from "0" to "232". Since the random number MR3-1 has a magnitude of "233", the total number of random numbers included in the update range is a prime number. For the random number MR3-1, the number of bytes of numerical data used to update its value is "1". The method of setting the maximum value of the random number MR3-1 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-1 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for the random number MR3-1 is the system clock input in the 8-bit random number circuit 104B. The acquisition condition of the random number MR3-1 is the start of fluctuation in the variable display of normal symbols. The period of the random number MR3-1 is 0.249 [ms].

The range of the random number MR3-2 is the range of numerical values that can update the random number MR3-2, and is "0" to "65518". The magnitude of the random number MR3-2 is the total number of random numbers included in the update range of the random number MR3-2, and is "65519" corresponding to the range of the random number MR3-2 from "0" to "65518". Since the random number MR3-2 has a magnitude of "65519", the total number of random numbers included in the update range is a prime number. The random number MR3-2 has "2" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random number MR3-2 is based on initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The random number MR3-2 is updated by hardware update using the 16-bit random number circuit 104A. The update condition for the random number MR3-2 is the system clock input in the 16-bit random number circuit 104A. The conditions for acquiring the random number MR3-2 include reading to a random number buffer by software corresponding to the start winning. The period of random number MR3-2 is 139.774 [ms].

The range of the random number MR3-3 is the range of numerical values that can update the random number MR3-3, and is "0" to "240". The magnitude of the random number MR3-3 is the total number of random numbers included in the update range of the random number MR3-3, and is "241" corresponding to the range of the random number MR3-3 from "0" to "240". Since the random number MR3-3 has a magnitude of "241", the total number of random numbers included in the update range is a prime number. The random number MR3-3 has "1" as the number of bytes of numerical data used to update its value. The method of setting the maximum value of the random number MR3-3 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-3 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for the random number MR3-3 is the system clock input in the 8-bit random number circuit 104B. The conditions for acquiring the random number MR3-3 include reading to the random number buffer by software corresponding to the start winning. The period of random number MR3-3 is 0.257 [ms].

The range of the random number MR3-4 is the range of numerical values that can update the random number MR3-4, and is "0" to "250". The magnitude of the random number MR3-4 is the total number of random numbers included in the update range of the random number MR3-4, and is "251" corresponding to the range of the random number MR3-4 from "0" to "250". Since the random numbers MR3-4 have a magnitude of "251", the total number of random numbers included in the update range is a prime number. The random number MR3-4 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random numbers MR3-4 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The method of updating the random numbers MR3-4 is hardware update using the 8-bit random number circuit 104B. The update condition for the random numbers MR3-4 is the system clock input in the 8-bit random number circuit 104B. The acquisition condition of the random number MR3-4 is, for example, readout to the random number buffer by the software corresponding to the start winning. The period of the random numbers MR3-4 is 0.268 [ms].

The software update SA1, which is a method of updating the random numbers MR1-2 and MR2-1, can be updated by adding 1 to the previous value each time the software update process is executed. At this time, if the updated value exceeds the maximum random number, it is changed to "0" as the minimum random number. If the updated value matches the random number initial value, the current random number is set using the corresponding initial random number and stored as a new random number initial value. For example, for the random number MR1-2, if the updated value matches the random number initial value, the current random number is set using the random number MR1-3 that is the initial value for the winning symbol, and the random number is set to a new value. Store as the random initial value. Regarding the random number MR2-1, when the updated value matches the random number initial value, the current random number is set using the random number MR2-2, which is the initial value for the symbol per normal symbol, and the random number is set to a new value. Store as the random initial value.

The software update SA2, which is a method of updating the random numbers MR1-3 and MR2-2, can be updated by adding 1 to the previous value each time the software update process is executed. At this time, if the updated value exceeds the maximum random number, it is changed to "0" as the minimum random number. In this case, unlike the software update SA1, the random number initial value is not used, so the value after the update is either the value obtained by adding 1 to the previous value or "0" which is the minimum value of the random number. .

FIG. 10-6 is a diagram for explaining the random number update period when updating the random number using the 16-bit random number circuit 104A and the 8-bit random number circuit 104B included in the random number circuit 104. FIG. Here, a random number that can be generated by channels RL0 to RL4 provided in the 16-bit random number circuit 104A is assumed to be a 16-bit random number RLn. A random number that can be generated by channels RS0 to RS4 provided in the 8-bit random number circuit 104B is assumed to be an 8-bit random number RSn. The period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A makes one cycle corresponds to whether or not the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of 2. are determined by different relations. The period of one cycle of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B corresponds to whether or not the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of 2. are determined by different relations.

FIG. 10-6(A) shows a 16-bit random number period setting example AKA21 in the 16-bit random number circuit 104A. The 16-bit random number period is a period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A makes one cycle. In the 16-bit random number cycle setting example AKA21, when the maximum value of the 16-bit random number RLn corresponds to 2 ^m −1 when m = 9 to 16, the cycle of the 16-bit random number sequence is proportional to the reciprocal of the count clock frequency, ie the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn is used as a variable. On the other hand, when the maximum value of the 16-bit random number RLn does not correspond to 2 ^m −1 when m=9 to 16, the cycle of the 16-bit random number sequence is the count clock frequency , i.e., 32 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn is used as a variable. In this way, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is the specific maximum value, the random number update cycle is shorter than when the maximum value is other than the specific maximum value. , the update speed of the random value is faster.

FIG. 10-6B shows an 8-bit random number period setting example AK22 in the 8-bit random number circuit 104B. The 8-bit random number period is a period in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B makes one cycle. In the 8-bit random number cycle setting example AKA22, when the maximum value of the 8-bit random number RSn corresponds to 2 ^m −1 when m = 5 to 8, the cycle of the 8-bit random number sequence is proportional to the reciprocal of the count clock frequency, ie the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn is used as a variable. On the other hand, when the maximum value of the 8-bit random number RSn does not correspond to 2 ^m −1 when m=5 to 8, the cycle of the 8-bit random number sequence is the count clock frequency , i.e., 16 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn is used as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is the specific maximum value, the random number update cycle is shorter than when the maximum value is other than the specific maximum value. , the update speed of the random value is faster.

FIG. 10-6(C) shows a random value comparison example AKA23 in which random values updatable by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B are compared. The 16-bit random number circuit 104A can update random numbers corresponding to the special symbol determination random number MR1-1 and the loss effect selection random number MR3-2. The 8-bit random number circuit 104B can update random numbers corresponding to the random number MR3-3 for selecting the variation pattern type and the random number MR3-4 for the variation pattern.

The random number MR1-1 has a maximum value of “65535” and corresponds to 2 ^m −1 when m=16. As a result, the period of the random number MR1-1 is 4.369 [ms], and the update speed at this time is 15000 [times/ms]. The random number MR3-2 has a maximum value of “65518” and does not correspond to 2 ^m −1 when m=9 to 16. As a result, the period of the random number MR3-2 is 139.774 [ms], and the update speed at this time is 469 [times/ms]. The random number MR3-3 has a maximum value of “240” and does not correspond to 2 ^m −1 when m=5 to 8. As a result, the period of the random number MR3-3 is 0.257 [ms], and the update speed at this time is 938 [times/ms]. The random number MR3-4 has a maximum value of “250” and does not correspond to 2 ^m −1 when m=5 to 8. As a result, the period of the random numbers MR3-4 is 0.268 [ms], and the update speed at this time is 938 [times/ms].

Thus, the game random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR1-1 for special symbol determination and a random number MR3-2 for selecting a losing effect. These random number MR1-1 and random number MR3-2 both have numerical data with a number of bytes of "2", and are composed of two bytes as a specific number of bytes. Since the size of the random number MR1-1 is "65536" and the size of the random number MR3-2 is "65519", it is assumed that the total number of random numbers included in the update range of the random number MR1-1 is a specific number. case, the total number of random numbers included in the update range of the random numbers MR3-2 is a predetermined number smaller than the specific number. The update speed of the random number MR1-1 is 15000 [times/ms], and the update speed of the random number MR3-2 is 469 [times/ms]. becomes faster. As a result, synchronous generation of random numbers can be suppressed, and random numbers can be appropriately updated.

The game random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR3-2 for selecting a losing effect. The game random numbers that can be updated by the 8-bit random number circuit 104B include a random number MR3-3 for selecting the type of variation pattern and a random number MR3-4 for variation pattern. All of these random numbers MR3-2 to MR3-4 are prime numbers in total within the update range. The update speed of the random number MR3-2 is 469 [times/ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times/ms]. In other words, the update speed of the random numbers MR3-3 and MR3-4 is twice the integer multiple of the update speed of the random number MR3-2. Therefore, when the random number MR3-2 is the first random number and the random numbers MR3-3 and MR3-4 are the second random numbers, the update speed of the first random value is the first speed, and the second random value is A second rate in which the update rate is an integral multiple of the first rate. The update range of the random number MR3-2 is "0" to "65518", the update range of the random number MR3-3 is "0" to "240", and the update range of the random number MR3-3 is "0" to Since it is "250", the total number of random numbers included in each update range is different between the first random number value and the second random number value, and the total number of random numbers included in both update ranges is a prime number. As a result, it is possible to suppress the synchronous generation of random numbers and appropriately update the random numbers.

A plurality of registers such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and general-purpose registers including an accumulator are provided inside the CPU 103 . Index registers, flag registers, and general-purpose registers may be provided with main registers and sub-registers. The registers included in the main register and sub-registers and the stack pointer may be provided so as to configure a plurality of register banks. The plurality of register banks may include a first register bank for inside the area that can be used when executing the game program, and a second register bank for outside the area that can be used when executing the non-game program. . As a result, for example, when switching between a game program and a non-game program, it is no longer necessary to save the values stored in general-purpose registers to the stack area and restore them from the stack area, increasing the amount of programs and the processing load. can be prevented.

The program counter is for holding the address value of the instruction to be executed next by the CPU 103, and is also called a PC register. The stored value of the program counter is sequentially counted up each time each instruction is executed, or the address value of the branch destination by the branch instruction is set. The interrupt register can hold the upper address value of the interrupt vector table, and is also called an I register. The value stored in the I register is set corresponding to the start of power supply to the pachinko gaming machine 1 .

A stack pointer can hold an address value corresponding to a game stack area or a non-game stack area, and is also called an SP register. The value stored in the stack pointer is specified by a predetermined register including the program counter or an instruction corresponding to the occurrence of an interrupt, the execution of a PUSH instruction, or the execution of a subroutine call instruction such as a CALL instruction, a CALLF instruction, or an RST instruction. It is possible to specify a save destination address for saving and holding the stored value or immediate value in the registered register. The value stored in the stack pointer can specify a read address for restoring the value stored in the saved register in response to the end of interrupt processing, the execution of a POP instruction, the end of subroutine processing, etc. Along with this return, the stored value is updated to a value indicating the corresponding address after reading. In addition, the value stored in the stack pointer can be set to a value stored in a register specified by a load instruction such as an LD instruction or an immediate value.

The index register includes an IX register and an IY register each having a 2-byte storage capacity capable of storing 16-bit data. The accumulator is also called the A register. In addition, general-purpose registers include a plurality of registers having a storage capacity of 1 byte that can store 8-bit data, such as B register, C register, D register, E register, H register, and L register. The B and C registers can be used as a BC register of pair registers capable of storing 16-bit data. The D register and E register can be used as a pair register DE register capable of storing 16-bit data. The H register and L register can be used as the HL register of paired registers capable of storing 16-bit data.

The internal register of the CPU 103 can update the stored value corresponding to the operation instruction and transfer instruction executed by the CPU 103, and the program address and data address or the built-in register address provided in the game control microcomputer 100 specification, operation data and to hold transfer data.

In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute the program includes transfer instructions such as load instructions, subroutine call instructions, jump instructions, other arithmetic instructions including arithmetic operation instructions and logical operation instructions, input It includes output instructions and the like. Computer programs such as game programs and non-game programs executable by the CPU 103 are prepared in advance as program codes describing these various instructions and stored in the ROM 101 .

The load instruction is used to store and set data read from the memory area of the ROM 101 or RAM 102 or the internal device area in the internal register of the CPU 103, or to store the value stored in the internal register of the CPU 103 in the memory area of the RAM 102 or the internal device area. It is a transfer instruction that can be used for writing and storing data in an internal register of the CPU 103, the storage area of the RAM 102, or the built-in device area as an immediate value specified by the operand. The object to which data is transferred by the load instruction can be specified corresponding to the instruction code and the operand, and generally includes the transfer source and transfer destination of the data. However, when an immediate value is specified by an operand, the source of the data is not included.

Load instructions include regular LD instructions, special LDQ instructions, special LDF instructions, and special ICPLD instructions. A normal LD instruction is also called a normal transfer instruction. A special LDQ instruction is also called a first special transfer instruction. A special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both the upper address and the lower address when transferring data to the storage area of the ROM 101 or RAM 102 or the internal device area. . The LD instruction, which is a normal transfer instruction, uses a pair register such as the HL register as a pointer to transfer data to the storage area of the ROM 101 or RAM 102 or the built-in device area. Data can be transferred by specifying an address with a pointer.

The LDQ instruction, which is the first special transfer instruction, can transfer data by specifying only a lower address using the Q register, which is a special register included in the internal registers of the CPU 103 . A stored value indicating an upper address is set in advance in the Q register, and by combining it with the lower address specified by the LDQ instruction, the address of the transfer destination or transfer source can be specified and data can be transferred.

The LDQ instruction, which is the first special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the value stored in the Q register, the amount of program code may increase rather than the normal LD instruction. Therefore, in the game work area of addresses F000 [H] to F0D7 [H], the function setting register area of addresses FE00 [H] to FEBF [H], and the function control register area of addresses FF00 [H] to FFFF [H] , data transfer using the LDQ instruction, which is the first special transfer instruction, may be executed in response to processing that requires multiple transfers of various data.

The LDF instruction, which is the second special transfer instruction, can transfer data by designating only a lower address for stored data in a specific address range. The specific address range is, for example, a range of addresses 1200[H] to 1DFF[H]. Therefore, the game data area of the ROM 101 is set in advance so as to be included in this specific address range, and by combining with the lower address specified by the LDF instruction, the address of the transfer source is specified and the data is transferred. can be done. Since the game data area of the ROM 101 is read-only and not writable, the address of the game data area is never specified as the transfer destination address.

The LDF instruction, which is the second special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, since the specific address range is fixed according to the specification, the storage area for frequently used data, such as the game data area of the ROM 101, is set so as to be included in the specific address range, and the second special transfer instruction is It suffices if the transfer of data using the LDF instruction can be executed.

The ICPLD instruction, which is the third special transfer instruction, compares the update target value with the comparison determination value, and updates the update target value by adding 1 when the update target value is less than the comparison determination value. If the update target value is greater than or equal to the comparison determination value, the update target value is changed to the minimum value "0". The value to be updated may be the value indicated by the stored data at the address pointed to by the pointer, or may be the value stored in the register. The comparison determination value may be a value stored in a register or a value indicated by an operand of the ICPLD instruction.

As described above, the ICPLD instruction, which is the third special transfer instruction, compares the update target value with the comparison determination value, adds 1 to the update target value if the comparison result is less than the comparison determination value, and adds 1 to the update target value. is greater than or equal to the comparison judgment value, the update target value is changed to the minimum value.

Note that setting a stored value in an internal register of the CPU 103 using an immediate value or the like by an operand of a transfer instruction is also called a set. Reading the data stored in the game data area of the ROM 101 or the game work area of the RAM 102 and storing it in the internal register of the CPU 103 is also called loading. Storing the value stored in the internal register of the CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of the RAM 102 is also called storing.

FIG. 10-7 is a flow chart showing an example of the power supply start handling process P_POWER_ON. The power supply start corresponding process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control shown in FIG. is. When the power supply start handling process P_POWER_ON is executed, the CPU 103 sets the interrupt prohibition (step AKS1), and then sets the stack pointer initial value in the area to the stack pointer (step AKS2). The initial value of the in-area stack pointer may be an address F200[H] obtained by adding 1 to the final address of the game stack area corresponding to the initial state in which no saved data is stored in the game stack area.

Following step AKS2, a transfer instruction for setting an internal register of CPU 103 sets a connection confirmation signal ON output value (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is ON, and may be 00 [H], for example. At this time, a transfer instruction for setting the Q register contained in the internal register of the CPU 103 is used to set the upper address of the function control register in the Q register (step AKS4). The function control register upper address is a value FF[H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. When the upper address of the function control register is thus set, the connection confirmation signal ON output value is stored by the transfer command using the upper address indicated by the stored value of the Q register (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set at the upper address of the function control register area by step AKS4. Therefore, by a transfer instruction for writing to the storage area of the specified address, such as a special 2-byte LDQ instruction specifying the lower address, the function control register of the specified address in the function control register area is checked for the connection confirmation set in step AKS3. A signal on output value can be stored. At step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the ON state.

When the connection confirmation signal is set to ON state by step AKS5, the SCU0 command register clear output value is stored by the transfer instruction using the upper address indicated by the stored value of the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set at the upper address of the function control register area by step AKS4. The SCU0 command register clear output value can be specified by the transfer instruction operand. Therefore, a transfer instruction for writing to a storage area at a specified address, such as a 3-byte special LDQ instruction that specifies a lower address and an SCU0 command register clear output value, causes SCU0 to be transferred to the function control register at the specified address in the function control register area. Command register clear output value can be stored. At step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register provided at address FF28[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU0 of serial communication circuit 139 is controlled to the initial state.

After step AKS6, the SCU1 command register clear output value is stored by a transfer instruction using the upper address indicated by the stored value of the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The stored value of the Q register is set at the upper address of the function control register area by step AKS4. The SCU1 command register clear output value can be specified by the transfer instruction operand. Therefore, a transfer instruction for writing to a storage area at a specified address, such as a 3-byte special LDQ instruction that specifies a lower address and an SCU0 command register clear output value, causes SCU1 to be transferred to the function control register at the specified address in the function control register area. Command register clear output value can be stored. At step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register provided at address FF2C[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using the channel SCU1 of the serial communication circuit 139 is controlled to the initial state.

When these serial communication functions are controlled to the initial state, the upper address of the interrupt vector table is set by the transfer instruction for setting the internal register of CPU 103 (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of the ROM 101 . Interrupt vector table, for example timer interrupt processing P_PCT for game control executed corresponding to the occurrence of timer interrupt, the leading address is stored in the table position corresponding to the interrupt order. Such an interrupt vector table upper address is set in the I register by a transfer instruction for setting an internal register of CPU 103 (step AKS9).

After step AKS9, the value stored in the Q register is updated by subtracting 1 (step AKS10). The value stored in the Q register was set to the upper address of the function control register area by step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. In this way, after the function control registers provided in the function control register area are set, the function setting registers provided in the function setting register area can be set. At this time, a function setting register storage value table address is set by a transfer instruction for setting a pointer (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of the ROM 101 . Then, the number of processes is loaded by a transfer instruction for reading the stored data at the address pointed by the pointer (step AKS12). Further, setting using the function setting register storage value table is performed by the function setting register store instruction (step AKS13). The function setting register store instruction specifies the function setting register by the stored data at the address when the address indicated by the pointer is incremented by 1, and sets the function setting register indicated by the stored data at the address when the address indicated by the pointer is incremented by 2. Any instruction may be used as long as it repeats the steps of storing a value in a specified function setting register, adding 2 to the stored value of the pointer, and subtracting 1 from the number of processes until the number of processes becomes zero. Thus, initial setting of the function setting register is enabled.

When the initial setting of the function setting register is completed in step AKS13, the access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to 01 [H], for example, by a transfer instruction for setting the internal register of the CPU 103 . Such an access permission output value is stored in the RWM access protect register by a transfer instruction for writing to the storage area of the top address in the function setting register area. The RWM access protect register enables function control to permit access to the RWM RAM 102 in response to the setting of 01[H], which is the access permission output value. Therefore, by storing the access permission output value in the RWM access protect register in step AKS14, access to the RAM 102 is permitted in response to the start of power supply in the pachinko game machine 1. FIG.

After step AKS14, the upper address of the game work area, which is the work area of RAM 102, is set in the Q register (step AKS15), and the power supply start corresponding process P_POWER_ON ends. Thus, after step AKS14 permits access to the RAM 102, the value F0[H] indicating the upper address of the game work area in the RAM 102 is set in the Q register. After step AKS15, when the LDQ instruction, which is the first special transfer instruction, is executed, the value stored in the Q register, F0[H], can be used as the high-order address of the transfer destination or transfer source without being specified by an operand. can. As a result, it is possible to reduce the program capacity of the processing using the game work area in the RAM 102 and improve the marketability of the game machine.

FIG. 10-8 shows a configuration example AKT01 of the function setting register storage value table used in the power supply start handling process P_POWER_ON. In the power supply start corresponding process P_POWER_ON, for example, by using the function setting register storage table whose address is set by step AKS11, the number of processes is loaded by step AKS12, and each function setting register is stored by the function setting register store instruction of step AKS13. Value is stored. In the function setting register storage value table of the configuration example AKT01, a value 18 [H] indicating the number of processes is stored at the leading address 1200 [H]. At step AKS12, this table data is read out and loaded into the internal register of CPU103. After that, the function setting register store instruction of step AKS13 sequentially reads the table data combining the lower addresses of the function setting registers and the stored values, and makes it possible to store the stored values in the function setting registers corresponding to the respective lower addresses. .

In the function setting register storage value table of the configuration example AKT01, the value stored in the function setting register with the smaller value indicating the lower address can be set first, and the value stored in the function setting register with the larger value indicating the lower address can be set later. The table data is structured so that As a result, in the function setting register area, the value stored in the function setting register closest to the start address is set first, and the value stored in the function setting register closest to the final address is set later. Value is set. This facilitates the design and management of the data indicating the values stored in the function setting registers, and enhances the marketability of the gaming machine.

The 16-bit random number circuit 104A can start updating from the channel in which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RL0 to RL3. The 8-bit random number circuit 104B can start updating from the channel in which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RS0 to RS3. The function setting register area of the setting example AKA01 shown in FIG. A setting register, an RL2 maximum value setting register of addresses FE43[H] to FE44[H], and an RL3 maximum value setting register of addresses FE45[H] to FE46[H] are four in the 16-bit random number circuit 104A. They are provided corresponding to channels RL0 to RL3. This function setting register area includes an RS0 maximum value setting register at address FE47[H], an RS1 maximum value setting register at address FE48[H], an RS2 maximum value setting register at address FE49[H], and an address FE4A. The [H] RS3 maximum value setting register is provided corresponding to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the function setting register storage value table of the configuration example AKT01, among these maximum value setting registers, the value stored in the RL0 maximum value setting register is set first, the value stored in the RL2 maximum value setting register is set next, The table data is configured so that the value stored in the RS1 maximum value setting register is set next, the value stored in the RS2 maximum value setting register is set next, and the RS3 maximum value setting register is set last. Therefore, the update of channel RL0 in 16-bit random number circuit 104A is initiated first, the update of channel RL2 in 16-bit random number circuit 104A is initiated next, and the update of channel RS1 in 8-bit random number circuit 104B is initiated next. The update of channel RS2 in 8-bit random number circuit 104B is started next, and the update of channel RS3 in 8-bit random number circuit 104B is started last. In this way, the update of the random number is started in order from the random number for which the maximum value of the random number is set. Numerical updates are possible.

The power supply start corresponding process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control, which is the start-up process that is executed based on the start of the power supply in the pachinko gaming machine 1, and the function setting of the configuration example AKT01. Using the register storage value table, it is possible to set a storage value in a function setting register area as a storage area related to functions. At this time, since the random number maximum value updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start corresponding process P_POWER_ON can be executed as the maximum value setting process. The 16-bit random number circuit 104A can update the first random number consisting of 16 bits corresponding to 2 bytes as the specific number of bytes. The 8-bit random number circuit 104B can update a second random number composed of 8 bits corresponding to 1 byte as a predetermined number of bytes smaller than the specific number of bytes. Then, when executing the power supply start handling process P_POWER_ON, after setting the maximum random number value of the first random number value that can be updated by the 16-bit random number circuit 104A using the function setting register storage value table of the configuration example AKT01, The maximum random value of the second random value that can be updated by the 8-bit random number circuit 104B is set. In this way, by setting the second random number of a predetermined number of bytes after setting the first random number of the specific number of bytes, the first random number and the second random number are stably updated to obtain an appropriate random number. Numerical updates are possible.

FIG. 10-9 shows a configuration example of the RWM access protect register. The RWM access protect register is provided at address FF00[H] in the configuration example AKA02 of the function control register area shown in FIG. 10-4. The stored value of the RWM access protect register becomes a different value corresponding to access prohibition or access permission of the RAM 102 serving as RWM.

FIG. 10-9(A) shows a bit configuration example of the RWM access protect register. The RWM access protect register can store 8-bit data RAP with bit numbers from "0" to "7", and bit data RAP0 with bit number "0" is set to 0 [B] or 1 [B]. It is possible. On the other hand, the bit data from bit number "1" to bit number "7" are always set to 0[B] and indicate fixed values that are never set to "1".

FIG. 10-9B is a diagram for explaining a usage example of bit data RAP of the RWM access protect register. In the bit data RAP, the bit data RAP0 with bit number "0" is the RWM access control bit. Setting 0 [B] disables access to RWM, and setting 1 [B] allows access to RWM. Corresponding to the start of power supply in the pachinko game machine 1, the bit data RAP0 of the bit number "0" is set to 0 [B] which is the initial value. As a result, access to the RAM 102 serving as RWM can be prohibited in response to the start of power supply in the pachinko gaming machine 1 .

FIG. 10-10 is a flowchart showing an example of power-off processing P_POWER_OFF. The power-off process P_POWER_OFF is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. 5, and can be executed in step S51 each time a timer interrupt occurs. When the power-off processing P_POWER_OFF is executed, the CPU 103 sets a backup monitoring timer address by a transfer instruction for setting a pointer (step AKS31). The backup watchdog timer address is the address of the backup watchdog timer provided in the game work area of the RAM 102 .

Enter the input port number "3" (step AKS32). Input port number "3" is an input port to which "3" is assigned as the port number, and includes a power confirmation signal input bit. Therefore, a logical product operation is executed using the input data of the input port number "3" and the check data corresponding to the bit position of the power supply confirmation signal input bit. At this time, it is determined whether or not the power confirmation signal input bit is "0" depending on whether or not the zero flag is on (step AKS33). The power confirmation signal input bit indicates that the power confirmation signal is off when its bit value is 0 [B] corresponding to "0", and its bit value is 1 [B] corresponding to "1". ] indicates that the power confirmation signal is on.

If the power confirmation signal input bit is not "0" but "1" (step AKS33; No), the backup monitoring timer clear data is stored by a transfer instruction that can update the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing clear data in the backup monitor timer, the backup monitor timer can be cleared when the power confirmation signal is in the ON state, corresponding to other than the power failure determination.

When the power supply confirmation signal input bit is "0" corresponding to step AKS33 (step AKS33; Yes), the time counted by the backup monitoring timer is updated by adding 1 (step AKS35). Also, the backup monitor timer is loaded by a transfer command for reading out the stored data at the address indicated by the pointer (step AKS36). Then, by an operation return instruction (step AKS37) that can compare the time value measured by the backup monitoring timer and the determination value corresponding to the backup determination time, it is confirmed that the backup monitoring timer does not indicate the backup determination time (step AKS38). This operation return instruction, when the timing value by the backup monitoring timer and the judgment value corresponding to the backup judgment time are different, corresponds to the zero flag which becomes OFF state, ends the power off processing and goes to the special symbol process processing allow the return of In this way, when the backup monitoring timer does not indicate the backup determination time (step AKS38; Yes), the power-off process is terminated.

When the backup monitoring timer indicates the backup determination time corresponding to step AKS38 (step AKS38; No), checksum calculation processing P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC of step AKS39 may be the same process as the checksum calculation process included in the RWM check process P_RWM_CHK of step S2 in the main process P_MAIN for game control shown in FIG. In this way, by executing a common checksum calculation process corresponding to the start and stop of the power supply in the pachinko gaming machine 1, it is possible to determine whether or not the stored contents in the game work area of the RAM 102 are held without change. Thus, it becomes possible to determine whether or not restoration is possible using backup data. The checksum data created by the checksum calculation process P_SUM_CALC of step AKS39 is stored in the checksum buffer by a transfer instruction for writing to the storage area of the address indicated by the pointer (step AKS40).

After step AKS40, the clear data is set to the output value data by an exclusive OR operation instruction (step AKS41). This exclusive OR operation instruction performs an exclusive OR operation of the stored values of a single register, so that all bit values are exclusive ORed with the same value. It can be initialized to clear data of 00[H]. Such clear data is stored in the RWM access protect register by a transfer instruction for writing to the storage area of the leading address in the function setting register area (step AKS42). The RWM access protect register enables function control to prohibit access to the RWM RAM 102 in response to the setting of 00[H], which is clear data. Therefore, by storing the clear data in the RWM access protect register in step AKS42, access to the RAM 102 is prohibited in response to the stoppage of power supply to the pachinko game machine 1. FIG.

After step AKS42, the output port numbers "0" to "10" are cleared (step AKS43). Output port numbers "0" to "10" are output ports with port numbers from "0" to "10", and are all output ports in the game control microcomputer 100. Therefore, according to step AKS43, all the output ports in the game control microcomputer 100 are set to the clear state in response to the stop of the power supply in the pachinko game machine 1. FIG. At this time, a transfer instruction for setting an internal register of CPU 103 is used to set a connection confirmation signal OFF output value (step AKS44). The connection confirmation signal OFF output value is a value indicating that the connection confirmation signal is OFF, and may be 01 [H], for example. Such a connection acknowledgment signal OFF output value is stored in the output port number "1" register by a transfer instruction for writing to the storage area of the specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the OFF state.

Following step AKS45, the PTC0 interrupt inhibit output value is set by a transfer instruction for setting the internal register of CPU 103 (step AKS46). The PTC0 interrupt disable output value is an output value for setting the generation of timer interrupt using the channel PTC0 of the timer circuit 136 to a disabled state. This PTC0 interrupt inhibition output value is stored in the PTC0 control register by a transfer instruction for writing to the function setting register of the specified address in the function setting register area (step AKS47). The PTC0 control register can set the use state of the timer function using the channel PTC0 of the timer circuit 136 . At step AKS47, the PTC0 interrupt prohibition output value set at step AKS46 is stored in the PTC0 control register, so that the timer interrupt for game control is prohibited in response to the stoppage of the power supply in the pachinko game machine 1. set.

When the setting corresponding to the elapse of the backup determination time is performed, a transition is made to a standby state by execution of loop processing. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether or not the power confirmation signal input bit is "0" (step AKS49). When the power confirmation signal input bit is "0" corresponding to the power confirmation signal being off (step AKS49; Yes), the loop processing returning to step AKS48 is continued. Thus, by maintaining the standby state until the operation is stopped due to the power interruption in response to the stoppage of power supply to the pachinko game machine 1, it is possible to prevent inconvenient changes in stored data and runaway processing by the CPU 103.例文帳に追加

When the power confirmation signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), after the vector table address is set in the stack pointer at power failure recovery (step AKS50) , the interrupt return instruction terminates the power-off process P_POWER_OFF. The vector table address for recovery from power failure is the address of the vector table for recovery from power failure provided in the game program area of the ROM 101 . The interrupt return instruction can use the stack pointer as a pointer to set the stored data in the storage area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the storage data in the storage area indicated by the address specified by the storage value of the stack pointer is set in the lower byte of the program counter, and the storage area specified by the value obtained by adding 1 to the storage value of the stack pointer is stored in the storage area indicated by the address. Store data in the upper byte of the program counter.

FIG. 10-11 is a diagram for explaining a usage example of the data configuration regarding power-off processing P_POWER_OFF. In the power-off process P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves the checksum data using the checksum buffer. In addition, by setting the vector table address at the time of power failure recovery at step AKS50, the operation is not stopped after the stop of the power supply in the pachinko game machine 1 is detected, and when the normal power supply is resumed, the game control Make the program for .exe executable from the beginning. Thus, the power-off process P_POWER_OFF enables control when the power supply to the pachinko gaming machine 1 is stopped by using the backup monitoring timer, checksum buffer, and power-off restoration vector table.

FIG. 10-11A shows a configuration example AKB01 of a storage area that serves as a backup data area. The backup data area of the configuration example AKB01 can store backup setting data used when backing up the data stored in the game work area of the RAM 102 . This backup data area includes a backup watchdog timer at address F000[H] and a checksum buffer at address F0DE[H]. The address F000[H] is the top address of the game work area, and the address F0DE[H] is the last address of the game work area. Thus, by providing backup data areas at the start address and the end address of the game work area, it is possible to appropriately back up the data stored in the game work area of the RAM 102 .

FIG. 10-11(B) shows a configuration example AKT11 of the power-off recovery vector table. The power-off recovery vector table of the configuration example AKT11 can designate a return destination address from power-off processing in response to an interrupt return instruction when normal power supply is resumed. The power failure recovery vector table consists of lower address specification data 00 [H] stored at address 0016 [H] in the game program area of ROM 101 and upper address specified data 00 [H] stored at address 0017 [H] in the game program area of ROM 101. Designated data 00[H] are included as table data. In step AKS50 of the power-off process P_POWER_OFF, data indicating the address 0016[H] is set in the stack pointer as the vector table address for power-off recovery. After that, by the interrupt return instruction, the stored value of the program counter is set to 0000 [H] and the processing is returned, thereby making it possible to execute the main processing P_MAIN for game control from the beginning.

FIG. 10-12 is a flow chart showing an example of the random number update process P_RANDOM. Random number update process P_RANDOM is included in the process that can be called from timer interrupt process P_PCT for game control shown in FIG. It can be executed in step S56. On the other hand, the random number update process P_RANDOM is not included in the process that can be called from the main process P_MAIN for game control shown in FIG. never Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt after the lapse of a predetermined time, it is not included in the second process that can be repeatedly executed until the first process is executed. do not have. In addition, the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, but the game control is executed based on the start of power supply in the pachinko game machine 1. In the main process P_MAIN for , after the start-up process such as the power supply start corresponding process P_POWER_ON in step S1, it is not called in the standby process as a repeated loop process and cannot be executed.

The random number update process P_RANDOM uses the internal registers of the CPU 103 such as the B register, the DE register, and the HL register to indicate the values of the random number MR1-2 for the winning symbol and the random number MR2-1 for the normal symbol per symbol. Allow numeric data to be updated. The random number MR1-2 for the winning symbol corresponds to the special symbol game, which is the variable display of the special symbol in the first special symbol display device 4A or the second special symbol display device 4B, and the final special symbol that results in the display of the special symbol. Used to determine the design. The normal symbol-per-symbol random number MR2-1 corresponds to the normal symbol game in which the normal symbol is variably displayed on the normal symbol display device 20, and is used to determine the determined normal symbol, which is the display result of the normal symbol. In the random number update process P_RANDOM, when updating the random number MR1-2 for the winning symbol and when updating the random number MR2-1 for the normal symbol per symbol, B register, DE register, and HL are common internal registers. A register can be used to update each random value.

When the random number update process P_RANDOM is executed, the CPU 103 sets the winning symbol random number counter address by a transfer command for setting the HL register used as the random number pointer (step AKS61). The winning symbol random number counter address is the address of the winning symbol random number counter provided in the game work area of the RAM 102 . The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, by storing the address of the winning symbol random number counter in the random number pointer by the LDQ instruction, the winning symbol random number MR1-2 can be set as the random number to be updated.

Following step AKS61, a transfer instruction for setting the B register used as the maximum random number register sets the maximum random number value corresponding to the winning symbol maximum random number determination value (step AKS62). The random number maximum value register can store the maximum value that the random number value to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning symbol, the maximum value included in the update range of the random number MR1-2, such as C7 [H] corresponding to "199", is stored in the random number maximum value register by the LD command. . As a result, it is possible to set the maximum random number value of the random number MR1-2 set as the random number value to be updated in step AKS61.

After step AKS62, a transfer instruction for setting the DE register used as the initial value pointer sets the random number initial value data buffer address for winning symbols (step AKS63). The winning design random number initial value data buffer address is the address of the winning design random number initial value data buffer provided in the game work area of the RAM 102 . The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and enables acquisition and modification of the random number initial value by setting the stored value. In step AKS63, by storing the address of the winning design random number initial value data buffer in the initial value pointer by the LDQ instruction, it is possible to acquire the random number initial value corresponding to the random number MR1-2 which is the random number to be updated in step AKS61. and set mutable. Subsequently, an initial value change random number update process P_RANCP is executed by a subroutine call instruction (step AKS64). The initial value change random number update process P_RANCP in step AKS64 can update random numbers MR1-2 for winning symbols, which are random numbers to be updated, and change the initial value of random numbers, based on the settings in steps AKS61 to AKS63. to

After the initial value change random number update process P_RANCP in step AKS64, the random number counter address for normal design per design is set by the transfer command for setting the HL register used as the random number pointer (step AKS65). The normal per-symbol random number counter address is the address of the normal per-symbol random number counter provided in the game work area of the RAM 102 . In step AKS65, by storing the address of the normal per-symbol random number counter in the random number pointer by means of the LDQ command, the normal per-symbol random number MR2-1 can be set as the random number to be updated.

Following step AKS65, a transfer command for setting the B register used as a random number maximum value register sets the random number maximum value corresponding to the normal symbol per symbol random number maximum judgment value (step AKS66). In step AKS66, for the random number MR2-1 for the normal symbol per symbol, the maximum value included in the update range of the random number MR2-1, such as C6 [H] corresponding to the maximum value "198", is set to the maximum random number value by the LD command. Store in a register. As a result, it is possible to set the maximum random number value of the random number MR2-1, which is the random number value to be updated in step AKS65.

After step AKS66, a transfer instruction for setting the DE register used as the initial value pointer is used to set the random number initial value data buffer address for normal symbols per symbol (step AKS67). The normal per-symbol random number initial value data buffer address is the address of the normal per-symbol random number initial value data buffer provided in the game work area of the RAM 102 . In step AKS67, the random number initial value can be obtained for the random number MR2-1, which is the random number to be updated in step AKS65, by storing the address of the random number initial value data buffer for the normal symbol per symbol in the initial value pointer by the LDQ instruction. and set mutable. Subsequently, an initial value change random number update process P_RANCP is executed by a subroutine call instruction common to step AKS64 (step AKS68). The initial value change random number update process P_RANCP of step AKS68 updates the random number MR2-1 for the normal symbol per symbol, which is the random number to be updated, and changes the initial value of the random number, based on the settings of steps AKS65 to AKS67. Make it executable.

FIGS. 10-13 are diagrams for explaining a usage example of a data structure relating to random number update processing P_RANDOM. In the random number update process P_RANDOM, step AKS64 of step AKS64 is performed using the winning symbol random number counter whose address is set in the random number pointer in step AKS61 and the winning symbol initial value data buffer whose address is set in the initial value pointer in step AKS63. An initial value change random number update process P_RANCP is executed. Also, in the random number update process P_RANDOM, a normal per-symbol random number counter having an address set in the random number pointer in step AKS65, a normal per-symbol random number initial value data buffer having an address set in the initial value pointer in step AKS67, is used to execute the initial value change random number update process P_RANCP of step AKS68. The winning symbol random number counter is provided in the special symbol random number buffer area, and can store numerical data corresponding to the winning symbol random numbers MR1-2. The winning symbol random number initial value data buffer is provided in the winning symbol random number data area, and can store numerical data corresponding to the random number initial values of the random numbers MR1-2. The normal per-symbol random number counter is provided in the winning-symbol random number data area, and can store numerical data corresponding to the normal per-symbol random number MR2-1. The normal winning symbol random number initial value data buffer is provided in the winning symbol random number data area, and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM consists of a winning symbol random number initial value data buffer provided in a winning symbol random number data area, a normal symbol per symbol random number counter, and a normal symbol per symbol random number initial value data buffer. , and a winning symbol random number counter provided in the special symbol random number buffer area, software can update the random number MR1-2 and the random number MR2-1.

FIG. 10-13(A) shows a configuration example AKB11 of the winning symbol random number data area. The winning symbol random number data area of the configuration example AKB11 includes a winning symbol random number initial value data buffer at address F050 [H], a winning symbol initial value random number counter at address F051 [H], and a normal symbol at address F052 [H]. It includes a winning symbol random number counter, a normal symbol per symbol random number initial value data buffer at address F053 [H], and a normal symbol per symbol initial value random number counter at address F054 [H]. Of these, the address F050 [H] of the random number initial value data buffer for the winning design is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, and the address F052 [H] of the random number counter for the normal design is the random number update process. A random number pointer is set by step AKS65 of P_RANDOM, and the address F053 [H] of the random number initial value data buffer for normal symbols is set to the initial value pointer by step AKS67 of random number update process P_RANDOM. The winning symbol initial value random number counter can store numerical data corresponding to the random numbers MR1-3 as the winning symbol initial value. The normal per-symbol initial value random number counter can store numerical data corresponding to the random number MR2-2 as the normal per-symbol initial value.

FIG. 10-13(B) shows a configuration example AKB12 of the special symbol random number buffer area. The special symbol random number buffer area of the configuration example AKB12 includes a special symbol determination random number buffer at address F07F [H], a winning symbol random number counter at address F081 [H], and a variation pattern type selection at address F082 [H]. It includes a random number buffer, a variation pattern random number buffer at address F083[H], and a loss effect selection random number buffer at address F084[H]. Among them, the address F081 [H] of the winning symbol random number counter is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The special symbol determination random number buffer can store numerical data corresponding to the special symbol determination random number MR1-1 obtained from the 16-bit random number circuit 104A. The variation pattern type selection random number buffer can store numerical data corresponding to the variation pattern type selection random number MR3-3 obtained from the 8-bit random number circuit 104B. The fluctuation pattern random number buffer can store numerical data corresponding to the fluctuation pattern random numbers MR3-4 obtained from the 8-bit random number circuit 104B. The random number buffer for selecting the losing effect can store numerical data corresponding to the random number MR3-2 for selecting the losing effect obtained from the 16-bit random number circuit 104A.

FIG. 10-14 is a flow chart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in FIG. 10-12. , and can be executed in step AKS68 after setting the random number MR2-1 for the normal symbol per symbol in steps AKS65 to AKS67. Such an initial value change random number update process P_RANCP makes it possible to update the value of the random number MR1-2 using the numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. Further, the initial value change random number update process P_RANCP makes it possible to update the value of the random number MR2-1 using numerical data corresponding to the random number MR2-1 for normal per symbol in step AKS68.

When executing the initial value change random number update process P_RANCP, the CPU 103 first executes a comparison addition instruction (step AKS101). In this comparison-addition instruction, the storage data at the address indicated by the value stored in the HL register, which is a random number pointer, is used as an update target value, and the value stored in the B register, which is a random number maximum value register, as a comparison judgment value. It can be executed by a single ICPLD instruction. The value stored in the HL register, which is a random number pointer, indicates the address of the random number counter in which numerical data corresponding to the random number value to be updated is stored. The value stored in the B register, which is the maximum random number value register, indicates the maximum random number value set corresponding to the random number value to be updated. When the count value of the random number counter indicating the random value to be updated is less than the value stored in the random number maximum value register, the count value of the random number counter is incremented by 1, so that the random value to be updated is incremented by 1. be done. On the other hand, if the count value of the random number counter that indicates the random value to be updated is greater than or equal to the value stored in the random number maximum value register, the random number counter is cleared and the count value is initialized to "0". The random value is changed to the minimum random value. Therefore, the comparison addition instruction in step AKS101 is to compare the random number value to be updated with the maximum random number value, to add 1 to the random number value to be updated if the result of the comparison is less than the maximum random number value, and to It is a single instruction including changing the random value to be updated to the minimum random value if it is greater than or equal to the value. In this way, when updating the random number value to be updated by the initial value change random number update process P_RANCP, a single comparison addition instruction is first executed. By executing such a single compare-add instruction first, it is possible to suppress the occurrence of malfunctions and appropriately update the random value.

When the comparison addition instruction is executed in step AKS101, the random number pointed to by the random number pointer is loaded by the transfer instruction for reading the stored data (step AKS102). Also, the random number pointer and the initial value pointer are exchanged (step AKS103). Then, the random number loaded in step AKS102 is compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). At this time, it is determined whether or not the compared random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random value to be updated. Therefore, in step AKS104, after executing the comparison-addition instruction of step AKS101, the random number to be updated after being updated by the comparison-addition instruction is compared with the random number initial value.

If the random value differs from the value stored in the random number initial value data buffer pointed to by the initial value pointer in response to step AKS105 (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the comparison addition instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated indicates the random number value to be updated after updating. When the initial value change random number update process P_RANCP ends according to the determination result of step AKS105, the value stored in the random number counter indicating the update target random number value after update is stored as it is as the current random number value. Therefore, in step AKS105, if the updated random number value after update does not match the random number initial value, the initial value change random number update process P_RANCP is terminated, and the updated random number value after update is stored as the current random number value. be able to.

If the random value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer corresponding to step AKS105 (step AKS105; No), the initial value indicated by adding 1 to the value stored in the initial value pointer. Load the random number counter (step AKS 106). In the configuration example AKB11 of the winning symbol random number data area shown in FIG. H] is provided with a winning symbol initial value random number counter. In addition, at the next address F054 [H] when 1 is added to the address F053 [H] in which the random number initial value data buffer for normal per symbol is provided, the initial value random number counter for normal per symbol is provided. . Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the winning symbol random number initial value data buffer, the count value of the winning symbol initial value random number counter is read. In step AKS106, when the stored value of the initial value pointer indicates the address of the normal per-symbol random number initial value data buffer, the count value of the normal per-symbol initial value random number counter is read. Thus, in step AKS106, the count value of the initial value random number counter can be read as the initial value random number value.

When the initial value random number counter is loaded in step AKS106, the read count value of the initial value random number counter is stored in the random number counter indicated by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 can store the count value of the initial value random number counter as the current random number value to be updated. Therefore, if the updated random number value after the update matches the random number initial value as a result of the determination in step AKS105, then in step AKS107 the initial value random number value read out in step AKS106 is stored as the current random number value. can be done.

Following step AKS107, the count value of the initial value random number counter read out in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108). finish. Since the stored value of the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, the count value of the initial value random number counter can be stored as a new random number initial value at step AKS108. Therefore, if the random number value to be updated after the update matches the initial random number value according to the determination result of step AKS105, the random number value for the initial value is stored as the current random number value in step AKS107, and in step AKS108, it is read by step AKS106. The generated initial value random number can be stored as a new random number initial value. In this way, by setting a new random number initial value, the uncertainty of the random number is increased, and by storing it as the current random number, an increase in the data capacity is prevented, and the random number can be appropriately updated.

In the random number update process P_RANDOM shown in FIG. 10-12, steps AKS61 to AKS63 are performed for the random numbers MR1-2 for winning symbols. Initial value change random number update process P_RANCP is executed. The initial value change random number update process P_RANCP makes it possible to update the random number value to be updated and change the initial random number value based on the settings of the random number value to be updated, the maximum random number value, and the initial value of the random number. The initial value change random number update process P_RANCP of step AKS64 uses the random number maximum value set by step AKS62 and the random number initial value set by step AKS63 for the random number MR1-2 for the winning symbol that is the random value to be updated by step AKS61. update. In addition, the initial value change random number update process P_RANCP of step AKS64 is for the random number MR1-2 for the winning symbol set as the random value to be updated by step AKS61. Allows you to change the initial random number value. In this way, by updating the set random number value to be updated, it is possible to appropriately update the random number value.

In the random number update process P_RANDOM, steps AKS65 to AKS67 are performed for the random number MR2-1 for normal symbol per symbol. After setting the update target random number value, the maximum random number value, and the random number initial value, the initial value change random number update is performed in step AKS68. Execute process P_RANCP. The initial value change random number update process P_RANCP of step AKS68 is the random number maximum value set by step AKS66 or the random number initial value set by step AKS67 for the random number MR2-1 for the normal symbol per symbol, which is the random value to be updated by step AKS65. to allow updates using In addition, the initial value change random number update process P_RANCP of step AKS68 is performed when the random number MR2-1 for the normal symbol per symbol set as the random value to be updated by step AKS65 matches the random number initial value set by step AKS67. In addition, it is possible to change the random number initial value. In this way, by updating the set random number value to be updated, it is possible to appropriately update the random number value. Also, by updating the set random number value to be updated and changing the initial value of the random number, it is possible to appropriately update the random number value.

The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol used when determining the display result of the special symbol by the first update process consisting of steps AKS61 to AKS64, and can update the display result of the normal symbol. The normal symbol-per-symbol random number MR2-1 used for determination can be updated by the second update process consisting of steps AKS65 to AKS68. Then, the random number MR1-2 for the winning symbol is updated as the first random number in steps AKS61 to AKS64, and then the random number MR2-1 for the normal symbol per symbol is updated as the second random number in steps AKS65 to AKS68. . A fixed special symbol, which is a display result of the special symbol, corresponds to the maximum value of the number of openings of the big winning opening in the jackpot game state. In addition, the fixed special symbol, which is the display result of the special symbol, is whether or not it is controlled to the probability variable state after the end of the big win game state, and the maximum value of the variable display times that can be executed in the time saving state after the end of the big win game state. may also correspond to On the other hand, the fixed normal symbol, which is the display result of the normal symbol, corresponds to the opening time and the number of openings of the second big winning opening. Therefore, the display result of the special symbol attracts a higher degree of player's attention than the display result of the normal symbol. After updating the random number MR1-2 as the first random value and then updating the random number MR2-1 as the second random value by the random number update processing P_RANDOM, which is the specific update processing, the display result attracts the player's attention. By updating the first random value used for determination before the second random value, it is possible to suppress the occurrence of defects and appropriately update the random value.

In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2 as the first random value, and steps AKS65 to AKS68 can update the random number MR2-1 as the second random value. Then, the initial value change random number update process P_RANCP of step AKS64 can be called and executed corresponding to the random number MR1-2 that becomes the first random value, and step AKS68 can be executed corresponding to the random number MR2-1 that becomes the second random value. can be executed by calling the initial value change random number update process P_RANCP. In this way, the random number update process P_RANDOM, which is a specific update process, calls the initial value change random number update process P_RANCP, which is a common update process, in correspondence with the first random value and the second random value. The random number MR1-2 as a numerical value and the random number MR2-1 as a second random value are updated so that their initial values can be changed. This initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random number and second random number, and enables appropriate random number updates. become.

In the random number update process P_RANDOM, steps AKS61 to AKS64 for enabling update of the random number MR1-2 as the first random value are the first update process, steps AKS65 to AKS65 for enabling update of the random number MR2-1 as the second random value. The AKS 68 becomes the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM calls the initial value change random number update process P_RANCP as a common update process in the first update process and the second update process, thereby generating the random numbers MR1-2 and MR1-2 as the first random values. The random number MR2-1 as the second random number is updated and their initial values are made changeable. This initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random number and second random number, and enables appropriate random number updates. become.

In the random number update process P_RANDOM, steps AKS61 to AKS64 for enabling update of the random number MR1-2 as the first random value are the first update process, steps AKS65 to AKS65 for enabling update of the random number MR2-1 as the second random value. The AKS 68 becomes the second update process. In the first update process and the second update process, the HL register, B register, and DE register of the CPU 103, which are common internal storage means, are used to store the random number MR1-2 as the first random value and the second random number MR1-2. Random number MR2-1 as a numerical value can be updated. In this manner, the first random number value and the second random number value are stably updated using the common internal storage means, so that the random number value can be appropriately updated.

In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP in step AKS64, in steps AKS61 to AKS63, the winning symbol random number counter address, the winning symbol random number maximum judgment value, and the winning symbol random number initial value data Reference destination information such as a buffer address is stored in the HL register, B register, and DE register of the CPU 103 as internal storage means. Also, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP at step AKS68, at steps AKS65 to AKS67, the random number counter address per normal symbol, the maximum judgment value for random number per normal symbol, the normal Reference destination information such as the per-symbol random number initial value data buffer address for the design is stored in the HL register, B register and DE register of the CPU 103 as internal storage means. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS61, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS65, are said to set the HL register of the CPU 103. The random number counter address for winning symbols is set by step AKS61, but the random number counter address for normal symbols is set by step AKS65, so different reference destination information can be set. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS62, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS66, are said to set the B register of the CPU 103. In step AKS62, the maximum random number value corresponding to the maximum judgment value of the random number for the winning symbol is set. Different reference destination information can be set. The instruction used to update the random number MR1-2, which becomes the first random value in step AKS63, and the instruction used to update the random number MR2-1, which becomes the second random value in step AKS67, are said to set the DE register of the CPU 103. The random number initial value data buffer address for winning symbols is set by step AKS63, but the random number initial value data buffer address for normal symbols is set by step AKS67, so different reference destination information can be set. be. In steps AKS61 to AKS63 and steps AKS65 to AKS67, different reference information can be set using common instructions such as LD and LDQ instructions, which are transfer instructions for setting internal registers of the CPU 103. do. Then, in steps AKS64 and AKS68, an initial value change random number update process P_RANCP is called and executed by a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is the specific update process, the instruction used to update the random number MR1-2 as the first random value and the instruction used to update the random number MR2-1 as the second random value are , are common. Stable update of the first random value and the second random value by making it possible to update the random number MR1-2 as the first random value and the random number MR2-1 as the second random value using a common instruction. to update the appropriate random value.

In the random number update process P_RANDOM, the random number MR1-2 as the first random number can be updated by steps AKS61 to AKS64 as the first update process, and the second random number and the second random number are updated in steps AKS65 to AKS68 as the second update process. The random number MR2-1 is made updatable. Then, the initial value change random number update process P_RANCP can be called and executed in steps AKS64 and AKS68. Since the initial value change random number update process P_RANCP shown in FIG. 10-14 first executes a single comparison addition instruction, the random number MR1-2 as the first random number is updated and the second random number is In both cases, the compare-add instruction is made executable first. By executing such a comparison-addition instruction first, it is possible to suppress the occurrence of defects in the first random number value and the second random number value, and to appropriately update the random number value.

When the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM, the random numbers MR1-2 for the winning symbols can be updated, and the random numbers MR1-3 as the initial values for the winning symbols are changed. can be used to change the random number initial value corresponding to the winning symbol random number MR1-2. In addition, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it is possible to update the random number MR2-1 for the normal symbol per symbol, and the normal value per symbol normal value for the symbol. The random number initial value corresponding to the random number MR2-1 for normal per symbol can be changed by using the random number MR2-2. Therefore, the random numbers MR1-3, which are the initial values for the winning symbols, are updated by executing the initial value change random number update process P_RANCP in step AKS64 of the random number update process P_RANDOM. This is the first initial value random number used when changing the random number initial value corresponding to the pattern random number MR1-2. The random number MR2-2, which is the initial value for the pattern per normal pattern, is changed by executing the initial value change random number update process P_RANCP in step AKS68 of the random number update process P_RANDOM. This is the second initial value random number used when changing the random number initial value corresponding to the per-symbol random number MR2-1.

FIG. 10-15 is a flow chart showing an example of the initial value determination random number update process P_TFINIT. The initial value determination random number update process P_TFINIT is included in the process that can be called from the main process P_MAIN for game control shown in FIG. is executable. In addition, the random number update process P_TFINIT for initial value determination is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. It can be executed in step AKS57 in response to the occurrence. Therefore, the initial value determination random number update process P_TFINIT consists of a first process that can be executed in response to a timer interrupt caused by the elapse of a predetermined time, and a second process that can be repeatedly executed until the first process is executed. included. In addition, the initial value determination random number update process P_TFINIT can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, and is executed based on the start of power supply in the pachinko game machine 1. In the main process P_MAIN for the game control performed, after starting process such as power supply start corresponding process P_POWER_ON of step S1, it is called by step S9 included in the standby time process as a repeated loop process and can be executed. . In this way, the random number update process P_IFINIT for initial value determination is included in processes that can be executed in response to periodic timer interrupts as random number update processes for initial values, and is also included in processes that can be executed irregularly and repeatedly. Since the update cycle and update speed of the random number for initial value become indeterminate by being included, the uncertainty of the random number for initial value is increased, and it is possible to update the random number appropriately.

When the initial value determination random number update process P_TINIT is executed, the CPU 103 sets the winning symbol initial value random number counter address by a transfer command for setting a pointer (step AKS81). The winning symbol initial value random number counter address is the address F051 [H] assigned to the winning symbol initial value random number counter in the configuration example AKB11 of the winning symbol random number data area shown in FIG. 10-13(A). be. When the pointer is set in this manner, the count value of the winning symbol initial value random number counter can be updated within the update range of "0" to "199" by a comparison addition command (step AKS82). This compare-add instruction can be executed by a single ICPLD instruction, which is the third special transfer instruction, with the stored data at the address pointed by the pointer as the update target value and the immediate value specified by the operand as the comparison determination value. The stored value of the pointer indicates the address of the random number counter in which the numerical data corresponding to the update target initial value random number is stored. The immediate value specified by the operand indicates the maximum random number for initial value set corresponding to the random number for initial value to be updated. Then, when the count value of the random number counter indicating the random value for the initial value to be updated is less than the maximum value of the random number for the initial value, the count value of the random number counter is updated by adding 1 to the value for the initial value to be updated. 1 is added to the random number. On the other hand, if the count value of the random number counter indicating the random value for the initial value to be updated is greater than or equal to the value stored in the maximum random value register for the initial value, the random number counter is cleared and the count value is initialized to "0". By doing so, the random number for the initial value to be updated is changed to the minimum random number. Therefore, in the comparison addition instruction of step AKS82, the random numbers MR1-3 which are the winning symbol initial values are set as the update target initial value random values, and the update target initial value random values are compared with the initial value random number maximum value. If the comparison result is less than the maximum random number for initial value, 1 is added to the random number for initial value to be updated. A single instruction containing changing the number to a random minimum value. Note that the comparison-addition instruction is not limited to the ICPLD instruction in which the address of the stored data indicating the value to be updated is specified by a pointer. even an ICPLDQ instruction where the low address is set using the immediate value specified. In this case, the immediate value specified by the second operand of the comparison-addition instruction should be set as the comparison determination value. By updating the random number for the initial value to be updated using such a comparison-addition instruction, it is possible to suppress the occurrence of defects and appropriately update the random number.

After step AKS82, an initial value random number counter address for normal design per design is set by a transfer command for setting a pointer (step AKS83). The normal per-symbol initial value random number counter address is the address F054 assigned to the normal per-symbol initial value random number counter in the configuration example AKB11 of the winning symbol random number data area shown in FIG. 10-13 (A). [H]. When the pointer is set in this way, the count value of the initial value random number counter for normal symbol per symbol can be updated within the update range of "1" to "198" (step AKS84), and the initial value The determination random number update process P_TFINIT ends. The comparison-addition instruction in step AKS84 may be the same comparison-addition instruction as in step AKS82. However, in the comparison addition command of step AKS84, the random number MR2-2, which is the initial value for the normal symbol per symbol, is set as the random number for the initial value to be updated. The immediate value is set to a different value than the compare-add instruction of step AKS82. Therefore, in the comparison addition command of step AKS84, the random number MR2-2, which is the initial value for the normal symbol per symbol, is set as the random number for the initial value to be updated, and the random number for the initial value to be updated is the maximum random number for the initial value. If the comparison result is less than the maximum random number for initial value, add 1 to the random number for initial value to be updated. If the result of comparison is greater than or equal to the maximum random number for initial value, the initial value to be updated It is a single instruction that includes changing the random value to the minimum random value. By updating the random number for the initial value to be updated using such a comparison-addition instruction, it is possible to suppress the occurrence of defects and appropriately update the random number.

The initial value determination random number update process P_TFINIT updates the random number MR1-3 as the winning symbol initial value by steps AKS81 and AKS82 as the update of the first initial value random number. Along with this, the random number update process P_TFINIT for initial value determination updates the random number MR2-2, which is the initial value for the normal symbol per symbol, in steps AKS83 and AKS84 as the update of the second initial value random number. The random numbers MR1-3 to be the winning symbol initial values are the first random numbers used when changing the random number initial values when the update target random numbers are the winning symbol random numbers MR1-2 to be the first random values. Random value for initial value. The random number MR2-2, which is the initial value for the normal per-symbol pattern, is used when changing the initial value of the random number when the random number to be updated is the random number MR2-1 for the normal per-symbol pattern, which is the second random value. is a random value for the second initial value to be set. Steps AKS81 and AKS82 of the initial value determination random number update process P_TFINIT are the first initial value update process capable of updating the first initial value random number value. Steps AKS83 and AKS84 of the initial value determination random number update process P_TFINIT are second initial value update processes capable of updating the second initial value random number value. By updating the random number for the first initial value and the random number for the second initial value, it is possible to update the random number appropriately so that the uncertainty of the first random number and the second random number can be reliably increased. Become.

In addition, the initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol as the first random value for the initial value in steps AKS81 and AKS82, and then the second random number in steps AKS83 and AKS84. The random number MR2-2, which is the initial value for the normal symbol per symbol, is updated as the random value for the initial value. Therefore, the initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol that is the first initial value random number by steps AKS81 and AKS82 that are the first initial value update process. By steps AKS83 and AKS84, which are the second initial value update process, the random number MR2-1, which is the second initial value random number and which is the initial value for the normal symbol per symbol, is updated.

FIG. 10-16 is a flow chart showing an example of the starting port switch passing process P_TZU_ON. The starting port switch passage processing P_TZU_ON is included in the processing that can be called from the special symbol process processing P_TPROC shown in FIG. Yes, it can be executed in step S108 when the second start winning flag is ON in step S107. When the CPU 103 executes the starting opening switch passing process P_TZU_ON, the CPU 103 sets a starting opening winning memory counter address by a transfer command for setting a pointer (step AKS201). The start opening winning memory counter address is the address of the first starting opening winning memory counter or the second starting opening winning memory counter provided in the game work area of the RAM 102 . At step AKS201, different addresses in the game work area can be specified in correspondence with the first starting opening winning table or the second starting opening winning table set by the special symbol process P_TPROC. For example, the upper address F0 [H] of the game work area, which is the work area, is set to the upper byte of the pointer by the transfer command, and is stored in the first start winning table or the second starting winning table pointed to by the table pointer. The lower address of the starting opening winning storage counter is set to the lower byte of the pointer by a transfer command. As a result, the value indicating the address of the first starting opening winning memory counter or the second starting opening winning memory counter is stored in the internal register of the CPU 103 as a pointer. Subsequently, a start entry winning memory counter is loaded by a transfer command for reading the stored data at the address pointed by the pointer (step AKS202).

After step AKS202, it is determined whether or not the count value of the starting entry winning memory counter is equal to or greater than the counter maximum value (step AKS203). For example, if the value loaded in step AKS202 and the maximum counter value such as "4" can be compared and returned by a comparison return instruction, if the counter maximum value is exceeded (step AKS203; Yes), the start switch passage processing P_TZU_ON is completed and returns to the special symbol process processing P_TPROC. On the other hand, if it is less than the maximum value of the counter (step AKS203; No), the count value of the starting entrance winning prize storage counter is updated by adding 1 (step AKS204). In this case, an arithmetic logical operation instruction for incrementing the stored data at the address pointed by the pointer enables update of adding 1 to the count value of the first start entry winning memory counter or the second starting entry winning memory counter.

After step AKS204, a buffer address for special symbol determination is set as a transfer destination (step AKS205). The special symbol determination buffer address is the first special symbol determination buffer included in the first special symbol reservation buffer provided in the game work area of the RAM 102 or the second special symbol determination buffer included in the second special symbol reservation buffer. is the address of In step AKS205, the first starting winning prize table or the second starting winning prize table set by the special symbol process P_TPROC, the count value of the first starting winning prize counter or the second starting winning prize counter loaded by step AKS202, and , a different address in the game work area can be specified.

The first special symbol reservation buffer includes a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first loss effect selection buffer. For example, the buffer number is changed from "0" to "4" corresponding to the case where the variable display of the first special symbol is being executed and the number of first reserved memories that have not been executed yet. are secured as a plurality of storage areas, such as five storage areas corresponding to . The second special symbol reservation buffer includes a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second loss effect selection buffer. For example, the buffer number is changed from "0" to "4" corresponding to the case where the variable display of the second special symbol is being executed and the number of second reserved memories that have not yet been executed. are secured as a plurality of storage areas, such as five storage areas corresponding to .

In step AKS205, the value corresponding to the buffer size of the first pending storage buffer or the second pending storage buffer is multiplied by the count value of the starting entrance winning counter, and the first pending storage buffer of buffer number "1" is multiplied. Alternatively, the multiplied value is added to the lower address of the second reserved storage buffer. By setting such an addition value to the transfer destination pointer, it is sufficient that the special symbol determination buffer address can be set to the transfer destination.

Following step AKS205, the RL0 hard latch random value register address is set (step AKS206). The RL0 hard latch random value register address is the address of the RL0 hard latch random value register provided in the function control register area. For example, the upper address FF [H] of the function control register area is set to the upper byte of the pointer by the transfer instruction, and the RL0 hardware stored in the first starting entry winning table or the second starting entry winning table pointed to by the table pointer The lower address of the latch random value register is set to the lower byte of the pointer by a transfer instruction. The first starting entry winning table stores the lower address of the RL0 hard latch random number register with buffer number "0". The second start winning prize table stores the lower address of the RL0 hard latch random number register with buffer number "1". As a result, as the address of the RL0 hard latch random value register, different addresses are stored in the internal register of the CPU 103 as a pointer for the first start winning and the second starting winning.

After step AKS206, the RL0 hard latch random value register is loaded by a transfer instruction for reading out the stored data at the address indicated by the pointer (step AK207). The stored value of the RL0 hard latch random number register obtained in this way is stored in the special symbol determination random number buffer by a transfer command for writing to the storage area of the specified address in the game work area of RAM 102 (step AKS208). Thus, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, the numerical data indicating the value of the special symbol determination random number MR1-1 is extracted, The value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

After step AKS208, the RL2 soft latch random value register is loaded by a transfer instruction for reading stored data from the storage area of the specified address in the function control register area (step AKS209). The stored value of the RL2 soft latch random number register acquired at this time is stored in the random number buffer for selecting a failure effect by a transfer command for writing to the memory area of the specified address in the game work area of the RAM 102 (step AKS210). Thus, by storing the numerical data obtained from the RL2 soft-latch random value register in the random number buffer for selecting the losing effect, the numerical data indicating the value of the random number MR3-2 for selecting the losing effect is extracted. The value of the random number MR3-2 can be stored in the random number buffer for selecting the losing effect.

After step AKS210, the RS1 soft latch random value register is loaded by a transfer instruction for reading out stored data from the storage area of the specified address in the function control register area (step AKS211). The stored value of the RS1 soft latch random number register obtained at this time is stored in the variation pattern type selection random number buffer by a transfer command for writing to the memory area of the specified address in the game work area of the RAM 102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft latch random number register in the random number buffer for selecting the variation pattern type, the numerical data indicating the value of the random number MR3-3 for selecting the variation pattern type is extracted. and the value of the random number MR3-3 can be stored in the variation pattern type selection random number buffer.

After step AKS212, the RS2 soft latch random number register is loaded by a transfer instruction for reading out stored data from the storage area of the specified address in the function control register area (step AKS213). The stored value of the RS2 soft latch random number register obtained at this time is stored in the fluctuation pattern random number buffer by a transfer command for writing to the memory area of the specified address in the game work area of the RAM 102 (step AKS214). Thus, by storing the numerical data obtained from the RS2 soft latch random number register in the random number buffer for the fluctuation pattern, the numerical data indicating the value of the random number MR3-4 for the fluctuation pattern is extracted, and the random number MR3 A value of -4 can be stored in the fluctuation pattern random number buffer.

Following step AKS214, block transfer from the random number buffer to the special symbol determination buffer is performed (step AKS215). The random number buffer is a random number buffer for special symbol judgment in which the value of the random number MR1-1 is stored in step AKS208, a random number buffer for selecting a loss effect in which the value of the random number MR3-2 is stored in step AKS210, and a random number MR3- in step AKS212. A variation pattern type selection random number buffer storing the value of 3, and a variation pattern random number buffer storing the values of the random numbers MR3-4 in step AKS214. In step AKS215, the address of the random number buffer for special symbol determination is set as the transfer source, and the value corresponding to the buffer size of the random number buffer is set as the number of transfers. In addition, the buffer address for special symbol determination to be the transfer destination is set by step AKS205. By executing a block transfer instruction based on these settings, each random number value temporarily stored in the random number buffer is stored as new pending information in the first pending storage buffer or the second pending storage buffer. can be made

When the new memory information is stored in step AKS215, it is determined whether or not the conditions for the winning effect are established (step AKS216). The prize-winning effect condition may be set in advance as a condition for enabling execution of the look-ahead effect. For example, when the specified value for start-up winning is "2", it is determined that the conditions for the performance at the time of winning are met. In addition, when the starting opening winning specified value is "1", the time saving function flag is "0" corresponding to not being in the time saving state, and corresponding to not being in the small winning game state or the big winning game state. When the special symbol process code is less than 03 [H], it is determined that the winning effect condition is met. When it is determined that the winning effect condition is satisfied (step AKS216; Yes), the winning effect process P_GAME_CHK is executed (step AKS217). Winning effect processing P_GAME_CHK includes a hit determination of a special symbol, selects a specified value for effect corresponding to the determination result, and enables transmission of a winning effect command.

When it is determined that the winning effect condition is not satisfied in response to step AKS216 (step AKS216; No), or after executing the winning effect process in step AKS217, the transfer command for setting the pointer is used to perform the effect A storage information designation command transmission table address is set (step AKS218). The performance storage information designation command transmission table address is the address of the performance storage information designation command transmission table stored in the game data area of the ROM 101 . Then, by executing the command set process P_COM_SET (step AKS219), it becomes possible to transmit the first effect storage information designation command or the second effect storage information designation command as the start winning command. The first effect memory information designation command is a effect control command that designates the first reserved memory number indicated by the count value of the first start opening winning memory counter. The second effect memory information designation command is a effect control command that designates the second reserved memory number indicated by the count value of the second start opening winning memory counter. In this way, the command set processing P_COM_SET of step AKS219 allows the main board 11 to transmit the effect control command, which is the start winning command, to the effect control board 12 .

After step AKS219, a starting entry winning buffer storage counter address is set by a transfer instruction for setting a pointer (step AKS220). The starting entry winning buffer storage counter address is the address of the starting entry winning buffer storage counter provided in the game work area of the RAM 102 . In this way, the count value of the start-up winning buffer storage counter to which the address is set is updated so as to be incremented by one (step AKS221). Also, the pointer is updated corresponding to the starting entry winning buffer storage counter by a compound transfer instruction for setting the register and pointer (step AKS222). For example, by loading the count value of the starting entry winning buffer storage counter after updating by step AKS221 into the internal register of the CPU 103 and updating the stored value of the pointer by adding 1, the start address of the starting entry winning buffer A value indicating is stored in the pointer. Furthermore, by adding the loaded count value of the starting entry winning buffer storage counter to the stored value of the pointer, it is possible to specify the storage area of the buffer number to be updated in the starting entry winning prize buffer.

When the pointer is updated by step AKS222, the start winning designation value is loaded (step AKS223). The specified starting entry winning prize value corresponds to the first starting winning prize table or the second starting winning prize table set by the special symbol process P_TPROC, and indicates the first starting winning prize or the second starting winning prize. "2" can be set. At step AKS223, a transfer command for reading out table data from the first starting winning prize table or the second starting winning winning table makes it possible to acquire the starting winning designation value. The starting opening winning designation value thus obtained is stored in the starting opening winning prize buffer by a transfer command for writing to the storage area of the address pointed by the pointer (step AKS224), and the starting opening switch passage processing P_TZU_ON ends.

FIG. 10-17 is a diagram for explaining an example of use of the data configuration regarding the start switch passage processing P_TZU_ON. In the starting opening switch passage processing P_TZU_ON, various Settings and controls are performed. Then, for example, the first starting opening winning memory counter and the second starting opening winning memory counter whose count value can be updated by step AKS204 are provided in the special symbol control data area, and the first reserved memory number and the second reserved memory number Corresponding data can be stored. A starting winning buffer storage counter that can update the count value by AKS 221 and a starting winning winning buffer in which a specified value for starting winning is stored by AKS 224 are provided in the starting winning buffer area, and the first starting winning and the second starting The total number of wins and the order of occurrence can be stored. Also, in the command set process P_COM_SET of step AKS219, the first effect memory information designation command transmission table or the second effect memory information designation command transmission table whose address is set by step AKS218 is used.

In this way, the starting opening switch passage processing P_TZU_ON includes the first starting opening winning table or the second starting opening winning table, the first starting opening winning memory counter provided in the special symbol control data area, or the second starting opening winning memory counter. Variable display of special symbols using a starter winning buffer storage counter, a starter winning buffer, a first performance storage information specification command transmission table or a second performance storage information specification command transmission table provided in the starter winning buffer area. Enables control over a special game that is.

FIG. 10-17 (A1) shows a configuration example AKT21 of the first starting entry winning table. The first start winning prize table of the configuration example AKT21 includes the lower address of the first starting winning prize storage counter, the lower address of the RL0 hard latch random value register number "0", and the first special symbol determination buffer number "1". , the address of the first effect storage information specification command transmission table, and the start entry winning prize specification value "1".

The first start opening winning storage counter is provided in the game work area of the RAM 102, and can store data corresponding to the first reserved storage number. RL0 hard latch random value register number "0" is an RL0 hard latch random value register with register number "0" provided in the function control register area, and can generate channel RL0 provided in the 16-bit random number circuit 104A. For the random number MR1-1 for special symbol determination, numerical data indicating its value can be acquired by a hard latch and stored. The first special symbol determination buffer number "1" is the first special symbol determination buffer included in the first reserved storage buffer of the buffer number "1" in the first special symbol reserved buffer. The first effect memory information designation command transmission table is stored in the game data area of the ROM 101 and used when transmitting the first effect memory information designation command designating the first reserved memory number. The start entry winning designation value "1" is a designated value indicating that the first starting winning prize has occurred.

FIG. 10-17 (A2) shows a configuration example AKT22 of the second starting entry winning table. The second starting winning prize table of the configuration example AKT22 includes the lower address of the second starting winning prize storage counter, the lower address of the RL0 hard latch random value register number "1", and the second special symbol determination buffer number "1". , the address of the second effect storage information specification command transmission table, and the start entry winning prize specification value "2".

The second start opening winning memory counter is provided in the game work area of the RAM 102, and can store data corresponding to the second reserved memory number. RL0 hard latch random value register number "1" is an RL0 hard latch random value register with register number "1" provided in the function control register area, and channel RL0 provided in the 16-bit random number circuit 104A can be generated. For the random number MR1-1 for special symbol determination, numerical data indicating its value can be acquired by a hard latch and stored. The second special symbol determination buffer number "1" is the second special symbol determination buffer included in the second reserved storage buffer of the buffer number "1" in the second special symbol reserved buffer. The second effect memory information designation command transmission table is stored in the game data area of the ROM 101 and used when transmitting the second effect memory information designation command designating the second reserved memory number. The start entry winning designation value "2" is a designated value indicating that the second starting winning prize has occurred.

FIG. 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of the configuration example AKB21 relates to control by special symbol process processing P_TPROC, such as a special symbol game that is a variable display of special symbols, a small winning game state and a big winning game state that can be controlled based on the display result. Various data can be stored. This special symbol control data area includes a special symbol process timer at address F030 [H], a hit flag at address F032 [H], a special symbol process code at address F033 [H], and a first timer at address F034 [H]. A start opening winning prize storage counter, a jackpot pattern determination buffer at address F035 [H], a small hit pattern determination buffer at address F036 [H], a jackpot winning number counter at address F037 [H], and an address F038 [H] ] counter for the number of times of opening a large winning opening, a large winning opening opening pattern timer at address F039 [H], a large winning opening opening pattern table pointer at address F03B [H], a demonstration display flag at address F03D [H], and a second start entry winning storage counter of address F099[H].

The special symbol process timer can store a clock value corresponding to the control time by the special symbol process P_TPROC. The special symbol process code can specify the process selected in the special symbol process P_TPROC. The first start opening winning memory counter can store a count value corresponding to the first reserved memory number. The big-hit symbol determination buffer can store data corresponding to the big-hit symbol designating value. The jackpot design designation value is a designation value corresponding to the determined special design displayed when the display result is "big hit" in the variable display of the special design, and enables the setting of the type of the jackpot game state. The small-hit design determination buffer can store data corresponding to the small-hit design specified value. The small winning symbol specified value is a specified value corresponding to the fixed special symbol displayed when the display result is "small winning" in the variable display of the special symbols, and the liquor in the small winning game state can be set. The big winning hole winning number counter can store a count value corresponding to the number of game balls that have passed through the big winning hole formed by the special variable winning ball device 50 . The large winning opening opening number counter can store a count value corresponding to the number of openings of the large winning opening in the small winning game state or the big winning game state. The large winning opening opening pattern timer can store a time value corresponding to the remaining time for controlling the large winning opening to be opened in the small winning game state or the big winning game state. The large winning opening opening pattern table pointer can specify the storage address of the large winning opening opening pattern table in which the opening time of the large winning opening is set. The demonstration display flag can store a flag value corresponding to an ON state or an OFF state corresponding to whether or not the demonstration display is being executed. The second start opening winning memory counter can store a count value corresponding to the second reserved memory number.

FIG. 10-17 (B2) shows a configuration example AKB22 of the starting entry winning buffer area. The starting opening winning buffer area of the configuration example AKB22 can store various data related to the first starting winning and second starting winning that occurs when the game ball enters the first starting winning opening and second starting winning opening. This starting entry winning buffer area includes a starting entry winning buffer storage counter of address F0BA [H] and starting entry winning buffer numbers "0" to "8" of addresses F0BB [H] to F0C3 [H]. there is

The starting winning buffer storage counter can store a count value corresponding to the number of effective starting winning designated values stored in the starting winning buffer area. Therefore, the count value of the starting entry winning buffer storage counter indicates the total number of times of the first starting winning and the second starting winning. The starting winning buffer numbers "0" to "8" are starting winning buffers to which the buffer numbers "0" to "8" are assigned, and the starting winning buffers are arranged in order of occurrence of the first starting winning and the second starting winning. Winning designation values can be stored. As a result, the information stored in the start-up winning buffer indicates the order of occurrence of the first start-up winning and the second start-up winning.

FIG. 10-17 (C1) shows a configuration example AKT23 of the first effect storage information specification command transmission table. The first effect storage information specifying command transmission table of the configuration example AKT23 is configured to include table data indicating the first effect storage information specifying command high-order byte and the first start winning prize storage counter reference specified value. there is The command set process P_COM_SET of step AKS219 enables transmission of the first effect storage information designation command when the first effect storage information designation command transmission table is used. The first effect storage information designation command can set the lower byte corresponding to the count value of the first start opening winning storage counter. By transmitting such a first effect memory information designation command, the effect control board 12 can be notified of the first reserved memory number.

FIG. 10-17 (C2) shows a configuration example AKT24 of the second effect storage information specification command transmission table. The second effect storage information specification command transmission table of the configuration example AKT24 is configured to include table data indicating the second effect storage information specification command upper byte and the second start opening winning storage counter reference specification value. there is The command set process P_COM_SET of step AKS219 enables transmission of the second effect storage information designation command when the second effect storage information designation command transmission table is used. The second effect storage information specifying command can set the lower byte corresponding to the count value of the second starting opening winning storage counter. By transmitting such a second effect memory information designation command, the effect control board 12 can be notified of the second reserved memory number.

The starting opening switch passing process P_TZU_ON shown in FIG. 10-16 stores the value stored in the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a losing effect in step AKS210. , numerical data indicating the value of the random number MR3-2 can be extracted. In addition, in the starting port switch passage process P_TZU_ON, the stored value of the RS1 soft latch random number register loaded in step AKS211 is stored in the fluctuation pattern type selection random number buffer in step AKS212 to generate a fluctuation pattern type selection random number MR3- 3, numerical data indicating its value can be extracted. Further, in the starting port switch passing process P_TZU_ON, the value stored in the RS2 soft latch random number register loaded at step AKS213 is stored in the fluctuation pattern random number buffer at step AKS214. Numerical data indicating the value can be extracted. Here, the random number MR3-2 for selecting the losing effect is the first random number, the random number MR3-3 for selecting the type of variation pattern is the second random number, and the random number MR3-4 for the variation pattern is the third random number. In this case, the starting opening switch passage process P_TZU_ON is executed in response to the occurrence of the starting winning, so the first random value, the second random value, and the third random value generate the starting winning, which is a common extraction. It becomes possible to extract when the conditions are met. The random number MR3-2 for selecting the losing effect is included in the game random number that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting the variation pattern type and the random number MR3-4 for the variation pattern are 8-bit. The total number of random numbers included in the game random numbers that can be updated by the random number circuit 104B and all included in the update range is a prime number. The update speed of the random number MR3-2 is 469 [times/ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times/ms]. In other words, the update speed of the random numbers MR3-3 and MR3-4 is twice the integer multiple of the update speed of the random number MR3-2. The update range of the random number MR3-2 is "0" to "65518", the update range of the random number MR3-3 is "0" to "240", and the update range of the random number MR3-4 is "0" to "250". , the total number of random numbers included in each update range is different, and the total number of random numbers included in each update range is a prime number. As described above, when the update speed of the second random value and the third random value is an integral multiple of the update speed of the first random value, the total number of random values included in each update range is different, and both are updated. The total number of random values in the range is prime. As a result, it is possible to suppress the occurrence of synchronization among the first random value, the second random value, and the third random value, and to appropriately update the random value.

FIG. 10-18 is a flow chart showing an example of the special symbol normal process P_TNORMAL. The special symbol normal process P_TNORMAL is included in the process that can be called from the special symbol process process P_TPROC shown in FIG. is executable. When the special symbol normal process P_TNORMAL is executed, the CPU 103 sets a start opening winning buffer storage counter address by a transfer command for setting a pointer (step AKS241). The starting entry winning buffer storage counter address is the address of the starting entry winning buffer storage counter provided in the game work area of the RAM 102 . In this way, it is determined whether or not the count value of the starting entry winning buffer storage counter to which the address is set is "0" (step AKS242). For example, if the stored data at the address pointed to by the pointer is 00[H] corresponding to "0" or not, an arithmetic jump instruction causes the processing to branch, causing the count value of the starting entry winning buffer storage counter to become "0". ” and other than “0”, different processing contents can be executed.

When the count value of the start-up winning buffer storage counter is not "0" corresponding to step AKS242 (step AKS242; No), the count value of the start-up winning buffer storage counter is updated by subtracting 1 (step AKS243 ). In addition, block transfer for shift of the start-up winning buffer is performed (step AKS244). In step AKS244, the transfer destination address is set to the lower address BB [H] of the starting entry winning buffer number "0", the transfer source address is set to the lower address BC [H] of the starting entry winning buffer number "1", and the number of transfers is started. Each is set to "8", which is the buffer size of the winning buffer. After that, by executing a block transfer instruction, the contents stored in the start-up winning buffer may be transferred and shifted one unit at a time to the previous buffer. Then, the storage area of the start-up winning buffer number "8" may be initialized by clearing it.

After step AKS244, a second special symbol determination control table address is set by a transfer command for setting a table pointer (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of the ROM 101 . At this time, it is determined whether or not the specified starting winning prize value is "1" by executing the starting winning winning check process (step AKS246). For example, in the starting winning prize check process, the zero flag is turned on when the starting winning designation value is "1", and the zero flag is turned off when the starting winning designation value is "2". After such a starting point winning check process is executed, a jump instruction for branching the process depending on whether the zero flag is in the OFF state is executed when the starting point winning specified value is "1" or "2". , different processing contents can be executed.

When the start opening winning designation value is "1" corresponding to step AKS246 (step AKS246; Yes), the first special symbol determination control table address is set by the transfer command for setting the table pointer (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of the ROM 101 . At step AKS247, the value of the table pointer is overwritten by a transfer instruction for setting the table pointer. Thus, in the special symbol normal process P_TNORMAL, after the second special symbol determination control table address is set in step AKS245, in step AKS246 the start opening winning designation value corresponds to "1", in step AKS247 the first special Reset the design determination control table address by overwrite setting. Thus, when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, the program capacity required for table setting can be reduced, and the marketability of the pachinko game machine 1 is enhanced. be able to. Also, when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, the processing by the jump instruction as the branch instruction is simplified to facilitate confirmation at the design stage. As a result, the marketability of the pachinko game machine 1 can be enhanced.

In response to step AKS246, when the designated value for start-up winning is "2" and not "1" (step AKS246; No), after step AKS247, the special symbol determination process P_TDECISION is executed (step AKS248), After executing the variation pattern setting process P_TPATSET (step AKS249), the special symbol normal process ends.

In response to step AKS242, when the count value of the starting entry winning buffer storage counter is "0" (step AKS242; Yes), it is determined whether or not the demonstration display flag is on (step AKS250). The demonstration display flag is a flag indicating that the demonstration display is being executed. When the demonstration display flag is ON (step AKS250; Yes), the special symbol normal process ends. On the other hand, if the demonstration display flag is off (step AKS250; No), a transfer command for setting the demonstration display flag stores 01 [H], which is a designated value during demonstration display, in the demonstration display flag. (Step AKS251). As a result, the demonstration display flag is set to the ON state. Also, a transfer command for setting a pointer is used to set a standby command transmission table address (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of the ROM 101 . Then, after executing the command set process P_COM_SET (step AKS253), the special symbol normal process ends.

FIGS. 10-19 are diagrams for explaining a usage example of the data configuration regarding the special symbol normal processing P_TNORMAL. In the special symbol normal process P_TNORMAL, the special symbol determination process of step AKS248 is executed using the second special symbol determination control table whose address is set by step AKS245 or the first special symbol determination control table whose address is set by step AKS247. be. In the command set process P_COM_SET of step AKS253, the standby command transmission table whose address is set in step AKS252 is used. In this way, the special symbol normal process P_TNORMAL uses the first special symbol determination control table, the second special symbol determination control table, or the standby command transmission table to control the special symbol game, which is a variable display of special symbols. to

FIG. 10-19 (A1) shows a configuration example AKT31 of the first special symbol determination control table. The first special symbol determination control table of the configuration example AKT31 includes the address of the first special symbol buffer shift control table, the lower address of the first special symbol determination buffer number "0", and the first winning symbol buffer number "0". , the lower address of the first special symbol buffer, and the address of the work setting table after the determination of the first special symbol. The first special symbol buffer shift control table is stored in the game data area of the ROM 101 and used when shifting the storage contents of the first special symbol reservation buffer. The first special symbol determination buffer number "0" is the first special symbol determination buffer included in the first reserved storage buffer of the buffer number "0" in the first special symbol reserved buffer. The first winning symbol buffer number "0" is the first winning symbol buffer included in the first reserved storage buffer of the buffer number "0" in the first special symbol reserved buffer. The first special symbol buffer is provided in the game work area of the RAM 102 and is capable of storing a special symbol pattern designated value corresponding to the fixed special symbol to be stopped and displayed in the first special symbol game by the first special symbol display device 4A. . The work setting table after the first special symbol hit determination is stored in the game data area of the ROM 101, and is used when initializing the data corresponding to the end of the special symbol determination process P_TDECISION.

FIG. 10-19 (A2) shows a configuration example AKT32 of the second special symbol determination control table. The second special symbol determination control table of the configuration example AKT32 includes the address of the second special symbol buffer shift control table, the lower address of the second special symbol determination buffer number "0", and the second winning symbol buffer number "0". , the lower address of the second special symbol buffer, and the address of the work setting table after the determination of the second special symbol. The second special symbol buffer shift control table is stored in the game data area of the ROM 101 and used when shifting the storage contents of the second special symbol reservation buffer. The second special symbol determination buffer number "0" is the second special symbol determination buffer included in the second reserved storage buffer with the buffer number "0" in the second special symbol reserved buffer. The second winning symbol buffer number "0" is the second winning symbol buffer included in the second reserved storage buffer of the buffer number "0" in the second special symbol reserved buffer. The second special symbol buffer is provided in the game work area of the RAM 102 and is capable of storing a special symbol pattern designation value corresponding to the fixed special symbol to be stopped and displayed in the second special symbol game by the second special symbol display device 4B. . The work setting table after the second special symbol hit determination is stored in the game data area of the ROM 101 and used when initializing the data corresponding to the end of the special symbol determination process P_TDECISION.

FIG. 10-19B shows a configuration example AKT33 of the standby command transmission table AKT33. The standby command transmission table of the configuration example AKT33 includes the number of processes, the second specific number of times designation command upper byte, the specific number of times command buffer reference designation value, the background color designation command upper byte, and the special symbol state designation code reference designation value , a customer waiting demonstration command upper byte, and a customer waiting demonstration command lower byte. The command set processing P_COM_SET of step AKS253 enables transmission of the second specific number of times designation command, background color designation command, and customer waiting demonstration command using the standby command transmission table of the configuration example AKT33. The second specific number of times designation command can set the lower byte corresponding to the stored value of the specific number of times command buffer. The background color designation command can set the lower byte corresponding to the special symbol state designation code. The customer waiting demo command can set the lower byte using the fixed value 03 [H].

FIG. 10-20 is a flow chart showing an example of the special symbol determination process P_TDECISION. The special symbol determination process P_TDECISION is included in the processes that can be called from the special symbol normal process P_TNORMAL shown in FIGS. When the special symbol determination process P_TDECISION is executed, the CPU 103 sets a special symbol buffer shift control table address by a transfer command for setting a pointer (step AKS301). The special symbol buffer shift control table address is the address of the first special symbol buffer shift control table or the second special symbol buffer shift control table stored in the game data area of the ROM 101 . In step AKS301, different addresses in the game data area can be specified corresponding to the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, the value indicating the address 13C2 [H] of the first special symbol buffer shift control table is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating the address 13C8 [H] of the second special symbol buffer shift control table is set in the pointer.

Following step AKS301, a special symbol buffer shift process P_TBUFSHIFT is executed (step AKS302). The special symbol buffer shift process P_TBUFSHIFT of step AKS302 uses the first special symbol buffer shift control table or the second special symbol buffer shift control table whose address is set by step AKS301, and uses the first special symbol buffer shift or the second special symbol buffer shift control table. It is possible to shift the memory contents of the symbol holding buffer. For example, after setting the transfer destination address, the transfer source address, and the number of transfers, by executing the block transfer instruction, the first reserved storage buffer of the first special symbol buffer and the second reserved storage buffer of the second special symbol buffer The contents stored in the buffer may be transferred and shifted by one unit to the previous buffer.

After step AKS302, the buffer for special symbol determination with buffer number "0" is loaded (step AKS303). The special symbol determination buffer with the buffer number "0" is the first special symbol determination buffer included in the first reservation storage buffer with the buffer number "0" in the first special symbol reservation buffer, or the second special symbol determination. buffer for In step AKS303, special symbols are selected from the first special symbol reserve buffer or the second special symbol reserve buffer in correspondence with the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal process P_TNORMAL. A value stored in the determination buffer can be read. For example, the upper address F0 [H] of the game work area that becomes the work area is set to the upper byte of the pointer by the transfer command, and the first special symbol determination control table or the second special symbol determination control table pointed to by the table pointer After setting the lower address of the stored first special symbol determination buffer number "0" or the second special symbol determination buffer number "0" to the lower byte of the pointer by the transfer command, in the game work area pointed to by the pointer It is sufficient if the random number MR1-1 for special symbol determination stored in the buffer for special symbol determination of buffer number "0" can be read by reading the stored data of the address.

After step AKS303, a special symbol jackpot determination process P_TFVR_CHK is executed (step AKS304). The special symbol big hit determination process P_TFVR_CHK at step AKS304 compares the value of the special symbol determination random number MR1-1 read out at step AKS303 with the big hit determination value, and determines the special symbol display result as "big hit". It is possible to determine whether or not to Determination of whether or not to make the special figure display result "big hit" is also called special symbol big hit determination, and determines whether or not to control to a big hit game state as an advantageous state. Then, when it is determined that the special symbol display result is "big win" in the special symbol big win determination, 01 [H] as the big win designated value is stored in the hit flag. The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F032 [H]. The special symbol jackpot determination process of step AKS304 may be performed by a transfer command for writing to the memory area of the designated address in the game work area of the RAM 102, so that the jackpot designation value can be stored in the hit flag. Incidentally, the hit flag may be set to 00 [H], which is the initial value, by a clear command executed in response to the start of the special symbol big hit determination process P_TFVR_CHK in step AKS304.

Along with the special symbol big hit determination process P_TFVR_CHK of step AKS304, the special symbol small hit determination process P_TLITTLE_CHK is executed (step AKS305). The special symbol small hit determination process P_TLITTLE_CHK of step AKS305 compares the value of the random number MR1-1 for special symbol determination read out by loading the special symbol determination buffer in step AKS303 with the small hit determination value. By doing so, it is possible to determine whether or not the special figure display result is a "small hit". Determination of whether or not to make the special figure display result "small hit" is also called special symbol small hit determination, and determines whether or not to control to a small hit game state as a predetermined state. Then, when it is determined that the special symbol display result is "small hit" in the special symbol small hit determination, 02 [H], which is the small hit designated value, is stored in the hit flag. The special symbol small hit determination process P_TLITTLE_CHK of step AKS305 can store the small hit specified value in the hit flag by a transfer command for writing to the storage area of the specified address in the game work area of the RAM102.

In the special symbol small hit determination process P_TLITTLE_CHK of step AKS305, the small hit determination value is included in a range different from the big hit determination value, so the special symbol big hit determination determines that the special symbol display result is "big hit". After that, the special symbol display result is not determined to be "small hit" by the special symbol small hit determination. However, for example, due to the occurrence of an error, etc., after the special symbol big hit determination determines that the special symbol display result is a "big hit", the special symbol small hit determination determines that the special symbol display result is a "small hit". , the small hit specified value will be stored in the hit flag. Therefore, when the determination that the special figure display result is "big hit" by the special symbol big hit determination and the determination that the special figure display result is "small hit" by the special symbol small hit determination conflict, from the small hit game state In order not to be controlled to a jackpot game state with a high degree of advantage, it is possible to prevent cheating due to a defect in the determination process and to appropriately control the game.

When the special symbol small hit determination process P_TLITTLE_CHK of step S305 is executed, the winning symbol buffer of buffer number "0" is loaded (step AKS306). The winning symbol buffer with the buffer number "0" is the first winning symbol buffer included in the first reserved storage buffer with the buffer number "0" in the first special symbol buffer, or the buffer number in the second special symbol buffer. This is the second winning symbol buffer contained in the second pending storage buffer of "0". In step AKS306, a winning symbol is selected from the first special symbol buffer or the second special symbol buffer in correspondence with the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal process P_TNORMAL. It is possible to read the stored value of the buffer for For example, the upper address F0 [H] of the game work area that becomes the work area is set to the upper byte of the buffer pointer by the transfer command, and the first special symbol determination control table or the second special symbol determination control table pointed to by the table pointer After setting the lower address of the special symbol determination buffer stored in the transfer instruction to the lower byte of the buffer pointer, by reading the stored data of the address in the game work area pointed to by the buffer pointer, the buffer number "0" It is sufficient if the random numbers MR1-2 for winning symbols stored in the buffer for winning symbols can be read.

After step AKS306, the special symbol buffer lower address is loaded (step AKS307). The special symbol buffer lower address is the address of the first special symbol buffer or the second special symbol buffer provided in the game work area of the RAM 102 . In step AKS307, a different lower address can be specified corresponding to the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the lower address B8[H] of the first special symbol buffer is set to the lower byte of the buffer pointer. Also, when the second special symbol determination control table is set, a value indicating the lower address B9 [H] of the second special symbol buffer is set to the lower byte of the buffer pointer. The upper byte of the buffer pointer has already stored the upper address F0[H] of the game work area by step AKS306.

Following step AKS307, a special symbol information setting process P_TZU_SET is executed (step AKS308). The special symbol information setting process P_TZU_SET makes it possible to determine a fixed special symbol to be stopped and displayed in the special symbol game, and stores a special symbol pattern designation value corresponding to the determination result in the special symbol buffer. After the special symbol information setting process P_TZU_SET, the work setting table address is set after the special symbol hit determination (step AKS309). The post-special symbol hit determination work setting table address is the address of the work setting table after the first special symbol hit determination or the work setting table after the second special symbol hit determination stored in the game data area of the ROM 101 . In step AKS309, a different address in the game data area can be specified in correspondence with the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, the value indicating the address 12BB[H] of the work setting table after the first special symbol hit determination is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating the address 12C0 [H] of the work setting table after the second special symbol hit determination is set in the pointer.

After step AKS309, a data set process P_DATASET is executed (step AKS310), and the special symbol determination process P_TDECISION ends. The data setting process P_DATASET of step AKS310 uses the work setting table after special symbol hit determination whose address is set by step AKS309, in the first reserved storage buffer or second reserved storage buffer of buffer number "0", A buffer for special design determination and a buffer for winning design can be initialized by clearing them. For example, when the work setting table is set after the first special symbol hit determination, the first special symbol determination buffer and The first winning symbol buffer is initialized. Also, when the work setting table is set after the second special symbol hit determination, in the second reservation storage buffer of the buffer number "0" included in the second special symbol reservation buffer, the A second winning symbol buffer is initialized.

FIG. 10-21 is a diagram for explaining a usage example of the data configuration regarding the special symbol determination process P_TDECISION. In the special symbol determination process P_TDECISION, the special symbol big hit determination process P_TFVR_CHK of step AKS304 and the special symbol small hit determination process P_TLITTLE_CHK of step AKS305 use the random number MR1-1 for special symbol determination, and the display result in the variable display of the special symbol. is determined as a "big hit" or a "minor hit" in response to the start of the variable display. Also, in the special symbol information setting process P_TZU_SET of step AKS308, the special symbol buffer loaded with the lower address by step AKS307 is used. In this way, the special symbol determination process P_TDECISION makes it possible to control a special symbol game, which is a variable display of special symbols, using the random number MR1-1 for special symbol determination and the special symbol buffer.

FIG. 10-21(A) shows a special symbol determination example AKC01 by special symbol big hit determination processing P_TFVR_CHK of step AKS304 and special symbol small hit determination processing P_TLITTLE_CHK of step AKS305. The special symbol big hit determination process P_TFVR_CHK of step AKS304 can execute a comparison operation with the big hit determination value in order to determine whether or not the value of the random number MR1-1 for special symbol determination is within the big hit determination range. to The jackpot determination value includes a jackpot lower limit decision value and a jackpot upper limit decision value. When the value of the random number MR1-1 is subtracted from the jackpot lower limit judgment value, if the carry flag is off, the value of the random number MR1-1 is equal to or less than the jackpot lower limit judgment value, and the carry flag is on. If there is, the value of the random number MR1-1 is a value exceeding the jackpot lower limit judgment value. If the value of the random number MR1-1 is equal to or less than the jackpot lower limit judgment value, the special pattern jackpot judgment processing P_TFVR_CHK is ended in response to the fact that the value is not within the jackpot judgment range, and the special pattern judgment processing P_TDECISION is returned to. On the other hand, when the value of the random number MR1-1 exceeds the jackpot lower limit judgment value, the value of the random number MR1-1 is subtracted from the jackpot upper limit judgment value. At this time, if the carry flag is in an OFF state, the value of the random number MR1-1 is a value equal to or less than the jackpot upper limit judgment value, and if the carry flag is in an ON state, the value of the random number MR1-1 exceeds the jackpot upper limit judgment value. is. Therefore, if the value of the random number MR1-1 is equal to or less than the jackpot upper limit judgment value, 01 [H], which is the jackpot designation value, is stored in the hit flag corresponding to being within the jackpot judgment range. If the value of the random number MR1-1 exceeds the jackpot upper limit judgment value, it returns to the special pattern judgment processing P_TDECISION by ending the special pattern jackpot judgment processing P_TFVR_CHK corresponding to the fact that it is not within the jackpot judgment range.

As an example, the jackpot lower limit judgment value may be set to "60000" and the jackpot upper limit judgment value may be set to "60285" in advance. As a result, as in the special symbol determination example AKC01, the value of the random number MR1-1 corresponds to "1" and "2", and the jackpot determination range is from "60001" to "60285". If it is within, the determination result for the special figure display result is "big hit".

The special symbol small hit determination process P_TLITTLE_CHK of step AKS305 compares the random number MR1-1 for special symbol determination with the small hit determination value in order to determine whether the value is within the small hit determination range. be executable. The small hit determination value includes a small hit lower limit determination value and a small hit upper limit determination value. Then, when the value of the random number MR1-1 is subtracted from the small hit lower limit judgment value, if the carry flag is off, the value of the random number MR1-1 is less than the small hit lower limit judgment value, and the carry flag is on. If it is in the state, the value of the random number MR1-1 is a value exceeding the small hit lower limit judgment value. If the value of the random number MR1-1 is less than the small hit lower limit judgment value, it is not within the small hit judgment range. return. On the other hand, when the value of the random number MR1-1 exceeds the small hit lower limit judgment value, the value of the random number MR1-1 is subtracted from the small hit upper limit judgment value. At this time, if the carry flag is off, the value of the random number MR1-1 is less than the small hit upper limit judgment value, and if the carry flag is on, the value of the random number MR1-1 is equal to the small hit upper limit judgment value. It is a value exceeding Therefore, if the value of the random number MR1-1 is equal to or less than the small hit upper limit judgment value, 02 [H], which is the small hit designation value, is stored in the hit flag corresponding to being within the small hit judgment range. . If the value of the random number MR1-1 exceeds the small hit upper limit judgment value, in response to the fact that it is not within the small hit judgment range, by ending the special symbol small hit judgment process P_TLITTLE_CHK To the special symbol judgment process P_TDECISION return. The small hit upper limit determination value may be set to different values corresponding to the case where the starting entry winning designation value is "1" and the case where it is "2".

As an example, the small hit lower limit judgment value may be set in advance so as to be common to "21000" when the starting opening winning designation value is "1" and when it is "2". In addition, the small hit upper limit judgment value is set in advance so that it becomes "21285" when the starting entrance winning judgment value is "1", and becomes "29282" when the starting entrance winning designation value is "2". It is good if it is. As a result, as in the special symbol determination example AKC01, the value of the random number MR1-1 corresponds to "1", and the value of the random number MR1-1 is within the small hit determination range from "21001" to "21285". And, when the value of the random number MR1-1 is within the small hit determination range from "21001" to "29282" corresponding to the starting opening winning specified value "2", the determination result about the special figure display result is a "small hit".

FIG. 10-21(B) shows a configuration example AKB31 of the special symbol buffer area. The special symbol buffer area of the configuration example AKB31 can store a special symbol pattern designation value corresponding to a fixed special symbol that is stopped and displayed as a display result of the special symbol. This special symbol buffer area includes a first special symbol buffer of address F0B8[H] and a second special symbol buffer of address F0B9[H]. The first special symbol buffer can store a special symbol pattern specified value when the first special symbol game is executed by the first special symbol display device 4A. The second special symbol buffer can store a special symbol pattern specified value when the second special symbol game is executed by the second special symbol display device 4B. The special symbol pattern specified value is a specified value of a display pattern corresponding to a confirmed special symbol which is a display result in variable display of special symbols by the first special symbol display device 4A and the second special symbol display device 4B, and is a special symbol for big hits. It includes a pattern specified value and a small hit special symbol pattern specified value. The jackpot special symbol pattern designation value is a display corresponding to the confirmed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result is "big hit" in the variable display of special symbols. It is the specified value of the pattern. The small hit special symbol pattern specified value corresponds to the fixed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result is "small hit" in the variable display of the special symbols. This is the specified value of the display pattern.

FIG. 10-22 is a flow chart showing an example of the special symbol information setting process P_TZU_SET. The special symbol information setting process P_TZU_SET is included in the process that can be called from the special symbol determination process P_TDECISION shown in FIG. is executed, step AKS 308 can be executed. When the CPU 103 executes the special symbol information setting process P_TZU_SET, the hit flag is loaded (step AKS321). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F032 [H]. At step AKS321, the hit flag may be loaded by a transfer command for reading out the data stored at the specified address in the game work area of RAM102. Then, it is confirmed that the hit flag is not the jackpot designation value by an arithmetic jump instruction that can compare the hit flag and the determination value corresponding to the jackpot designation value (step AKS322).

When the hit flag is the jackpot designated value corresponding to step AKS322 (step AKS322; No), the buffer for the winning design of buffer number "0" is set (step AKS323). The winning symbol buffer with the buffer number "0" is loaded by step AKS306 of the special symbol determination process P_TDECISION whose stored value is shown in FIG. 10-20. By transferring this load content to a processing register included in the internal register of the CPU 103, it can be set as a processing target. The stored value of the winning symbol buffer having the buffer number "0" thus set is stored in the special symbol buffer (step AKS324). The special symbol buffer is the first special symbol buffer or the second special symbol buffer loaded with the lower address by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. As a result, for the winning symbol random number MR1-2 stored in the winning symbol buffer with the buffer number "0", numerical data indicating the random number is stored in the first special symbol buffer or the second special symbol buffer. . Therefore, the numerical data indicating the value of the random number MR1-2 can be used as a jackpot special pattern pattern designation value corresponding to the special pattern in which the fixed special pattern is the jackpot pattern when the special pattern display result is "jackpot". be.

Following step AKS324, the starting entry winning buffer of buffer number "0" is loaded into the starting entry winning designation value (step AKS325). The starting entry winning buffer of buffer number "0" is provided in the starting entry winning buffer area of the configuration example AKB22 shown in FIG. 10-17 (B2), and is assigned an address F0BB[H]. In step AKS325, the start-up winning buffer of buffer number "0" may be loaded by a transfer command for reading stored data from the memory area of the designated address in the game work area of RAM102.

After step AKS325, a jackpot information data selection process P_TFVR_ZU is executed (step AKS326). The jackpot information data selection process P_TFVR_ZU selects the starting entry winning designation value loaded by step AKS325, the stored value of the winning symbol buffer loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20, and the like. By using, it is possible to determine the jackpot symbol designation value, and to set the jackpot information setting data corresponding to the decision result. The big-hit information setting data is data indicating a big-hit effect designation value, a fanfare display designation value, and a big-hit end display designation value. The jackpot design specified value determined by the jackpot information data selection process P_TFVR_ZU is stored in the jackpot pattern determination buffer (step AKS327). The jackpot symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F035[H]. At step AKS327, the jackpot symbol designation value may be stored by a transfer command for writing to the memory area of the designated address in the game work area of RAM102.

After step AKS327, big hit information setting data is transferred (step AKS328). In this case, in the big-hit information setting table stored in the game data area of the ROM 101, the storage address of the big-hit information setting data corresponding to the determination result of the big-hit symbol designating value is set to the pointer designating the transfer source. . Also, the address of the effect pattern information buffer provided in the game work area of the RAM 102 is set in the buffer pointer that designates the transfer destination. Furthermore, the data size of the big hit information setting data is set to the number of transfers. After that, the big win information setting data read out from the big win information setting table may be transferred and stored in the effect pattern information buffer, the fanfare display buffer, and the big win end display buffer by a block transfer command. At this time, a variable command designation buffer is set (step AKS329). The variable command designation buffer is provided at the next address of the jackpot end display buffer in the game work area of the RAM 102, and the stored value can be set using the transfer destination address updated by the block transfer command of step AKS327. For example, 01 [H], which is the variable command designation value corresponding to the fact that the special figure display result is determined to be a "jackpot", may be set as the storage value of the variable command designation buffer. In addition, by clearing the variable command designation buffer corresponding to the production state after the end of the jackpot game state, the storage value of the production pattern information buffer, etc., when the stored value is initialized to 00 [H] There may be

When the variable command designation buffer is set by step AKS329, the maximum value buffer for the number of openings of the big winning opening is set (step AKS330). The maximum number of opening times of the big winning opening is provided at the next address of the variable command designation buffer in the game work area of the RAM 102, and can store the maximum number of opening times to control the opening of the big winning opening in the jackpot game state. be. In step AKS330, the number of times the big winning opening is opened is determined using the jackpot symbol designation value determined by the big winning information data selection process P_TFVR_ZU in step AKS326 and the maximum number of times the big winning opening is opened using the table of maximum number of times the big winning opening is opened stored in the game data area of the ROM 101. A maximum value can be determined. If the storage value corresponding to the maximum number of opening times of the big winning opening determined at this time is stored in the maximum number of opening number of big winning openings by a transfer command for writing it in the storage area of the designated address in the game work area of the RAM 102. good.

When the hit flag is not the big hit designated value corresponding to step AKS322 (step AKS322; Yes), the hit flag and the determination value corresponding to the small hit designated value can be compared by an arithmetic jump instruction, the hit flag is not a small hit specified value (step AKS331). When the hit flag is the small hit designated value (step AKS331; No), the small hit special design pattern designated value is stored in the special design buffer (step AKS332). The small-hit special symbol pattern designation value may be created by adding a preset small-hit symbol addition value to the stored value read from the buffer for winning symbols of the buffer number "0". In addition, as the small hit special symbol pattern specified value, a value different from the big hit special symbol pattern specified value may be prepared in advance. The special symbol buffer is the first special symbol buffer or the second special symbol buffer loaded with the lower address by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. In step AKS332, a small winning special symbol pattern specified value created using a small winning symbol added value or the like is transferred to the storage area of the specified address in the game work area of the RAM 102 by the transfer command to write the first special symbol buffer or It may be stored in the second special symbol buffer.

After storing the small hit special design pattern designated value by step AKS332, the small hit design designated value is determined (step AKS333). The small winning design specified value is the first set corresponding to the stored value of the winning design buffer loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20 and the start opening winning prize specified value It can be determined using a small hit state setting table or a second small hit state setting table. The small winning design specified value determined at this time is stored in the small winning design determination buffer (step AKS334). The small hit symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F036 [H]. In step AKS334, the small winning design specified value may be stored by a transfer command for writing to the storage area of the specified address in the game work area of RAM102.

After step AKS334, a designated value for small hit effect is determined (step AKS335). The small-hit performance specified value can be determined using the small-hit information setting table stored in the game data area of the ROM 101 and the small-hit design specified value determined in step AKS333. The small hit effect specified value determined at this time is stored in the effect symbol information buffer (step AKS336). At step AKS336, the small hit effect specified value determined at step AKS335 may be stored in the effect symbol information buffer by a transfer command for writing into the memory area of the specified address in the game work area of RAM102.

When the specified value for small hit effect is stored in step AKS336, data for setting small hit information is transferred (step AKS337). The small-hit information setting data is data indicating a small-hit fanfare display designated value and a small-hit ending display designated value. In step AKS337, in the small-hit information setting table stored in the game data area of the ROM 101, the storage address of the small-hit information setting data corresponding to the determination result of the small-hit performance specified value is set to the pointer that specifies the transfer source. set. Also, the address of the small win fanfare display buffer provided in the game work area of the RAM 102 is set as the transfer destination. Furthermore, the data size of the small hit information setting data is set to the number of transfers. Thereafter, the data for setting the small hit information read from the table for setting the small hit information may be transferred and stored in the small hit fanfare display buffer and the small hit ending display buffer by the block transfer command.

Corresponding to step AKS331, when the hit flag is not the small hit designated value (step AKS331; Yes), the losing special design pattern designated value is stored in the special design buffer (step AKS338). As for the loss special symbol pattern specified value, a value different from the big hit special symbol pattern specified value and the small win special symbol pattern specified value should be prepared in advance. For example, it may be possible to set F1 [H] as the loss special symbol pattern designation value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer loaded with the lower address by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. At step AKS338, if a loss special symbol pattern specified value prepared in advance is stored in the first special symbol buffer or the second special symbol buffer by a transfer command for writing into the memory area of the specified address in the game work area of the RAM 102. good.

Following step AKS338, the performance symbol information buffer is cleared (step AKS339). The effect pattern information buffer can store the effect designation value corresponding to the case where the special symbol display result is "big win" or "minor win". On the other hand, corresponding to the case where the special figure display result is "losing", the stored value is initialized to 00 [H] by clearing the effect pattern information buffer. Also, the variable command designation buffer is cleared (step AKS340).

After steps AKS330, AKS337, and AKS340, a command transmission table address before start of fluctuation is set by a transfer instruction for setting a pointer (step AKS341). The pre-variation start command transmission table address is the address of the pre-variation start command transmission table stored in the game data area of the ROM 101 . Then, after executing the command set process P_COM_SET (step AKS342), the special symbol information setting process P_TZU_SET ends.

FIG. 10-23 is a flow chart showing an example of the jackpot information data selection process P_TFVR_ZU. The jackpot information data selection process P_TFVR_ZU is called in the special symbol information setting process P_TZU_SET shown in FIG. 10-22, and can be executed in step AKS326 when the hit flag is the jackpot specified value in step AKS322. When the CPU 103 executes the jackpot information data selection process P_TFVR_ZU, it sets a second jackpot state setting table address by a transfer command for setting a pointer (step AKS401). The second jackpot state setting table address is the address of the second jackpot state setting table stored in the game data area of the ROM 101 .

After step AKS401, it is confirmed that the value specified for starting winning prize is not "1" (step AKS402). The start winning designation value is stored in the internal register of the CPU 103 by step AKS325 of the special symbol information setting process P_TZU_SET shown in FIG. 10-22. When this start-up winning designation value is "1" (step AKS402; No), the first jackpot state setting table address is set by a transfer command for setting a pointer (step AKS403). The first jackpot state setting table address is the address of the first jackpot state setting table stored in the game data area of the ROM 101 . At step AKS403, the value of the pointer is overwritten by a transfer instruction for setting the pointer. Thus, in the special symbol information setting process P_TZU_SET, after setting the second jackpot state setting table address in step AKS401, in step AKS402 corresponding to the start opening winning a prize specified value "1", in step AKS403 the first The jackpot state setting table address is reset by overwrite setting. Thus, when the frequency of use of the second big win state setting table is higher than the use frequency of the first big win state setting table, the program capacity required for setting the table can be reduced, and the marketability of the pachinko game machine 1 is enhanced. be able to. In addition, when the frequency of use of the second jackpot state setting table is higher than that of the first jackpot state setting table, processing by a jump command as a branch command is simplified to facilitate confirmation at the design stage. As a result, the marketability of the pachinko game machine 1 can be enhanced.

In response to step AKS402, when the specified value for start-up winning is "2" and not "1" (step AKS401; Yes), a winning symbol buffer is set after step AKS403 (step AKS404). The winning symbol buffer is a winning symbol buffer with buffer number "0" loaded in step AKS306 of the special symbol determination process P_TDECISION whose stored value is shown in FIG. 10-20. By transferring this load content to a processing register included in the internal register of the CPU 103, it can be set as a processing target. The stored value of the hit pattern buffer set in this way is used together with the second big hit state setting table set at step AKS401 or the first big hit state setting table set at step AKS403 to determine the second distribution. A value comparison process P_HANTEI2 is executed (step AKS405).

In the second sorting determination value comparison process P_HANTEI2, the data stored at the top address of the table is set as the start number data, the data stored at the next address is set as the number of processing data, and the start number data is initialized as the sorting result data. After that, the process of comparing the numerical data set as the comparison value and the sorting judgment value indicated by the stored data after the next address of the processing count data is performed in increasing order from the beginning side of the table address to the end side. Execution is allowed until the distribution judgment value exceeds the value. At this time, if the sorting judgment value is equal to or less than the comparison value, the sorting result data is updated by adding 1 to proceed to the next comparison. finish. Even if the number of comparisons corresponds to the number of processes data, if the sorting judgment value does not exceed the comparison value, the stored data after the next address can be used to repeat the process from the setting of the start number data and the number of processes data. . In the second sorting determination value comparison process P_HANTEI2 of step AKS405, the random number MR1-2 for the winning design, which is the stored value of the winning design buffer, is set as a comparison value, and the first big win state setting table or the second big win state setting is performed. The stored data of the table enables determination of the jackpot design value indicated by the distribution result data as the type of jackpot game state corresponding to the display result by the first special pattern display device 4A or the second special pattern display device 4B. 2nd distribution judgment value comparison processing P_HANTEI2 should just be executable also when determining a small hit design specified value by step AKS333 of special design information setting processing P_TZU_SET. In this case, the winning symbol random number MR1-2, which is the value stored in the winning symbol buffer, is set as a comparison value, and the data stored in the first small winning state setting table or the second small winning state setting table, The small hit designation value indicated by the distribution result data can be determined as the type of small win game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B.

When the second distribution determination value comparison process P_HANTEI2 of step AKS405 is completed, big hit information setting data is determined (step AKS406). The data for setting the jackpot information includes the jackpot information data designation table selected corresponding to the stored value of the performance state selection buffer, and the jackpot pattern designation value determined by the second sorting judgment value comparison process P_HANTEI2 of step AKS405. It suffices if the data set can be selected from a plurality of types of data sets prepared in advance using the data set. The effect state selection buffer should be able to set a stored value corresponding to the effect state after the end of the jackpot game state.

FIG. 10-24 is a diagram for explaining an example of use of the data configuration corresponding to the control of the jackpot game state with respect to the special symbol information setting process P_TZU_SET and the jackpot information data selection process P_TFVR_ZU. In step AKS322 of the special symbol information setting process P_TZU_SET, when the hit flag is the jackpot specified value, the jackpot information data selection process P_TFVR_ZU can be executed in step AKS326. In this jackpot information data selection process P_TFVR_ZU, the second jackpot state setting table whose address is set by step AKS401 or the first jackpot state setting table whose address is set by step AKS403 is used to perform the second distribution of step AKS405. By executing the determination value comparison process P_HANTEI2, it is possible to determine the jackpot symbol designation value. After that, in step AKS328 of the special pattern information setting process P_TZU_SET, the big hit information setting data read from the big hit information setting table corresponding to the big hit design specified value is transferred to the performance pattern information buffer, the fanfare display buffer, and the big hit end display buffer. can be transferred and stored. The effect pattern information buffer, the fanfare display buffer, and the big win end display buffer are provided in the effect pattern information area, and can store setting data when the game is controlled to the big win game state. Further, in step AKS330 of the special symbol information setting process P_TZU_SET, the maximum number of times of opening the big winning opening can be determined using the maximum number of times of opening the big winning opening corresponding to the specified value of the big winning opening.

In this way, the big-hit information data selection process P_TFVR_ZU makes it possible to determine the big-hit symbol designation value using the first big-hit state setting table or the second big-hit state setting table. The special pattern information setting process P_TZU_SET can set the stored values of the production pattern information buffer, the fanfare display buffer and the jackpot display buffer provided in the production pattern information area, and the number of times the big winning opening is opened corresponding to the jackpot pattern specified value. Make the maximum value determinable.

FIG. 10-24 (A1) shows a configuration example AKT41 of the first jackpot state setting table. In the first jackpot state setting table of the configuration example AKT41, the value 00 [H] corresponding to the jackpot design designation value "1" is stored at the head address 1AFD [H], and the number of processes is shown at the next address 1AFE [H]. A value of 0A[H] is stored. Then, the stored data after the address 1AFF[H] indicates the distribution determination values corresponding to the jackpot symbol designation values "1" to "10". The second distribution determination value comparison process P_HANTEI2 of step AKS405 corresponds to the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer when the first jackpot state setting table of the configuration example AKT41 is used. It is possible to determine one of the jackpot symbol designation values "1" to "10". For example, when the random number MR1-2 for the winning symbol is 00 [H] corresponding to the minimum value of the random number "0", the designated jackpot symbol value "1" is determined.

FIG. 10-24 (A2) shows a configuration example AKT42 of the second big hit state setting table. In the second jackpot state setting table of the configuration example AKT42, the value 0A [H] corresponding to the jackpot symbol designation value "11" is stored at the head address 1B09 [H], and the number of processes is shown at the next address 1B0A [H]. A value of 04[H] is stored. The stored data after the address 1B0B[H] indicate the distribution determination values corresponding to the jackpot symbol designation values "11" to "14". The second sorting determination value comparison process P_HANTEI2 of step AKS405 corresponds to the winning symbol random number MR1-2 indicated by the winning symbol buffer stored value when the second jackpot state setting table of the configuration example AKT42 is used. It is possible to determine one of the jackpot symbol designation values "11" to "14". For example, when the random number MR1-2 for the winning symbol is 00 [H] corresponding to the minimum value of the random number "0", the designated jackpot symbol value "11" is determined.

FIG. 10-24(B) shows a configuration example AKB41 of the effect symbol information area. The performance symbol information area of the configuration example AKB41 can store various data related to game control and performance control including variable display of performance symbols corresponding to the case of being controlled to the big win game state or the small win game state. This effect pattern information area includes a effect pattern information buffer at address F056 [H], a fanfare display buffer at address F057 [H], a jackpot end display buffer at address F058 [H], and a variation command at address F059 [H]. It includes a designated buffer, an address F05A[H] big winning mouth opening maximum value buffer, a small win fanfare display buffer at address F05F[H], and a small win ending display buffer at address F060[H]. .

FIG. 10-24(C) shows a determination example AKD01 of the maximum number of openings of the big winning opening. In step AKS330 of special pattern information setting processing P_TZU_SET, the maximum value of the number of times of opening the big winning opening corresponding to the jackpot design specified value determined by the second distribution judgment value comparison processing P_HANTEI2 is determined in step AKS405 of big hit information data selection processing P_TFVR_ZU. It is possible. In the example AKD01 for determining the maximum number of opening times of the big winning opening, the maximum number of opening the big winning opening corresponds to 02 [H] corresponding to "2", 04 [H] corresponding to "4", and "7". 07 [H] corresponding to ``10'' and 0A [H] corresponding to ``10''. In addition, the first jackpot state setting table of the configuration example AKT41 is used when the starting opening winning prize designation value is "1", and enables determination of one of the jackpot design designation values "1" to "10". . On the other hand, the second jackpot state setting table of the configuration example AKT42 is used when the starting opening winning prize designation value is "2", and can determine any of the jackpot design designation values "11" to "14". to On the other hand, in the example AKD01 for determining the maximum number of opening times of the big winning opening, the maximum number of opening the big winning opening is set to , 04[H] corresponding to "4" and 0A[H] corresponding to "10". On the other hand, in the example AKD01 for determining the maximum number of opening times of the big winning opening, in the case of 0A [H] to 0D [H] corresponding to the specified value of the jackpot design "11" to "14", the maximum number of opening the big winning opening is , 02 [H] corresponding to "2", 04 [H] corresponding to "4", 07 [H] corresponding to "7", and 0A [H] corresponding to "10". Either can be determined.

Thus, in the example AKD01 for determining the maximum number of opening times of the big winning opening, in the case of 00 [H] corresponding to the designated jackpot symbol value "1", the maximum number of opening opening times of the big winning opening is 04 [H] corresponding to "4". H]. This corresponds to the smaller "4" of "4" or "10", which is the maximum number of openings of the big winning opening that can be determined when the starting opening winning designation value is "1". The jackpot symbol designating value "1" can be determined when the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer is the minimum random number value "0". In addition, in the example AKD01 for determining the maximum number of opening times of the big winning opening, in the case of 0A [H] corresponding to the jackpot design value "11", the maximum number of opening the big winning opening is 02 [H] corresponding to "2". becomes. This is the smallest "2" out of the maximum number of openings of the big winning opening "2", "4", "7", and "10" that can be determined when the starting opening winning prize designation value is "2". corresponds to The jackpot symbol designating value "11" can be determined when the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer is the minimum random number value "0". Therefore, among the special symbol games in which the special symbols are variably displayed on the first special symbol display device 4A or the second special symbol display device 4B, the special symbol display result is a "big win". When the symbol random number MR1-2 is the minimum random number "0", the display result is not determined to be more advantageous than when the random number is other than the minimum random number. As a result, when the random numbers MR1-2 for the winning symbols are used as the first random numbers, it is possible to appropriately update the random numbers so as to prevent cheating due to defects in the first random numbers.

FIG. 10-25 is a diagram for explaining an example of use of the data configuration corresponding to the control of the small winning game state with respect to the special symbol information setting process P_TZU_SET and the like. When the hit flag is the small hit designated value in step AKS331 of the special design information setting process P_TZU_SET, step AKS333 enables determination of the small hit design designated value. In this case, if the start opening winning designation value is "1", the small winning design designated value is determined using the first small winning state setting table. On the other hand, if the start opening winning designation value is "2", the second small winning state setting table is used to determine the small winning symbol designated value. After that, at step AKS339 of the special symbol information setting process P_TZU_SET, the small hit effect specified value determined at step AKS338 is stored in the effect symbol information buffer. Then, in step AKS340 of the special pattern information setting process P_TZU_SET, the small hit information setting data read from the small hit information setting table corresponding to the small hit design specified value is stored in the small hit fanfare display buffer and the small hit ending display buffer. , can be transferred and stored. The production pattern information buffer, the small winning fanfare display buffer, and the small winning ending display buffer are provided in the production pattern information area shown in FIG. can be stored. Also, in step S112 of the special symbol process processing P_TPROC shown in FIG. 6, when the special symbol process code corresponds to 03 [H] and the small hit opening pre-processing P_TLFAN is executed, the work setting during the small hit opening To make it possible to determine the opening time and the number of opening times of a big winning opening by using a table or the like.

In this way, the special symbol information setting process P_TZU_SET makes it possible to determine the specified value of the small winning symbol using the first small winning state setting table or the second small winning state setting table. In addition, the special design information setting process P_TZU_SET can set the storage value of the production design information buffer provided in the production design information area, the small winning fanfare display buffer and the small winning ending display buffer. Furthermore, the small hit opening pre-processing P_TLFAN executed corresponding to being controlled to the small hitting gaming state can determine the opening time and the opening times of the big winning opening.

FIG. 10-25 (A1) shows a configuration example AKT43 of the first small hit state setting table. In the first small hit state setting table of the configuration example AKT43, the value 00 [H] corresponding to the small hit design specified value “1” is stored at the top address 1B0B [H], and the number of processes is stored at the next address 1B0C [H]. A value 01 [H] indicating is stored. Then, the stored data at the address 1B0D[H] indicates the distribution determination value corresponding to the small winning design designation value "1". The step AKS333 of the special symbol information setting process P_TZU_SET corresponds to the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer when the first small winning state setting table of the configuration example AKT43 is used. , can be determined only to the small hit symbol specified value "1". Therefore, when the random number MR1-2 for the winning symbol is 00 [H] corresponding to the minimum value of the random number "0", the small winning symbol designation value "1" is determined.

FIG. 10-25 (A2) shows a configuration example AKT44 of the second small hit state setting table. In the second small hit state setting table of the configuration example AKT44, the value 01 [H] corresponding to the small hit design specified value "2" is stored at the top address 1B0E [H], and the number of processes is stored at the next address 1B0F [H]. A value 06 [H] indicating is stored. Then, the stored data after the address 1B10 [H] show the sorting determination values corresponding to the small winning symbol designating values "2" to "7". The step AKS333 of the special symbol information setting process P_TZU_SET corresponds to the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer when the second small winning state setting table of the configuration example AKT44 is used. , It is possible to determine any of the small hit symbol designation values "2" to "7". For example, when the random number MR1-2 for the winning symbol is 00 [H] corresponding to the minimum value of the random number "0", the small winning symbol designating value "2" is determined.

FIG. 10-25(B) shows a determination example AKD02 of the big winning opening opening mode. In the small hit opening pre-processing P_TLFAN, it is possible to determine the large winning opening opening mode corresponding to the starting opening winning specified value. It is sufficient that the mode of opening the big winning opening can be determined from a plurality of modes in which the opening time and number of openings of the big winning opening are different. In the big winning opening opening mode determination example AKD02, the opening time is 36 [ms] and the number of times of opening is 15 [times]. Further, in the example AKD02 of determining the large winning opening opening mode, the opening time is 1600 [ms] and the number of times of opening is 1 [times], corresponding to the specified starting opening winning prize value "2". be.

In this way, the opening mode of the large winning opening in the small winning game state is the opening time and the number of openings of the large winning opening corresponding to the starting opening winning designated value, regardless of the value of the small winning symbol designated value. can be determined differently. The small winning symbol designating value can be determined corresponding to the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer. Then, if the specified value for the start opening winning prize is the same value, the case where the random number MR1-2 for the winning symbol is the minimum random number "0" and the case where it is other than the minimum random number are common big winnings. Mouth open mode is determined. Therefore, among the special symbol games that are variable display of special symbols in the first special symbol display device 4A or the second special symbol display device 4B, corresponding to the special symbol game in which the special symbol display result is "small hit", When the random number MR1-2 for the winning symbol is the minimum random number "0", the display result is not determined to be more advantageous than when the random number is other than the minimum random number. As a result, when the random numbers MR1-2 for the winning symbols are used as the first random numbers, it is possible to appropriately update the random numbers so as to prevent cheating due to defects in the first random numbers.

FIG. 10-26 is a flow chart showing an example of the variation pattern setting process P_TPATSET. The variation pattern setting process P_TPATSET is included in the process that can be called from the special symbol normal process P_TNORMAL shown in FIGS. When the CPU 103 executes the variation pattern setting process P_TPATSET, it loads a hit flag (step AKS361). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F032 [H]. At step AKS361, the win flag may be loaded by a transfer command for reading out the data stored at the specified address in the game work area of RAM102. Then, it is confirmed that the hit flag is not the jackpot designation value by an arithmetic jump instruction that can compare the hit flag and the determination value corresponding to the jackpot designation value (step AKS362).

In response to step AKS362, when the hit flag is the jackpot designated value (step AKS362; No), the jackpot pattern determination buffer is loaded (step AKS363). The jackpot symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F035[H]. At step AKS363, the jackpot pattern determination buffer may be loaded by a transfer command for reading out the data stored at the specified address in the game work area of RAM102. At this time, a state-specific jackpot selection table address is set by a transfer instruction for setting a pointer (step AKS364). The status-specific jackpot selection table address is the address of the status-specific jackpot selection table stored in the ROM 101 . After that, a hit time variation pattern type table selection process P_TPATA is executed (step AKS365). The variation pattern type table selection process P_TPATA at step AKS365 makes it possible to select the variation pattern type distribution table corresponding to the special figure display result "big hit".

When the hit flag is not the big hit designated value corresponding to step AKS362 (step AKS362; Yes), the hit flag and the determination value corresponding to the small hit designated value can be compared by an arithmetic jump instruction, the hit flag is not a small hit specified value (step AKS366). When the hit flag is the small hit designated value (step AKS366; No), the variable command designation buffer is set (step AKS367). The variable command designation buffer is provided in the performance symbol information area of the configuration example AKB41 shown in FIG. 10-24(B), and is assigned an address F059[H]. At step AKS367, 01 [H] may be stored in the variation command specification buffer by a transfer command for writing to the storage area of the specified address in the game work area of RAM 102 . Also, the small hit symbol determination buffer is loaded (step AKS368). The small hit symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned an address F036 [H]. In step AKS368, the small hit design determination buffer may be loaded by a transfer command for reading out the storage data of the specified address in the game work area of RAM102. At this time, a state-specific small hit selection table address is set by a transfer instruction for setting a pointer (step AKS369). The state-by-state small hit selection table address is the address of the state-by-state small hit selection table stored in the ROM 101 . After that, a hit variation pattern type table selection process P_TPATA is executed (step AKS370). The variation pattern type table selection process P_TPATA at step AKS370 makes it possible to select the variation pattern type distribution table corresponding to the special figure display result "small hit".

When the hit flag is not a small hit designated value corresponding to step AKS366 (step AKS366; Yes), the change pattern type table selection process P_TPATH at the time of losing is executed (step AKS371). Loss time fluctuation pattern type table selection process P_TPATH of step AKS371 corresponds to the special figure display result "losing", and enables selection of the fluctuation pattern type sorting table.

After steps AKS365, AKS370, and AKS371, the variation pattern type selection buffer with buffer number "0" is loaded (step AKS372). The variation pattern type selection buffer with buffer number "0" is the first variation pattern type selection buffer included in the first reservation storage buffer with buffer number "0" in the first special symbol reservation buffer, or the second special This is the second variation pattern type selection buffer included in the second reserved storage buffer with the buffer number "0" in the design reserved buffer. In step AKS372, after setting the address of the second variation pattern type selection buffer of the buffer number "0", start-up winning check processing is executed, and if the start-up winning designation value is "1", the buffer number After setting the address of the first variation pattern type selection buffer of "0", by the transfer command for reading the stored data of the set address, it is stored in the variation pattern type selection buffer of buffer number "0" It is sufficient if the random number MR3-3 for selecting the variation pattern type can be read.

When the random number MR3-3 for selecting the variation pattern type is read by step AKS372, variation pattern sorting table selection processing P_TPATTBL is executed (step AKS373). The variation pattern sorting table selection process P_TPATTBL of step AKS373 includes the variation pattern sorting table selected by any of steps AKS365, AKS370, and AKS371, and the random number MR3-3 for selecting the variation pattern type read out by step AKS372. , to enable selection of the fluctuation pattern distribution table.

After step AKS373, the fluctuation pattern buffer with buffer number "0" is loaded (step AKS374). The variation pattern buffer with the buffer number "0" is the first variation pattern buffer included in the first suspension storage buffer with the buffer number "0" in the first special symbol suspension buffer, or the second special symbol suspension buffer This is the second variation pattern buffer contained in the second reserved storage buffer with the buffer number "0". In step AKS374, after setting the address of the buffer for the second variation pattern of the buffer number "0", start-up winning check processing is executed, and if the start-up winning designation value is "1", the buffer number "0" ”, and then the random number for the variation pattern stored in the variation pattern buffer with buffer number “0” by the transfer command for reading the stored data at the set address. It is sufficient if MR3-4 can be read.

When the random number MR3-4 for the variation pattern is read in step AKS374, the second sorting determination value comparison process P_HANTEI2 is executed (step AKS375). The second sorting judgment value comparison process of step AKS375 uses the variation pattern sorting table selected by step AKS373 and the random number MR3-4 for the variation pattern read by step AKS374 to determine the variation pattern. to At this time, the variation pattern designating data corresponding to the determined variation pattern is stored in the effect symbol variation pattern buffer (step AKS376). The performance symbol variation pattern buffer is provided in the game work area of the RAM 102, and can store different variation pattern designation data corresponding to the determination result of the variation pattern.

Following step AKS376, a variable command transmission table is selected (step AKS377). At step AKS377, the variable command transmission table is made selectable using the variable command transmission table selection table and the stored values of the variable command designation buffer. As a result, for example, different variation command transmission tables may be selected depending on whether the special figure display result is "big win" or "minor win" or "losing". The variation command transmission table includes the number of processes, the upper byte of the design information specification command, the design information specification code reference specification value, the performance design specification command high byte, the performance design specification code reference specification value, the performance design variation command, It is configured to include table data indicating a reference designated value of the fluctuation pattern designated data. Thereafter, command set processing P_COM_SET is executed (step AKS378). The command set process P_COM_SET of step AKS378 makes it possible to transmit the symbol information designation command, the performance symbol designation command, and the performance symbol variation command using the variation command transmission table selected by step AKS377. By command set processing P_COM_SET of such step AKS378, it is possible to transmit from the main board 11 to the effect control board 12 the effect control command that becomes the command at the start of fluctuation.

When the transmission of the command at the start of variation is made possible by step AKS378, the special symbol variation time is set (step AKS379). In step AKS379, the special symbol variation time table and variation pattern designating data are used to execute the time data expansion process, thereby making it possible to set different special symbol variation times corresponding to the determination result of the variation pattern. Subsequently, a transfer instruction for setting a pointer is used to set the work table address after setting the variation pattern (step AKS380). The post-variation pattern setting work table address is the address of the post-variation pattern setting work table stored in the game data area of the ROM 101 . Next, the data set process P_DATASET is executed (step AKS381), and the fluctuation pattern setting process P_TPATSET ends. The data set processing P_DATASET of step AKS381 uses the work table after setting the variation pattern whose address is set by step AKS380, sets the special symbol process code to 01 [H] which is the special symbol variation processing specified value, and special symbol The value stored in the display buffer during fluctuation is set to 01 [H], which is the display data during special symbol fluctuation. In addition, the special symbol display update timer, the buffer for selecting the losing effect with the buffer number "0", the buffer for selecting the type of variation pattern with the buffer number "0", and the buffer for variation pattern with the buffer number "0" are cleared. can be initialized by At this time, different buffers and timers can be set and cleared by referring to different tables depending on whether the specified value for start-up winning is "1" or "2".

FIG. 10-27(A) is a flow chart showing an example of the hit variation pattern type table selection process P_TPATA. Hit time fluctuation pattern type table selection process P_TPATA is included in the process that can be called from the fluctuation pattern setting process P_TPATSET shown in FIG. It can be executed, and when the hit flag is a small hit designated value in step AKS366, it can be executed in step AKS370. When the CPU 103 executes the hit variation pattern type table selection process P_TPATA, it loads the effect state selection buffer (step AKS421). The effect state selection buffer is provided in the game work area of the RAM 102, and can set a stored value corresponding to the effect state after the end of the big win game state. At step AKS421, it is sufficient if the value stored in the effect state selection buffer can be read out by a transfer command for reading out the stored data at the specified address in the game work area of RAM102.

Following step AKS421, a variation pattern type selection table is determined (step AKS422). At step AKS422, the variation pattern type selection table can be determined using the state-based big hit selection table or the state-based small hit selection table and the stored value of the performance state selection buffer read out at step AKS421. The address of the state-by-state jackpot selection table is set by step AKS364 when the winning variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The address of the small hit selection table by state is set by step AKS369 when the hit time variation pattern type table selection process P_TPATA is executed at step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. . The state-based big win selection table and the state-based small win selection table are configured to include table data enabling determination of different variation pattern type selection tables corresponding to the stored values in the performance state selection buffer. Therefore, by step AKS422, it is possible to determine different variation pattern type selection tables corresponding to the stored values of the presentation state selection buffer depending on whether the special figure display result is a "big win" or a "minor win". .

When the variation pattern type selection table is determined by step AKS422, the winning design designation value is set (step AKS423). In step AKS423, the content loaded from the big win design determination buffer or the small win design determination buffer may be set as a processing target by transferring it to a processing register included in the internal register of CPU103. The big hit pattern determination buffer is loaded by step AKS363 when the winning variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The small hit pattern determination buffer is loaded by step AKS368 when the hit time fluctuation pattern type table selection process P_TPATA is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26. The value stored in the big-hit design determination buffer indicates the big-hit design specified value. The value stored in the small-hit design determination buffer indicates a small-hit design specified value. Using the hit symbol designation value set in this way together with the variation pattern type selection table determined in step AKS422, the sorting determination value comparison process P_HANTEI is executed (step AKS424).

The sorting determination value comparison process P_HANTE compares the numeric data set as the comparison value with the sorting determination value indicated by the table storage data, and compares the comparison values in increasing order from the beginning to the end of the table address. Execution is allowed until the distribution judgment value exceeds . At this time, if the distribution determination value is equal to or less than the comparison value, the process proceeds to the next comparison, and corresponding to the distribution determination value exceeding the comparison value, the data stored in the table can be read out as designated data. In the distribution judgment value comparison process P_HANTEI of step AKS424, the jackpot design value or the small hit design designation value is set as a comparison value, and the data stored in the variation pattern type selection table specifies the distribution judgment value that exceeds the comparison value. Data is read.

When the distribution judgment value comparison processing P_HANTEI of step AKS424 ends, the variation pattern type distribution table is determined (step AKS425), and the winning variation pattern type table selection processing P_TPATA ends. In step AKS425, by adding the specified data read by the distribution judgment value comparison process P_HANTEI in step AKS424 to the top address of the fluctuation pattern type distribution table, the pointer is pointed to the address of the fluctuation pattern type distribution table to be used. By setting to , it is possible to determine the fluctuation pattern type distribution table.

FIG. 10-27 (B1) shows a variation pattern classification table determination example AKD11 in which the special figure display result corresponds to "jackpot". When the special figure display result is "jackpot", in step AKS405 of the jackpot information data selection process P_TFVR_ZU shown in FIG. Any of the values 00[H] to 0D[H] corresponding to "14" can be determined. Hit time variation pattern type table selection process P_TPATA is, when executed in step AKS365 of variation pattern setting process P_TPATSET shown in FIG. A distribution table can be determined. In the variation pattern type distribution table determination example AKD11, it is possible to determine one of the variation pattern type distribution tables AKU01 to AKU03 corresponding to the values 00 [H] to 0D [H] indicating the jackpot design value.

FIG. 10-27 (B2) shows a variation pattern classification table determination example AKD12 corresponding to the special figure display result "small hit". When the special figure display result is "small hit", in step AKS333 of the special symbol information setting process P_TZU_SET shown in FIG. Any of [H] to 06[H] can be determined. Hit time variation pattern type table selection process P_TPATA is, when executed in step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. A classification distribution table can be determined. In the variation pattern type distribution table determination example AKD12, it is possible to determine either the variation pattern type distribution table AKU11 or AKU12 corresponding to 00 [H] to 06 [H] indicating the small winning symbol designation value.

FIG. 10-28(A) is a flow chart showing an example of the change pattern type table selection process P_TPATH at the time of failure. Loss time fluctuation pattern type table selection process P_TPATH is included in the process that can be called from the fluctuation pattern setting process P_TPATSET shown in FIG. can be executed with When the CPU 103 executes the change pattern type table selection process P_TPATH at the time of failure, the CPU 103 sets the failure selection table address by state by the transfer command for setting the pointer (step AKS441). The status-specific loss selection table address is the address of the first status-specific loss selection table or the second status-specific loss selection table stored in the game data area of the ROM 101 . At step AKS441, different addresses in the game data area can be designated in correspondence with the case where the start entry winning designation value is "1" and the case where it is "2". As a result, when the start-point winning designation value is "1", the address of the first state-by-state loss selection table can be set, and when the start-point winning designation value is "2", the second state-by-state loss selection can be set. The address of the table is configurable. Then, the effect state selection buffer is loaded (step AKS442). The effect state selection buffer is provided in the game work area of the RAM 102, and can set a stored value corresponding to the effect state after the end of the big win game state.

Following step AKS442, a reservation-by-hold loss effect distribution selection table is determined (step AKS443). In step AKS443, using the first state-by-state loss selection table or the second state-by-state loss selection table in which the address is set in step AKS441 and the stored value of the effect state selection buffer loaded in step AKS442, To make it possible to determine a failure performance distribution selection table. The first state-by-state loss selection table and the second state-by-state loss selection table are configured to include table data enabling determination of different retention-by-hold loss effect distribution selection tables corresponding to the stored values of the performance state selection buffer. It is In addition, the retention-by-hold loss effect distribution selection table is configured to include table data that enables determination of a different loss effect distribution table corresponding to the count value of the start winning prize storage counter. Therefore, according to step AKS443, depending on whether the specified value of starting opening winning prize is "1" or "2", a different losing effect distribution selection table for each hold is determined corresponding to the stored value of the effect state selection buffer. can do.

After step AKS443, the starting entry winning memory counter is loaded (step AKS444). The starting entry winning prize memory counter is the first starting entry winning prize memory counter when the starting entry winning designation value is "1" or the second starting entry winning prize memory counter when the starting entry winning designation value is "2". . In step AKS444, after setting the second starting opening winning memory counter address to the memory pointer, starting opening winning check processing is executed, and when the starting opening winning designation value is "1", the first starting opening winning memory counter address is set. After the address is set in the storage pointer, the count value of the first start winning prize storage counter or the second start winning prize storage counter can be obtained by a transfer command for reading out the stored data of the address set in the storage pointer. do it.

After step AKS444, a sorting determination value comparison process P_HANTEI is executed (step AKS445). In the distribution judgment value comparison process P_HANTEI of step AKS445, the count value of the first starting entrance winning prize storage counter or the second starting entrance winning prize storage counter acquired by step AKS444 is set as a comparison value, and the losing by hold determined by step AKS443 Designated data corresponding to a distribution determination value exceeding the comparison value is read out from the data stored in the effect distribution selection table.

When the distribution determination value comparison process P_HANTEI of step AKS445 is completed, a losing effect distribution table is determined (step AKS446). At step AKS446, the address of the losing effect distribution table to be used is set to the pointer by adding the specified data read by the distribution judgment value comparison process P_HANTEI of step AKS445 to the top address of the losing effect distribution table. By doing so, it is possible to determine the losing effect distribution table.

After step AKS446, the buffer for selecting a loss effect with buffer number "0" is loaded (step AKS447). The buffer number "0" for losing effect selection buffer is the first loss effect selection buffer included in the first reserved storage buffer for buffer number "0" in the first special symbol reserved buffer, or the second special symbol reserved buffer. This is the second losing effect selection buffer included in the second reserved storage buffer with the buffer number "0" in the buffer. In step AKS447, after setting the address of the second losing effect selection buffer of buffer number "0", when the starting opening winning prize specified value is "1" by starting opening winning prize check processing, buffer number "0" After setting the address of the first losing effect selection buffer, by the transfer command for reading the stored data of the set address, the losing effect selection buffer stored in the losing effect selection buffer of the buffer number "0" , as long as the random number MR3-2 can be read.

When the random number MR3-2 for selecting the loss effect is read out in step AKS447, the sorting determination value comparison process P_HANTEI is executed (step AKS448). The distribution determination value comparison process P_HANTEI of step AKS448 uses the losing effect distribution table determined by step AKS446 and the random number MR3-2 for selecting the losing effect read by step AKS447, and uses the fluctuation pattern type distribution table. allows you to determine the offset value of In this case, the random number MR3-2 for selecting the loss effect read out at step AKS447 is set as a comparison value, and the data stored in the loss effect distribution table determined at step AKS446 determines the distribution judgment value exceeding the comparison value. The offset value of the fluctuation pattern type sorting table indicated by the designated data corresponding to can be read.

When the distribution judgment value comparison process P_HANTEI of step AKS448 is completed, the fluctuation pattern type distribution table is determined (step AKS449), and the fluctuation pattern type table selection process P_TPATH at the time of failure is completed. In step AKS449, by adding the offset value indicated by the specified data read by the distribution judgment value comparison process P_HANTEI in step AKS448 to the top address of the variation pattern type distribution table, the variation pattern type distribution table to be used By setting the address of the pointer, it is possible to determine the fluctuation pattern type distribution table.

FIG. 10-28 (B1) shows a loss effect distribution table determination example AKD21 corresponding to the first special figure loss. The first special figure loss corresponds to the start entry winning designation value "1", and the special figure display result becomes "losing" in the special figure game using the first special figure by the first special symbol display device 4A. is the case. When the start opening winning designation value is "1", at step AKS444 of the change pattern type table selection process P_TPATH at the time of loss, it is possible to acquire the count value of the first starting opening winning storage counter. The count value of the first start opening winning memory counter indicates the first reserved memory number. Then, by the distribution judgment value comparison process P_HANTEI of step AKS445, the designated data corresponding to the count value of the first start winning prize storage counter is read, and the loss effect distribution table corresponding to the number of first pending storage is created in step AKS446. can decide. In the lost effect distribution table determination example AKD21, one of the lost effect distribution tables AKV01 to AKV04 can be determined corresponding to the first reserved storage numbers "0" to "3".

FIG. 10-28 (B2) shows a loss effect distribution table determination example AKD22 corresponding to the second special figure loss. The second special figure loss corresponds to the start entry winning designation value "2", and the special figure display result becomes "losing" in the special figure game using the second special figure by the second special symbol display device 4B. is the case. In the case where the specified value of the start opening winning prize is "2", the count value of the second starting opening winning prize counter can be acquired in step AKS444 of the change pattern type table selection process P_TPATH at the time of loss. The count value of the second start opening winning memory counter indicates the second reserved memory number. Then, by the distribution judgment value comparison process P_HANTEI of step AKS445, the specified data corresponding to the count value of the second start winning prize memory counter is read, and the losing effect distribution table corresponding to the second pending memory number is created in step AKS446. can decide. In the failure effect distribution table determination example AKD22, it is possible to determine only the common failure effect distribution table AKV11 corresponding to the second reserved storage numbers "0" to "3".

FIG. 10-28(C) shows a variation pattern type sorting table determination example AKD23 in the case of the losing effect sorting table AKV01. The losing effect distribution table AKV01 can be determined when the first reserved storage number is "0" in the losing effect distribution table determination example AKD21 when the start opening winning prize designation value is "1". When the start opening winning prize specified value is "1", in step AKS447 of the change pattern type table selection process P_TPATH at the time of loss, random number MR3- 2 can be read. Then, by the allocation determination value comparison process P_HANTEI of step AKS448, the specified data corresponding to the random number MR3-2 for selecting the loss effect is read, and the variation pattern type allocation table can be determined in step AKS449. In the variation pattern type distribution table determination example AKD23, one of the variation pattern type distribution tables AKU21 to AKU25 can be determined in correspondence with the random number MR3-2 for selecting the loss effect.

FIG. 10-29 is a diagram for explaining a configuration example of a fluctuation pattern classification table. The hit variation pattern type table selection process P_TPATA shown in FIG. 10-27 (A) is executed at step AKS365 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. 10-27 (B1) in the variation pattern type distribution table determination example AKD11 shown in FIG. Either can be determined. The hit variation pattern type table selection process P_TPATA shown in FIG. 10-27 (A) is executed at step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. In response to the value determination result, a plurality of variation pattern type sorting tables such as either the variation pattern type sorting table AKU11 or AKU12 in the variation pattern type sorting table determination example AKD12 shown in FIG. 10-27 (B2) Either of them can be determined. Step AKS449 of the change pattern type table selection process P_TPATH at the time of loss shown in FIG. Any one of a plurality of variation pattern type distribution tables, such as any one of AKU21 to AKU25, can be determined. Then, the fluctuation pattern sorting table selection process P_TPATTBL executed at step AKS373 of the fluctuation pattern setting process P_TPATSET shown in FIG. It is possible to select the variation pattern type by referring to the variation pattern type distribution table, and it is possible to select the variation pattern distribution table corresponding to the selection result.

FIG. 10-29(A) shows a configuration example of the fluctuation pattern classification table AKU01. The variation pattern type distribution table AKU01 is included in a plurality of variation pattern type distribution tables that can be determined in correspondence with the jackpot design value. The fluctuation pattern type sorting table AKU01 in FIG. 10-29 (A) corresponds to the random number MR3-3 for selecting the fluctuation pattern type, so that any one of the fluctuation pattern types CPA01 to CPA05 can be determined. Table data is configured.

FIG. 10-29 (B1) shows a configuration example of the fluctuation pattern classification table AKU11. The variation pattern type distribution table AKU11 is included in a plurality of variation pattern type distribution tables that can be determined corresponding to the small winning symbol designation value. The fluctuation pattern type sorting table AKU11 in FIG. 10-29 (B1) corresponds to all the fluctuation pattern type selection random numbers MR3-3, so that only the common fluctuation pattern type CPB01 can be determined. Data is configured.

FIG. 10-29 (B2) shows a configuration example of the fluctuation pattern classification table AKU12. The variation pattern type distribution table AKU12 is included in a plurality of variation pattern type distribution tables that can be determined corresponding to the small winning symbol designation value. The fluctuation pattern type sorting table AKU12 in FIG. 10-29 (B2) corresponds to all the fluctuation pattern type selection random numbers MR3-3, so that only the common fluctuation pattern type CPB02 can be determined. Data is configured.

FIG. 10-29 (C1) shows a configuration example of the fluctuation pattern classification table AKU21. The variation pattern type distribution table AKU21 is included in a plurality of variation pattern type distribution tables that can be determined in correspondence with the random number MR3-2 for selecting a failure effect. The fluctuation pattern type distribution table AKU21 in FIG. 10-29 (C1) corresponds to the random number MR3-3 for selecting the fluctuation pattern type, so that it can be determined to either the fluctuation pattern type CPC01 or CPC02. Table data is configured.

FIG. 10-29 (C2) shows a configuration example of the fluctuation pattern classification table AKU22. The variation pattern type distribution table AKU22 is included in a plurality of variation pattern type distribution tables that can be determined in correspondence with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type sorting table AKU22 in FIG. 10-29 (C2) corresponds to all the fluctuation pattern type selection random numbers MR3-3, so that only the common fluctuation pattern type CPC03 can be determined. Data is configured.

FIG. 10-29 (C3) shows a configuration example of the fluctuation pattern classification table AKU23. The variation pattern type distribution table AKU23 is included in a plurality of variation pattern type distribution tables that can be determined in correspondence with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type sorting table AKU23 in FIG. 10-29 (C3) corresponds to all the fluctuation pattern type selection random numbers MR3-3, so that only the common fluctuation pattern type CPC04 can be determined. Data is configured.

FIG. 10-29 (C4) shows a configuration example of the fluctuation pattern classification table AKU24. The fluctuation pattern type distribution table AKU24 is included in a plurality of fluctuation pattern type distribution tables that can be determined in correspondence with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type distribution table AKU24 in FIG. 10-29 (C4) corresponds to the random number MR3-3 for selecting the fluctuation pattern type, so that it can be determined as one of the fluctuation pattern types CPC05 to CPC07 Table data is configured.

FIG. 10-29 (C5) shows a configuration example of the fluctuation pattern classification table AKU25. The variation pattern type distribution table AKU25 is included in a plurality of variation pattern type distribution tables that can be determined in correspondence with the random number MR3-2 for selecting a losing effect. The fluctuation pattern type sorting table AKU25 in FIG. 10-29 (C5) corresponds to all the fluctuation pattern type selection random numbers MR3-3, so that only the common fluctuation pattern type CPC08 can be determined. Data is configured.

FIGS. 10-30 to 10-32 are diagrams for explaining configuration examples of variation pattern sorting tables that can be used corresponding to variation pattern types. In the fluctuation pattern sorting table selection process P_TPATTBL executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in FIG. Correspondingly, a variation pattern distribution table is selected. After that, the second distribution judgment value comparison process P_HANTEI2 of step AKS375 uses the random number MR3-4 for the fluctuation pattern read out by step AKS374 to make it possible to determine the fluctuation pattern by referring to the fluctuation pattern distribution table. .

FIG. 10-30 (A1) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPA01. The variation pattern type CPA01 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined corresponding to the jackpot design value. In the configuration example of FIG. 10-30 (A1), the variation pattern distribution table corresponds to the random number MR3-4 for the variation pattern, so that it can be determined to any of the variation patterns PA01 to PA03, PA51, and PA52. , where the table data is structured. In this way, for the variation pattern type CPA01, the distribution determination value is set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PA01 to PA03, PA51, and PA52 can be determined.

FIG. 10-30 (A2) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPA02. The variation pattern type CPA02 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined in correspondence with the jackpot design value. In the configuration example of FIG. 10-30 (A2), the variation pattern distribution table can be determined to be any of the variation patterns PA04 to PA11, PA21 to PA23, and PA54 corresponding to the random number MR3-4 for the variation pattern. The table data is structured as follows. Thus, for the variation pattern type CPA02, the distribution determination value is set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PA04 to PA11, PA21 to PA23, and PA54 can be determined.

FIG. 10-30 (A3) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPA03. The variation pattern type CPA03 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined corresponding to the jackpot design value. In the configuration example of FIG. 10-30 (A3), the variation pattern distribution table can be determined to be any of the variation patterns PA31 to PA38, PA24 to PA26, and PA55 corresponding to the random number MR3-4 for the variation pattern. The table data is structured as follows. Thus, for the variation pattern type CPA03, the distribution determination value is set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PA31 to PA38, PA24 to PA26, and PA55 can be determined.

FIG. 10-30 (A4) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPA04. The variation pattern type CPA04 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined corresponding to the jackpot design value. In the configuration example of FIG. 10-30 (A4), the fluctuation pattern distribution table corresponds to the random numbers MR3-4 for all fluctuation patterns, so that only the common fluctuation pattern PA41 can be determined. Table data is configured. Thus, for the variation pattern type CPA04, the distribution determination value is set by the storage data of the variation pattern distribution table so that only the variation pattern PA41 can be determined.

FIG. 10-30 (A5) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPA05. The variation pattern type CPA05 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU01 that can be determined corresponding to the jackpot design value. In the configuration example of FIG. 10-30 (A5), the fluctuation pattern distribution table corresponds to the random numbers MR3-4 for all fluctuation patterns, so that only the common fluctuation pattern PA42 can be determined. Table data is configured. Thus, for the variation pattern type CPA05, the distribution determination value is set by the storage data of the variation pattern distribution table so that it can be determined only for the variation pattern PA42.

FIG. 10-30 (B1) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPB01. The variation pattern type CPB01 can be determined corresponding to all the variation pattern type selection random numbers MR3-3 when using the variation pattern type distribution table AKU11 that can be determined corresponding to the small winning symbol designation value. . In the configuration example of FIG. 10-30 (B1), the fluctuation pattern distribution table corresponds to the random numbers MR3-4 for all fluctuation patterns, table data so that only the common fluctuation pattern PB01 can be determined is configured. In this way, for the variation pattern type CPB01, the distribution determination value is set according to the data stored in the variation pattern distribution table so that only the variation pattern PB01 can be determined.

FIG. 10-30 (B2) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPB02. Variation pattern type CPB02 can be determined corresponding to all variation pattern type selection random numbers MR3-3 when using the variation pattern type distribution table AKU12 that can be determined corresponding to the small winning symbol designation value. . In the configuration example of FIG. 10-30 (B2), the fluctuation pattern distribution table is such that the table data can be determined to be one of the fluctuation patterns PB11 to PB14 corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, for the variation pattern type CPB02, the distribution determination value is set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PB11 to PB14 can be determined.

FIG. 10-31(A) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC01. The variation pattern type CPC01 is a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when using the variation pattern type distribution table AKU21 that can be determined corresponding to the random number MR3-2 for selecting the losing effect. Decidable. In the configuration example of FIG. 10-31 (A), the fluctuation pattern distribution table corresponds to the random numbers MR3-4 for all fluctuation patterns, table data so that only the common fluctuation pattern PC01 can be determined is configured. In this way, for the variation pattern type CPC01, the distribution determination value is set according to the data stored in the variation pattern distribution table so that only the variation pattern PC01 can be determined.

FIG. 10-31(B) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC02. The variation pattern type CPC02 is a predetermined ratio corresponding to the random number MR3-3 for selecting the variation pattern type when the variation pattern type distribution table AKU21 that can be determined corresponding to the random number MR3-2 for selecting the losing effect is used. Decidable. In the configuration example of FIG. 10-31 (B), the variation pattern distribution table corresponds to the variation pattern random numbers MR3-4, and any of the variation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49 The table data is structured so that it can be determined whether In this way, the variation pattern type CPC02 can be determined by any one of the variation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49, and the distribution determination value is determined by the data stored in the variation pattern distribution table. set.

FIG. 10-31(C) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC03. The variation pattern type CPC03 corresponds to all the variation pattern type selection random numbers MR3-3 when using the variation pattern type distribution table AKU22 that can be determined corresponding to the random numbers MR3-2 for selecting the losing effect. Decidable. In the configuration example of FIG. 10-31 (C), the variation pattern distribution table is a table so that it can be determined to any one of the variation patterns PC11 to PC18 and PC101 corresponding to the random number MR3-4 for the variation pattern. Data is configured. In this way, the variation pattern type CPC03 has a distribution determination value set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PC11 to PC18 and PC101 can be determined.

FIG. 10-31(D) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC04. The variation pattern type CPC04 corresponds to all the variation pattern type selection random numbers MR3-3 when using the variation pattern type distribution table AKU23 that can be determined in correspondence with the random number MR3-2 for selecting the loss effect. Decidable. In the configuration example of FIG. 10-31 (D), the variation pattern distribution table is a table so that it can be determined to any one of the variation patterns PC19 to PC27 and PC102 corresponding to the random number MR3-4 for the variation pattern. Data is configured. In this way, the variation pattern type CPC04 has a distribution determination value set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PC19 to PC27 and PC102 can be determined.

FIG. 10-32(A) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC05. The variation pattern type CPC05 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when the variation pattern type distribution table AKU24 that can be determined corresponding to the random number MR3-2 for selecting the losing effect is used. can be determined by In the configuration example of FIG. 10-32 (A), the fluctuation pattern distribution table is such that the table data is such that it is possible to determine any one of the fluctuation patterns PC28 to PC43 corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, the variation pattern type CPC05 has a distribution determination value set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PC28 to PC43 can be determined.

FIG. 10-32(B) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC06. The variation pattern type CPC06 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when the variation pattern type distribution table AKU24 that can be determined corresponding to the random number MR3-2 for selecting the losing effect is used. is determinable by a second ratio different from . The second percentage is a percentage lower than the first percentage. In the configuration example of FIG. 10-32 (B), the fluctuation pattern distribution table is such that the table data can be determined to be any one of the fluctuation patterns PC44 to PC59 corresponding to the random number MR3-4 for the fluctuation pattern. It is configured. In this way, the variation pattern type CPC06 has a distribution determination value set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PC44 to PC59 can be determined.

FIG. 10-32(C) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC07. The variation pattern type CPC07 is the first ratio corresponding to the random number MR3-3 for selecting the variation pattern type when the variation pattern type distribution table AKU24 that can be determined corresponding to the random number MR3-2 for selecting the losing effect is used. and a third percentage different from the second percentage. The third percentage is a percentage lower than the first percentage and the second percentage. In the configuration example of FIG. 10-32 (C), the variation pattern distribution table is such that the table data can be determined to be any one of the variation patterns PC60 to PC75 corresponding to the random number MR3-4 for the variation pattern. It is configured. In this way, the variation pattern type CPC07 has a distribution determination value set according to the data stored in the variation pattern distribution table so that any one of the variation patterns PC60 to PC75 can be determined.

FIG. 10-32(D) shows a configuration example of a variation pattern sorting table corresponding to the variation pattern type CPC08. The variation pattern type CPC08 corresponds to all the variation pattern type selection random numbers MR3-3 when using the variation pattern type distribution table AKU25 that can be determined in correspondence with the random number MR3-2 for selecting the losing effect. Decidable. In the configuration example of FIG. 10-32 (D), the fluctuation pattern distribution table corresponds to the random numbers MR3-4 for all fluctuation patterns, table data so that only the common fluctuation pattern PC02 can be determined is configured. In this way, for the variation pattern type CPC08, the distribution determination value is set according to the data stored in the variation pattern distribution table so that only the variation pattern PC02 can be determined.

FIG. 10-33(A) is a flow chart showing an example of the normal symbol process processing P_FPROC. The normal symbol process process P_FPROC is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. 5, and can be executed at step AKS59 each time a timer interrupt occurs. When the normal symbol process P_FPROC is executed, the CPU 103 sets a gate switch passage corresponding flag (step AKS501). The gate switch passage corresponding flag setting causes the state of the gate switch 21 included in the switch-on buffer to be reflected in the flag register of the CPU 103 by executing a logic operation instruction or the like. At this time, the ON state of the zero flag in the flag register indicates that the gate switch passage flag is OFF. On the other hand, the fact that the zero flag is off indicates that the gate switch passage corresponding flag is on. After that, it is determined whether or not the gate switch passage corresponding flag is ON (step AKS502). When the gate switch passage corresponding flag is ON (step AKS502; Yes), gate switch passage processing P_FZU_ON is executed (step AKS503).

When the gate switch passage correspondence flag is off corresponding to step AKS502 (step AKS502; No), after the gate switch passage processing P_FZU_ON in step AKS503, the normal symbol process processing jump table is transferred by the transfer instruction to set the pointer. set (step AKS504). The normal symbol process processing jump table is an address management table that enables selection and execution of processing corresponding to the read value of the normal symbol process code. Normal pattern process code, corresponding to the progress of the game control in the pachinko gaming machine 1, it is possible to update setting to any of 00 [H] ~ 04 [H], also referred to as normal pattern process code.

Following step AKS504, the normal design process code is loaded by a transfer command for reading stored data (step AKS505). Next, by executing the 2-byte data selection process P_ABXEXEC (step AKS506), the address of the process selected corresponding to the normal design process code is acquired. The address obtained at this time is set in the pointer. After that, by executing the process pointed to by the pointer by the subroutine call command (step AKS507), the process selected corresponding to the normal symbol process code can be executed. When the process selected in this way ends and returns to normal design process processing P_FPROC by a return command, this normal design process processing P_FPROC also ends and returns to timer interrupt processing P_PCT for game control by a return command.

FIG. 10-33(B) shows a configuration example of the configuration example AKT51 of the normal symbol process processing jump table used in the normal symbol process processing P_FPROC. The normal symbol process processing jump table includes table data that can set the address of the process selected in correspondence with the normal symbol process code to the internal register of the CPU 103 used as a pointer. The normal symbol process processing jump table of the configuration example AKT51 includes normal symbol normal processing P_FNORM when the normal symbol process code is 00 [H] and normal symbol variation processing P_FSCRL when the normal symbol process code is 01 [H]. And, the normal design stop processing P_FSTOP when the normal design process code is 02 [H], the normal electric accessory operation pre-processing P_FINT when the normal design process code is 03 [H], and the normal design process code 04 [H] includes table data that can set the address value corresponding to the normal electric accessary product operation process P_FOPEN in the pointer.

The normal design normal process P_FNORM determines whether or not to start the normal design game based on the presence or absence of the stored normal design reservation information, determines the fixed normal design to be stopped and displayed in the variable display of the normal design, and normal To determine a normal pattern variation pattern which is a pattern variation pattern. The normal design fluctuation process P_FSCRL measures the elapsed time after the normal design starts to change in the normal design display device 20, and can judge whether the normal design fluctuation time corresponding to the normal design fluctuation pattern has passed. to The normal design stop process P_FSTOP measures the elapsed time after the normal design stops changing on the normal design display device 20, and makes it possible to determine whether or not the normal design stop time has passed. To enable renewal of a normal pattern process code and various settings corresponding to a normal pattern display result when a normal pattern stop time elapses. In this embodiment, it suffices if the normal symbol process code can be updated to 03[H] corresponding to all the normal symbol display results. The normal electric role product operation preprocessing P_FINT and the normal electric role product operation process P_FOPEN are performed by controlling the normal electric role product solenoid 81 to open the second start winning opening formed in the variable winning ball device 6B from the closed state to the open state. This is the processing for making it changeable.

FIG. 10-34 is a diagram for explaining an example of use of a data structure relating to control of a normal pattern game that is variable display of normal patterns. For example, the normal design process process P_FPROC shown in FIG. 10-33(A) uses the normal design process code loaded by step AKS505, and by executing the 2-byte data selection process P_ABXEXEC of step AKS506, in step AKS507 To enable execution of processing selected corresponding to a normal pattern process code. The normal design process code is provided in the normal design control data area, and the stored value can be updated corresponding to the control state of the normal design game and the second start winning opening. The gate switch passing process P_FZU_ON of step AKS503 is capable of reading the random number MR2-1 for the normal per-symbol pattern. Store and save. The normal symbol-per-symbol buffer is provided in the normal symbol-per-symbol buffer area, and can store numerical data indicating the value of the read random number MR2-1 until the number of normal symbol reserved storage reaches the upper limit. . Thus, normal design process processing P_FPROC and processing that can be executed in the normal design process processing P_FPROC is normally variable display of the design using the stored data in the normal design control data area and the buffer area for the design per normal design. Allows control over the Universal Map game.

FIG. 10-34(A) shows a configuration example AKB51 of the normal symbol control data area. The normal symbol control data area of the configuration example AKB51 includes normal symbol process processing P_FPROC, such as the normal symbol game, which is a variable display of normal symbols, and the closed state and open state of the second start winning opening that can be controlled based on the display result. It is possible to store various data related to control by, for example. This normal design control data area includes a normal design process code at address F03E [H], a gate passage storage counter at address F03F [H], a normal design buffer at address F040 [H], and a normal design at address F041 [H]. The electric accessory release pattern timer, the normal electric accessory release pointer at address F043 [H], the normal electric accessory winning number counter at address F045 [H], and the normal symbol process timer at address F04A [H]. contains.

The normal design process code can designate the process selected in the normal design process P_FPROC. The gate passing storage counter can store a count value corresponding to the number of game balls detected by the gate switch 21 . The normal design buffer can store data corresponding to the normal design designation value. The normal design designation value is a designation value corresponding to the fixed normal design which is the display result of the variable display of the normal design by the normal design display device 20, and includes the design designation value per normal design. The normal per-symbol design designation value is a designation value corresponding to the fixed normal design displayed by the normal design display device 20 when the display result is "general per design" in the variable display of the normal design. The normal electric accessory opening pattern timer can store a time value corresponding to the remaining time for controlling the second start winning opening to the open state. The normal electric accessory opening pointer can specify the storage address of the normal electric accessory opening pattern table in which the time for controlling the second start winning opening to be opened is set. The normal electric accessory winning number counter can store a count value corresponding to the number of game balls detected by the second starting port switch 22B. The normal design process timer can store a clock value corresponding to the control time by the normal design process processing P_FPROC.

FIG. 10-34(B) shows a configuration example AKB52 of the normal symbol-per-symbol buffer area. The normal symbol-per-symbol buffer area of the configuration example AKB52 can store numerical data indicating the value of the normal symbol-per-symbol random number MR2-1 read out when the game ball passes through the passage gate 41. be. This normal per-symbol buffer area includes normal per-symbol buffer numbers "1" to "4" of addresses F046[H] to F049[H]. The normal symbol-per-symbol buffer numbers "1" to "4" are normal symbol-per-symbol buffers to which the buffer numbers "1" to "4" are assigned, and the random number MR2 in the order in which the game balls pass through the passage gate 41. A value of -1 can be stored. As a result, the stored information in the normal symbol-per-symbol buffer indicates the number of game balls that have passed through the passage gate 41, and also indicates the value of the random number MR2-1 read corresponding to each passage.

FIG. 10-35 is a flowchart illustrating an example of gate switch pass processing P_FZU_ON. Gate switch passage processing P_FZU_ON is included in the processing that can be called from normal symbol process processing P_FPROC shown in FIG. is executable. When the CPU 103 executes the gate switch passing process P_FZU_ON, the CPU 103 sets a gate passing storage counter address by a transfer instruction for setting a pointer (step AKS601). The gate passage memory counter address is the address of the gate passage memory counter provided in the game work area of the RAM 102 . Subsequently, a transfer instruction for reading the stored data at the address indicated by the pointer loads the gate passing storage counter (step AKS602).

After step AKS602, it is determined whether or not the count value of the gate passage storage counter is equal to or greater than the counter maximum value (step AKS603). For example, if the value loaded in step AKS602 and the maximum counter value such as "4" can be compared and returned by a comparison return instruction, if the counter maximum value is exceeded (step AKS603; Yes), the gate switch passage processing P_FZU_ON is executed. It ends and returns to normal design process processing P_FPROC. On the other hand, if it is less than the counter maximum value (step AKS603; No), the count value of the gate passage memory counter is updated by adding 1 (step AKS604). In this case, an arithmetic logical operation instruction for incrementing the stored data at the address pointed to by the pointer can update the count value of the gate passing storage counter by adding one.

After step AKS604, a buffer address for normal design per design is set by a transfer command for setting a pointer (step AKS605). In this case, the address of the normal symbol-per-symbol buffer of the buffer number "0" provided in the game work area of the RAM 102 is set in the pointer. Then, the value loaded in step AKS 602 is added to the stored value of the pointer. As a result, in the normal-symbol-per-symbol buffer area, the address of the normal-symbol-per-symbol buffer for storing the normal-symbol-per-symbol random number MR2-1 can be set in the pointer. Following this, the normal symbol per symbol random number counter is stored (step AKS606), and the gate switch passing process P_FZU_ON ends. In step AKS606, the value read out by designating the lower address of the random number counter per symbol in the game work area of the RAM 102 is transferred to the memory area of the address pointed by the pointer. It is sufficient if the value of the random number MR2-1 obtained from the counter can be stored in the normal symbol-per-symbol buffer.

FIG. 10-36 is a flow chart showing an example of normal symbol normal processing P_FNORM. The normal symbol normal process P_FNORM is included in the process that can be called from the normal symbol process process P_FPROC shown in FIG. 10-33(A). , can be executed in step AKS507. The CPU 103 loads the gate passage storage counter when the normal symbol normal process P_FNORM is executed (step AKS621). In this case, the count value of the gate pass storage counter can be acquired by a transfer command for setting the value read by designating the lower address of the gate pass storage counter in the game work area of the RAM 102 to the internal register of the CPU 103. . Then, it is determined whether or not the count value of the gate passage memory counter is "0" by an operation return instruction for returning the process when the second zero flag in the flag register of the CPU 103 is ON (step AKS622). At this time, if the second zero flag is ON state, corresponding to the fact that the count value of the gate passage storage counter is "0" (step AKS622; Yes), the normal design normal process P_FNORM ends, normal design process Return to process P_FPROC.

When the count value of the gate passing storage counter is not "0" corresponding to step AKS622 (step AKS622; No), the normal symbol per symbol setting table address is set by the transfer command for setting the pointer ( step AKS 623). The normal per-symbol design setting table address is the address of the normal per-symbol design setting table stored in the game data area of the ROM 101 . After that, the normal symbol-per-symbol buffer of the buffer number "1" is loaded (step AKS624). In step AKS624, the lower address of the normal symbol-per-symbol buffer in the game work area of the RAM 102 is specified and the read value is set in the internal register of the CPU 103 by a transfer command for setting the buffer number "1". 1" for the normal symbol-per-symbol random number MR2-1 stored in the normal symbol-per-symbol buffer.

When the normal symbol per symbol random number MR2-1 is read by step AKS624, the second sorting determination value comparison process P_HANTEI2 is executed (step AKS625). In the second sorting determination value comparison process P_HANTEI2 of step AKS625, the value of the random number MR2-1 read out in step AKS624 is set as a comparison value, and the address is set in step AKS623. , The normal symbol-per-symbol designated value indicated by the distribution result data can be determined as the display result by the normal symbol display device 20. - 特許庁When the normal per-symbol design value is determined by the second sorting determination value comparison process P_HANTEI2 of step AKS625, the normal design-per-symbol design value is stored in the normal design buffer (step AKS626). The normal design buffer is provided in the normal design control data area shown in FIG. 10-34(A), and is assigned an address F040[H]. At step AKS626, the normal symbol-per-symbol designating value may be stored by a transfer command for writing to the memory area of the designated address in the game work area of the RAM102.

After step AKS626, 1 is subtracted from the gate passage memory counter (step AKS627). Then, the normal symbol-per-symbol buffer is shifted (step AKS628). In this case, in the normal-symbol-per-symbol buffer area provided in the game work area of the RAM 102, the address of the normal-symbol-per-symbol buffer of the buffer number "2" is set to the pointer specifying the transfer source. Also, the address of the normal symbol-per-symbol buffer with the buffer number "1" is set in the buffer pointer that designates the transfer destination. Further, the number of times of transfer corresponding to the data size of the normal symbol per symbol buffer area is set. After that, the stored contents of the buffer for the symbol per normal symbol may be sequentially transferred and shifted by a block transfer command. At this time, the normal symbol per symbol buffer of buffer number "4" is cleared to initialize the stored contents.

After step AKS628, the first normal design variation pattern distribution table address is set by a transfer command for setting a pointer (step AKS629). The first normal symbol variation pattern distribution table address is the address of the first normal symbol variation pattern distribution table stored in the game data area of the ROM 101 . Also, by the time saving check process, it is confirmed that the time saving function flag is not the time saving operation specified value (step AKS630). At this time, if the time saving function flag is the time saving operation specified value (step AKS630; No), the second normal symbol variation pattern distribution table address is set by the transfer command for setting the pointer (step AKS631). The second normal symbol variation pattern distribution table address is the address of the second normal symbol variation pattern distribution table stored in the game data area of the ROM 101 .

When the time saving function flag is not the time saving operation specified value corresponding to step AKS630 (step AKS630; Yes), after step AKS631, the RS3 software latch random number register is loaded (step AKS632). In this case, the stored value read by designating the address of the RS3 soft latch random number register in the function control register area, by the transfer instruction for setting the internal register of the CPU103, the random number MR3-1 for normal symbol variation pattern It should be enabled as Then, a second allocation determination value comparison process P_HANTEI2 is executed (step AKS633). 2nd distribution decision value comparison processing P_HANTEI2 of step AKS633, the value of random number MR3-1 which is read with step AKS632 is set as comparison value, 1st normal design fluctuation pattern distribution table whose address is set with step AKS629 or step AKS631 By the storage data of the second normal symbol variation pattern distribution table whose address is set by, the normal symbol variation pattern indicated by the distribution result data can be determined.

When the normal symbol variation pattern is determined by the second distribution determination value comparison process P_HANTEI2 of step AKS633, the normal symbol variation time corresponding to the normal symbol variation pattern is set (step AKS634). In step AKS634, by executing the time data expansion process using the normal symbol variation time table and the normal symbol variation pattern designation data, the normal symbol variation time corresponding to the determination result of the normal symbol variation pattern can be set. do. Subsequently, a transfer instruction for setting a pointer is used to set a work table address at the time of normal design fluctuation (step AKS635). The normal design fluctuation time work table address is the address of the normal design fluctuation time work table stored in the game data area of the ROM 101 . Next, the data set process P_DATASET is executed (step AKS636), and the normal design normal process P_FNORM ends. Data set processing P_DATASET of step AKS636 uses the work table at the time of normal design fluctuation whose address is set by step AKS635, sets the normal design process code to 01 [H] which is the designated value for normal design fluctuation processing, and normal design The value stored in the display buffer during fluctuation is set to 01 [H], which is the display data during normal symbol fluctuation. In addition, initialization is made possible by clearing the normal symbol display update timer.

FIG. 10-37 is a diagram for explaining an example of use of the data structure relating to normal symbol normal processing P_FNORM. In the normal symbol normal process P_FNORM, the normal symbol per symbol setting table whose address is set by step AKS623 is used to execute the second sorting determination value comparison process P_HANTEI2 of step AKS625, thereby setting the normal symbol per symbol designation value. Make it determinable. Also, using the first normal design variation pattern distribution table address set by step AKS629 or the second normal design variation pattern distribution table address set by step AKS631, the second distribution determination value comparison process P_HANTEI2 of step AKS633 By executing, it is possible to determine the normal symbol variation pattern. In step AKS634, using the normal symbol variation time table, it is possible to set the normal symbol variation time corresponding to the determination result of the normal symbol variation pattern. Also, in step AKS507 of the normal symbol process processing P_FPROC shown in FIG. , using a work setting table or the like at the time of normal electric accessory operation, it is possible to determine the opening time of the ordinary electric accessory provided corresponding to the second start winning opening.

In this way, the normal design normal process P_FNORM makes it possible to determine the design value per normal design using the normal per design design setting table. Also, the normal design normal process P_FNORM makes it possible to determine the normal design variation pattern using the first normal design variation pattern distribution table or the second normal design variation pattern distribution table. Furthermore, the normal design normal process P_FNORM makes it possible to determine the normal design fluctuation time using the normal design fluctuation time table. Ordinary electric auditors operation pre-processing P_FINT executed corresponding to the execution result of the general figure game can determine the opening time of ordinary electric auditors.

FIG. 10-37(A) shows a configuration example AKT61 of the normal symbol-per-symbol setting table. In the normal symbol-per-symbol setting table of the configuration example AKT61, the value 00 [H] corresponding to the first normal per-symbol design value is stored at the top address 1B54 [H], and the number of processes is stored at the next address 1B55 [H]. The value 03 [H] indicated is stored. Then, the stored data after the address 1B56 [H] show the distribution determination values corresponding to the first to third normal per-symbol design designation values. The second sorting determination value comparison process P_HANTEI2 of step AKS625 is, when the normal symbol-per-symbol setting table of the configuration example AKT61 is used, the first to third normal symbol-per-symbol random numbers MR2-1. It is possible to determine one of the normal symbol per symbol designation values. In the configuration example AKT61, the first normal per-symbol design value is 00 [H], the second normal per-symbol design value is 01 [H], and the third normal per-symbol design value is 02 [H]. is. For example, when the normal per-symbol random number MR2-1 is 00 [H] corresponding to the minimum value of the random number "0", the first normal per-symbol designating value is determined.

FIG. 10-37 (B1) shows a configuration example AKT62 of the first normal symbol variation pattern distribution table. In the first normal symbol variation pattern distribution table of the configuration example AKT62, the value 00 [H] corresponding to the specified value of the normal symbol variation pattern FPZ1 is stored at the top address 1B59 [H], and the number of processes is stored at the next address 1B5A [H]. A value of 04 [H] is stored. Then, the stored data after the address 1B5B[H] indicates the distribution determination value corresponding to the normal pattern variation patterns FPZ1 to FPZ4. 2nd distribution decision value comparison processing P_HANTEI2 of step AKS633, when the 1st normal design fluctuation pattern distribution table of configuration example AKT62 is used, corresponds to random number MR3-1 for normal design fluctuation pattern, normal design fluctuation pattern Any one of FPZ1 to FPZ4 can be determined.

FIG. 10-37 (B2) shows a configuration example AKT63 of the second normal symbol variation pattern distribution table. In the second normal symbol variation pattern distribution table of the configuration example AKT63, the value 04 [H] corresponding to the specified value of the normal symbol variation pattern FPZ5 is stored at the top address 1B5F [H], and the number of processes is stored at the next address 1B60 [H]. A value of 04 [H] is stored. The stored data after the address 1B61 [H] indicates the distribution determination values corresponding to the normal pattern variation patterns FPZ5 to FPZ8. 2nd distribution decision value comparison processing P_HANTEI2 of step AKS633, when the 2nd normal design fluctuation pattern distribution table of configuration example AKT63 is used, corresponds to random number MR3-1 for normal design fluctuation pattern, normal design fluctuation pattern Any one of FPZ5 to FPZ8 can be determined.

FIG. 10-37(C) shows a normal symbol variation time determination example AKD61. In the determination example AKD61, the normal design fluctuation time is determined to be 1000 [ms] corresponding to the normal design fluctuation patterns FZP1 to FZP4, and the normal design fluctuation time is set to 100 [ms] corresponding to the normal design fluctuation patterns FZP5 to FZP8. It is determined. In step AKS634, the normal design fluctuation time corresponding to the normal design fluctuation pattern determined by the second distribution determination value comparison process P_HANTEI2 of step AKS633 is set. The normal symbol variation patterns FZP1 to FZP4 can be determined using the first normal symbol variation pattern distribution table of the configuration example AKT61 when the time saving function flag is off. The normal symbol variation patterns FZP5 to FZP8 can be determined using the second normal symbol variation pattern distribution table of the configuration example AKT62 when the time saving function flag is on. As a result, the normal pattern variation time, which is the variable display time of normal patterns, can be set to be shorter when the time reduction control is performed than when the time reduction control is not performed.

FIG. 10-37(D) shows a normal electric accessory opening time determination example AKD62. In normal electric auditors operation pre-processing P_FINT, it is possible to determine the normal electric auditors opening time corresponding to the time saving operation specified value and the normal per symbol symbol specified value. The normal electric accessory opening time is the value 00 [H] corresponding to the "x" indicating that the time saving operation specified value is not in the time saving state, and the design value 00 [H] to 02 [ H] is determined to be 16 ms. On the other hand, the normal electric accessary product operating time is the value 01 [H] corresponding to the value 01 [H] corresponding to the time saving operation specified value indicating that the time saving state is in the time saving state. ] to 02[H], it is determined to be 5000 ms.

In this way, the normal electric accessory opening time can be determined at different times corresponding to the time saving operation designated value, regardless of which value the normal per-symbol design value is. The normal per-symbol designated value can be determined corresponding to the normal per-symbol random number MR2-1 read out from the normal per-symbol buffer. And if the time saving operation specified value is the same value, the normal normal that is common in the case where the random number MR2-1 for the symbol per normal symbol is the minimum random number "0" and the case other than the minimum random number Determined by the electric accessory operating time. Therefore, when the random number MR2-1 for the symbol per normal symbol is the minimum random number "0" corresponding to the special symbol game which is the variable display of the normal symbol on the normal symbol display device 20, the random number other than the minimum value is not determined to be a more favorable display result than if . As a result, when the random number MR2-1 for normal symbol-per-symbol is used as the second random number, it is possible to update the random number appropriately so as to prevent cheating due to the defect of the second random number.

In the game control microcomputer 100 shown in FIG. 10-1, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B generate random numbers MR1- 1, random number MR3-2 for selection of loss effect, random number MR3-3 for selection of variation pattern type, random number MR3-4 for variation pattern, random number MR3-1 for normal symbol variation pattern, numerical value indicating each value Data can be updated. In addition, when the CPU 103 executes the random number update process P_RANDOM shown in FIG. 10-12, among the random numbers included in the game random numbers, the random number MR1-2 for the winning symbol and the initial value for the winning symbol are obtained. It is possible to update numerical data indicating the respective values of the random number MR1-3, the normal per-symbol random number MR2-1, and the normal per-symbol-per-symbol initial value random number MR2-2.

In step AKS248 of the special symbol normal process shown in FIG. 10-18, when the special symbol determination process P_TDECISION shown in FIG. By the symbol small hit determination process, it becomes possible to determine whether or not the special symbol display result is a "big hit" or a "small hit" using the random number MR1-1 for special symbol determination. Then, in step AKS308 of the special symbol determination process P_TDECISION, when the special symbol information setting process P_TZU_SET shown in FIG. Using the random numbers MR1-2, it becomes possible to determine the big hit design designated value and the small hit design designated value corresponding to the fixed special design which is the display result of the special design. Also, when the second distribution determination value comparison process P_HANTEIS is executed at step AKS625 of the normal symbol normal process shown in FIG. It becomes possible to determine the design value per normal design corresponding to the determined normal design as the display result. The jackpot design specified value determined using the random number MR1-2 for the winning design is determined in step AKS330 of the special design information setting process P_TZU_SET, and the maximum number of times of opening the big winning opening shown in FIG. 10-24 (C) is determined. As in example AKD01, the maximum number of openings of the big winning opening can be set. The normal symbol-per-symbol designated value determined using the normal per-symbol random number MR2-1 is determined by the normal symbol process code in step AKS507 of the normal symbol process process P_FPROC shown in FIG. 10-33(A). 03 [H] when the normal electric role product operation preprocessing P_FINT is executed, like the normal electric role product opening time determination example AKD62 shown in FIG. 10-37 (D), the normal electric role Make it possible to set the opening time of objects. Therefore, the winning symbol random numbers MR1-2 are used for determining the display result by the first special symbol display device 4A and the second special symbol display device 4B, and the kind of big win game state that is advantageous for the player can be set. do. The normal symbol-per-symbol random number MR2-1 is used to determine the display result of the normal symbol display device 20, and is used to change the state in which the game ball easily passes through the second start winning opening serving as the starting area. Make it configurable.

In this way, it is possible to execute processing related to game control using random numbers that become various game random numbers. The random number MR2-1 for the normal per symbol pattern is called by the random number update process P_RANDOM shown in FIG. can be updated in Here, the random number MR2-1 for normal symbol per symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199". The total number of numbers is prime. Therefore, at least one of the first random number value and the second random number value that can be updated by the common update process is a prime number in total within the update range. In this way, the shared update process prevents an increase in program capacity, and by keeping the total number of random numbers included in the update range to be prime numbers, it is possible to suppress the synchronization of random numbers and enable appropriate random number updates. Become.

The random number MR1-2 for winning symbols, which is the first random number, has an update range of "0" to "199", and the total number of random numbers included in the update range is "200". The total number of included random numbers is non-prime. The random number MR1-2 for the winning pattern is used to determine the designated value of the big-hit design in the finalized special design, and it is determined whether or not the variable probability state occurs after the end of the state of the big-hit game, corresponding to the designated value of the big-hit design. In some cases. In this case, the determination ratio of the jackpot symbol designation value corresponds to the probability variable entry rate, which is the ratio controlled to the probability variable state. The probability variable entry rate is included in the important specifications of the pachinko game machine 1, and it is desirable to set it to a value that is clearly recognizable. However, if the total number of random numbers included in the update range of the random numbers MR1-2 for the winning symbols is a prime number, the denominator of the probability variable entry rate is a prime number, and it is difficult to express it as a percentage. It may be difficult to recognize the rate. Therefore, among the random number MR1-2 for the winning symbol and the random number MR2-1 for the normal symbol per symbol that can be updated by the common update process, the random number MR2-1 for the normal symbol per symbol is a random number included in the update range. While the total number of numerical values is a prime number, the random numbers MR1-2 for winning symbols may have a non-prime total number included in the update range. As a result, it is possible to appropriately update the random number so that the specification of the pachinko game machine 1 can be clearly recognized while suppressing the synchronous occurrence of the random number.

As for the random numbers MR1-2 for winning symbols, which are the first random numbers, the total number of random numbers included in the update range may be a prime number. This makes it possible to more reliably suppress synchronous generation of random numbers that can be updated by a common update process, and to appropriately update random numbers.

In the random number update process P_RANDOM shown in FIG. 10-12, steps AKS61 to AKS64 can update the random number MR1-2 as the first random value, and steps AKS65 to AKS68 can update the random number MR2-1 as the second random value. can be updated. The random number update process P_RANDOM stores the random number MR1-2 as the first random value and the random number MR2-1 as the second random value in the HL register, B register, and DE register of the CPU 103, which are common internal storage means. can be updated using In this manner, the first random number value and the second random number value are stably updated using the common internal storage means, so that the random number value can be appropriately updated.

The CPU 103 executing the random number update process P_RANDOM shown in FIG. 10-12 sets the random number MR1-2 for the winning design as the first random number, and sets the random number MR2-1 for the normal design as the second random number. In this case, the first update means can update the first random value and the second random value in each update range by random number update processing. In addition, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B include a random number MR1-1 for special symbol determination, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting a variation pattern type, and a variation pattern. When the third random number and fourth random number are set from among the random numbers MR3-4, the third random number and fourth random number are updated by the system clock input as the clock signal for the random number. It becomes the second update means that can be updated in the range. Then, for example, the random number MR2-1 for normal symbol per symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199", so the second random number is updated. The total number of random numbers in the range will be prime. On the other hand, for example, the random number MR3-2 for selecting the loss effect has an update range of "0" to "65518", the total number of random numbers included in the update range is "65519", and the variation pattern type selection The random number MR3-3 for the fluctuation pattern has an update range of "0" to "240", and the total number of random numbers included in the update range is "241". Since the range is "0" to "250" and the total number of random numbers included in the update range is "251", at least one of the third random number and the fourth random number is included in the update range. The total number of random values received is prime. In this way, even if the updating methods are different between the first updating means and the second updating means and the updating methods are the same, at least one of the random values is a prime number in the update range, thereby suppressing the occurrence of synchronization. It is possible to update the appropriate random value.

The 16-bit random number circuit 104A and the 8-bit random number circuit 104B include a random number MR1-1 for special symbol determination, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-3 for selecting a variation pattern. When a first random value and a second random value are set from the random numbers MR3-4, the first random value and the second random value can be updated by a system clock input serving as a random number clock signal. A means of updating. The CPU 103 that executes the random number update process P_RANDOM shown in FIG. 10-12 sets the third random number from among the random number MR1-2 for the winning symbol and the random number MR2-1 for the normal winning symbol. In this case, the third random number value can be updated by the random number updating process. Based on the start of power supply in the pachinko gaming machine 1, the CPU 103 executing the main process P_MAIN for game control shown in FIG. When executed, the stored value of the function setting register area is set by the function setting register store instruction of step AKS13. At this time, by setting the stored value of the maximum value setting register provided corresponding to the 16-bit random number circuit 104A and the 8-bit random number circuit 104B, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B It is possible to execute maximum value setting processing for setting the maximum random number value of the random number value updated by . Then, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B, which serve as the first update means, start updating the first random number when the maximum value of the first random number is set in the maximum value setting process. After that, the update of the second random number is started by setting the random number maximum value of the second random number. CPU103 that executes the main processing P_MAIN for game control shown in FIG. Correspondingly, the game control timer interrupt process P_PCT shown in FIG. 5 can be executed, and by executing the random number update process P_RANDOM in step S56, the update of the third random value is started. In this way, the CPU 103 that executes the random number update process P_RANDOM, which is the second update means, can update the third random value after executing the maximum value setting process in the power supply start support process P_POWER_ON. Uncertainty is increased by first starting to update random numbers that are highly related to game values, such as the random number MR1-1 for symbol determination, and appropriate random numbers can be updated.

In the bit data RAP of the RWM access protect register shown in FIG. 10-9(B), the bit data RAM0 of bit number "0" is the initial value corresponding to the start of power supply in the pachinko game machine 1. It is set to 0 [B]. As a result, access to the RWM RAM 102 is prohibited in response to the fact that the value stored in the RWM access protect register, which is the specific storage area, is set to the first stored value. The CPU 103, which has executed the power supply start handling process P_POWER_ON shown in FIG. store the permission output value in In this way, after setting a stored value in the function setting register area, which is a storage area related to functions, a second stored value that permits access to the RAM 102 as storage means can be set in the RWM access protect register, which is a specific storage area. is. Then, as the next processing after setting the second stored value, by executing the RWM check processing P_RWM_CHK of step S2 in the main processing P_MAIN processing for game control shown in FIG. It is possible to execute confirmation processing for confirming whether or not the control state can be restored based on the contents. In this way, it is possible to prevent the contents stored in the storage means from being changed unnecessarily, thereby ensuring the execution of the confirmation process and appropriately updating the random number value.

The CPU 103 executing the power-off processing P_POWER_OFF shown in FIG. 10-10 stores the checksum data generated by the checksum calculation processing P_SUM_CALC of step AKS39 in the checksum buffer in step AKS40, thereby stopping the power supply. In response to , it is possible to execute stop storage processing for storing checksum data, which is recovery information for recovering the control state, in a storage area such as a checksum buffer of the RAM 102 as storage means. After such stop storage processing is executed, the clear data set in the output value data in step AKS41 is stored in the RWM access protect register in step AKS42, thereby setting the first stored value in the specific storage area. It is possible to execute storage processing at the time of stop. After the stop time storage process is executed, the loop process of steps AKS48 and AKS49 is performed to shift to a standby state in which game control is not executed. In response to the recovery of the power supply in this standby state, if the power confirmation signal input bit is not "0" at step AKS49, the vector table address at power failure recovery is set to the stack pointer at step AKS50. After that, by ending the power-off processing P_POWER_OFF by an interrupt return command, the main processing P_MAIN for game control shown in FIG. enable. This prevents unstable operation when the power supply is restored, and enables appropriate updating of the random value.

In the address map in the game control microcomputer 100 shown in FIG. 10-2, the function setting register area of the built-in register assigned the addresses FE00 [H] to FEBF [H] is included in the game control microcomputer 100 The function control register area of the built-in register assigned with the address FF00 [H] ~ FFFF [H] is the first area for function setting using various circuits that are included in the game control microcomputer 100 Various circuits is the second area for function control using . Of these, the RWM access protect register at address FF00[H] is a specific storage area in which a storage value indicating whether or not to permit access to the RAM 102, which is RWM, can be set. Based on the start of power supply in the pachinko gaming machine 1, the CPU 103 executing the main process P_MAIN for game control shown in FIG. When executed, it is possible to execute a control storage process for setting the stored value of the function control register area, which is the second area, in steps AKS5 to AKS7. After such control storage processing is executed, steps AKS11 to AKS13 can execute setting storage processing for setting the stored values in the function setting register area, which is the first area. After such setting storage processing is executed, a stored value that permits access to the RAM 102, which is a storage means, can be set in the RWM access protect register as a specific storage area in step AKS14. In this way, it is possible to prevent the contents stored in the storage means from being changed unnecessarily, and to appropriately update the random number value.

(Problem Solving Means and Effect of Characteristic Portion 01AK)
(1-1) A gaming machine that can be controlled in an advantageous state for a player,
updating means capable of updating the random value;
a first display means capable of variably displaying special identification information;
a second display means capable of executing variable display of normal identification information,
The kind of advantageous state is determined according to the display result by the first display means,
Determining a mode of change for changing the starting area to a guidance state in which the game medium can easily pass, in accordance with the display result by the second display means;
The means of updating
The first random value used for determining the display result by the first display means and the second random value used for determining the display result by the second display means can be updated in each update range by a common update process,
The first random value and the second random value can be updated using a common internal storage means,
For the first random number, the total number of random numbers included in the update range is not a prime number,
The total number of random numbers included in the update range of the second random number is a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, the CPU 103 that executes the random number update process P_RANDOM. The special identification information may be, for example, special symbols. The first display means may be, for example, the first special symbol display device 4A and the second special symbol display device 4B. The normal identification information may be, for example, normal symbols. The second display means may be, for example, the normal symbol display device 20 or the like. The display result by the first display means may be, for example, a confirmed special symbol that is the display result of the special symbol. The display result by the second display means may be, for example, a confirmed normal symbol that is a normal symbol display result. The type of advantageous state may be, for example, the maximum value of the number of openings of the big winning opening. The change mode may be, for example, normal electric accessory opening time. The first random value may be, for example, random number MR1-2. The second random value may be, for example, random number MR2-1. The update process may be, for example, an initial value change random number update process P_RANCP. The internal storage means may be the HL register, B register, DE register, etc. of the CPU 103, for example. The total number of the first random numbers may be, for example, the magnitude of the random numbers MR1-2 being "65536". The total number of second random numbers may be, for example, the size of the random number MR2-1 is "199".
According to such a configuration, the common update process prevents an increase in program capacity, and the total number of random numbers included in the update range is a prime number, so that the first random number and the second random number are synchronized. can be suppressed to update the appropriate random value.

(1-2) When executing update processing, the updating means updates the random number value to be updated and changes the initial random number value after setting the random number value to be updated, the maximum random number value, and the initial random number value. and may be executable.
Here, the settings for executing the update process may be, for example, steps AKS61 to AKS63 and steps AKS65 to AKS67. The update of the random number value to be updated and the change of the initial value of the random number may be performed, for example, by executing the initial value change random number update process P_RANCP in steps AKS64 and AKS68.
In such a configuration, it is possible to appropriately update the random number value by updating the set random number value to be updated.

(1-3) The update means may update the second random value after updating the first random value by a specific update process.
Here, the specific update process may be, for example, random number update process P_RANDOM.
In such a configuration, by updating the first random number value used for determining the display result that attracts the attention of the player before the second random number value, the occurrence of defects is suppressed and the appropriate random number value is updated. can be updated.

(1-4) the update means updates the first random value and the second random value by calling a common update process corresponding to the first random value and the second random value by a specific update process; The initial values of the first random value and the second random value may be changeable.
Here, the common update process may be, for example, the initial value change random number update process P_RANCP of steps AKS64 and AKS68 in the random number update process P_RANDOM.
In such a configuration, the common update process prevents an increase in program capacity, stably updates the first random number value and the second random number value, and makes it possible to appropriately update the random number value.

(1-5) The updating means may be capable of updating the first random value and the second random value using a common internal storage means by a specific update process.
For example, in the random number update process P_RANDOM, the HL register is set by steps AKS61 and AKS65, the B register is set by steps AKS62 and AKS66, and the DE register is set by steps AKS63 and AKS67. Execution of the random number update process P_RANCP is sufficient.
In such a configuration, it is possible to stably update the first random number value and the second random number value using the common internal storage means, and to appropriately update the random number value.

(1-6) When the update means stores the reference destination information in the internal storage means before the common update process by the specific update process, the first random number value and the second random number value are common. It may be possible to set different reference destination information in the internal storage means using instructions.
Here, the internal storage means may be, for example, an HL register, a B register, a DE register, or the like. A common instruction may be a transfer instruction such as an LD instruction or an LDQ instruction. The different reference destination information is, for example, the address F081 [H] of the random number counter for the winning symbol, the address F052 [H] of the random number counter for the normal symbol, and the address F050 [H] of the random number initial value data buffer for the winning symbol. The address F053 [H] of the random number initial value data buffer for per symbol may be used.
In such a configuration, by making it possible to update the first random number value and the second random number value using a common instruction, the first random number value and the second random number value can be stably updated and appropriate Random values can be updated.

(1-7) When executing the update process, the updating means can change the initial random number value after updating the random number value to be updated in response to the fact that the random number value to be updated matches the initial random number value. be,
For example, in the initial value change random number update process P_RANCP, after updating the random number value to be updated in step AKS101, in response to matching with the stored value of the random number initial value data buffer in step AKS105, a new random number initialization is performed in step AKS108. It is sufficient if it stores a value.
In such a configuration, it is possible to appropriately update the random number by updating the random number to be updated and changing the initial value of the random number.

(1-8) When the update means executes update processing to update the random number value to be updated,
comparing the random value to be updated with the maximum random value;
adding 1 to the random number value to be updated if the comparison result is less than the maximum random number value;
A single compare-add instruction may be executed first, including changing the random value to be updated to the minimum random value if the result of the comparison is greater than or equal to the maximum random value.
Here, the comparison addition instruction may be, for example, the part of step AKS101.
In such a configuration, by executing the comparison-addition instruction first, it is possible to suppress the occurrence of defects and appropriately update the random number value.

(1-9) The updating means may first execute the comparison-addition instruction both when updating the first random value and when updating the second random value.
For example, step AKS101 in the initial value change random number update process P_RANCP of steps AKS64 and AKS68 may be performed.
In such a configuration, by executing the comparison-addition instruction first, it is possible to suppress the occurrence of defects in the first random number value and the second random number value, and to appropriately update the random number value.

(1-10) When determining the display result by the first display means, when the first random number value is the minimum random number value, the display result is more advantageous than when the first random number value is other than the minimum random number value. not determined by
When determining the display result by the second display means, when the second random number value is the minimum random number value, the display result must not be determined to be more advantageous than when the second random number value is other than the minimum random number value. good too.
Here, a display result with a high degree of advantage may not be determined, for example, in the case of determination of the number of times of opening the big winning opening AKD01 or the example of determining the manner of opening the big winning opening AKD02.
With such a configuration, it is possible to appropriately update the random number value so as to prevent fraudulent acts due to defects in the first random number value and the second random value.

(1-11) The updating means is
It is possible to execute initial value update processing that can update the initial value random value used when changing the initial value of the random number,
After executing the comparison-addition instruction, comparing the random number to be updated after being updated by the comparison-addition instruction with the initial random number value,
If the random number to be updated after updating does not match the initial random number value, store the random number to be updated after updating as the current random number,
If the random number to be updated after the update matches the initial random number value, the random number value for the initial value obtained by the initial value update process can be stored as the current random number value and as a new initial random number value. good.
Here, the random number for the initial value may be, for example, the random number MR1-3 or the random number MR2-2. The initial value update process may be, for example, an initial value determination random number update process P_TFINIT. The comparison with the random number initial value may be performed, for example, at step AKS105. If it does not match the random number initial value, for example, it may be Yes in step AKS105. If it matches the initial value of the random number, for example, steps AKS106 to AKS108 in the case of No in step AKS105 may be performed.
In such a configuration, the uncertainty of the random number is increased by setting the new random number initial value, and by storing the current random number as well, an increase in the data capacity is prevented, and the random number is appropriately updated. becomes possible.

(1-12) The update means is
a first initial value update process for updating a first initial value random number value used when changing the random number initial value, corresponding to the case where the random number value to be updated is the first random number value;
a second initial value update process for updating the random number value for the second initial value used when changing the initial value of the random number, corresponding to the case where the random number value to be updated is the second random number value; It may be possible to execute an update process.
Here, the random number for the first initial value may be, for example, the random number MR1-3. The first initial value update process may be steps AKS81 and AKS82 in the initial value determination random number update process P_TFINIT, for example. The random number for the second initial value may be, for example, the random number MR2-2. The second initial value update process may be steps AKS83 and AKS84 in the initial value determination random number update process P_TFINIT, for example.
In such a configuration, by updating the first initial value random number value and the second initial value random number value, it is possible to appropriately update the random number value.

(1-13) The updating means may update the second random number value for initial value after updating the random number value for first initial value by initial value update processing.
For example, in the initial value determination random number update process P_TFINIT, steps AKS83 and AKS84 may be executed after steps AKS81 and AKS82.
In such a configuration, by updating the first random value for initial value with higher priority before the second random value for initial value with lower priority, the occurrence of defects can be suppressed and an appropriate random value can be obtained. can be updated.

(1-14) When executing the initial value update process, the updating means performs the following operations based on the settings regarding the initial value random number value to be updated and the initial value maximum random number value:
comparing the random number for initial value to be updated with the maximum random number for initial value;
If the comparison result is less than the maximum random number for initial value, 1 is added to the random number for initial value to be updated;
If the result of the comparison is greater than or equal to the maximum random number value for initial value, a single compare-add instruction may be executed including changing the random value for initial value to be updated to the minimum random number value.
Here, the comparison addition instruction may be, for example, steps AKS82 and AKS84.
In such a configuration, by updating the random number value for the initial value to be updated using the comparison addition instruction, it is possible to suppress the occurrence of troubles and appropriately update the random number value.

(1-15) The updating means is
a random number update process capable of updating a random number value to be updated;
an initial value random number update process capable of updating the initial value random number used when changing the random number initial value corresponding to the random number to be updated,
The first process that can be executed in response to the timer interrupt due to the elapse of the predetermined time includes random number update process and initial value random number update process,
The second process that can be repeatedly executed until the first process is executed may not include the random number update process and may include the initial value random number update process.
Here, the random number value to be updated may be, for example, the random number MR1-2 or the random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number for the initial value may be, for example, the random number MR1-3 or the random number MR2-2. The initial value random number update process may be, for example, the initial value determination random number update process P_TFINIT. The first process may be timer interrupt process P_PCT for game control, for example. The second process may be steps S8 to S10 in the main process P_MAIN for game control, for example.
In such a configuration, the random number update process for initial value increases the uncertainty of the random number for initial value, and it is possible to update the random number appropriately.

(1-16) The update process is
a random number update process capable of updating a random number value to be updated;
an initial value random number update process capable of updating the initial value random number used when changing the random number initial value corresponding to the random number to be updated,
The random number update process and the initial value random number update process can be called and executed in the timer interrupt process that controls the progress of the game,
The initial value random number update process may be invoked and executed in the standby process that is repeated after the startup process that is executed based on the start of power supply.
Here, the random number value to be updated may be, for example, the random number MR1-2 or the random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number for the initial value may be, for example, the random number MR1-3 or the random number MR2-2. The initial value random number update process may be, for example, the initial value determination random number update process P_TFINIT. Timer interrupt processing may be, for example, timer interrupt processing P_PCT for game control. The start-up process may be, for example, steps S1 to S7 in the main process P_MAIN for game control. The standby process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the random number update process for initial value increases the uncertainty of the random number for initial value, and it is possible to update the random number appropriately.

(2-1) A gaming machine that can be controlled in an advantageous state advantageous to a player,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means,
The updating means can update a first random value for determining whether or not to control to an advantageous state and a second random value different from the first random value,
The first random value is composed of a specific number of bytes, and the total number of random values included in the update range is a specific number,
the second random number is composed of a specific number of bytes, and the total number of random numbers included in the update range is a predetermined number smaller than the specific number;
The first random value may be updated faster than the second random value.
Here, the advantageous state may be, for example, a jackpot game state. The gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC. The first random value may be, for example, random number MR1-1. The second random value may be, for example, random number MR3-2. The specific number of bytes may be, for example, 2 bytes. The specific number may be, for example, "65536", which is the size of the random number MR1-1. The predetermined number may be, for example, "65519", which is the magnitude of the random number MR3-2. The high update speed may be, for example, if the update speed of the random number MR1-1 in the random value comparison example AKA23 is 15000 [times/ms] and the update speed of the random number MR3-2 is 469 [times/ms].
In such a configuration, it is possible to appropriately update the random number value so that intentional control of the advantageous state becomes difficult due to the high update speed of the first random number value regarding the advantageous state.

(2-2) A gaming machine capable of playing games,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means,
The update means can update the first random value and a second random value different from the first random value,
the first random value has an update rate of the first rate;
The second random value is a second speed at which the update speed is an integral multiple of the first speed,
The total number of random numbers included in each update range may be different between the first random number value and the second random number value, and the total number of random numbers included in each update range may be a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC. The first random value may be, for example, random number MR3-2. The second random number may be random numbers MR3-3 and MR3-4, for example. The first speed may be, for example, 469 [times/ms]. The second speed may be, for example, 938 [times/ms]. The total number of random numbers may be, for example, "65519" for the size of the random number MR3-2, "241" for the size of the random number MR3-3, and "251" for the size of the random number MR3-4. .
In such a configuration, even if the update speed is an integral multiple, the total number of random numbers included in the update range is different prime numbers, thereby suppressing the occurrence of synchronization between the first random number and the second random number. Appropriate random value update is possible.

(2-3) A gaming machine capable of playing games,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means,
The updating means can update a first random value, a second random value different from the first random value, and a third random value different from the first random value and the second random value,
The processing means can extract the first random value, the second random value, and the third random value by establishing a common extraction condition,
the first random value has an update rate of the first rate;
The second random value and the second random value are a second speed at which the update speed is an integral multiple of the first speed,
The total number of random numbers included in each update range may be different for the first random number, the second random number, and the third random number, and the total number of random numbers included in each update range may be a prime number.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC. The first random value may be, for example, random number MR3-2. The second random value may be, for example, random number MR3-3. The third random value may be, for example, random number MR3-4. The first speed may be, for example, 469 [times/ms]. The second speed may be, for example, 938 [times/ms]. The total number of random numbers may be, for example, "65519" for the size of the random number MR3-2, "241" for the size of the random number MR3-3, and "251" for the size of the random number MR3-4. .
In such a configuration, even if the update speed is an integer multiple, the total number of random numbers included in the update range is different prime numbers, so that the first random number, the second random number, and the third random number are synchronously generated. can be suppressed to update the appropriate random value.

(2-4) A gaming machine capable of playing games,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means,
The means of updating
a first update means capable of updating the first random value and the second random value in each update range by random number update processing;
a second update means capable of updating the third random value and the fourth random value in each update range by the random number clock signal;
at least one of the first random value and the second random value has a total number of random values included in the update range that is a prime number;
At least one of the third random number value and the fourth random number value may be a prime number in total within the update range.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, the 16-bit random number circuit 104A, the 8-bit random number circuit 104B, or the CPU 103 that executes the random number update process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The first random value may be, for example, random number MR2-1. The second random value may be, for example, random number MR1-2. The random number update process may be, for example, random number update process P_RANDOM. The third random value may be, for example, random number MR3-3. The fourth random value may be, for example, random number MR3-4. The random number clock signal may be, for example, a system clock. The total number of random numbers included in the update range is, for example, "199" for the size of the random number MR2-1, "200" for the size of the random number MR1-2, and "241" for the size of the random number MR3-3. , or "251", which is the size of the random number MR3-4.
In such a configuration, the updating method differs between the first updating means and the second updating means. It is possible to suppress the occurrence of synchronism and appropriately update the random value.

(3-1) A gaming machine capable of playing games,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means;
storage means including storage areas for functions of the update means and the processing means;
The processing means performs maximum value setting processing for setting the maximum value of the random value updated by the updating means when setting the stored value in the storage area related to the function by the start-up processing executed based on the start of power supply. is executable and
The means of updating
a first updating means capable of updating a first random value composed of a specific number of bytes;
a second updating means capable of updating a second random value composed of a predetermined number of bytes smaller than the specific number of bytes;
When executing the maximum value setting process, the processing means may set the maximum random number value of the second random value after setting the maximum random value of the first random value.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, the random number circuit 104 or the like. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100 or the like. The start-up process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start handling process P_POWER_ON. The specific number of bytes may be, for example, 2 bytes. The first random value may be, for example, random number MR3-2. The first updating means may be, for example, a 16-bit random number circuit 104A. The predetermined number of bytes may be, for example, 1 byte. The second random number may be random numbers MR3-3 and MR3-4, for example. The second update means may be, for example, an 8-bit random number circuit 104B. Setting the maximum random number value of the first random value and setting the maximum random number value of the second random value may be performed by executing step AKS13 using the function setting register storage value table AKT01.
In such a configuration, by setting the second random value of a predetermined number of bytes after setting the first random value of the specific number of bytes, the first random value and the second random value are stably updated, Appropriate random value update is possible.

(3-2) The updating means may start updating in order from the random number values to which the maximum random number value is set.
For example, using the function setting register stored value table AKT01, a 16-bit random number circuit channel RL0 of channel number "0", a 16-bit random number circuit channel RL2 of channel number "2", and an 8-bit random number of channel numbers "1" to "3" Any portion that sets the maximum value for the circuit channels RS1 to RS3 may be used.
In such a configuration, the uncertainty of the random number value is increased by the timing of starting the update of the random number value, the processing load is reduced, and the random number value can be appropriately updated.

(3-3) A gaming machine capable of playing games,
updating means capable of updating the random value;
A processing means capable of executing processing related to game control using a random value updated by the updating means;
storage means including storage areas for functions of the update means and the processing means;
The processing means performs maximum value setting processing for setting the maximum value of the random value updated by the updating means when setting the stored value in the storage area related to the function by the start-up processing executed based on the start of power supply. is executable and
The means of updating
a first updating means capable of updating the first random value and the second random value with a random number clock signal;
a second update means capable of updating the third random value by a random number update process;
In the maximum value setting process executed by the processing means, the first updating means updates the first random number value by setting the maximum random number value of the first random number value, and after starting the update of the first random number value, is set, the update of the second random value is started,
The second updating means may start updating the third random value after the processing means executes the maximum value setting process.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The update means may be, for example, the random number circuit 104 or the CPU 103 that executes the random number update process P_RANDOM. The processing means may be, for example, the CPU 103 that executes the special symbol process P_TPROC or the normal symbol process P_FPROC. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100 or the like. The start-up process may be, for example, the main process P_MAIN for game control. The maximum value setting process may be, for example, steps AKS11 to AKS13 in the power supply start handling process P_POWER_ON. The first random number may be random numbers MR1-1 and MR3-2, for example. The second random number may be random numbers MR3-3 and MR3-4, for example. The first updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The third random value may be, for example, random numbers MR1-2 and MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The second updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM in step S56. To start updating the first random number, for example, the function setting register stored value table AKT01 is used to set the maximum value to the 16-bit random number circuit channel RL0 with the channel number "0" and the 16-bit random number circuit channel RL2 with the channel number "2". Any part to be set can be used. If the update of the second random number is started, for example, by using the function setting register storage value table AKT01, the maximum value is set in the 8-bit random number circuit channels RS1 to RS3 of the channel numbers "1" to "3". good. The start of the update of the third random number may be, for example, a part that executes the random number update process P_RANDOM of step S56 in the timer interrupt process P_PCT for game control after the power supply start corresponding process P_POWER_ON of step S1 is executed. .
In such a configuration, by first starting to update the random number MR1-1, etc., which is highly related to the game value, the uncertainty is increased, and it is possible to appropriately update the random number.

(4-1) a storage means capable of storing information relating to game control;
storage means including storage areas for functions of the update means and the processing means;
a specific storage area among the storage areas related to the function can be set to a first stored value that prohibits access to the storage means in response to the start of power supply;
The processing means
After setting the stored value in the storage area related to the function, a second stored value that permits access to the storage means can be set in the specific storage area,
After the second stored value is set in the specific storage area, confirmation processing may be performed to confirm whether the control state can be restored based on the contents stored in the storage means.
Here, the storage means may be, for example, the RAM 102 or the like. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100 or the like. The specific storage area may be, for example, an RWM access protect register. The first stored value may be, for example, 00[H]. The second stored value may be, for example, 01[H]. The second stored value can be set in the specific storage area by executing step AKS14 in the power supply start support process P_POWER_ON, for example. The confirmation process may be, for example, the RWM check process P_RWM_CHK in step S2.
In such a configuration, the contents stored in the storage means can be prevented from being changed unnecessarily, so that the confirmation process can be reliably executed, and the random number value can be appropriately updated.

(4-2) The processing means is
In response to the stoppage of power supply, it is possible to execute stoppage storage processing for storing restoration information for restoring the control state in the storage means,
After the stop storage process is executed, the stop storage process of setting the first stored value in the specific storage area can be executed,
After the storage processing at the time of stop is executed, the game control is shifted to a standby state in which the game control is not executed, and in response to the recovery of the power supply in the standby state, the start-up processing based on the activation of the game machine is started. may be executable from
The recovery information may be, for example, checksum data. The storage process at the time of stop may be, for example, the checksum calculation process of step AKS39 or the part of step AKS40 in the power-off process P_POWER_OFF. The storing process at stop may be, for example, steps AKS41 and AKS42 in the power-off process P_POWER_OFF. The transition to the standby state may be performed, for example, by executing steps AKS48 and AKS49 in power-off processing P_POWER_OFF. What is executable from the beginning of the start-up process may be, for example, executing step AKS50 in the power-off process P_POWER_OFF and then executing the RET instruction.
With such a configuration, it is possible to prevent unstable operation when the power supply is restored, and to appropriately update the random number value.

(4-3) a storage means capable of storing information on game control;
storage means including storage areas for functions of the update means and the processing means;
The storage means, as a storage area for functions,
a first area for setting functions;
a second region for functional control;
the second area includes a specific storage area in which a stored value indicating whether or not to permit access to the storage means can be set;
The processing means, in a start-up process executed based on the start of power supply,
A control storage process for setting a stored value in the second area can be executed,
After the control storage process is executed, a setting storage process for setting a stored value in the first area can be executed,
After the storage processing for setting is executed, it may be possible to set a stored value that permits access to the storage means in the specific storage area.
Here, the storage means may be, for example, the RAM 102 or the like. The storage area related to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100 or the like. The first area may be, for example, the function setting register area of setting example AKA01. The second area may be, for example, the function control register area of the setting example AKA02. The specific storage area may be, for example, an RWM access protect register. The start-up process may be, for example, the main process P_MAIN for game control. The control storage process may be, for example, steps AKS5 to AKS7 in the power supply start support process P_POWER_ON. The setting storing process may be, for example, steps AKS11 to AKS13 in the power supply start corresponding process P_POWER_ON. The fact that the stored value can be set in the specific storage area may be achieved by, for example, executing step AKS14 in the power supply start handling process P_POWER_ON.
In such a configuration, it is possible to prevent the contents stored in the storage means from being changed unnecessarily and to appropriately update the random number value.

(Description of Characteristic Portion 003AK)
FIG. 11-1 shows a memory area of addresses 0000[H] to 3FFF[H] allocated to the ROM 101 for the characteristic portion 003AK. A game program area included in the memory area of the ROM 101 is assigned addresses 0000[H] to 0BD2[H], and has a total storage capacity of 3027 bytes. A game data area included in the memory area of the ROM 101 is assigned addresses 1200[H] to 1D33[H] and has a total storage capacity of 2868 bytes. A non-game program area included in the memory area of the ROM 101 is assigned addresses 2000[H] to 24DD[H]. A non-game data area included in the memory area of the ROM 101 is assigned addresses 24DE[H] to 2576[H]. A ROM comment area included in the memory area of the ROM 101 is assigned addresses 2E00[H] to 2E3F[H]. A program management area included in the memory area of the ROM 101 is assigned addresses 3FC0[H] to 3FFF[H].

The memory area of the ROM 101 includes an unused area to which addresses 0BD3[H] to 11FF[H] are assigned between the game program area and the game data area. The unused area of addresses 0BD3[H] to 11FF[H] has a total storage capacity of 1069 bytes. The memory area of the ROM 101 includes an unused area assigned addresses 1D34[H] to 1FFF[H] between the game data area and the non-game program area. The unused area at addresses 1D34[H] to 1FFF[H] has a total storage capacity of 1228 bytes. The memory area of the ROM 101 includes an unused area assigned addresses 2577[H] to 2DFF[H] between the non-game data area and the ROM comment area. The memory area of the ROM 101 includes an unused area assigned addresses 2E40[H] to 3FBF[H] between the ROM comment area and the program management area.

Zero data with a storage value of 00[H] is stored as unused data in these unused areas. In this way, the unused area stores zero data with a storage value of 00[H] as unused data indicating 0. FIG. The unused area may be any area to which access by the CPU 103 is prohibited. For example, it is sufficient if access prohibition can be set for all or part of the unused area by specifying the program code end address and program code start address stored in the program management area.

In the game control microcomputer 100 , the ROM 101 can store programs, and the CPU 103 can control the progress of the game according to the programs stored in the ROM 101 . Therefore, the ROM 101 can correspond to storage means capable of storing programs. The CPU 103 can correspond to control means capable of controlling the progress of a game by a program stored in a storage means. In addition, an externally attachable storage device different from the ROM 101 constitutes storage means capable of storing programs, and the game control microcomputer 100 as a whole can control the progress of the game according to the programs stored in this storage device. It may be configured as a control means.

The game program area stores programs related to game control. The game data area stores data used for executing the program stored in the game program area. A non-game program area and a non-game data area are provided as storage areas different from the game program area and the game data area. Therefore, the game program area can correspond to the first storage area in which programs related to game control are stored. The game data area can correspond to the second storage area storing data used for executing the program stored in the first storage area. The non-game program area and the non-game data area can correspond to a third storage area different from the first storage area and the second storage area.

In the memory area of the ROM 101, when the game program area is the first storage area and the game data area is the second storage area, the unused area at addresses 0BD3[H] to 11FF[H] is the first storage area. It becomes an unused storage area capable of storing unused data between it and the second storage area. Unused data indicating all 0 is stored in the unused storage area. In this case, the total storage capacity of the game program area, which is the first storage area, is 3027 bytes, which is larger than the total storage capacity of the unused area, which is 1069 bytes.

In the memory area of the ROM 101, when the game program area is the first storage area, the game data area is the second storage area, and the non-game program area and the non-game data area are the third storage area, address 0BD3 [H] The unused area from 11FF[H] to 1D34[H] to 1FFF[H] becomes an unused storage area capable of storing unused data between the first storage area and the second storage area. becomes an unused storage area capable of storing unused data between the second storage area and the third storage area. Unused data indicating all 0 is stored in the unused storage area. In this case, the total storage capacity of the game data area, which is the second storage area, is 2868 bytes, which is larger than the total storage capacity of the unused area, which is 2297 bytes.

In the memory area of the ROM 101, the unused area corresponding to the unused storage area capable of storing unused data between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area is A single area in which consecutive addresses are assigned and unused data indicating 0 is stored may be used. In the memory area of the ROM 101, it corresponds to an unused storage area capable of storing unused data between the game data area corresponding to the second storage area and the non-game program area and non-game data area corresponding to the third storage area. The unused area may be a single area in which consecutive addresses are assigned and unused data indicating 0 is stored.

For example, in the address map of the game control microcomputer 100, such as a memory area assigned an address in the ROM 101, before and after the storage area, the smaller assigned address is the front, and the larger assigned address is the rear. are specified corresponding to the magnitude relationship of the address values. Therefore, the second area assigned with an address value larger than that of the first area becomes the second area located behind the first area, and the third area assigned with an address value smaller than that of the first area becomes , becomes a third area arranged in front of the first area. The first area, the second area, and the third area may be arbitrarily set according to the size relationship of the addresses assigned according to the specifications of the pachinko gaming machine 1 . The arrangement of each area in the memory area of the ROM 101 including the game program area, game data area, non-game program area, non-game data area, and other unused areas is assigned according to the specifications of the pachinko gaming machine 1. Any setting can be made by the address.

FIG. 11-2 shows a setting example 003AKA01 of unused data in the game program area contained in the memory area of the ROM 101. FIG. In setting example 003AKA01, the processing start address includes the start address of the program module and the start address of the table data. The end address for processing includes the end address of the program module and the end address of the table data. The unused data amount is the number of bytes that is the storage capacity of the area in which zero data with a storage value of 00 [H] is stored as unused data indicating 0. FIG. Thus, the start address for processing is the start address of the program or the start address of data available for program execution, and the end address for processing is the end address of the program or the end address of data available for program execution. However, the data that can be used for program execution may include data that is not used for program execution due to various instructions and settings in the implemented program.

In the game program area included in the memory area of the ROM 101, addresses 0008[H], 0010[H], 0018[H], 0020[H], 0028[H], 0030[H], 0038[H], 0040[ H] is predetermined as a restart address at which program modules can be arranged. The restart address is an 8-byte address where the lower 1 digit of the address is 0 [H] or 8 [H] in the area assigned addresses 0008 [H] to 0040 [H] included in the game program area. is. Therefore, the restart address can correspond to a plurality of specific addresses assigned at predetermined intervals. The CPU 103 is prepared with an RST instruction, which is a 1-byte restart instruction that can be executed by calling a program module whose start address is a predetermined restart address.

FIG. 11-3 shows a configuration example of the RST instruction. As shown in FIG. 11-3(A), the RST instruction is configured using the operation code from the 0th bit to the 7th bit, and all bits other than the 3rd bit to the 5th bit are 1 [B ]. As shown in FIG. 11-3(B), the operation code from the 3rd bit to the 5th bit in the RST instruction is a parameter determined corresponding to the specified address which is the calling address of the program module. For example, parameter 001 [B] corresponds to address 0008 [H], parameter 010 [B] corresponds to address 0010 [H], parameter 011 [B] corresponds to address 0018 [H], parameter 100 [B] corresponds to ] corresponds to address 0020[H], parameter 101[B] corresponds to address 0028[H], parameter 110[B] corresponds to address 0030[H], parameter 111[B] corresponds to address 0038[ H], and parameter 000[B] corresponds to address 0040[H]. Therefore, each parameter of 3 digits in binary number is associated with an address of 4 digits in hexadecimal number.

An operation code including parameters is used when a program module is called by an RST instruction, which is a restart instruction. The RST instruction designates a parameter whose data amount is smaller than the address in the memory area of the ROM 101, and makes it possible to call the program module stored at the address corresponding to the designated parameter. The operation code of the RST instruction includes a 3-digit binary variable t, and multiple restart addresses can be specified using the operation code in which parameters are substituted for the variable. Thus, the RST instruction is a call instruction that, by designating a value corresponding to a predetermined restart address, can call and execute a program stored at the restart address corresponding to the designated value. be.

The CPU 103 is prepared with a CALL instruction different from the RST instruction as a call instruction for calling and executing the program stored in the game program area. A CALL instruction is a call instruction that calls and makes executable a program stored at an address specified by an operand. When a program is called and executed by the CALL instruction, the operand of the CALL instruction designates a total of two bytes consisting of the upper byte and the lower byte constituting the start address of the program. The CPU 103 specifies the start address of the program from the operands of such CALL instructions. Thus, a CALL instruction may correspond to a first call instruction that calls a program stored at a specified address by specifying an address. On the other hand, the RST instruction specifies a parameter with a smaller amount of data than the address so that the program stored at a specific address corresponding to the specified parameter among a plurality of specific addresses assigned at predetermined intervals can be retrieved. It may correspond to a second call instruction to call.

Of the game programs that control the progress of the game, program modules that are frequently used are at least partly stored in a restart area having a restart address as a start address. In the setting example 003AKA01 shown in FIG. 11-2, special symbol process processing end check processing P_TPRO_END, time saving check processing P_JTN_CHK, 2 bytes 1 byte addition processing P_ABX, output processing P_OUT, 2 bytes data selection processing P_ABXEXC, second distribution determination Each program module is stored in the restart area corresponding to each process of the value comparison process P_HANTEI2, the starting entry winning check process P_STR_CHK, the sorting judgment value comparison process P_HANTEI, and the command set process P_COM_SET. The data stored in the restart area also includes a vector table upon power restoration.

The program module of the special symbol process process end check process P_TPRO_END has the address 0008 [H] as the start address. The program module of the time saving check process P_JTN_CHK has the address 0010 [H] as the start address. The program module of the 2-byte 1-byte addition process P_ABX has address 0018[H] as the start address. The program module of the 2-byte data selection process P_ABXEXC has address 0020[H] as the start address. The program module of the second distribution determination value comparison process P_HANTEI2 uses address 0028[H] as the start address. The program module of the start entry winning check process P_STR_CHK has address 0030 [H] as the start address. The program module of the distribution determination value comparison process P_HANTEI uses the address 0038[H] as the start address. The program module of the command set process P_COM_SET has address 0040[H] as the start address.

In the restart area, the area from one restart address to before the next restart address is 8 bytes, except for the case of address 0040 [H] where one restart address is the last restart address. , an area from after the end address of the program module whose start address is one restart address to before the next restart address when a program module of less than 8 bytes is stored with the restart address as the start address can store other program modules and table data.

For example, in the program module of the time saving check process P_JTN_CHK, the address 0010 [H] included in a plurality of restart addresses is the start address, and 0014 [H] is the end address. In this case, it is possible to store the table data of the power failure recovery time vector table in the area from the address 0010 [H] which is one restart address to the address 0018 [H] which is the next restart address. . A power-off recovery vector table such as the configuration example AKT11 has lower address specification data 00[H] stored at address 0016[H] and upper address specification data 00[H] stored at address 0017[H]. and are included as table data.

For example, in the program module of the 2-byte 1-byte addition process P_ABX, the address 0018[H] included in the multiple restart addresses is the start address, and the address 001A[H] is the end address. In this case, the program module of the output process P_OUT can be stored in the area from address 0018[H], which is one restart address, to address 0020[H], which is the next restart address. The program module of the output process P_OUT may have an address 001B[H] different from a plurality of restart addresses as a start address and an address 001F[H] as an end address. Therefore, the restart area starting from address 0018[H], which is the restart address, can store program modules corresponding to a plurality of processes such as 2-byte 1-byte addition process P_ABX and output process P_OUT. becomes address 0018[H], and the end address for processing becomes address 001F[H].

In this way, other program modules and table data may be stored in the area from the end address of the program module whose start address is the restart address to the area before the next restart address. As a result, a plurality of program modules or a combination of program modules and table data can be stored in the area from one restart address to before the next restart address.

In the restart area, the area from one restart address to before the next restart address is 8 bytes, except for the case of address 0040 [H] where one restart address is the last restart address. , an area from after the end address of the program module whose start address is one restart address to before the next restart address when a program module of less than 8 bytes is stored with the restart address as the start address may store zero data with a storage value of 00[H] as unused data indicating 0.

FIG. 11-4 shows a description example of the program modules corresponding to the start entry winning check process P_STR_CHK and the sorting judgment value comparison process P_HANTEI among the program modules stored in the restart area. As shown in FIG. 11-4 (A), the start entry winning check process P_STR_CHK restarts from the address 0030 [H], which is one restart address, to the address 0038 [H], which is the next restart address. A program module is stored in the area, the address 0030[H] is the start address, and the LDQ instruction and the like are included. And, address 0034 [H] is the end address of the starting entry winning check process P_STR_CHK, and the process is returned by executing the RET instruction. As shown in FIG. 11-4(B), the sorting judgment value comparison process P_HANTEI is restarted from address 0038 [H], which is one restart address, to address 0040 [H], which is the next restart address. A program module is stored in the area, the address 0038[H] is the start address, and the LDIN instruction and the like are included. The distribution determination value comparison process P_HANTEI has an end address of address 003E[H], and the process is returned by executing the RET instruction.

The area of addresses 0035[H] to 0037[H] shown in FIG. 11-4(A) stores 3-byte zero data with a storage value of 00[H]. This area is after the end address 0034 [H] of the program module where the start entry winning check process P_STR_CHK ends with the RET instruction and returns to the process of the call source, and the address 0038 [H] which is the next restart address. ] before. Therefore, the area of addresses 0035[H] to 0037[H] is an area in which unused data is stored, unlike an area in which programs to be executed by the CPU 103 and data used in executing the programs can be stored. Therefore, the area of addresses 0035[H] to 0037[H] is included in the special storage area storing unused data indicating 0 at the special address. In this way, the area to which addresses 0035[H] to 0037[H] are allocated from address 0030[H], which is one restart address, to address 0038[H], which is the next restart address, is , is contained in a special storage area assigned a special address.

The area of address 003F[H] shown in FIG. 11-4(B) stores 1-byte zero data with a storage value of 00[H]. This area is located after the end address 003E[H] of the program module where the sorting judgment value comparison process P_HANTEI is terminated by the RET instruction and returns to the process of the call source, and the next restart address is the address 0040[H]. ] before. Therefore, the area of address 003F[H] is an area in which unused data is stored, unlike an area capable of storing programs executed by the CPU 103 and data used in executing the programs. Therefore, the area of address 003F[H] is included in the special storage area storing unused data indicating 0 at the special address. In this way, a special address is assigned to the area to which address 003F[H] is assigned from address 0038[H], which is one restart address, to before 0040[H], which is the next restart address. included in the special storage area.

In addition, as shown in FIG. 11-2, from the address 0014 [H], which is the end address of the time saving check process P_JTN_CHK, to the address 0016 [H], which is the top address of the vector table at the time of power failure recovery, the address 0015 [H] ] is included in the special storage area in which 1-byte zero data with a storage value of 00[H] is stored and unused data indicating 0 at the special address is stored. As a result, a special address is assigned to the area to which address 0015[H] is assigned from address 0010[H], which is one restart address, to address 0018[H], which is the next restart address. included in the special storage area. The 2-byte data selection process P_ABXEXC has a start address of 0020[H] and an end address of 0025[H]. In this case, addresses 0026[H], 0026[H], 0026[H], An area of 0027[H] stores 2-byte zero data with a storage value of 00[H] and is included in a special storage area in which unused data indicating 0 at a special address is stored. As a result, the area to which addresses 0026[H] and 0027[H] are allocated from address 0020[H], which is one restart address, to address 0028[H], which is the next restart address, is Contained in a special storage area assigned a special address.

Thus, in the restart area from one restart address to the next restart address included in a plurality of restart addresses, zero data with a storage value of 00[H] is stored, and 0 is stored at the special address. It may include an area where unused data is stored. Therefore, the special storage area includes an area in which unused data is stored from one specific address to the next specific address included in the plurality of specific addresses.

In this case, the area from address 0010 [H], which is one restart address where the program module of the time saving check process P_JTN_CHK is stored, to 0018 [H], which is the next restart address, is 1 byte of unused data includes a special storage area in which 2 bytes of unused data are stored in the area from 0020 [H], which is the first restart address where the program module of the 2-byte data selection process P_ABXEXC is stored, to the address 0028 [H], which is the next restart address. contains a special storage area that 3 bytes of unused data are stored in the area from 0030 [H], which is the restart address where the program module of the starting entrance winning check process P_STR_CHK is stored, to the address 0038 [H], which is the next restart address. contains a special storage area that 1-byte unused data is stored in the area from 0038 [H], which is one restart address in which the program module of the distribution judgment value comparison process P_HANTEI is stored, to 0040 [H], which is the next restart address. contains a special storage area that Therefore, the total storage capacity of the special storage area to which the unused data indicating 0 is stored and to which the special address is assigned in the restart area is 7 bytes.

In addition, since a plurality of restart addresses are assigned every 8 bytes and each restart address becomes the start address of a program module, zero data with a storage value of 00[H] is stored in the restart area, and a special address is stored. The special storage area in which unused data indicating 0 is stored includes a plurality of areas to which discontinuous addresses are assigned. Zero data with a storage value of 00[H] is stored in the restart area, and unused data indicating 0 is stored in the special address. A special address is assigned so that the

FIG. 11-5 shows a storage example of table data included in the interrupt vector table XTBL_INTR. In the game program area included in the memory area of the ROM 101, the address 0060[H] is defined as an address at which the interrupt vector table XTBL_INTR can be arranged. For example, it is sufficient if the lower byte 60[H] of the address 0060[H] can be set as the vector address according to the interrupt factor by the setting data of the interrupt initialization stored in the program management area. Further, it is sufficient if the upper byte 00[H] of address 0060[H] is set as the interrupt vector table upper address by step AKS8 of the power supply start handling process, and can be set in the I register by step AKS9.

The setting data for interrupt initialization can set vector addresses corresponding to a plurality of interrupt factors. The interrupt mask register at address FE00[H] included in the function setting register area can store setting values including bit values corresponding to whether or not to use multiple maskable interrupts. In the power supply start correspondence setting process, the function setting register stored value table address is set in step AKS11, the number of processes is loaded in step AKS12, and then the function setting register store instruction is executed in step AKS13 to set the interrupt mask register. is set to 7E[H]. The interrupt controller 135 enables maskable interrupts corresponding to multiple interrupt sources, such as seven types of maskable interrupts IR0-IR6. When the value stored in the interrupt mask register is 7E[H], the maskable interrupt IR0 is enabled and the other maskable interrupts IR1 to IR6 are disabled.

The interrupt vector table XTBL_INTR contains table data capable of setting interrupt processing start addresses corresponding to a plurality of maskable interrupts IR0 to IR6. The table data at addresses 0060[H] and 0061[H] specify the interrupt processing start address corresponding to the maskable interrupt IR0. The table data at addresses 0062[H] and 0063[H] specify the interrupt processing start address corresponding to the maskable interrupt IR1. The table data at addresses 0064[H] and 0065[H] specify the interrupt processing start address corresponding to the maskable interrupt IR2. The table data at addresses 0066[H] and 0067[H] specify the interrupt processing start address corresponding to the maskable interrupt IR3. The table data at addresses 0068[H] and 0069[H] specify the interrupt processing start address corresponding to the maskable interrupt IR4. The table data at addresses 006A[H] and 006B[H] specify the interrupt processing start address corresponding to the maskable interrupt IR5. The table data at addresses 006C[H] and 006D[H] specify the interrupt processing start address corresponding to the maskable interrupt IR6. Therefore, the area of addresses 0060[H] to 006D[H] for storing the table data included in the interrupt vector table XTBL_INTR can correspond to an address storage area capable of storing the address of the interrupt processing program.

When the value stored in the interrupt mask register is 7E[H], only the maskable interrupt IR0 is enabled and the other maskable interrupts IR1 to IR6 are disabled. , addresses 0060[H] and 0061[H] are used data for specifying the interrupt processing start address, while table data at addresses 0062[H] to 006D[H] are unused data. . For example, the table data of address 0060 [H] indicates the lower address, which is the lower byte of the start address, for timer interrupt processing P_PCT for game control. The table data of address 0061 [H] indicates the upper address which is the upper byte of the start address for timer interrupt processing P_PCT for game control. As a result, the program that becomes the timer interrupt process P_PCT for game control becomes an interrupt process program whose address is stored by the interrupt vector table XTBL_INTR. On the other hand, in the table data of addresses 0062[H] to 006D[H], 12-byte zero data with a storage value of 00[H] is interrupt vector unused data. In this way, the area of addresses 0062[H] to 006D[H] is an area in which unused data is stored, unlike an area in which programs executed by the CPU 103 and data used in executing the programs are stored. Become. Therefore, the area of addresses 0062[H] to 006D[H] is included in the special storage area storing unused data indicating 0 at the special address.

When the area of addresses 0060[H] to 006D[H] for storing table data contained in the interrupt vector table XTBL_INTR is used as an address storage area, the area to which addresses 0062[H] to 006D[H] are assigned is a special Contained in a special storage area with an assigned address. In this case, the special storage area includes an area in which unused data is stored in the address storage area. The area assigned addresses 0062[H] to 006D[H] has a total storage capacity of 12 bytes. Therefore, when the area of addresses 0060[H] to 006D[H] serves as an address storage area, a special address is assigned in this address storage area and unused data indicating 0 is stored. The capacity is 12 bytes.

Thus, the game program area includes an area in which unused data indicating 0 is stored. In the game program area, an area in which unused data indicating 0 is stored may correspond to a special storage area to which a special address is assigned. In addition, the total storage capacity of the special storage area in which the unused data indicating 0 is stored with the special address assigned in the restart area is 7 bytes. When the area of addresses 0060[H] to 006D[H] for storing the table data included in the interrupt vector table XTBL_INTR serves as an address storage area, unused data indicating 0 is assigned a special address in this address storage area. The total storage capacity of the special storage area in which is stored is 12 bytes. Thus, the total storage capacity of the special storage area in the game program area is 19 bytes. The total storage capacity of the unused storage areas corresponding to unused storage areas capable of storing unused data between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area is 1069 bytes. is. Therefore, the total storage capacity of the special storage area is 19 bytes, which is smaller than the total storage capacity of the unused area, 1069 bytes.

The total memory capacity of the game program area corresponding to the first memory area is greater than the total memory capacity of the unused memory area that can store unused data between the first memory area and the second memory area. is also big. When such a first storage area includes a special storage area, the total storage capacity of the special storage area is smaller than the total storage capacity of the unused area. This increases the possibility of identifying the unused area and the special storage area, and enables appropriate storage area management so as to prevent misidentification of these areas.

Then, the special storage area to which special addresses are assigned in the restart area includes a plurality of areas to which discontinuous addresses are assigned. For example, the area of addresses 0035[H] to 0037[H] shown in FIG. 11-4(A) and the area of address 003F[H] shown in FIG. 11-4(B) are both special It may correspond to multiple areas contained in the storage area and assigned non-contiguous addresses. In addition, in the area from the address 0010 [H], which is the restart address where the program module of the time saving check process P_JTN_CHK is stored, to the address 0018 [H], which is the next restart address, 1 byte of unused data is The stored area is included in the special storage area, and can be included in a plurality of areas assigned addresses that are discontinuous from the special storage areas provided in the other restart areas. In the area from address 0020 [H], which is one restart address in which the program module of the 2-byte data selection process P_ABXEXC is stored, to address 0028 [H], which is the next restart address, 2 bytes of unused data are stored. The stored area is included in the special storage area, and can be included in a plurality of areas assigned addresses that are discontinuous from the special storage areas provided in the other restart areas. Therefore, the special memory area in which the unused data indicating 0 is stored and to which special addresses are assigned in the restart area includes a plurality of areas to which discontinuous addresses are assigned as special addresses.

Discrete addresses are assigned to the special storage area to which the special address is assigned in the restart area and the special storage area to which the special address is assigned in the area storing the table data included in the interrupt vector table XTBL_INTR. . The area for storing the table data included in the interrupt vector table XTBL_INTR is the area of addresses 0060 [H] and 0061 [H] among the areas of addresses 0060 [H] to 006D [H]. Program addresses are stored for P_PCT, and unused data indicating 0 is stored in the area of addresses 0062[H] to 006D[H]. Therefore, the special storage area to which the special address is assigned in the area for storing the table data included in the interrupt vector table XTBL_INTR is different from the special storage area to which the special address is assigned in the restart area. Contained in multiple regions.

In this way, the unused data storage addresses in the setting example 003AKA01 are assigned discontinuous addresses as special addresses in the special storage area, so that unused data indicating 0 are stored by assigning consecutive addresses. Unlike the unused area, unused data indicating 0 is less likely to be stored in the area where the special addresses are consecutive in the special storage area. This increases the possibility of identifying the unused area and the special storage area, and enables appropriate storage area management so as to prevent misidentification of these areas.

The total storage capacity of special storage areas to which special addresses are assigned in the restart area is smaller than the total storage capacity of special storage areas to which special addresses are assigned in the area storing table data included in interrupt vector table XTBL_INTR. As a result, the program modules are stored by efficiently using the memory area serving as the restart area, so that an increase in memory capacity in the game program area can be prevented. Also, the special storage area to which the special address is assigned in the restart area includes a plurality of areas to which discontinuous addresses are assigned, while the area for storing the table data included in the interrupt vector table XTBL_INTR is assigned a special address. The assigned special storage area includes a single area assigned consecutive addresses. In this case, the possibility of identifying the special memory area in the unused area and the restart area is higher than the possibility of identifying the special memory area in the unused area and the address memory area. Appropriate storage area management becomes possible so as to reliably prevent misrecognition of

Depending on the structure of the program modules and table data stored in the restart area, there may be cases where the restart area does not have a special storage area in which unused data indicating 0 is stored by allocating a special address. In addition, depending on the configuration of the interrupt program corresponding to multiple interrupt factors, a special storage area in which a special address is assigned to store table data included in the interrupt vector table XTBL_INTR and unused data indicating 0 is stored. Sometimes they don't. As described above, depending on the specifications of the pachinko machine 1, the special storage area may not include an area in which unused data is stored in the area from one specific address to the next specific address included in a plurality of specific addresses. There may be. Also, depending on the specifications of the pachinko gaming machine 1, the special storage area may not include an area where unused data is stored in the address storage area.

The zero data with a storage value of 00 [H] in the game program area is not limited to unused data that is not used for program execution, but may include use data that is used for program execution. . For example, when the interrupt vector table high-order address is set by step AKS8 of the power supply start corresponding processing P_POWER_ON, the high-order byte of the interrupt vector table address is directly specified by the operand in the transfer instruction for setting the internal register of the CPU 103. . Since the upper byte of the interrupt vector table address is 00 [H], zero data with a storage value of 00 [H] is stored in the game program area as use data used to set the interrupt vector table upper address. . Further, for example, when the access permission output value is stored in the RWM access protect register by step AKS14 of the power supply start corresponding processing P_POWER_ON, the address of the RWM access protect register is set by the operand in the transfer instruction for setting the internal register of the CPU 103. specified directly. The RWM access protect register is provided at the head of the function control register area as in the setting example AKA02, and is assigned an address FF00[H]. Therefore, zero data with a storage value of 00[H] is stored in the game program area as use data used to designate the lower byte of the address of the RWM access protect register.

In addition, for example, when the backup monitoring timer clear data is stored by step AKS34 of the power-off processing P_POWER_OFF, zero data indicating 00 [H] as the clear data is an operand in the transfer instruction that can update the stored data at the address pointed by the pointer. specified directly by Therefore, zero data with a storage value of 00 [H] is stored in the game program area as use data used for storing clear data in the backup monitor timer. For example, when clear data is stored in the RWM access protect register by step AKS42 of the power-off process P_POWER_OFF, the address of the RWM access protect register is directly specified by the operand in the transfer instruction. Therefore, zero data with a storage value of 00[H] is stored in the game program area as use data used to designate the lower byte of the address of the RWM access protect register. Furthermore, in the power failure recovery time vector table such as the setting example AKT11, the table data of addresses 0016 [H] and 0017 [H] specify the address 0000 [H] which is the start address for the main processing P_MAIN for game control It is used data for The power failure recovery vector table is used to set the stored value of the program counter when an interrupt return instruction is executed after the address is set in the stack pointer by step AKS50 of the power failure process P_POWER_OFF. In this way, the table data included in the power-off recovery time vector table is used as addressing data that enables the main processing P_MAIN for game control, which is the start-up processing based on the start-up of the pachinko gaming machine 1, to be executed from the beginning. . Therefore, zero data with a storage value of 00 [H] is stored in the game program area as addressing data that enables execution of the start-up process from the beginning.

Thus, the game program area includes an area in which use data indicating 0 is stored. In the game program area, an area in which usage data indicating 0 is stored may correspond to a predetermined storage area to which a predetermined address is assigned. In this case, the total storage capacity of the predetermined storage area is an unused storage area capable of storing unused data between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area. It should be smaller than the total storage capacity of the corresponding unused area. The total storage capacity of the special storage area and the predetermined storage area is an unused storage area capable of storing unused data between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area. It should be smaller than the total storage capacity of the corresponding unused area.

Further, the predetermined storage area to which the predetermined address is assigned in the game program area may include a plurality of areas to which discontinuous addresses are assigned. For example, addresses 0016 [H] and 0017 [H] of table data included in a power-off recovery time vector table such as setting example AKT11, addresses storing use data used in step AKS34 of power-off processing P_POWER_OFF, power supply The addresses storing the use data used in the address AKS42 of the power-off process P_POWER_OFF may be set so as to be discontinuous addresses. In this case, the use data stored in the predetermined storage area is, for example, the table data included in the power failure recovery time vector table, such as the setting example AKT11. Contains addressing data that enables

It should be noted that the use data stored in the predetermined storage area, ROM101 and RAM102, the upper byte of the address assigned to any memory area in the built-in register of the game control microcomputer 100, the lower byte, or the upper byte and lower byte It may contain any addressable addressing data, such as both bytes. The use data stored in the predetermined storage area may include stored value setting data that can be used when setting stored values in arbitrary registers, counters, timers, and other memory areas. The use data indicating 0 that can be used when setting the stored value of the register is also referred to as register initial setting data. The use data indicating 0 that can be used when setting the stored value of the counter is also called counter initial setting data. The use data indicating 0 that can be used when setting the stored value of the timer is also called timer initial setting data.

Depending on the structure of the program or table data stored in the game program area, there may be a case where the game program area does not have a predetermined storage area in which use data indicating 0 is stored by allocating a predetermined address. Also, depending on the configuration of the programs and table data stored in the game program area, for example, in the area storing the table data of the vector table at the time of power failure recovery, a predetermined address is assigned and use data indicating 0 is stored. It may not have a predetermined storage area. In addition, there may be cases where the area in which arbitrary addressing data is stored does not have a predetermined storage area in which a predetermined address is assigned and use data indicating 0 is stored. There may be a case where there is no prescribed storage area for storing use data indicating 0, to which a prescribed address is assigned, as the area for storing the register initialization data. In some cases, there is no predetermined storage area in which the use data indicating 0 is stored in which a predetermined address is assigned as the area in which the counter initial setting data is stored. There may be a case where there is no predetermined storage area in which use data indicating 0 is stored in which a predetermined address is assigned as an area for storing timer initial setting data. As described above, due to the specifications of the pachinko game machine 1, even if the game program area corresponding to the first storage area does not include the normal storage area in which the predetermined address is assigned and the use data indicating 0 is stored. good. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the predetermined storage area may not include the addressing data that enables the start-up processing based on the startup of the gaming machine from the beginning. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the predetermined storage area may not include addressing data that can specify any address. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the predetermined storage area may not include setting data that can be stored in any storage area.

FIG. 11-6 shows a setting example 003AKA11 of zero data that becomes unused data or used data in the game data area included in the memory area of the ROM 101. FIG. The zero data having a stored value of 00[H] in the game data area includes a case of used data used for program execution and a case of unused data not used for program execution. The data stored in the game data area can constitute table data included in various tables. In setting example 003AKA11, the table data start address is the start address of table data included in various tables. The table data end address is the end address of table data included in various tables. The zero data amount is the number of bytes that constitute the storage capacity of the area in which zero data, which is unused data or used data, is stored. Therefore, the table data start address is the start address of data available for program execution, and the table data end address is the end address of data available for program execution. However, the data that can be used for program execution may include data that is not used for program execution due to various instructions and settings in the implemented program.

In the game data area included in the memory area of the ROM 101, the area of addresses 1200[H] to 121D[H] contains the display device control table XD_DG, the first special symbol display control table XD_TOKUZU1, the second special symbol display control table XD_TOKUZU2, Corresponding to each of the first special symbol buffer shift control table XD_TBUFSHIFT1, the second special symbol buffer shift control table XD_TBUFSHIFT2, and the normal symbol stop display table XD_FZU_STOP, the table data included therein are stored. The area of addresses 121E[H] to 1227[H] stores the table data included in the normal pattern reserved storage number display table XD_FMEM. The area of addresses 1228[H] to 1231[H] stores table data included in the first reserved storage number display table XD_TMEM1. The area of addresses 1232[H] to 123B[H] stores table data included in the second reserved storage number display table XD_TMEM2. The area of addresses 123C[H] to 1247[H] stores table data included in the variation pattern command distribution selection table XP_TPAT_TBL. The area of addresses 1248[H] to 1250[H] stores table data included in the right-handed round number display table XD_TOKU1. The area of addresses 1251[H] to 1258[H] stores table data included in the solenoid pattern distribution selection table XP_YSOL_SEL.

In the game data area, in the area where table data included in various tables are stored, zero data with a storage value of 00 [H] may be stored as use data indicating 0. In addition, in the game data area, the area where table data included in various tables is stored may store zero data with a storage value of 00 [H] as unused data indicating 0.

FIG. 11-7 shows a storage example of table data included in various tables. The normal figure pending storage number display table XD_FMEM shown in FIG. 11-7(A) has a table data start address of 121E [H] and a table data end address of 1227 [H]. The general pattern reserved memory number display table XD_FMEM is used to execute a program that controls the display of the general pattern reserved memory number in the general pattern reservation display 25C, and the general pattern reserved memory number corresponds to "0" to "4". It contains table data that will be the display data. The first reserved storage count display table XD_TMEM1 shown in FIG. 11-7(B) has a table data start address of 1228 [H] and a table data end address of 1231 [H]. The first reserved memory number display table XD_TMEM1 is used to execute a program that controls the display of the first reserved memory number on the first reserved display device 25A, and the first reserved memory number corresponds to "0" to "4". It contains table data that will be the display data. The right-handed round number display table XD_TOKU1 shown in FIG. 11-7(C) has a table data start address of 1248 [H] and a table data end address of 1250 [H]. The right-handed round number display table XD_TOKU1 is used to execute a program that controls the display of the right-handed indicator lamp and the light-emitting member that serves as the round number indicator, and displays display data corresponding to the jackpot game state and the number of rounds. contains a table of data.

The storage data at addresses 121E[H] and 121F[H] shown in FIG. bytes. These stored data are zero data of a total of 2 bytes with a storage value of 00[H]. The storage data of addresses 1220[H] and 1221[H] are the first and second bytes of the display data used corresponding to the number of normal pattern reserved storage "1". Among them, the storage data at address 1221 [H] is 1-byte zero data with a storage value of 00 [H]. The storage data at addresses 1222[H] and 1223[H] are the first and second bytes of the display data used corresponding to the number of normal-pattern reserved storage "2". Among them, the storage data at address 1223[H] is 1-byte zero data with a storage value of 00[H]. The storage data at addresses 1224[H] and 1225[H] are the first and second bytes of the display data used corresponding to the number of normal-pattern reserved storage "3". These stored data are all non-zero data with storage values other than 00[H]. The storage data at addresses 1226[H] and 1227[H] are the first and second bytes of the display data used corresponding to the number of normal-pattern reserved storage "4". These stored data are all non-zero data with storage values other than 00[H].

The general pattern holding display device 25C is configured using a light emitting body such as two LEDs, and can change the light emission state corresponding to the first byte of the display data read from the general pattern holding storage number display table XD_FMEM. 1 light emitting unit and a second light emitting unit capable of changing the light emitting state in accordance with the second byte of the display data read from the normal figure reserved storage number display table XD_FMEM. The general pattern suspension display 25C may be able to display the number of general pattern suspension storage in a recognizable manner by the light emitting states of the first light emitting unit and the second light emitting unit. The first and second light emitting units of such a normal map holding display 25C can correspond to light emitting means. For example, the first light emitting unit of the normal pattern pending display 25C is turned off corresponding to 00 [H] in the first byte in the display data read from the normal pattern pending storage number display table XD_FMEM, and the first byte is 20 Lighting corresponding to [H] and flashing corresponding to the first byte corresponding to 24 [H] is sufficient. In addition, the second light-emitting part of the normal pattern holding display 25C is turned off corresponding to 00 [H] in the second byte in the display data read from the normal pattern holding storage number display table XD_FMEM, and the second byte is 20. Lighting corresponding to [H] and flashing corresponding to the second byte corresponding to 24 [H] is sufficient. Table data at addresses 121E[H], 121F[H], 1221[H], and 1223[H] in the general pattern reserved storage number display table XD_FMEM are used data used for program execution. It becomes zero data of 00 [H]. Therefore, areas of addresses 121E[H], 121F[H], 1221[H] and 1223[H] are included in the normal storage area storing use data indicating 0 at normal addresses. In this case, the usage data stored in the normal storage area includes extinguishing control data that can be used to extinguish the light emitting means.

The storage data at addresses 1228[H] and 1229[H] shown in FIG. bytes. These stored data are zero data of a total of 2 bytes with a storage value of 00[H]. The stored data at addresses 122A[H] and 122B[H] are the first and second bytes of the display data used corresponding to the first reserved storage number "1". Among them, the stored data at address 122B[H] is 1-byte zero data with a stored value of 00[H]. The stored data at addresses 122C[H] and 122D[H] are the first and second bytes of the display data used corresponding to the first reserved storage number "2". Among them, the storage data at address 122D[H] is 1-byte zero data with a storage value of 00[H]. The stored data at addresses 122E[H] and 122F[H] are the first and second bytes of the display data used corresponding to the first reserved storage number "3". These stored data are all non-zero data with storage values other than 00[H]. The storage data at addresses 1230[H] and 1231[H] are the first and second bytes of the display data used corresponding to the first reserved storage number "4". These stored data are all non-zero data with storage values other than 00[H].

The first reservation display 25A is configured using a light emitter such as two LEDs, and is capable of changing the light emission state corresponding to the first byte of the display data read from the first reservation storage number display table XD_TMEM1. 1 light emitting unit and a second light emitting unit capable of changing the light emitting state corresponding to the second byte of the display data read from the first reserved storage number display table XD_TMEM1. The first pending display 25A only needs to be able to display the first pending stored number in a recognizable manner by means of the light emitting states of the first light emitting section and the second light emitting section. The first light emitting portion and the second light emitting portion of the first suspension display 25A may correspond to light emitting means. For example, the first light emitting unit of the first pending display 25A is turned off when the first byte corresponds to 00 [H] in the display data read from the first pending memory count display table XD_TMEM1, and the first byte is 80. Lighting corresponding to [H] and flashing corresponding to the first byte corresponding to 90 [H] is sufficient. In addition, the second light emitting unit of the first reservation display 25A is turned off when the second byte corresponds to 00 [H] in the display data read from the first reservation storage number display table XD_TMEM1, and the second byte is 80. Lighting corresponding to [H] and flashing corresponding to the second byte corresponding to 90 [H] are sufficient. In the first reserved memory number display table XD_TMEM1, table data at addresses 1228[H], 1229[H], 122B[H], and 122D[H] are used data used for program execution. It becomes zero data of 00 [H]. Therefore, areas of addresses 1228[H], 1229[H], 122B[H] and 122D[H] are included in the normal storage area storing use data indicating 0 at normal addresses. In this case, the usage data stored in the normal storage area includes extinguishing control data that can be used to extinguish the light emitting means.

The storage data of address 1248[H] shown in FIG. 11-7(C) is display data used for 2 rounds with the number of rounds "2" in the jackpot game state. The stored data at address 1249[H] is display data used for 3 rounds with the number of rounds "3" in the jackpot game state. The stored data at address 124A[H] is display data used for 4 rounds with the number of rounds "4" in the jackpot game state. These stored data are non-zero data with storage values other than 00[H]. The stored data at the address 124B[H] is display data corresponding to 5 rounds of the number of rounds "5" in the jackpot game state. The stored data at the address 124C[H] is display data corresponding to 6 rounds of the number of rounds "6" in the jackpot game state. According to the specifications of the pachinko game machine 1, when the number of rounds in the jackpot game state is not set to "5" or "6", the table data of addresses 124B[H] and 124C[H] become unused data. Thus, the areas of addresses 124B[H] and 124C[H] are areas in which unused data are stored, unlike areas in which data used by the CPU 103 for program execution can be stored. The stored data at address 124D[H] is display data used for 7 rounds with the number of rounds "7" in the jackpot game state. The stored data at the address 124E[H] is display data corresponding to 8 rounds of the number of rounds "8" in the jackpot game state. The stored data at the address 124F[H] is display data corresponding to 9 rounds of the number of rounds "9" in the jackpot game state. According to the specifications of the pachinko game machine 1, when the number of rounds in the jackpot game state is not set to "8" or "9", table data of addresses 124E[H] and 124F[H] become unused data. Thus, the areas of addresses 124E[H] and 124F[H] are areas in which unused data are stored, unlike areas in which data used by the CPU 103 for program execution can be stored. The stored data at address 1250[H] is display data used for 10 rounds of the number of rounds "10" in the jackpot game state.

The right-handed indicator lamp and the light-emitting member that serves as the number-of-rounds indicator include one or more light-emitting units that can change the light-emitting state in accordance with the display data read from the number-of-right-handed rounds display table XD_TOKU1. should be The light-emitting member that serves as a right-handed indicator light and the light-emitting member that serves as a round number indicator should be able to recognizably display the right-handed notification and the number of rounds corresponding to the jackpot game state by the light emitting state of the light emitting portion. Such a light-emitting member that serves as a right-handed indicator lamp and a light-emitting member that serves as a round number indicator can correspond to the light-emitting means. Table data at addresses 124B[H], 124C[H], 124E[H], and 124F[H] in the right-handed round number display table XD_TOKU1 are unused data that are not used for program execution, and the stored value is 00[ H]. Therefore, the areas of addresses 124B[H], 124C[H], 124E[H] and 124F[H] are included in the special memory area storing unused data indicating 0 at the special address. In this case, the unused data stored in the special storage area includes state-related data corresponding to the number of rounds different from the number of rounds executable in an advantageous state advantageous to the player, such as a jackpot game state.

In addition, as shown in FIG. 11-6, in the second reserved storage number display table XD_TMEM2, address 1232[H] is the table data start address and address 123B[H] is the table data end address. The area of addresses 1232[H] to 123B[H] stores 4-byte zero data with a storage value of 00[H], and a normal storage area in which use data indicating 0 at a normal address is stored. including. In the variation pattern command distribution selection table XP_TPAT_TBL, address 123C[H] is the table data start address and address 1247[H] is the table data end address. The area of addresses 123C[H] to 1247[H] stores 1-byte zero data with a storage value of 00[H], and is a normal storage area storing use data indicating 0 at a normal address. including. In the solenoid pattern distribution selection table XP_YSOL_SEL, address 1251 [H] is the table data start address and address 1258 [H] is the table data end address. The area of addresses 1251 [H] to 1258 [H] stores 2-byte zero data with a storage value of 00 [H], and a normal storage area storing use data indicating 0 at a normal address. including.

In this way, the game data area stores zero data with a storage value of 00[H], a normal storage area storing use data indicating 0 at a normal address, and an unused data area indicating 0 at a special address. and a special storage area in which is stored. The use data stored in the normal storage area includes extinguishing control data that can be used to extinguish the light emitting means. The unused data stored in the special storage area includes state-related data corresponding to a number of rounds different from the number of rounds that can be executed in an advantageous state advantageous to the player.

In this case, the game data area includes a normal storage area storing 216 bytes of zero data as used data and a special storage area storing 19 bytes of zero data as unused data. In addition, the game data area stores zero data with a storage value of 00 [H], and the normal storage area stores use data indicating 0 at the normal address. include. Zero data with a storage value of 00 [H] is stored in the game data area, and unused data indicating 0 is stored in the special address. The special storage area includes a plurality of areas to which discontinuous addresses are assigned. . In the game data area, zero data with a storage value of 00 [H] is stored, and in the normal storage area where use data indicating 0 is stored in the normal address, an area of a specific number of bytes or more, such as 16 bytes, is stored. Ordinary addresses are assigned in a non-contiguous manner. Zero data with a storage value of 00 [H] is stored in the game data area, and unused data indicating 0 is stored in the special address. A special address is assigned to prevent

The use data indicating 0 stored in the normal storage area is a table that can be used as an offset value for setting a reference table address when selecting a table using various designated values or random values. It may also contain selection data. Use data indicating 0 stored in the normal storage area is a variation pattern that can be used as an offset value for setting a reference variation pattern when determining a variation pattern using various specified values and random values. It may also include decision data. In addition, the use data indicating 0 stored in the normal storage area is a decision value setting that can be used to set a reference decision value when deciding the control mode using various specified values and random numbers. may contain data.

Thus, the game data area includes an area in which use data indicating 0 is stored and an area in which unused data indicating 0 is stored. In the game data area, an area in which usage data indicating 0 is stored may correspond to a normal storage area to which a normal address is assigned. In the game data area, an area in which unused data indicating 0 is stored may correspond to a special storage area to which a special address is assigned. The total storage capacity of the normal memory area in which the normal address is assigned in the game data area and the use data indicating 0 is stored is 216 bytes. The total storage capacity of the special storage area in which the unused data indicating 0 is stored with the special address assigned in the game data area is 19 bytes. The total storage capacity of unused storage areas between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area is 1069 bytes. The total storage capacity of unused storage areas between the game data area corresponding to the second storage area and the non-game program area and non-game data area corresponding to the third storage area is 1228 bytes. . Therefore, the total storage capacity of the normal storage area of 216 bytes is smaller than the total storage capacity of the unused storage area of 2297 bytes. Also, the total storage capacity of 235 bytes of the normal storage area and the special storage area is smaller than the total storage capacity of the unused storage area of 2297 bytes. This increases the possibility of distinguishing the unused area from the normal storage area, and enables appropriate storage area management so as to prevent misidentification of these areas. In addition, the possibility of identifying unused areas, normal storage areas, and special storage areas is increased, and appropriate storage area management is enabled so as to prevent misidentification of these areas.

Then, the normal storage area to which normal addresses are assigned in the game data area includes a plurality of areas to which discontinuous addresses are assigned. For example, areas of addresses 121E[H], 121F[H], 1221[H], and 1223[H] shown in FIG. 11-7(A), and address 1228[H] shown in FIG. H], 1229[H], 122B[H], and 122D[H] are all included in the normal storage area and can correspond to a plurality of areas to which discontinuous addresses are assigned. In addition, 4-byte zero data in the area from address 1232 [H], which is the table data start address where the table data of the second reserved storage number display table XD_TMEM2 is stored, to address 123B [H], which is the table data end address is stored as use data is included in the normal storage area, and can be included in a plurality of areas to which addresses are assigned discontinuously from other normal storage areas provided in the game data area. 1-byte zero data is used in the area from address 123C [H], which is the table data start address where the table data of the fluctuation pattern command distribution selection table XP_TPAT_TBL is stored, to address 1247 [H], which is the table data end address. The area stored as data is included in the normal storage area, and can be included in a plurality of areas to which addresses are assigned discontinuously from other normal storage areas provided in the game data area. In the area from the table data start address address 1251 [H] to the table data end address address 1258 [H] where the table data of the solenoid pattern distribution selection table XP_YSOL_SEL is stored, 2-byte zero data is used as data. The stored area is included in the normal storage area, and can be included in a plurality of areas to which addresses are assigned discontinuously from other normal storage areas provided in the game data area. Therefore, the normal storage area in which normal addresses are assigned and use data indicating 0 is stored in the game data area includes a plurality of areas in which discontinuous addresses are assigned as normal addresses. This increases the possibility of distinguishing the unused area from the normal storage area, and enables appropriate storage area management so as to prevent misidentification of these areas.

The special storage area to which special addresses are assigned in the game data area includes a plurality of areas to which discontinuous addresses are assigned. For example, the areas of addresses 124B[H], 124C[H], 124E[H], and 124F[H] shown in FIG. It may correspond to multiple assigned regions. In addition, in the area where table data contained in an arbitrary table is stored, the area where zero data is stored as unused data is included in the special storage area, and is different from other special storage areas provided in the game data area. can be included in multiple areas to which discontinuous addresses are assigned. Therefore, the special storage area in which the unused data indicating 0 is stored by assigning special addresses in the game data area includes a plurality of areas to which discontinuous addresses are assigned as special addresses. This increases the possibility of identifying unused areas, normal storage areas, and special storage areas, and enables appropriate storage area management so as to prevent misidentification of these areas.

Depending on the configuration of the table data stored in the game data area, there may be cases where the game data area does not have a normal storage area in which use data indicating 0 is stored, to which a normal address is assigned. Also, depending on the configuration of the table data stored in the game data area, the game data area may not have a special storage area in which unused data indicating 0 is stored, to which a special address is assigned. As described above, due to the specifications of the pachinko game machine 1, even if the game data area corresponding to the second storage area does not include the normal storage area in which the normal address is assigned and the use data indicating 0 is stored. good. Also, depending on the specifications of the pachinko game machine 1, the game data area corresponding to the second storage area may not include a special storage area in which unused data indicating 0 is stored and assigned a special address. .

Depending on the structure of the table data stored in the game data area, for example, in the area where the table data of the normal figure reserved memory number display table XD_FMEM and the first reserved memory number display table XD_TMEM1 are stored, normal addresses are assigned and 0 It may not have a regular storage area where the indicated usage data is stored. Also, for example, the area storing the table data of the right-handed round number display table XD_TOKU1 may not have a special storage area in which a special address is assigned and unused data indicating 0 is stored. As described above, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the normal storage area may not include extinguishing control data that can be used to extinguish the light emitting means. Also, according to the specifications of the pachinko game machine 1, the unused data stored in the special storage area may not include state-related data corresponding to the number of rounds different from the number of rounds that can be executed in an advantageous state advantageous to the player. There may be

FIG. 11-8 shows an output example 003AKB01 of the dump list. The dump list is an output of the memory contents of each area to which addresses are assigned in the address map, and can be displayed using any display device or printed using any printing device. . The contents stored in the memory area of the ROM 101 or the like are output in units of a predetermined data size, such as 16 bytes, according to a dump list. In the dump list of the output example 003AKB01, a plurality of horizontal display lines correspond to different upper bytes of addresses in the address map. In the dump list of output example 003AKB01, a plurality of display columns representing vertical alignment correspond to different lower bytes of addresses in the address map. Thus, when the dump list is output in association with the upper and lower bytes of the address, the unit size of the program and data that can be displayed on one display line is 16 bytes.

In this case, between the game program area and the game data area, between the game data area and the non-game program area and the non-game data area, etc., the unused areas capable of storing unused data are equal to the total storage capacity is greater than a specific number of bytes, and all zero data with a storage value of 00[H] is stored as unused data indicating 0. In a dump list such as the output example 003AKB01, zero data with a storage value of 00 [H] is displayed continuously over multiple display lines because the total storage capacity of the unused area is greater than the specified number of bytes. Therefore, unused areas can be easily identified. On the other hand, in the game program area and the game data area, when consecutive addresses are assigned to areas in which zero data with a storage value of 00 [H] are stored, the data are displayed consecutively in the dump list. It may be difficult to distinguish between unused areas. Therefore, in the game program area and the game data area, addresses are assigned so that the areas in which zero data with a storage value of 00 [H] are stored are not contiguous with areas of a specific number of bytes or more.

The game program area includes a special storage area storing unused data indicating 0 at a special address. In this special storage area, the portion to which consecutive addresses are assigned is a 12-byte area from addresses 0062[H] to 006D[H] of the area for storing table data contained in the interrupt vector table XTBL_INTR. is. In this way, special addresses are assigned to the special storage areas so that areas of 16 bytes or more, which is a specific number of bytes, do not continue. As a result, the unused area and the special storage area can be easily identified, and appropriate storage area management is possible so as to prevent erroneous recognition of these areas.

The game program area includes a predetermined storage area storing use data indicating 0 at a predetermined address. In this predetermined storage area, the portion to which consecutive addresses are assigned may be, for example, a 2-byte area of addresses 0016 [H] and 0017 [H] for storing table data included in the power failure recovery vector table. Just do it. In this manner, predetermined addresses are assigned to the predetermined storage areas so that areas of 16 bytes or more, which is a specific number of bytes, are not continuous. As a result, the unused area and the predetermined storage area can be easily identified, and appropriate storage area management is possible so as to prevent misidentification of these areas.

The game data area includes a normal storage area storing use data indicating 0 at a normal address. In this normal storage area, the portion to which consecutive addresses are assigned is, for example, two bytes of addresses 121E [H] and 121F [H] in the area for storing table data included in the normal figure reserved storage number display table XD_FMEM. , or a 2-byte area with addresses 1228[H] and 1229[H] in the area for storing the table data included in the first reserved storage number display table XD_TMEM1. In this way, normal addresses are assigned to the normal storage areas so that areas of 16 bytes or more, which is a specific number of bytes, are not continuous. As a result, the unused area and the normal storage area can be easily identified, and proper storage area management is possible so as to prevent misidentification of these areas.

The game data area includes a special storage area in which unused data indicating 0 at a special address is stored. In this special storage area, the portion to which consecutive addresses are assigned is, for example, two bytes of addresses 124B[H] and 124C[H] in the area for storing the table data contained in the right-handed round number display table XD_TOKU1. or an area corresponding to 2 bytes of addresses 124E[H] and 124F[H]. In this way, specific addresses are assigned to the special storage areas so that areas of 16 bytes or more, which are the specific number of bytes, are not continuous. As a result, the unused area and the special storage area can be easily identified, and appropriate storage area management is possible so as to prevent misidentification of these areas.

The game data area includes a normal storage area storing use data indicating 0 at a normal address and a special storage area storing unused data indicating 0 at a special address. Therefore, depending on the arrangement of the normal storage area and the special storage area, it may be difficult to distinguish between the game data area and the adjacent unused area. Therefore, the game data area stores data indicating values other than 0 at the start address and the end address. For example, since the game data area is an area of addresses 1200 [H] to 1D33 [H], non-zero data with a storage value other than 00 [H] is stored at the start address 1200 [H], and the end address 1D33 [H] stores non-zero data with a storage value other than 00 [H]. In a dump list like output example 003AKB01, at address 1200[H], which is the start address of the game data area, the stored value is 08[H] other than 00[H], and address 1D33[H], which is the end address of the game data area. H], by setting the stored value to 02[H] other than 00[H], data indicating a value other than 0 is stored. As a result, it is possible to easily identify the unused area and the game data area arranged before and after the game data area, and it is possible to appropriately manage the storage areas so as to prevent misidentification of them.

Further, the game data area stores data indicating other than 0 at the address next to the start address and the address before the end address. For example, since the start address of the game data area is address 1200[H], non-zero data with a storage value other than 00[H] is stored at the next address 1201[H]. Since the end address of the game data area is 1D33[H], non-zero data having a storage value other than 00[H] is stored at the previous address 1D32[H]. In a dump list such as the output example 003AKB01, the start address of the game data area is 1200[H], and at the next address 1201[H], the stored value is changed to 10[H] other than 00[H], and the game data The end address of the area is 1D33[H], and by setting the storage value to 2B[H] other than 00[H] at the previous address 1D32[H], data indicating a value other than 0 is stored. ing. Thus, the game data area stores data other than 0 in a continuous 2-byte area after the start address including the start address and a continuous 2-byte area before the end address including the end address. be done. As a result, it is possible to more easily identify unused areas and game data areas placed before and after the game data area, and it is possible to appropriately manage storage areas so as to reliably prevent misidentification of these areas. become.

In addition, it is not limited to a continuous 2-byte area, but an area allocated with a plurality of continuous addresses after the start address including the start address of the game data area, and before the end address including the end address of the game data area Data indicating a value other than 0 may be stored corresponding to an area to which a plurality of consecutive addresses are assigned. For example, a non-zero range including a plurality of addresses is preset, a non-zero range area after the start address including the start address of the game data area, and a non-zero range before the end address including the end address of the game data area , and data indicating values other than 0 may be stored corresponding to . In this case, the non-zero range set corresponding to the start address of the game data area and the non-zero range set corresponding to the end address of the game data area have address ranges of different sizes. may For example, a post-start non-zero range and a pre-end non-zero range having an address range different in size from the post-start non-zero range are preset as non-zero ranges including a plurality of addresses. Then, corresponding to the post-start non-zero range area after the start address including the start address of the game data area and the pre-end non-zero range area before the end address including the end address of the game data area. Data indicating other than 0 may be stored. Arbitrary storage areas different from the unused areas in the memory area of the ROM 101, such as the game program area, the non-game program area, and the non-game data area, are provided corresponding to the start address and the end address in the same way as the game data area. Program code or data representing a non-zero value may be stored in the non-zero range area defined. However, for example, like the program management area, zero data with a storage value of 00 [H] is stored in the area of the zero setting range before the end address including the end address, corresponding to the setting based on the specifications of the pachinko game machine 1 may be stored.

Total storage capacity of first storage area, total storage capacity of second storage area, total storage capacity of unused storage area, total storage capacity of special storage area, total storage capacity of normal storage area, normal storage area and special storage area can be arbitrarily changed according to the specifications of the pachinko game machine 1. However, the total storage capacity of the first storage area should be larger than the total storage capacity of unused storage areas capable of storing unused data between the first storage area and the second storage area. The total storage capacity of the special storage area should be smaller than the total storage capacity of unused storage areas capable of storing unused data between the first storage area and the second storage area. The total storage capacity of the second storage area is unused storage capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area. It should be larger than the total storage capacity of the area. The total storage capacity of the normal storage area is an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area. is smaller than the total storage capacity of The total storage capacity of the normal storage area and the special storage area is such that unused data can be stored between the first storage area and the second storage area and between the second storage area and the third storage area. It should be smaller than the total storage capacity of unused storage areas.

The special storage area, the predetermined storage area, the normal storage area, and the special storage area may be assigned addresses so that areas of any specific number of bytes, not limited to 16 bytes, are not contiguous. For example, the specific number of bytes may be any number of bytes different from 16 bytes, such as 8 bytes, 32 bytes, or 64 bytes. The special storage area, the predetermined storage area, the normal storage area, and the special storage area are any specific number of bytes or more that can be easily recognized as a storage area different from the unused storage area when, for example, a dump list is displayed. Any address may be assigned so that the areas are not contiguous.

(Problem Solving Means and Effects of Characteristic Portion 003AK)
[1-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by a program stored in the storage means;
The memory means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
an unused storage area capable of storing unused data between the first storage area and the second storage area;
Unused data indicating all 0 is stored in the unused storage area,
the total storage capacity of the first storage area is greater than the total storage capacity of the unused storage area;
The first storage area includes a special storage area storing unused data indicating 0 at the special address,
The total storage capacity of the special storage area is less than the total storage capacity of the unused storage area, and
The special storage area includes multiple areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The storage means may be, for example, the ROM 101 or the like. The control means may be, for example, the CPU 103 or the like. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The unused storage area may be, for example, an unused area of addresses 0BD3[H] to 11FF[H]. The total storage capacity of the first storage area may be, for example, 3027 bytes. The total storage capacity of unused storage areas may be, for example, 1069 bytes. The special storage area may be, for example, a storage area for unused data in setting example 003AKA01. The total storage capacity of the special storage area may be, for example, 19 bytes. The discontinuous addresses may be, for example, storage addresses of unused data in setting example 003AKA01.
According to such a configuration, discontinuous addresses are assigned as special addresses storing unused data in the special storage area, and the total storage capacity of the special storage area is smaller than that of the unused storage area. Appropriate management of the storage area becomes possible so as to prevent misidentification of the storage area as an unused storage area.

[1-2] A special address may be assigned to the special storage area so that areas of a specific number of bytes or more are not contiguous.
Here, the specific number of bytes may be, for example, 16 bytes.
In such a configuration, it is possible to appropriately manage the storage area so as to prevent misidentification of the special storage area as an unused storage area when the dump list is displayed.

[1-3] The control means
a first call instruction that calls a program stored at the specified address by specifying the address;
a second call instruction for calling a program stored at a specific address corresponding to the specified parameter among a plurality of specific addresses assigned at predetermined intervals by specifying a parameter having a data amount smaller than the address; is executable and
The special storage area may include an area in which unused data is stored from one specific address to the next specific address included in the plurality of specific addresses.
Here, the first call instruction may be, for example, a CALL instruction. The second call instruction may be, for example, an RST instruction. The specific address may be, for example, a restart address.
In such a configuration, unused data is stored so as to prevent misidentification of the special storage area as an unused storage area, and appropriate storage area management becomes possible.

[1-4] the storage means includes an address storage area capable of storing the address of the interrupt processing program;
The special storage area may include an area where unused data is stored in the address storage area.
Here, the interrupt processing program may be, for example, a program such as a timer interrupt processing P_PCT for game control. The address storage area may be, for example, an area of addresses 0060[H] to 006D[H] for storing table data included in the interrupt vector table XTBL_INTR. The area in which unused data is stored in the address storage area may be, for example, an area of addresses 0062[H] to 006D[H].
In such a configuration, unused data is stored so as to prevent misidentification of the special storage area as an unused storage area, and appropriate storage area management becomes possible.

[1-5] the first storage area includes a predetermined storage area storing use data indicating 0 at a predetermined address;
The predetermined storage area may include a plurality of areas to which discontinuous addresses are assigned as predetermined addresses.
Here, the predetermined addresses are, for example, the addresses 0016 [H] and 0017 [H] of the table data included in the power failure recovery time vector table, the addresses where the use data used in step AKS34 of the power failure processing P_POWER_OFF are stored, Any address may be used as long as it stores the use data used in step AKS42 of the power-off process P_POWER_OFF.
In such a configuration, use data indicating 0 is stored so as to prevent the predetermined storage area from being misidentified as an unused storage area, and appropriate storage area management becomes possible.

[1-6] The use data stored in the predetermined storage area may include addressing data that enables execution of start-up processing based on start-up of the gaming machine from the beginning.
Here, the start-up process may be, for example, the main process P_MAIN for game control. The addressing data may be, for example, zero data with a storage value of 00 [H] in the vector table for power failure recovery.
In such a configuration, use data indicating 0 is stored so as to prevent the predetermined storage area from being misidentified as an unused storage area, and appropriate storage area management becomes possible.

[2-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by a program stored in the storage means;
The memory means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
a third storage area different from the first storage area and the second storage area;
an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area;
Unused data indicating all 0 is stored in the unused storage area,
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
the second storage area includes a normal storage area storing use data indicating 0 at a normal address;
The total storage capacity of regular storage is less than the total storage capacity of unused storage, and
The normal storage area may include multiple areas to which discontinuous addresses are assigned as normal addresses.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The storage means may be, for example, the ROM 101 or the like. The control means may be, for example, the CPU 103 or the like. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The third storage area may be, for example, a non-game program area and a non-game data area. The unused storage area may be, for example, an unused area of addresses 0BD3[H] to 11FF[H] and an unused area of addresses 1D34[H] to 1FFF[H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of unused storage areas may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area for zero data, which is used data in setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The discontinuous addresses may be, for example, storage addresses of zero data that are used data in setting example 003AKA01.
According to such a configuration, discontinuous addresses are assigned as normal addresses in which used data are stored in the normal storage area, and since the normal storage area has a smaller total storage capacity than the unused storage area, Appropriate storage area management becomes possible so as to prevent erroneous recognition of an area as an unused storage area.

[2-2] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by a program stored in the storage means;
The memory means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
a third storage area different from the first storage area and the second storage area;
an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area;
Unused data indicating all 0 is stored in the unused storage area,
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
The second storage area is
a normal storage area storing use data indicating 0 at a normal address;
a special storage area in which unused data indicating 0 at the special address is stored;
The total storage capacity of the normal storage area and the special storage area is less than the total storage capacity of the unused storage area, and
The normal storage area includes multiple areas to which discontinuous addresses are assigned as normal addresses,
The special storage area may include multiple areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The storage means may be, for example, the ROM 101 or the like. The control means may be, for example, the CPU 103 or the like. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The third storage area may be, for example, a non-game program area and a non-game data area. The unused storage area may be, for example, an unused area of addresses 0BD3[H] to 11FF[H] and an unused area of addresses 1D34[H] to 1FFF[H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of unused storage areas may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area for zero data, which is used data in setting example 003AKA11. The special storage area may be, for example, a storage area for zero data, which is unused data in setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The total storage capacity of the special storage area may be, for example, 19 bytes. Discontinuous addresses as normal addresses may be, for example, storage addresses of zero data that is used data in setting example 003AKA11. Discontinuous addresses as special addresses may be, for example, storage addresses of zero data that are unused data in setting example 003AKA11.
According to such a configuration, discontinuous addresses are assigned as normal addresses storing used data in the normal storage area, and discontinuous addresses are assigned as special addresses storing unused data in the special storage area. Also, since the total storage capacity of the normal storage area and the special storage area is smaller than that of the unused storage area, it is possible to prevent misidentification of the normal storage area and the special storage area as unused storage areas. can be managed.

[2-3] The use data stored in the normal storage area may include extinguishing control data that can be used to extinguish the light emitting means.
Here, the light emitting means may be, for example, the first light emitting section and the second light emitting section in the normal symbol display device 20, the first light emitting section and the second light emitting section in the first special symbol display device 4A, and the like. The extinguishing control data is, for example, zero data with a storage value of 00 [H] in the normal diagram reservation number display table XD_FMEM, zero data with a storage value of 00 [H] in the first reservation number display table XD_TMEM1, etc. Just do it.
In such a configuration, use data indicating 0 is stored so as to prevent misidentification of the normal storage area as an unused storage area, and appropriate storage area management becomes possible.

[2-4] The unused data stored in the special storage area may include state-related data corresponding to a different number of rounds than the number of rounds that can be executed in an advantageous state advantageous to the player.
Here, the advantageous state may be, for example, a jackpot game state. The state-related data may be, for example, zero data with a storage value of 00 [H] in the right-handed round number display table XD_TOKU1.

[2-5] Normal storage areas are assigned normal addresses so that areas larger than a specific number of bytes are not contiguous.
A special address may be assigned to the special storage area so that the area of a specific number of bytes or more is not contiguous.
Here, the specific number of bytes may be, for example, 16 bytes.
In such a configuration, it is possible to manage the storage areas appropriately so as to prevent misidentification of the normal storage area and the special storage area as unused storage areas when the dump list is displayed.

[3-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by a program stored in the storage means;
The memory means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
a third storage area different from the first storage area and the second storage area;
an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area;
Unused data indicating all 0 is stored in the unused storage area,
The second storage area is
use data indicating 0 at the normal address is stored;
Data indicating other than 0 at the start address and the end address may be stored.
Here, the gaming machine may be, for example, the pachinko gaming machine 1 or the like. The storage means may be, for example, the ROM 101 or the like. The control means may be, for example, the CPU 103 or the like. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The third storage area may be, for example, a non-game program area and a non-game data area. The unused storage area may be, for example, an unused area of addresses 0BD3[H] to 11FF[H] and an unused area of addresses 1D34[H] to 1FFF[H]. The normal address may be, for example, a storage address of zero data which is used data in setting example 003AKA11. The start address may be, for example, address 1200[H]. The end address may be, for example, address 1D33[H].
According to such a configuration, it is possible to appropriately manage the storage area so as to prevent misidentification of the second storage area as an unused storage area.

[3-2] The second storage area may store data indicating other than 0 at the address next to the start address and the address before the end address.
Here, the address following the start address may be, for example, address 1201[H]. The address before the end address may be, for example, address 1D32[H].
In such a configuration, it is possible to manage the storage area appropriately so as to prevent misidentification of the second storage area as an unused storage area.

1... Pachinko game machine 4A... First special symbol display device 4B... Second special symbol display device 11... Main board 12... Production control board 100... Game control microcomputer 101... ROM
102... RAM
103 ... CPU
104, 104A, 104B... random number circuit

Claims (1)

A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means capable of controlling the progress of the game by the program stored in the storage means;
The storage means
A first storage area in which a program related to game control is stored;
a second storage area storing data used for program execution;
a third storage area different from the first storage area and the second storage area;
an unused storage area capable of storing unused data between the first storage area and the second storage area and between the second storage area and the third storage area;
unused data indicating all 0 is stored in the unused storage area;
the total storage capacity of the second storage area is larger than the total storage capacity of the unused storage area;
The second storage area includes a normal storage area storing usage data indicating 0 at a normal address,
the total storage capacity of the normal storage area is smaller than the total storage capacity of the unused storage area;
A gaming machine, wherein the normal storage area includes a plurality of areas assigned normal addresses in which use data indicating 0 is stored.

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