JP2023056189A - electronic device - Google Patents

Abstract

To provide an electronic device that improves bonding strength between a first base on which an element structure is formed and a second base that seals the element structure while suppressing influence on operation of the element.SOLUTION: In an electronic device, an element chip 8 includes an element substrate 26 that has an element first major surface 28 and an opposite element second major surface 29, and includes a second layer 47 having a first monocrystalline silicon layer 60 and a first polycrystalline silicon layer 62 adjacent and surrounding the first monocrystalline silicon layer 60, an element structure 31 formed in a first single crystal silicon layer 60 on a surface layer portion of the element substrate 26 on the side of the element first main surface 28, and a lid substrate 27 that has a bonding layer 116 containing a metal capable of forming an eutectic with silicon, is bonded to the element substrate 26 via a bonding portion 43 formed by bonding the first polycrystalline silicon layer 62 and the bonding layer 116, and encapsulates the element structure 31.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to electronic devices.

For example, Patent Document 1 describes a first substrate having a first main surface and a first back surface, a second substrate having a second main surface and a second back surface, an element structure mounted on the first back surface, and an element structure. and a control element mounted on the first main surface, the second substrate being fixed to the first substrate with the second main surface facing the first back surface, and the second The substrate has a first part and a second part, and the element structure is positioned between the first part and the second part when viewed in the z direction, and between the first back surface and the second back surface in the z direction. An electronic device is disclosed having a portion located at a.

JP 2021-015895 A

An embodiment of the present disclosure can improve the bonding strength between the first base on which the element structure is formed and the second base that seals the element structure while suppressing the influence on the element operation. To provide an electronic device capable of

An electronic device according to an embodiment of the present disclosure is a first substrate having a first main surface and a second main surface opposite to the first main surface, comprising a first single crystal silicon layer and the first single crystal silicon layer. A first substrate including a semiconductor layer having a surrounding and adjacent first polycrystalline silicon layer, and an element formed on the first single crystal silicon layer on a surface layer portion of the first substrate on the first main surface side. and a bonding layer containing a metal capable of forming a eutectic with silicon, and bonded to the first base via a bonding portion formed by bonding the first polycrystalline silicon layer and the bonding layer. and a second substrate encapsulating the device structure.

1 is a schematic perspective view of an electronic device according to an embodiment of the present disclosure; FIG. 2 is a schematic plan view of the element chip of FIG. 1. FIG. FIG. 3 is an enlarged view of a portion surrounded by a two-dot chain line III in FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3. FIG. 5 is a cross-sectional view taken along line VV of FIG. 3. FIG. FIG. 6A is a diagram showing a part of the manufacturing process of the electronic device. FIG. 6B is a diagram showing the next step of FIG. 6A. FIG. 6C is a diagram showing the next step of FIG. 6B. FIG. 6D is a diagram showing the next step of FIG. 6C. FIG. 6E is a diagram showing the next step of FIG. 6D. FIG. 6F is a diagram showing the next step of FIG. 6E. FIG. 6G is a diagram showing the next step of FIG. 6F. FIG. 6H is a diagram showing the next step of FIG. 6G. FIG. 6I is a diagram showing the next step of FIG. 6H. FIG. 6J is a diagram illustrating the next step of FIG. 6I. FIG. 6K is a diagram illustrating the next step of FIG. 6J. FIG. 6L is a diagram illustrating the next step of FIG. 6K. FIG. 6M is a diagram showing the next step of FIG. 6L. FIG. 6N is a diagram showing the next step of FIG. 6M. FIG. 6O is a diagram showing the next step of FIG. 6N. FIG. 6P is a diagram showing the next step of FIG. 6O. FIG. 6Q is a diagram showing the next step of FIG. 6P. FIG. 6R is a diagram showing the next step of FIG. 6Q. FIG. 6S is a diagram showing the next step of FIG. 6R. FIG. 6T is a diagram showing the next step of FIG. 6S. FIG. 6U is a diagram illustrating the next step of FIG. 6T. FIG. 7 is a diagram showing processes related to the manufacturing process of the electronic device. FIG. 8 is a diagram showing a modification of the electronic device.

Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The terms "first", "second", "third", etc. in this disclosure are used merely as labels and are not necessarily intended to impose a permutation of the objects.
<Overall Configuration of Electronic Device 1>
FIG. 1 is a schematic perspective view of an electronic device 1 according to an embodiment of the present disclosure.

The electronic device 1 is, for example, a device that can be built in various electronic devices such as a smart phone, an electronic tablet, a digital camera, a video camera, an ECU (Electronic Control Unit) of an automobile, a car navigation system, an inkjet printer head, and the like. In this embodiment, the electronic device 1 may be a MEMS sensor including MEMS elements (acceleration sensor, gyro sensor, pressure sensor, etc.) formed by MEMS (Micro Electro Mechanical System) technology.

Referring to FIG. 1, electronic device 1 may be an electronic chip having a rectangular parallelepiped shape. The electronic device 1 has a device first major surface 2, an opposite device second major surface 3, and a device end surface 4 around the device first major surface 2 and the device second major surface 3. . The device first main surface 2 and the device second main surface 3 are respectively the upper surface and the lower surface of FIG. The device end surface 4 may be a device side surface surrounding the device first major surface 2 and the device second major surface 3 . In FIG. 1, the width direction of the electronic device 1 having a rectangular parallelepiped shape is defined as the first direction X, the longitudinal direction of the electronic device 1 is defined as the second direction Y, and the thickness direction of the electronic device 1 (device first principal direction). A normal direction of the surface 2 and the device second main surface 3) is defined as a third direction Z.

An external terminal 5 is formed on the device second main surface 3 . In this embodiment, a plurality of external terminals 5 are formed on the device second main surface 3 . The electronic device 1 can be mounted on a wiring board (not shown) inside the electronic device via the external terminals 5 .

The electronic device 1 includes a base substrate 6 , a control chip 7 as an example of a third substrate, an element chip 8 and a sealing resin 9 .

The base substrate 6 supports the control chip 7 and the element chip 8 from below in this embodiment. A control chip 7 is arranged on the base substrate 6 and an element chip 8 is arranged on the control chip 7 . The base substrate 6 may also be called a support substrate. In this embodiment, the base substrate 6 may be a printed circuit board (PCB).

The base substrate 6 is formed in a square plate shape (rectangular shape in FIG. 1). The base substrate 6 has a substrate first main surface 10 , a substrate second main surface 11 opposite thereto, and a substrate end surface 12 surrounding the substrate first main surface 10 and the substrate second main surface 11 . . The substrate first main surface 10 and the substrate second main surface 11 are respectively the upper surface and the lower surface in FIG. The substrate end surface 12 may be a substrate side surface surrounding the substrate first main surface 10 and the substrate second main surface 11 . The substrate second main surface 11 also forms the device second main surface 3 in this embodiment. Therefore, the external terminals 5 are formed on the substrate second main surface 11 .

A substrate pad region 13 is formed on the substrate first main surface 10 . The board pad area 13 is formed in a board lead-out portion 14 drawn out sideways from an end face 18 (described later) of the control chip 7 . In this embodiment, the substrate lead-out portion 14 is a portion that protrudes toward one side in the second direction Y with respect to the control chip 7 . Further, the board lead-out portion 14 is defined as a portion drawn out laterally from an element end face 30 (described later) of the element chip 8 or a portion protruding toward one side in the second direction Y with respect to the element chip 8 . You may

A plurality of substrate pads 15 are formed in the substrate pad area 13 . The plurality of substrate pads 15 are linearly arranged along the substrate end face 12 with a space therebetween. The board pads 15 may be electrically connected to the external terminals 5 via, for example, through holes (not shown) penetrating the base board 6 in the thickness direction.

The control chip 7 is formed in a square plate shape (rectangular shape in FIG. 1). The control chip 7 has a first major surface 16 , a second major surface 17 opposite thereto, and an end surface 18 surrounding the first major surface 16 and the second major surface 17 . The first major surface 16 and the second major surface 17 are respectively the top and bottom surfaces in FIG. The second major surface 17 of the control chip 7 may be a bonding surface with respect to the base substrate 6 . The end surface 18 of the control chip 7 may be a side surface of the control chip 7 surrounding the first major surface 16 and the second major surface 17 .

A control circuit 19 (ASIC: Application Specific Integrated Circuit) for controlling the element chip 8 is formed in the control chip 7 . The control circuit 19 may be formed, for example, on the surface layer portion of the control chip 7 on the first main surface 16 side. The control circuit 19 includes, for example, a charge amplifier that amplifies the electrical signal output from the element chip 8, a filter circuit (low-pass filter: LPF, etc.) that extracts a specific frequency component of the electrical signal, and a logical operation on the filtered electrical signal. It may include a logic circuit or the like for These circuits may be composed of CMOS devices, for example. In this embodiment, the control chip 7 may be a silicon substrate.

A first pad region 20 is formed on the first main surface 16 of the control chip 7 . The first pad region 20 is formed in a first lead-out portion 21 drawn out sideways from an element end face 30 (described later) of the element chip 8 . In this embodiment, the first lead-out portion 21 is a portion that protrudes toward one side in the second direction Y with respect to the element chip 8 .

A plurality of control pads 22 are formed in the first pad region 20 . The multiple control pads 22 may include multiple first control pads 23 and multiple second control pads 24 . The plurality of first control pads 23 are linearly arranged along the end face 18 of the control chip 7 at intervals. The plurality of second control pads 24 are arranged on the side of the element chip 8 with respect to the first control pads 23 , and are linearly arranged along the end face 18 of the control chip 7 at intervals. The plurality of first control pads 23 and the plurality of second control pads 24 may be adjacent to each other in the second direction Y on a one-to-one basis. The plurality of first control pads 23 are electrically connected to the plurality of substrate pads 15 via first wires 25 .

The element chip 8 includes an element substrate 26 as an example of a first base and a cover substrate 27 as an example of a second base.

The element substrate 26 is formed in a square plate shape (substantially square shape in FIG. 1). The element substrate 26 has an element first main surface 28 , an element second main surface 29 opposite to the element first main surface 28 , and an element end surface 30 around the element first main surface 28 and the element second main surface 29 . . The device first main surface 28 and the device second main surface 29 are respectively the top surface and the bottom surface in FIG. The element second main surface 29 may be a bonding surface for the control chip 7 . The element end surface 30 may be an element side surface surrounding the element first principal surface 28 and the element second principal surface 29 .

An element structure 31 is formed on the element substrate 26 . The element structure 31 may be formed, for example, on the surface layer portion on the side of the first main surface 28 of the element. The device structure 31 may be, for example, a device structure 31 that is liquid- and gas-tightly protected by being sealed with a lid substrate 27 . In this embodiment, device structure 31 may be a MEMS structure that outputs electrical signals based on physical actions or quantities. Therefore, the element chip 8 may be called a MEMS element. The element structure 31 may be formed, for example, in the central portion of the element substrate 26 spaced inwardly from the element end surface 30 .

A second pad region 32 is formed on the element first main surface 28 . The second pad area 32 is formed in a second lead-out portion 33 that is drawn out sideways from an end face 38 (described later) of the lid substrate 27 . In this embodiment, the second lead-out portion 33 is a portion that protrudes toward one side in the second direction Y with respect to the lid substrate 27 . A plurality of element pads 34 are formed in the second pad region 32 . The plurality of element pads 34 are linearly arranged along the element end surface 30 with a space therebetween. The multiple element pads 34 are electrically connected to the multiple second control pads 24 via the second wires 35 .

The lid substrate 27 is arranged on the element substrate 26 so as to cover the element structure 31 and physically protects the element structure 31 from the outside. The lid substrate 27 is formed in a square plate shape (substantially square shape in FIG. 1). The lid substrate 27 has a first major surface 36 , a second major surface 37 opposite thereto, and an end surface 38 around the first major surface 36 and the second major surface 37 . The first main surface 36 and the second main surface 37 are respectively the top surface and the bottom surface in FIG. The end surface 38 of the lid substrate 27 may be a side surface of the lid substrate 27 surrounding the first major surface 36 and the second major surface 37 . The second main surface 37 of the lid substrate 27 may be a bonding surface with respect to the element substrate 26 .

The sealing resin 9 cooperates with the base substrate 6 to form the external shape of the electronic device 1 and is formed in a substantially rectangular parallelepiped shape. The sealing resin 9 is made of a known molding resin such as epoxy resin. The sealing resin 9 covers the control chip 7 , the element chip 8 , the first wires 25 and the second wires 35 on the substrate first main surface 10 of the base substrate 6 . On the other hand, the substrate second main surface 11 and the substrate end surface 12 of the base substrate 6 are exposed from the sealing resin 9 .

The sealing resin 9 has a resin first main surface 39 , a resin second main surface 40 on the opposite side, and a resin end surface 41 around the resin first main surface 39 and the resin second main surface 40 . there is The first resin main surface 39 and the second resin main surface 40 are respectively the top surface and the bottom surface in FIG. The resin end surface 41 may be a resin side surface surrounding the resin first principal surface 39 and the resin second principal surface 40 . The resin second main surface 40 may be a bonding surface with respect to the base substrate 6 . The resin end surface 41 is a surface rising upward from the substrate end surface 12 . The resin end surface 41 is flatly continuous with the substrate end surface 12 . The device end face 4 may be formed by combining the resin end face 41 and the substrate end face 12 . Therefore, a boundary 42 between the resin end surface 41 and the substrate end surface 12 may be formed on the device end surface 4 over the entire circumferential direction of the electronic device 1 .
<Detailed description of the element chip 8>
FIG. 2 is a schematic plan view of the element chip 8 of FIG. 1. FIG. FIG. 3 is an enlarged view of a portion surrounded by a two-dot chain line III in FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3. FIG. 5 is a cross-sectional view taken along line VV of FIG. 3. FIG. The structure of the element chip 8 will be described in detail with reference to FIGS. 2 to 5. FIG.

The element chip 8 includes the element substrate 26 and the lid substrate 27 as described above. The element substrate 26 is defined as the element substrate 26 because it is a base material on which the element structure 31 (MEMS structure) is formed. defined as 27. As shown in FIG. 2 , the lid substrate 27 is bonded to the element substrate 26 via a bonding portion 43 surrounding the element structure 31 of the element substrate 26 . In this embodiment, the region where the device structure 31 is formed inside the junction 43 is the device region 44 , and the region opposite the device region 44 with respect to the junction 43 is the outside region 45 . The element substrate 26 and the lid substrate 27 may be defined as the first base material and the second base material, respectively, using ordinal numbers.

The element substrate 26 is made of a semiconductor material such as silicon. The element substrate 26 has the element first main surface 28 , the element second main surface 29 and the element end surface 30 as described above. The element first principal surface 28 may be a processed surface of the element substrate 26 on which the element structure 31 is formed, and the element second principal surface 29 may be a non-processed surface with respect to the processed surface.

The device substrate 26 in this embodiment includes a first layer 46 and a second layer 47 as an example of a semiconductor layer on the first layer 46 . The element substrate 26 has a laminated structure of a first layer 46 and a second layer 47, and as shown in FIGS. exposed to In this embodiment, the first layer 46 and the second layer 47 are formed to have the same shape (for example, a square shape) in plan view, and are joined so that their end surfaces 51 and 54 are flat and continuous. there is

The first layer 46 may be a semiconductor substrate (eg, a silicon substrate) in this embodiment. The thickness of the first layer 46 may be, for example, 200 μm or more and 1000 μm or less. The first layer 46 has a first major surface 49 , a second major surface 50 opposite the first major surface 49 , and an end surface 51 surrounding the first major surface 49 and the second major surface 50 . there is The second main surface 50 of the first layer 46 may be the device second main surface 29 of the device substrate 26 . The end surface 51 of the first layer 46 may be part of the element end surface 30 .

The second layer 47 is the layer on which the mechanical element structure 31 (in this embodiment, the MEMS structure) of the element chip 8 is formed. The second layer 47 may be a semiconductor layer (eg, a silicon epitaxial layer) in this embodiment. The second layer 47 has a first major surface 52, a second major surface 53 opposite the first major surface 52, and an end surface 54 around the first major surface 52 and the second major surface 53. there is The first main surface 52 of the second layer 47 may be the device first main surface 28 of the device substrate 26 . The end surface 54 of the second layer 47 may be part of the element end surface 30 .

Second layer 47 more specifically includes monocrystalline silicon layer 55 and polycrystalline silicon layer 56 . The monocrystalline silicon layer 55 may be defined as a layer composed of silicon crystals that are regularly arranged throughout. On the other hand, the polycrystalline silicon layer 56 may be defined as a layer composed of an aggregate of single crystal silicon and having irregular arrangement of crystals over the entire surface.

Monocrystalline silicon layer 55 and polycrystalline silicon layer 56 are formed laterally adjacent to each other along first main surface 52 . For clarity, polysilicon layer 56 is shown hatched in FIGS. 2 and 3, and polysilicon layer 56 is shown solid gray in FIGS. 4 and 5, the laterally adjacent configuration is such that the monocrystalline silicon layer 55 and the polycrystalline silicon layer 56 are in direct contact, and the interface 57 between them is the second layer 47. may be defined as a form extending linearly in the thickness direction of the second layer 47 from the first main surface 52 toward the second main surface 53 of the second layer 47 . In the laterally adjacent configuration, the second layer 47 on the first layer 46 is divided in the thickness direction of the second layer 47 into a plurality of semiconductor regions including at least a first silicon region and a second silicon region. , the first silicon region is the monocrystalline silicon layer 55 and the second silicon region is the polycrystalline silicon layer 56 . Monocrystalline silicon layer 55 and polycrystalline silicon layer 56 have physical and electrical connection at interface 57 in this embodiment.

The monocrystalline silicon layer 55 and the polycrystalline silicon layer 56 form flat surfaces that are continuous with each other on the element first main surface 28 of the element substrate 26 . More specifically, no steps are formed in the device first main surface 28 at the boundary (interface 57) between the monocrystalline silicon layer 55 and the polycrystalline silicon layer 56, and the upper surface 58 of the monocrystalline silicon layer 55 and the polycrystalline silicon layer 56 are in contact with each other. It is smoothly continuous with the upper surface 59 of the crystalline silicon layer 56 . Therefore, monocrystalline silicon layer 55 and polycrystalline silicon layer 56 may have the same thickness. In this embodiment, the monocrystalline silicon layer 55 and the polycrystalline silicon layer 56 have a thickness of 2 μm or more and 15 μm or less.

In this embodiment, monocrystalline silicon layer 55 includes first monocrystalline silicon layer 60 and second monocrystalline silicon layer 61 , and polycrystalline silicon layer 56 includes first polycrystalline silicon layer 62 . 2, a first monocrystalline silicon layer 60 is formed in the central portion of the second layer 47 and a first polycrystalline silicon layer 62 is formed around the first monocrystalline silicon layer 60 in plan view. , a second monocrystalline silicon layer 61 is formed further around the first polycrystalline silicon layer 62 .

A device structure 31 is formed in the first single crystal silicon layer 60 . The element structure 31 is formed not only in the entire thickness direction of the first single crystal silicon layer 60 but also in the surface layer portion of the first layer 46 on the first major surface 49 side. The element structure 31 includes a support portion 63 fixed to the first layer 46 and a cantilever structure 65 supported by the support portion 63 in a floating state with respect to the cavity 64 .

4 and 5, cavity 64 is a space inside element substrate 26 extending in a direction along element first main surface 28 of element substrate 26, and upper surface 66 formed by first layer 46, It is bounded by a bottom surface 67 and side surfaces 68 . Cavity 64 may optionally have a thickened portion at peripheral edge 69 near sides 68 . At the peripheral edge portion 69 of the cavity 64 , the upper surface 66 of the cavity 64 may be formed on the second layer 47 side beyond the boundary 48 between the first layer 46 and the second layer 47 . Further, the peripheral edge portion 69 of the cavity 64 may be an uneven surface 70 formed by undulating the top surface 66 and the bottom surface 67 . Note that the uneven surface 70 may be formed not only on the peripheral edge portion 69 of the cavity 64 but also on the entire top surface 66 and bottom surface 67 of the cavity 64 .

Referring to FIG. 2, support portion 63 is formed in an annular shape surrounding cavity 64 . A cavity 64 is defined by an inner peripheral surface 71 of the support portion 63 . On the other hand, the outer peripheral surface 72 of the support portion 63 is in contact with the first polycrystalline silicon layer 62 and forms an interface 57 between the first single crystal silicon layer 60 and the first polycrystalline silicon layer 62 . In this embodiment, the support portion 63 may be formed in a substantially quadrangular ring shape in plan view.

The cantilever structure 65 extends in the second direction Y from the support portion 63 and is cantilevered by the support portion 63 . The cantilever structure 65 includes, for example, a body portion 73 and a connection portion 74 that connects the body portion 73 and the support portion 63 .

The body portion 73 is spaced inwardly from the inner peripheral surface 71 of the annular support portion 63 and faces the cavity 64 in the third direction Z, which is the thickness direction of the element substrate 26 . The body portion 73 is formed in a substantially rectangular shape in plan view. An opening 75 is formed in the inner region of the body portion 73 so as to penetrate the body portion 73 in the thickness direction. In this embodiment, a plurality of openings 75 are formed in body portion 73 . 4 and 5, the boundary 48 between the first layer 46 and the second layer 47 is exposed on the side surface of the opening 75. As shown in FIG.

The connecting portion 74 includes a plurality of connecting portions 74 arranged at intervals along the first direction X. As shown in FIG. The plurality of connection portions 74 extend from one side forming the inner peripheral surface 71 of the support portion 63 toward the opposite side in plan view, and are connected to the main body portion 73 . Referring to FIG. 3 , the joint between connecting portion 74 and support portion 63 may be referred to as proximal end portion 76 of cantilever structure 65 .

Each connection portion 74 includes a cantilever isolation/insulation portion 77 as an example of a third isolation/insulation portion. Referring to FIG. 4, the cantilever isolation insulating portion 77 extends from the device first main surface 28 (the first main surface 52 of the second layer 47) of the device substrate 26 to the cavity 64, and the end portion exposed in the cavity 64. 78. End 78 of cantilever isolation insulator 77 may protrude into cavity 64 . The cantilever isolation insulating portion 77 is made of an insulating film. In this embodiment, the cantilever isolation insulator 77 is made of silicon oxide (SiO ₂ ). A portion of the cantilever structure 65 is physically and electrically isolated from the rest of the device structure 31 by a cantilever isolation insulator 77 . In this embodiment, the cantilever structure 65 is physically and electrically separated at the connection portion 74 into a first potential portion 79 on the body portion 73 side and a second potential portion 80 on the support portion 63 side. The first potential portion 79 is primarily the body portion 73 of the cantilever structure 65 and the second potential portion 80 is primarily the support portion 63 although including part of the cantilever structure 65 .

The first polycrystalline silicon layer 62 may contain impurities (n-type impurities in this embodiment). The first polycrystalline silicon layer 62 includes a base portion 81, a first protrusion 82 as an example of an inner portion, and a second protrusion 83 as an example of an outer portion.

The base portion 81 is formed in an annular shape surrounding the element structure 31 in plan view, and forms a joint portion 43 between the element substrate 26 and the lid substrate 27 . In this embodiment, the base portion 81 is formed in a quadrangular annular shape in a plan view, and includes an inner peripheral surface 84 as an example of an inner peripheral edge made up of four inner sides and an outer peripheral surface 84 as an example of an outer peripheral edge made up of four outer sides. 85.

The first protrusions 82 include a plurality of first protrusions 82 selectively extending from the inner peripheral surface 84 of the base portion 81 toward the cantilever structure 65 . The first projecting portion 82 is formed in the element region 44 . Referring to FIG. 3, in this embodiment, the plurality of first protrusions 82 are formed on extension lines in the extension direction of the connecting portion 74 of the cantilever structure 65 in the second direction Y. As shown in FIG. The plurality of first projecting portions 82 correspond to the plurality of connecting portions 74 on a one-to-one basis. They face each other via the portion 63 . As a result, the first projecting portion 82 and the connection portion 74 of the cantilever structure 65 can be brought close to each other, so that the first projecting portion 82 and the cantilever structure 65 can be connected with a short wiring distance.

The second protrusions 83 include a plurality of second protrusions 83 selectively extending from the outer peripheral surface 85 of the base portion 81 toward the opposite side of the cantilever structure 65 . The second projecting portion 83 is formed in the outer region 45 . In this embodiment, the plurality of second protrusions 83 are formed on extension lines of the extension direction of the first protrusions 82 in the second direction Y. As shown in FIG. The plurality of second protrusions 83 correspond to the plurality of first protrusions 82 on a one-to-one basis. 87 are opposed to each other with the base portion 81 interposed therebetween. As a result, the first projecting portion 82 and the second projecting portion 83 can be brought close to each other, so that the first contact region 99 and the second contact region 101, which will be described later, can be connected with a short wiring distance. A tip portion 88 of the second protrusion 83 and a tip portion 86 of the first protrusion 82 face in opposite directions.

3 and 4, between first polysilicon layer 62 and first layer 46, a first projecting portion 82 and a second projecting portion 83, which are electrically isolated from base portion 81, are provided. An embedded wiring structure 90 is formed to electrically connect the . The embedded wiring structure 90 is embedded on the second main surface 53 side (below the base portion 81 ) with respect to the base portion 81 , crosses the base portion 81 and spans between the element region 44 and the outer region 45 . Thus, the first polysilicon layer 62 and the first layer 46 are physically separated from each other by the embedded wiring structure 90 .

The buried wiring structure 90 includes a first buried insulating layer 91 , a first buried wiring layer 92 and a second buried insulating layer 93 . A first buried wiring layer 92 is sandwiched between a first buried insulating layer 91 and a second buried insulating layer 93 .

A first buried insulating layer 91 is formed on the first main surface 49 of the first layer 46 . The first buried insulating layer 91 may be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or a laminated structure thereof. The first buried insulating layer 91 has a thickness of 10 nm or more and 4 μm or less, for example. The thickness of the first embedded insulating layer 91 is not limited to the above range, and may be set appropriately in consideration of the parasitic capacitance of the first embedded wiring layer 92, for example.

The first embedded wiring layer 92 is formed on the first embedded insulating layer 91 . The first embedded wiring layer 92 is made of polycrystalline silicon in this embodiment, but may be made of a metal layer. When the first embedded wiring layer 92 is made of polycrystalline silicon, the first embedded wiring layer 92 may contain impurities (n-type impurities in this embodiment). The first embedded wiring layer 92 has a thickness of 800 nm or more, for example. The thickness of the first embedded wiring layer 92 is not limited to the range described above, and may be appropriately set in consideration of the current value or the like that flows through the first embedded wiring layer 92, for example.

The second embedded insulating layer 93 is formed on the first embedded wiring layer 92 and covers the first embedded wiring layer 92 . The second embedded insulating layer 93 may be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or a laminated structure thereof. The second embedded insulating layer 93 has a thickness of, for example, 10 nm or more and 4 μm or less. The thickness of the first embedded insulating layer 91 is not limited to the above range, and may be set appropriately in consideration of the parasitic capacitance of the first embedded wiring layer 92, for example.

A first contact opening 94 and a second contact opening 95 are formed in the second buried insulating layer 93 . A first contact opening 94 is formed below the first protrusion 82 in the element region 44 , and a second contact opening 95 is formed below the second protrusion 83 in the outer region 45 . A first end portion 96 and a second end portion 97 of the first embedded wiring layer 92 are exposed from the first contact opening 94 and the second contact opening 95, respectively. On the other hand, the second embedded insulating layer 93 entirely covers the first embedded wiring layer 92 below the base portion 81 . As a result, the base portion 81 and the first embedded wiring layer 92 are physically and electrically separated by the second embedded insulating layer 93 .

The first projecting portion 82 includes a first isolation insulating portion 98 . Referring to FIG. 3, first isolation insulating portion 98 is formed in an annular shape surrounding first contact opening 94 in plan view. Also, referring to FIG. 4 , the first isolation insulating portion 98 extends from the element first main surface 28 (the first main surface 52 of the second layer 47 ) of the element substrate 26 to the second buried insulating layer 93 . . Thus, the first isolation insulating portion 98 partitions a portion of the first projecting portion 82 as a first contact region 99 . The first contact region 99 is exposed from the device first main surface 28 of the device substrate 26 . The first contact region 99 is physically and electrically isolated from the portion of the first polysilicon layer 62 outside the first isolation insulating portion 98 . The first contact region 99 is connected to the first embedded wiring layer 92 (first end portion 96 ) at the first contact opening 94 . The first isolation insulating portion 98 is made of an insulating film. In this embodiment, the first isolation insulator 98 is made of silicon oxide (SiO ₂ ).

The second projecting portion 83 includes a second isolation insulating portion 100 . Referring to FIG. 3, second isolation insulating portion 100 is formed in an annular shape surrounding second contact opening 95 in plan view. Further, referring to FIG. 4 , second isolation insulating portion 100 extends from element first main surface 28 (first main surface 52 of second layer 47 ) of element substrate 26 to second embedded insulating layer 93 . . Thereby, the second isolation insulating portion 100 partitions a part of the second projecting portion 83 as a second contact region 101 . The second contact region 101 is exposed from the device first main surface 28 of the device substrate 26 . The second contact region 101 is physically and electrically isolated from the portion of the first polysilicon layer 62 outside the second isolation insulating portion 100 . The second contact region 101 is connected to the first embedded wiring layer 92 (second end portion 97 ) at the second contact opening 95 . As a result, the first protrusion 82 (first contact region 99 ) of the element region 44 and the second protrusion 83 (second contact region 101 ) of the outer region 45 are separated through the first embedded wiring layer 92 . electrically connected. The second isolation insulating section 100 is made of an insulating film. In this embodiment, the second isolation insulator 100 is made of silicon oxide (SiO ₂ ).

An exposed wiring structure 102 and an element pad 34 are formed on the element first main surface 28 of the element substrate 26 .

3 and 4, exposed wiring structure 102 electrically connects first contact region 99 and device structure 31 . The exposed wiring structure 102 includes a first exposed wiring structure 103 electrically connecting the first contact region 99 and the first potential portion 79 (body portion 73 ) of the element structure 31 , and the first contact region 99 and the element structure 31 . and a second exposed wiring structure 104 electrically connecting to the second potential portion 80 (supporting portion 63). First exposed interconnect structure 103 extends from first contact region 99 across first isolation insulation 98 and cantilever isolation insulation 77 to body portion 73 of cantilever structure 65 . A second exposed wiring structure 104 extends from the first contact region 99 across the first isolation insulating portion 98 to the support portion 63 .

First exposed wiring structure 103 and second exposed wiring structure 104 include underlying insulating layer 105 and exposed wiring layer 106 . Although FIG. 4 shows only the underlying insulating layer 105 and the exposed wiring layer 106 of the first exposed wiring structure 103, the second exposed wiring structure 104 has a similar structure. The exposed wiring layer 106 is exposed in the cavity 107 (element region 44 ) between the element substrate 26 and the lid substrate 27 and electrically connects the first contact region 99 and the element structure 31 . The underlying insulating layer 105 is formed between the exposed wiring layer 106 and the element substrate 26 . Underlying insulating layer 105 prevents electrical connection between exposed wiring layer 106 of first exposed wiring structure 103 , first polysilicon layer 62 (portions other than first contact region 99 ), and supporting portion 63 . Further, the underlying insulating layer 105 prevents electrical connection between the exposed wiring layer 106 of the second exposed wiring structure 104 and the first polysilicon layer 62 (the portion other than the first contact region 99). Base insulating layer 105 may be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or a laminated structure thereof. The exposed wiring layer 106 may be, for example, metal wiring such as aluminum (Al).

Element pads 34 are formed on second contact regions 101 . The element pads 34 are spaced inwardly from the second isolation insulating section 100 . The element pad 34 is in contact with the second contact region 101 and electrically connected to the second contact region 101 . Thus, an electric signal can be input from the element pad 34 to the element structure 31 via the exposed wiring structure 102 and the embedded wiring structure 90, and an electric signal detected by the element structure 31 can be output from the element pad 34. You can also For example, when the element structure 31 is a MEMS sensor (acceleration sensor) that detects acceleration, when the body portion 73 receives acceleration, the capacitance between the body portion 73 and the support portion 63 (or the first layer 46) changes. The amount of change is detected and taken out to the element pad 34 as an electrical signal corresponding to the acceleration. Also, the element pads 34 may be, for example, metal pads such as aluminum (Al).

The second single crystal silicon layer 61 is formed in a ring shape surrounding the element structure 31 in plan view. In this embodiment, the second single-crystal silicon layer 61 is formed in a quadrangular ring shape in plan view, and has an inner peripheral surface 108 consisting of four inner sides and an outer peripheral surface 109 consisting of four outer sides. The inner peripheral surface 108 of the second monocrystalline silicon layer 61 forms an interface 57 with the first polycrystalline silicon layer 62 . The outer peripheral surface 109 of the second single crystal silicon layer 61 forms the element end surface 30 . Therefore, the peripheral portion of the element substrate 26 along the element end surface 30 is formed of the second single crystal silicon layer 61 .

That is, in this embodiment, the element substrate 26 is a substrate composed of the first layer 46, a semiconductor layer formed on the substrate, the first monocrystalline silicon layer 60 having the element structure 31 formed thereon, and the first monocrystalline silicon layer 60 having the element structure 31 formed thereon. A second single crystal silicon layer 61 formed with an annular gap (recess 110) between itself and the first single crystal silicon layer 60, and between the first single crystal silicon layer 60 and the second single crystal silicon layer 61 and a semiconductor layer including the first polysilicon layer 62 embedded in the gap (recess 110).

The lid substrate 27 is made of a semiconductor material such as silicon. In this embodiment, lid substrate 27 is a silicon substrate. 4 and 5, lid substrate 27 has an annular mesa portion 111 along its outer periphery. In this embodiment, the mesa portion 111 is formed in a square annular shape along the four end faces 38 of the lid substrate 27 . The mesa portion 111 can be defined as a levee along the outer peripheral edge of the lid substrate 27 , so it may be called a peripheral levee of the lid substrate 27 .

A concave portion 112 is formed inside the mesa portion 111 in the lid substrate 27 . The recess 112 is formed by digging the second main surface 37 of the lid substrate 27 . As a result, a step is formed on the second main surface 37 of the lid substrate 27 due to the height difference between the top surface 113 of the mesa portion 111 and the bottom surface 114 of the recess 112 . The second main surface 37 of the lid substrate 27 is a generic term for the top surface 113 of the mesa portion 111, the bottom surface 114 of the recess 112, and the side surface 115 of the mesa portion 111 connecting the top surface 113 and the bottom surface 114 (side surface of the recess 112). It may be a flat surface. Sides 115 of mesa 111 may be slanted with respect to flat top 113 in this embodiment. As a result, the recessed portion 112 is tapered in a cross-sectional view such that the width of the recessed portion 112 narrows toward the bottom of the recessed portion 112 .

A bonding layer 116 is formed on the mesa portion 111 . The bonding layer 116 is made of a metal that can form a eutectic with silicon. Such metals include, for example, metals containing at least one of Au, Ge and Zn. In this embodiment, the bonding layer 116 contains Au as a main component and Ta and Pt as subcomponents. Also, the bonding layer 116 may be formed on the side surface 115 of the mesa portion 111 in addition to the top surface 113 of the mesa portion 111 . The bonding layer 116 (first bonding layer 117) on the top surface 113 of the mesa portion 111 and the bonding layer 116 (second bonding layer 118) on the side surface 115 of the mesa portion 111 may be separated from each other. Width W ₁ of first bonding layer 117 (bonding width of lid substrate 27) may be, for example, 20 μm to 120 μm. If the width _W1 is within this range, the lid substrate 27 can be bonded to the element substrate 26 with appropriate strength.

In this embodiment, the element substrate 26 and the cover substrate 27 are bonded together by the bonding layer 116 adhering to the first polysilicon layer 62 (base portion 81) of the element substrate 26 . A joint portion 43 between the element substrate 26 and the lid substrate 27 is formed by the first polycrystalline silicon layer 62 and the joint layer 116 . In this embodiment, as shown in FIG. 2, an annular junction 43 is formed surrounding the device structure 31 . Thereby, the element structure 31 is liquid-tightly and air-tightly protected by being sealed by the lid substrate 27 . A cavity 107 defined by the element first main surface 28 of the element substrate 26 , the bottom surface 114 of the recess 112 of the lid substrate 27 , and the side surface 115 of the mesa portion 111 of the lid substrate 27 is formed on the element structure 31 . , and the device structure 31 is sealed within the cavity 107 .

A metal filament 119 containing the material component of the bonding layer 116 extends through the base portion 81 of the first polycrystalline silicon layer 62 . In this embodiment, the metal filaments 119 may be Au filaments, Au—Si eutectic alloy filaments, or the like. Metal filament 119 extends, for example, from junction 43 downward in the thickness direction of first polysilicon layer 62 . The tip of the metal filament 119 may stop in the middle of the thickness direction of the first polycrystalline silicon layer 62 or may reach the second buried insulating layer 93 .

Further, the second bonding layer 118 may be formed with a surplus conductor 120 containing the material component of the bonding layer 116 and silicon. Excess conductor 120 may be, for example, part of a eutectic product formed during the eutectic reaction between bonding layer 116 and first polysilicon layer 62 . In this embodiment, the redundant conductor 120 may be an Au--Si eutectic alloy.
<Manufacturing Method of Electronic Device 1>
Next, a method for manufacturing the electronic device 1 will be described. When manufacturing the electronic device 1, the base substrate 6, the control chip 7 and the element chip 8 may be individually prepared. Below, the manufacturing process of the element chip 8 is mainly shown. 6A to 6U are diagrams showing part of the manufacturing process of the electronic device 1 in order of process. 6A to 6U show cross sections at the same cutting positions as in FIG.

To prepare the device chip 8, for example, referring to FIG. 6A, a semiconductor wafer 121 forming the first layer 46 of the device substrate 26 is prepared. Semiconductor wafer 121 is a silicon wafer in this embodiment.

Next, referring to FIG. 6B, a first buried insulating layer 91 is formed on the first main surface 49 of the semiconductor wafer 121 . The first embedded insulating layer 91 may be formed by, for example, thermal oxidation, CVD, or the like. An insulating material for the first embedded insulating layer 91 is formed over the entire surface of the first main surface 49 , and then the insulating material is selectively removed by patterning to form the first embedded insulating layer 91 .

Next, referring to FIG. 6C, a first embedded wiring layer 92 is formed on the first embedded insulating layer 91 . The first embedded wiring layer 92 may be formed by, for example, the CVD method. A conductive material of the first buried wiring layer 92 is formed on the entire surface of the first main surface 49 so as to cover the first buried insulating layer 91, and then patterning is performed to selectively remove the conductive material to form a first buried wiring layer. 1 Buried insulating layer 91 is formed.

Next, referring to FIG. 6D, a second embedded insulating layer 93 is formed on the first embedded wiring layer 92 . The second buried insulating layer 93 may be formed by, for example, the CVD method. The insulating material of the first buried insulating layer 91 is formed on the entire surface of the first main surface 49 so as to cover the first buried wiring layer 92, and then the insulating material is selectively removed by patterning to form the first buried wiring layer 92. A two-buried insulating layer 93 is formed. Thereby, an embedded wiring structure 90 is formed on the semiconductor wafer 121 .

Next, referring to FIG. 6E, a first contact opening 94 and a second contact opening 95 are formed by selectively removing the second buried insulating layer 93. As shown in FIG.

Next, referring to FIG. 6F, a single crystal silicon seed layer 122 for growing the single crystal silicon layer 55 of the second layer 47 is formed on the first major surface 49 . The single crystal silicon seed layer 122 may be formed by, for example, the CVD method. A single crystal silicon seed layer 122 is formed on the entire surface of the first main surface 49 so as to cover the embedded wiring structure 90 . Prior to forming the single-crystal silicon seed layer 122, it is preferable to perform a hydrogen baking process to remove the native oxide film on the first main surface 49. FIG. Thereby, the oxygen content of the single crystal silicon seed layer 122 can be reduced.

Next, referring to FIG. 6G, single crystal silicon is epitaxially grown from single crystal silicon seed layer 122 . Thereby, a single crystal silicon layer 55 is formed on the entire surface of the first main surface 49 .

Next, referring to FIG. 6H, a recess 110 is selectively formed extending from the first main surface of single crystal silicon layer 55 (first main surface 52 of second layer 47) to second buried insulating layer 93. . A recess 110 is formed in the region where the polysilicon layer 56 is to be formed. The recess 110 may be formed by, for example, anisotropic deep RIE (Reactive Ion Etching). The embedded wiring structure 90 is exposed inside the recess 110 . The formation of the recess 110 physically separates the monocrystalline silicon layer 55 into a first monocrystalline silicon layer 60 and a second monocrystalline silicon layer 61 .

Next, referring to FIG. 6I, a polysilicon seed layer 123 for growing polysilicon layer 56 of second layer 47 is formed on first major surface 52 . Polycrystalline silicon seed layer 123 may be formed by, for example, the CVD method. A polysilicon seed layer 123 is formed over the entire surface of the first main surface 52 so as to cover the embedded wiring structure 90 . A polysilicon layer 56 is formed along the inner surface of the recess 110 and covers the buried interconnect structure 90 inside the recess 110 . The recess 110 is not filled back with the polysilicon seed layer 123, and a space 124 for polysilicon growth defined by the polysilicon seed layer 123 remains inside the recess 110. FIG. Prior to forming the polysilicon seed layer 123, a hydrogen bake step is preferably performed to remove the native oxide film on the single crystal silicon layer 55. FIG. Thereby, the oxygen content of the single crystal silicon seed layer 122 can be reduced. Furthermore, since the native oxide film on the inner surface of recess 110 is removed, physical and electrical connection between polycrystalline silicon seed layer 123 and monocrystalline silicon layer 55 is ensured on the inner surface of recess 110 .

Next, referring to FIG. 6J, polycrystalline silicon is epitaxially grown from polycrystalline silicon seed layer 123 while introducing impurities. Thereby, a polycrystalline silicon layer 56 is formed on the entire surface of the first main surface 52 . The polycrystalline silicon layer 56 fills back the recess 110 and covers the entire surface of the monocrystalline silicon layer 55 . The dose amount of impurities may be appropriately adjusted according to the specifications of the electronic device 1 .

Next, referring to FIG. 6K, polysilicon layer 56 overflowing from within recess 110 is selectively removed. Polycrystalline silicon layer 56 is uniformly polished from the upper surface 59 side by, for example, the CMP method. This polishing is continued until the polycrystalline silicon layer 56 covering the monocrystalline silicon layer 55 is removed and the upper surface 58 of the polycrystalline silicon layer 56 and the upper surface 59 of the monocrystalline silicon layer 55 are flatly continuous. Thereby, a polysilicon layer 56 embedded in the recess 110 is formed.

Next, referring to FIG. 6L, first trench 125, second trench 126 and third trench 127 are formed. The first trench 125 is the trench for the first isolation insulator 98 , the second trench 126 is the trench for the second isolation insulator 100 , and the third trench 127 is the trench for the cantilever isolation insulator 77 .

The first trench 125 and the second trench 126 are trenches shallower than the third trench 127 . The first trench 125 and the second trench 126 are formed from the first major surface 52 of the second layer 47 through the second layer 47 and stop at the second buried insulating layer 93 . Specifically, the second embedded insulating layer 93 functions as an etching stopper layer during the formation of the first trench 125 and the second trench 126, and the etching of the first trench 125 and the second trench 126 is performed by the second embedded insulating layer 93. It stops in the middle of the thickness direction. On the other hand, the third trench 127 is formed to reach the semiconductor wafer 121 (first layer 46) through the second layer 47 from the first major surface 52 of the second layer 47. As shown in FIG.

The first trench 125, the second trench 126 and the third trench 127 may be formed by, for example, anisotropic deep RIE (Reactive Ion Etching). The first trench 125 and the second trench 126 have side surfaces made of the polysilicon layer 56 and bottom surfaces made of the second buried insulating layer 93 . The third trench 127 has side surfaces extending over the semiconductor wafer 121 (first layer 46) and the second layer 47, and has a bottom surface made of the semiconductor wafer 121 (first layer 46). Note that the first trench 125, the second trench 126 and the third trench 127 may be formed in the same process, or may be formed in separate processes.

Next, referring to FIG. 6M, semiconductor wafer 121 in which first trench 125, second trench 126 and third trench 127 are formed is thermally oxidized, and the inner surface of first trench 125 and the inner surface of second trench 126 are thermally oxidized. and the inner surface of the third trench 127 are exposed to an oxygen atmosphere. As a result, the first isolation insulating portion 98 is formed inside the first trench 125 , the second isolation insulating portion 100 is formed inside the second trench 126 , and the cantilever isolation insulating portion 77 is formed inside the third trench 127 . It is formed.

Next, referring to FIG. 6N, a base insulating layer 105 is formed on the second layer 47 . Base insulating layer 105 may be formed by, for example, the CVD method. An insulating material for the underlying insulating layer 105 is formed over the entire first main surface 52 of the second layer 47 , and then the insulating material is selectively removed by patterning to form the underlying insulating layer 105 .

Next, referring to FIG. 6O, exposed wiring layer 106 and element pads 34 are formed on second layer 47 . The exposed wiring layer 106 and the element pads 34 may be formed by, for example, sputtering. A conductive material of the exposed wiring layer 106 and the element pad 34 is formed on the entire surface of the first main surface 52 of the second layer 47, and then the conductive material is selectively removed by patterning to form the exposed wiring layer 106 and the element pad 34. Element pads 34 are formed. An exposed wiring structure 102 is thus formed on the second layer 47 .

Next, referring to FIG. 6P, a release trench 128 extending from the first main surface 52 of the second layer 47 through the second layer 47 to reach the semiconductor wafer 121 (first layer 46) is formed. Although not shown here, a release trench 128 corresponding to the opening 75 of the body portion 73 may be formed at the same time. The release trench 128 may be formed by, for example, anisotropic deep RIE (Reactive Ion Etching). For example, the pattern of release trenches 128 may be the opposite pattern of body portion 73 of device structure 31 .

Next, referring to FIG. 6Q, etching gas for forming cavity 64 is supplied through release trench 128 . Thereby, a cavity 64 is selectively formed under the second layer 47 and a cantilever structure 65 is formed.

Next, referring to FIG. 6R, a lid wafer 129 forming lid substrate 27 is prepared. Lid wafer 129 is a silicon wafer in this embodiment. A concave portion 112 is formed in the lid wafer 129 from the second main surface 37 to the middle of the thickness direction of the lid wafer 129 . The concave portion 112 may be formed by, for example, anisotropic etching using an alkaline aqueous solution such as KOH (potassium hydroxide). By forming the recess 112 , a mesa portion 111 is formed around the recess 112 .

Next, referring to FIG. 6S, bonding layer 116 is formed on mesa portion 111 . Bonding layer 116 is formed, for example, by forming a metal seed layer on the surface (eg, top surface 113 and side surface 115) of mesa portion 111 and then growing the material of bonding layer 116 from the metal seed layer by plating. good too. For example, the metal seed layer may be a layer formed by laminating Ta, Pt and Au in this order from the surface of the mesa portion 111 .

Next, referring to FIG. 6T, lid wafer 129 is aligned with semiconductor wafer 121 . For example, the position of lid wafer 129 is adjusted so that bonding layer 116 of lid wafer 129 is in contact with polycrystalline silicon layer 56 of semiconductor wafer 121 . At this time, a bonding material 130 is interposed between the bonding layer 116 and the polycrystalline silicon layer 56 . The bonding material 130 is an Au bonding material in this embodiment.

Next, referring to FIG. 6U, bonding layer 116 and polycrystalline silicon layer 56 are eutectic bonded via bonding material 130 to form bonding portion 43 . Eutectic bonding is performed, for example, at a temperature higher than the eutectic temperature of Au and polycrystalline silicon (approximately 363° C.). In this embodiment, for example, eutectic bonding is performed at a temperature that is about 40° C. to 50° C. higher than the eutectic temperature (for example, 390° C. or higher and 420° C. or lower). If the bonding temperature is within this range, the eutectic reaction can be promoted. A metal filament 119 composed of a eutectic product generated by this eutectic reaction diffuses into the polycrystalline silicon layer 56 to form a junction 43 . Also, the surplus conductor 120 generated during the eutectic reaction may remain on the bonding layer 116 (second bonding layer 118 in this embodiment).

After that, the semiconductor wafer 121 and the lid wafer 129 are divided into chip units to obtain the element chips 8 . Then, the element chip 8, the control chip 7 and the base substrate 6 are assembled as shown in FIG. 1 and sealed with the sealing resin 9, whereby the electronic device 1 is obtained.

6F to 6K, the single-crystal silicon layer 55 and the polycrystalline silicon layer 56 are formed in separate steps in the manufacturing process described above. As such, monocrystalline silicon layer 55 and polycrystalline silicon layer 56 may be formed in the same epitaxial growth step. In this case, the surface roughness 134 of the polycrystalline silicon layer 56 projecting above the upper surface 58 of the single crystal silicon layer 55 may be removed by CMP after the epitaxial growth. As a result, the upper surface 58 of the monocrystalline silicon layer 55 and the upper surface 59 of the polycrystalline silicon layer 56 can be flat and continuous (see FIG. 6K).
<Effect of Electronic Device 1>
As described above, according to the electronic device 1 , the bonding portion 43 is formed by bonding the bonding layer 116 to the first polycrystalline silicon layer 62 as shown in FIG. 4 . Polycrystalline silicon can form a eutectic with the metal (Au in this embodiment) of the bonding layer 116 at a lower eutectic temperature than monocrystalline silicon.

Therefore, the polycrystalline silicon and the metal material component of the bonding layer 116 can be easily interdiffused, and the element substrate 26 and the lid substrate 27 can be bonded with high bonding strength. Also, the element structure 31 is formed in the first single crystal silicon layer 60 . Unlike polycrystalline silicon, single-crystal silicon does not have many crystal grain boundaries, so that it is possible to suppress the influence of crystal grain boundaries on device operation. In this way, by providing a silicon layer having suitable properties for each of the element structure 31 and the bonding portion 43, the bonding strength between the element substrate 26 and the lid substrate 27 is improved while suppressing the influence on the element operation. can do.

A first embedded wiring layer 92 is formed on the second main surface 53 side with respect to the base portion 81 of the first polycrystalline silicon layer 62 . Thereby, the wiring can be led out from the element region 44 to the outer region 45 without dividing the junction 43 between the element substrate 26 and the lid substrate 27 in the middle. As a result, it is possible to secure a large area for the joint portion 43, so that the joint strength between the element substrate 26 and the lid substrate 27 can be further improved.

Further, since the first contact region 99 is part of the first polycrystalline silicon layer 62 , it is not necessary to separately provide a wiring space for connecting to the first embedded wiring layer 92 in the first projecting portion 82 . As a result, the area of the base portion 81 can be increased in place of the wiring space, so that the area of the joint portion 43 can be secured widely.

Further, since the second contact region 101 is a part of the first polycrystalline silicon layer 62, it is not necessary to separately provide a wiring space for connecting to the first embedded wiring layer 92 for the second protruding portion 83. FIG. As a result, the area of the base portion 81 can be increased in place of the wiring space, so that the area of the joint portion 43 can be secured widely.

While embodiments of the disclosure have been described, the disclosure may be embodied in other forms.

For example, as a bonding material used for eutectic bonding between lid wafer 129 and semiconductor wafer 121, bonding material 131 containing Ge (germanium) as a main component may be used. More specifically, referring to FIG. 8, the bonding material 131 may be formed by forming an Al layer 132 on the bonding layer 116 and forming a Ge layer 133 on the Al layer 132 . In this case, the bonding layer 116 is preferably a barrier layer that prevents Al from diffusing into the lid wafer 129 while ensuring wettability with Al. TiN, TiW, TaN, or the like, for example, can be used as the bonding layer 116 . Further, as shown in FIG. 8, the bonding layer 116 may integrally connect the portion on the top surface 113 and the portion on the side surface 115 of the mesa portion 111 . In addition, in this bonding layer 116, the Ge layer can be replaced with a Zn (zinc) layer.

In the above-described embodiment, the outermost periphery of the second layer 47 is formed of the second monocrystalline silicon layer 61. However, for example, a second polycrystalline silicon layer further surrounding the second monocrystalline silicon layer 61 is formed. may have been That is, the form of the silicon layer of the outer region 45 can be appropriately changed according to the specifications of the electronic device 1 as long as the bonding between the bonding layer 116 and the first polycrystalline silicon layer 62 can be secured.

Alternatively, the control chip 7 may be omitted by forming the control circuit 19 shown in FIG. In this case, the element chip 8 may be directly mounted on the base substrate 6 .

As described above, the embodiments of the present disclosure are illustrative in all respects and should not be interpreted in a restrictive manner, and are intended to include modifications in all respects.

The following features can be extracted from the description of this specification and drawings.

[Appendix 1-1]
A first substrate (26) having a first major surface (28) and an opposite second major surface (29), comprising a first monocrystalline silicon layer (55, 60) and said first monocrystalline silicon a first substrate (26) comprising a semiconductor layer (47) having first polysilicon layers (56, 62) adjacent to the perimeter of layers (55, 60);
an element structure (31) formed on the first single crystal silicon layers (55, 60) on a surface layer portion of the first substrate (26) on the first main surface (28) side;
a bonding layer (116) containing a metal capable of forming a eutectic with silicon, and a bonding portion (43) formed by bonding the first polycrystalline silicon layers (56, 62) and the bonding layer (116); ) and a second substrate (27) bonded to said first substrate (26) via a substrate (26) and encapsulating said device structure (31).

According to this configuration, the bonding portion (43) is formed by bonding the bonding layer (116) to the first polysilicon layers (56, 62). Polycrystalline silicon can form a eutectic with the metal of the bonding layer (116) at a lower eutectic temperature than monocrystalline silicon. Therefore, the metal material components of the polycrystalline silicon and the bonding layer (116) can be easily interdiffused, and the first substrate (26) and the second substrate (27) can be bonded with high bonding strength. can. Also, an element structure (31) is formed in the first monocrystalline silicon layer (55, 60). Unlike polycrystalline silicon, single-crystal silicon does not have many crystal grain boundaries, so that it is possible to suppress the influence of crystal grain boundaries on device operation. In this way, by providing a silicon layer having suitable properties for each of the element structure (31) and the junction (43), the first substrate (26) and the first substrate (26) are separated from each other while suppressing the influence on the element operation. It is possible to improve the bonding strength with the second base material (27).

[Appendix 1-2]
The first polysilicon layers (56, 62) are formed in a base portion (81) forming the junction (43) and an element region (44) inside the junction (43). comprising an inner portion (82) and an outer portion (83) formed in an outer region (45) opposite said device region (44) with respect to said junction (43);
The base portion (81) is formed on the second main surface (29) side with respect to the first polycrystalline silicon layers (56, 62) and extends from the inner portion (82) toward the outer portion (83). a first wiring layer (92) extending across and electrically connecting said inner portion (82) and said outer portion (83);
an insulating layer (93) formed between the first wiring layer (92) and the base portion (81) for electrically insulating the first wiring layer (92) from the base portion (81); The electronic device (1) according to Appendix 1-1, comprising:

According to this configuration, the first wiring layer (92) is formed on the second main surface (29) side with respect to the base portion (81) of the first polysilicon layer (56, 62). As a result, the wiring can be pulled out from the element region (44) to the outer region (45) without dividing the junction (43) between the first base (26) and the second base (27) in the middle. can. As a result, it is possible to secure a large area for the joint portion (43), so that the joint strength between the first base material (26) and the second base material (27) can be further improved.

[Appendix 1-3]
a first isolation insulator (98) extending from said first main surface (28) of said first substrate (26) to said insulation layer (93) to electrically isolate a portion of said inner portion (82); and,
and a first contact region (99) formed in the inner portion (82) surrounded by the first isolation insulating portion (98) and connected to the first wiring layer (92). An electronic device (1) according to .

According to this configuration, since the first contact region (99) is part of the first polysilicon layer (56, 62), the wiring space connected to the first wiring layer (92) is defined as the inner part (82). ) need not be provided separately. As a result, the area of the base portion (81) can be increased in place of the wiring space, so that the area of the joint portion (43) can be widened.

[Appendix 1-4]
formed on the first main surface (28) of the first substrate (26) and extending from the first contact region (99) across the first isolation insulator (98) toward the element structure (31) Electronic device (1) according to claim 1-3, comprising a second wiring layer (106) extending along the length of the first contact region (99) and electrically connecting said device structure (31).

According to this configuration, electrical connection between the device structure (31) and the outer region (45) can be provided through the first wiring layer (92) and the second wiring layer (106).

[Appendix 1-5]
a second isolation insulation (100) extending from said first main surface (28) of said first substrate (26) to said insulation layer (93) to electrically isolate a portion of said outer portion (83); and,
and a second contact region (101) formed in the outer portion (83) surrounded by the second isolation insulating portion (100) and connected to the first wiring layer (92). Or the electronic device (1) according to appendix 1-4.

According to this configuration, since the second contact region (101) is part of the first polysilicon layer (56, 62), the space for wiring connected to the first wiring layer (92) is defined as the outer portion (83). ) need not be provided separately. As a result, the area of the base portion (81) can be increased in place of the wiring space, so that the area of the joint portion (43) can be widened.

[Appendix 1-6]
Electronic device (1) according to clause 1-5, comprising a pad layer (34) formed on said second contact region (101).

[Appendix 1-7]
The base portion (81) of the first polycrystalline silicon layers (56, 62) is formed in a ring shape surrounding the element structure (31) in plan view,
said inner portion (82) includes a first projection (82) selectively projecting from an inner peripheral edge (84) of said annular base portion (81) and having said first contact area (99) formed thereon; The electronic device (1) according to any one of Appendices 1-3 to 1-6.

[Appendix 1-8]
The base portion (81) of the first polycrystalline silicon layers (56, 62) is formed in a ring shape surrounding the element structure (31) in plan view,
The outer portion (83) includes a second protrusion (83) selectively protruding from an outer peripheral edge (85) of the annular base portion (81) and having the second contact area (101) formed thereon. The electronic device (1) according to appendix 1-5 or appendix 1-6.

[Appendix 1-9]
The electronic device (1) according to any one of Appendixes 1-2 to 1-8, wherein the first wiring layer (92) includes a wiring layer (92) made of polycrystalline silicon.

[Appendix 1-10]
The electronic device (1) according to appendix 1-9, wherein the first wiring layer (92) made of polycrystalline silicon contains impurities.

According to this configuration, the resistance value of the first wiring layer (92) can be appropriately adjusted by controlling the impurity concentration according to the amount of current flowing through the first wiring layer (92).

[Appendix 1-11]
The electronic device (1) according to any one of Appendixes 1-2 to 1-10, wherein the insulating layer (93) has a thickness of 10 nm or more and 4 μm or less.

[Appendix 1-12]
The element structure (31) comprises a cavity (64) formed inside the first substrate (26) and a cantilever structure (65) supported in a floating state with respect to the cavity (64). The electronic device (1) according to any one of Appendixes 1-1 to 1-11, comprising a MEMS structure (31) having

[Appendix 1-13]
The MEMS structure (31) extends from the first major surface (28) of the first substrate (26) to the cavity (64) and connects the cantilever structure (65) with a first potential portion (79) and a second electrical potential portion (79). 13. Electronic device (1) according to appendix 1-12, comprising a third isolation insulator (77) electrically isolating from the two-potential part (80).

[Appendix 1-14]
The electronic device (1) according to Clause 1-12 or Clause 1-13, wherein said MEMS structure (31) comprises a support (63) supporting said cantilever structure (65).

[Appendix 1-15]
Said first monocrystalline silicon layer (55, 60) and said first polycrystalline silicon layer (56, 62) are in contact with each other and intersect said first major surface (28) of said first substrate (26). The electronic device (1) according to any one of Appendixes 1-1 to 1-14, which forms an interface (57) extending in a direction extending in the direction of .

[Appendix 1-16]
The first monocrystalline silicon layers (55, 60) and the first polycrystalline silicon layers (56, 62) on the first main surface (28) of the first substrate (26) are flat surfaces continuous with each other. Electronic device (1) according to any one of clauses 1-1 to 1-15, forming (58,59).

[Appendix 1-17]
The electronic device (1) according to any one of appendices 1-1 to 1-16, wherein the first polycrystalline silicon layers (56, 62) have a thickness of 2 μm or more and 15 μm or less.

[Appendix 1-18]
The electronic device (1) according to any one of Appendixes 1-1 to 1-17, wherein the bonding layer (116) includes a bonding layer (116) containing at least one of Au, Ge and Zn.

[Appendix 1-19]
19. The method according to any one of Appendixes 1-1 to 1-18, comprising a metal filament (119) extending into said first polycrystalline silicon layer (56, 62) and containing a material component of said bonding layer (116). Electronic device (1) as described.

[Appendix 1-20]
Appendixes 1-1 to 1, wherein the first base material (26) includes a silicon substrate (46) formed on a surface layer portion on the second main surface (29) side and supporting the semiconductor layer (47). -19. An electronic device (1) according to any one of Clauses -19.

[Appendix 1-21]
a third substrate (7) having a circuit (19) electrically connected to the first substrate (26);
and a sealing resin (9) that seals the first base material (26), the second base material (27) and the third base material (7). Electronic device (1) according to any one of the preceding claims.

Reference Signs List 1: electronic device 2: device first main surface 3: device second main surface 4: device end surface 5: external terminal 6: base substrate 7: control chip 8: element chip 9: sealing resin 10: substrate first main surface 11: substrate second main surface 12: substrate end surface 13: substrate pad area 14: substrate lead-out portion 15: substrate pad 16: first main surface 17: second main surface 18: edge surface 19: control circuit 20: first pad area 21 : first lead-out portion 22 : control pad 23 : first control pad 24 : second control pad 25 : first wire 26 : element substrate 27 : lid substrate 28 : element first main surface 29 : element second main surface 30 : Element end surface 31 : Element structure 32 : Second pad region 33 : Second lead-out portion 34 : Element pad 35 : Second wire 36 : First main surface 37 : Second main surface 38 : End surface 39 : Resin first main surface 40 : Resin second main surface 41 : Resin end surface 42 : Boundary 43 : Joint portion 44 : Element region 45 : Outer region 46 : First layer 47 : Second layer 48 : Boundary 49 : First main surface 50 : Second main surface Surface 51 : End surface 52 : First main surface 53 : Second main surface 54 : End surface 55 : Monocrystalline silicon layer 56 : Polycrystalline silicon layer 57 : Interface 58 : Upper surface 59 : Upper surface 60 : First monocrystalline silicon layer 61 : Second single crystal silicon layer 62 : First polycrystalline silicon layer 63 : Supporting portion 64 : Cavity 65 : Cantilever structure 66 : Upper surface 67 : Bottom surface 68 : Side surface 69 : Peripheral edge 70 : Concavo-convex surface 71 : Inner peripheral surface 72 : Periphery Surface 73 : Body portion 74 : Connection portion 75 : Opening 76 : Base end portion 77 : Cantilever separating and insulating portion 78 : End portion 79 : First potential portion 80 : Second potential portion 81 : Base portion 82 : First projecting portion 83 : second protruding portion 84 : inner peripheral surface 85 : outer peripheral surface 86 : tip portion 87 : base end portion 88 : tip portion 89 : base end portion 90 : buried wiring structure 91 : first buried insulating layer 92 : first buried wiring Layer 93 : Second buried insulating layer 94 : First contact opening 95 : Second contact opening 96 : First end 97 : Second end 98 : First isolation insulating portion 99 : First contact region 100 : Second isolation Insulating portion 101 : Second contact region 102 : Exposed wiring structure 103 : First exposed wiring structure 104 : Second exposed wiring structure 105 : Base insulating layer 106 : Exposed wiring layer 107 : Cavity 108 : Inner peripheral surface 109 : Outer peripheral surface 110 : Recess 111 : Mesa 112 : Recess 113 : Top surface 114 : Bottom surface 115 : Side surface 116 : Bonding layer 117 : First bonding layer 118 : Second bonding layer 119 : Metal filament 120 : Surplus conductor 121 : Semiconductor wafer 122 : Monocrystalline silicon seed layer 123 : Polycrystalline silicon seed layer 124 : Space 125 : First trench 126 : Second trench 127 : Third trench 128 : Release trench 129 : Lid wafer 130 : Bonding material 131 : Bonding material 132 : Al Layer 133: Ge layer 134: Surface roughness _W1 : Width X: First direction Y: Second direction Z: Third direction

Claims (21)

A first substrate having a first major surface and an opposite second major surface, the first substrate comprising a first monocrystalline silicon layer and a first polycrystalline silicon layer adjacent and surrounding the first monocrystalline silicon layer. a first substrate comprising a semiconductor layer;
an element structure formed in the first single crystal silicon layer on a surface layer portion of the first substrate on the first main surface side;
a bonding layer containing a metal capable of forming a eutectic with silicon; bonded to the first base via a bonding portion formed by bonding the first polycrystalline silicon layer and the bonding layer; and a second substrate encapsulating the device structure. The first polysilicon layer includes a base portion forming the junction portion, an inner portion formed in an element region inside the junction portion, and an inner portion formed in the element region inside the junction portion, and on the opposite side of the element region to the junction portion. an outer portion formed in the outer region;
formed on the second main surface side with respect to the first polycrystalline silicon layer and extending across the base portion from the inner portion toward the outer portion to electrically connect the inner portion and the outer portion; a first wiring layer to be connected;
2. The electronic device according to claim 1, further comprising an insulating layer formed between said first wiring layer and said base portion and electrically insulating said first wiring layer from said base portion. a first separating insulating portion extending from the first main surface of the first base material to the insulating layer and electrically separating a portion of the inner portion;
3. The electronic device according to claim 2, further comprising a first contact region formed in said inner portion surrounded by said first isolation insulating portion and connected to said first wiring layer. formed on the first main surface of the first substrate, extending from the first contact region across the first isolation insulating portion toward the element structure, and electrically connecting the first contact region and the element structure 4. The electronic device according to claim 3, further comprising a second wiring layer that is electrically connected. a second separating insulating portion extending from the first main surface of the first base material to the insulating layer to electrically separate a portion of the outer portion;
5. The electronic device according to claim 3, further comprising a second contact region formed in said outer portion surrounded by said second isolation insulating portion and connected to said first wiring layer. 6. The electronic device of claim 5, comprising a pad layer formed over the second contact region. the base portion of the first polycrystalline silicon layer is formed in a ring shape surrounding the element structure in plan view,
The electronic device according to any one of claims 3 to 6, wherein the inner portion selectively protrudes from an inner peripheral edge of the annular base portion and includes a first protrusion on which the first contact region is formed. . the base portion of the first polycrystalline silicon layer is formed in a ring shape surrounding the element structure in plan view,
7. The electronic device according to claim 5, wherein the outer portion selectively protrudes from the outer periphery of the annular base portion and includes a second protrusion on which the second contact area is formed. 9. The electronic device according to claim 2, wherein said first wiring layer includes a wiring layer made of polycrystalline silicon. 10. The electronic device according to claim 9, wherein said first wiring layer made of polycrystalline silicon contains impurities. The electronic device according to any one of claims 2 to 10, wherein the insulating layer has a thickness of 10 nm or more and 4 µm or less. 12. The element structure according to any one of claims 1 to 11, wherein the element structure includes a MEMS structure having a cavity formed inside the first base material and a cantilever structure supported in a state of being floating with respect to the cavity. The electronic device according to the paragraph. the MEMS structure includes a third isolation insulator extending from the first major surface of the first substrate to the cavity to electrically isolate the cantilever structure into a first potential portion and a second potential portion; 13. Electronic device according to claim 12. 14. The electronic device of claim 12 or 13, wherein the MEMS structure includes a support that supports the cantilever structure. 15. Said first monocrystalline silicon layer and said first polycrystalline silicon layer are in contact with each other and form an interface extending in a direction crossing said first main surface of said first base material. The electronic device according to any one of . 16. The first monocrystalline silicon layer and the first polycrystalline silicon layer on the first main surface of the first substrate form flat surfaces continuous with each other, according to any one of claims 1 to 15. The electronic device described in . The electronic device according to any one of claims 1 to 16, wherein said first polycrystalline silicon layer has a thickness of 2 µm or more and 15 µm or less. The electronic device according to any one of claims 1 to 17, wherein the bonding layer includes a bonding layer containing at least one of Au, Ge and Zn. An electronic device as claimed in any one of the preceding claims, comprising a metal filament extending into the first polysilicon layer and comprising the material constituents of the bonding layer. The electronic device according to any one of claims 1 to 19, wherein the first base includes a silicon substrate formed on a surface layer portion on the second main surface side and supporting the semiconductor layer. a third base on which a circuit electrically connected to the first base is formed;
The electronic device according to any one of claims 1 to 20, further comprising a sealing resin that seals the first base, the second base and the third base.

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