JP2023047899A - Data analysis program, data analysis method, and information processor - Google Patents

Abstract

To provide an information processor capable of increasing a speed of matrix calculations.SOLUTION: An information processor 10 identifies: a block with no other unprocessed blocks adjacent in a first direction and no other unprocessed blocks adjacent in a second direction orthogonal to the first direction which can start the process as processable blocks 13a, 13b, 13c from the unprocessed blocks among the grid-like multiple blocks included in matrix data 13. The information processor 10 allocates an empty thread out of threads 15a and 15b that are executed in parallel while giving priority to the one with larger calculation cost 14a, 14b, 14c among the processable blocks 13a, 13b, 13c.SELECTED DRAWING: Figure 1

Description

The present invention relates to a data analysis program, data analysis method, and information processing apparatus.

A computer may process matrix data in parallel using multiple threads. In the parallelization of matrix computation, matrix data may be divided into a plurality of grid-like blocks, and different threads may process different blocks in parallel. However, depending on the contents of the matrix calculation, the computer cannot always process the plurality of blocks in any order, and may have restrictions on the processing order. A processing order constraint may be a constraint that processing of a block does not begin while there is an unprocessed neighboring block in at least one of two particular orthogonal directions (e.g., down and left). .

For example, a framework has been proposed that performs matrix reduction of persistent homology in parallel using multiple threads. The proposed framework is a sweep that removes as many lower nonzero elements as possible from the upper triangular matrix by adding another column to the left of the column contained in the upper triangular matrix. enforce the law. The proposed framework processes the diagonal block first, and when all the diagonal blocks have been processed, it processes the upper right adjacent block to the diagonal block. Thus, the proposed framework processes blocks in order from diagonal to top right.

An information processing device is proposed in which a matrix is divided into a plurality of submatrices each having M rows and M columns, and a plurality of elements having the same relative position among the plurality of submatrices are stored in a continuous storage area. It is In addition, information processing that left-aligns non-zero elements contained in a sparse matrix, stores the left half submatrix in JDS (Jagged Diagonal Storage) format, and saves the right half submatrix in CRS (Compressed Row Storage) format. A device has been proposed.

JP 2016-66329 A WO2017/154946

Simon Zhang, Mengbai Xiao, Chengxin Guo, Liang Geng, Hao Wang and Xiaodong Zhang, "HYPHA: A Framework based on Separation of Parallelisms to Accelerate Persistent Homology Matrix Reduction", Proc. of the 33rd ACM International Conference on Supercomputing (ICS 2019) , pp. 69-81, June 2019

However, depending on the contents of the matrix calculation, the computer cannot always process all of the blocks included in the matrix data in the same calculation time. If there is a bottleneck block with a long computation time, the number of blocks for which processing can be started may gradually decrease under restrictions on the processing order. As a result, the degree of parallelism decreases and the speed of matrix computation may decrease. Therefore, in one aspect, the present invention aims to speed up matrix calculation.

In one aspect, a data analysis program is provided that causes a computer to perform the following processes. A second block not adjacent to another unprocessed block in the first direction and orthogonal to the first direction from among the unprocessed blocks among the plurality of lattice-shaped blocks included in the matrix data. Blocks that are not adjacent to other unprocessed blocks in the direction are identified as processable blocks from which processing can begin. When there are a plurality of processable blocks, empty threads among a plurality of threads to be executed in parallel are assigned with priority in order of higher calculation cost based on the calculated load of each processable block.

Also, in one aspect, a computer-implemented data analysis method is provided. Also, in one aspect, an information processing apparatus having a storage unit and a processing unit is provided.

In one aspect, matrix computation is speeded up.

1 is a diagram for explaining an information processing device according to a first embodiment; FIG. 2 is a block diagram showing an example of hardware of an information processing device; FIG. FIG. 4 is a diagram showing an example of a matrix used for persistent homology; It is a figure which shows the execution example of the sweep-out method with respect to a matrix. FIG. 10 is a diagram showing an example of a column management table; FIG. FIG. 10 is a diagram showing an example of parallelization of the sweep method using a plurality of threads; FIG. 10 is a diagram illustrating an example of the procedure of a sweep method according to the second embodiment; FIG. FIG. 10 is a diagram (continued 1) showing a procedure example of a sweeping method according to the second embodiment; FIG. 12 is a diagram (continuation 2) showing an example of the procedure of the sweeping method according to the second embodiment; FIG. 11 is a diagram (continued 3) showing a procedure example of a sweeping method according to the second embodiment; It is a figure which shows the calculation example of the calculation cost of each block. It is a figure which shows the example of the influence which a block priority has on parallel processing. 2 is a block diagram showing an example of software of an information processing device; FIG. FIG. 11 is a flowchart illustrating an example of a procedure for thread initialization; FIG. 13 is a flowchart illustrating an example of a procedure of thread processing according to the second embodiment; FIG. 10 is a diagram illustrating an example of the influence of calculation costs of peripheral blocks on parallel processing; It is a figure which shows the correction example of the calculation cost with reference to the surrounding block. FIG. 11 is a flow chart showing an example of a procedure of thread processing according to the third embodiment; FIG.

Hereinafter, this embodiment will be described with reference to the drawings.
[First embodiment]
A first embodiment will be described.

FIG. 1 is a diagram for explaining an information processing apparatus according to the first embodiment.
The information processing apparatus 10 according to the first embodiment processes matrix data in parallel using a plurality of threads. The information processing device 10 may be a client device or a server device. The information processing device 10 may be called a computer or a data analysis device.

The information processing device 10 has a storage unit 11 and a processing unit 12 . The storage unit 11 may be a volatile semiconductor memory such as a RAM (Random Access Memory), or may be a non-volatile storage such as an HDD (Hard Disk Drive) or flash memory. The processing unit 12 is, for example, a processor such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). However, the processing unit 12 may include a specific application electronic circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The processor executes programs stored in a memory such as a RAM (which may be the storage unit 11), for example. A collection of processors may be called a multiprocessor or simply a "processor."

The storage unit 11 stores matrix data 13 . The matrix data 13 may represent a square matrix or an upper triangular matrix that does not contain non-zero elements below the diagonal. The matrix data 13 may also indicate boundary matrices used for persistent homology. A boundary matrix is a square matrix containing rows and columns corresponding to topological simplexes such as points, lines, triangles, tetrahedra, and the like. The boundary matrix indicates the relationship between simplexes, such as a line segment having two points as its boundary, a triangle having three line segments as its boundary, and a tetrahedron having four triangles as its boundary.

For parallel processing, the matrix data 13 is divided into a plurality of grid-like blocks. Multiple blocks may be the same size, and may each include a certain number of rows and a certain number of columns. If the matrix data 13 indicates an upper triangular matrix, the blocks may form a triangle with the blocks on the diagonal and the blocks above the diagonal.

The processing unit 12 executes a plurality of threads including threads 15a and 15b in parallel. A thread may also be called a process. A plurality of threads may be executed by different cores of the processing unit 12 . However, the thread may be executed by a processor other than the processing unit 12 of the information processing device 10, or may be executed by an information processing device other than the information processing device 10. FIG. If there is an empty thread that is not processing a block among the plurality of threads, the processing unit 12 allocates an empty thread to any unprocessed block included in the matrix data 13, and causes the allocated thread to process the block. Let

Here, the processing unit 12 identifies a block that satisfies an order condition from unprocessed blocks included in the matrix data 13 as a processable block that can start processing. The order condition is that no unprocessed blocks are adjacent in a first direction and no unprocessed blocks are adjacent in a second direction orthogonal to the first direction. For example, the first direction is downward with increasing row numbers and the second direction is leftward with decreasing column numbers. In an initial state in which all blocks are unprocessed, the processing unit 12 may identify a diagonal block as a processable block.

The processable block changes as the processing by multiple threads progresses. The processing unit 12 identifies a block as a processable block when the processing of a block adjacent in the first direction and the processing of a block adjacent in the second direction are completed when viewed from a certain block. You may As an example, the processing unit 12 identifies processable blocks 13 a , 13 b , and 13 c from multiple blocks included in the matrix data 13 .

When there are a plurality of processable blocks, the processing unit 12 preferentially allocates free threads to the processable blocks in descending order of calculation cost. A computational cost is calculated for each processable block. The computational cost of a processable block is based on the computational load of that processable block. It can also be said that the computational cost indicates the load given to the threads. For example, the processing unit 12 calculates the calculation cost 14a of the processable block 13a, the calculation cost 14b of the processable block 13b, and the calculation cost 14c of the processable block 13c. When the calculation cost 14b is the highest, the processing unit 12 preferentially allocates free threads to the processable block 13b.

The computational cost may change as the processing progresses with multiple threads. The calculation cost of a certain block may be calculated based on the number of elements for which processing can be omitted among the plurality of elements included in the block. may be calculated based on the number of Columns for which processing can be omitted may be determined based on the processing results of other blocks located in the first direction when viewed from the block.

When a thread 15a is assigned to a certain block, the thread 15a processes that block. Thread 15a may update that block with another block in the second direction. The processing performed by thread 15a may be a sweep method that eliminates the lowest non-zero elements in a column by adding it to another column to the left of that column. Repeated addition of other columns minimizes the row number of the lowest non-zero element. When the lowest non-zero element that is not erased is determined for a certain column, the thread 15a may determine that subsequent processing of that column can be omitted.

In an initial state in which all blocks are unprocessed, it may be determined that processing can be omitted for some columns, such as columns with no non-zero elements. Further, based on the symmetry of the matrix data 13, whether or not to omit the i column may be determined based on the processing result of the i row. When processing of all blocks included in the matrix data 13 is completed, the processing unit 12 stops multiple threads including the threads 15a and 15b. The processing unit 12 outputs the processing result of the matrix data 13 . The processing unit 12 may display the processing result on a display device connected to the information processing device 10, store it in a non-volatile storage, or transmit it to another information processing device.

As described above, the information processing apparatus 10 according to the first embodiment selects processable blocks for which processing can be started from unprocessed blocks among a plurality of lattice-shaped blocks included in the matrix data 13. Identify. The processable blocks are subject to an order condition that no other unprocessed blocks are adjacent in a first direction and no other unprocessed blocks are adjacent in a second direction orthogonal to the first direction. is a block that satisfies The information processing apparatus 10 allocates empty threads among the plurality of threads to be executed in parallel, preferentially in descending order of calculation cost based on the calculated load of each processable block among the plurality of processable blocks.

As a result, the processing of the matrix data 13 is parallelized even if there are restrictions on the processing order, and the matrix calculation is speeded up. Also, even if there is a bottleneck block with a long calculation time, the processing of the block is preferentially started, so the situation where the number of processable blocks decreases as the processing progresses is suppressed. Therefore, a situation in which the number of processable blocks is less than the number of threads and the degree of parallelism is reduced is suppressed, and a plurality of threads are utilized to speed up the matrix calculation.

Note that the information processing apparatus 10 may specify blocks on the diagonal as processable blocks in the initial state, and after processing of some blocks on the diagonal is completed, other blocks on the diagonal and It may be processed in parallel with blocks that do not exist. As a result, the information processing apparatus 10 can maintain the degree of parallelism by utilizing a plurality of threads, compared to the case where processing of other blocks is started after all blocks on the diagonal line have been processed.

Further, the information processing apparatus 10 may calculate the calculation cost based on the processing results of blocks adjacent in the first direction. In that case, the information processing apparatus 10 may determine columns for which processing can be omitted based on the processing results of blocks adjacent in the first direction, and the calculation is performed based on the number of columns for which processing can be omitted. You can calculate the cost. Thereby, the information processing apparatus 10 can accurately estimate the calculation cost proportional to the calculation time of the thread.

Further, the information processing apparatus 10 may correct the calculation cost of the processable block based on the calculation cost of the unprocessed block within a specific range from the processable block. If the computation cost of an unprocessed block adjacent in the third direction opposite to the second direction is greater than the computation cost of the processable block, the information processing device 10 increases the computation cost of the processable block. may As a result, even if an unprocessed block with a high computational cost is hidden behind a processable block with a low computational cost, processing of the block with a high computational cost is started early, and the decrease in parallelism is suppressed. .

[Second embodiment]
Next, a second embodiment will be described.
The information processing apparatus 100 according to the second embodiment executes persistent homology matrix calculations in parallel using a plurality of threads. The information processing device 100 may be a client device or a server device. The information processing device 100 may be called a computer, parallel processing device, data analysis device, or matrix operation device.

FIG. 2 is a block diagram illustrating an example of hardware of an information processing apparatus.
The information processing apparatus 100 has a CPU 101, a RAM 102, an HDD 103, a GPU 104, an input interface 105, a medium reader 106 and a communication interface 107 connected to a bus. A CPU 101 corresponds to the processing unit 12 of the first embodiment. A RAM 102 or HDD 103 corresponds to the storage unit 11 of the first embodiment.

The CPU 101 is a processor that executes program instructions. CPU 101 loads at least part of the programs and data stored in HDD 103 into RAM 102 and executes the programs. The CPU 101 has a plurality of cores such as cores 101a, 101b, 101c, and 101d. Multiple cores can execute multiple threads in parallel. Note that the information processing apparatus 100 may have a plurality of CPUs. A collection of CPUs or a collection of CPU cores may be referred to as a multiprocessor or simply a processor.

The RAM 102 is a volatile semiconductor memory that temporarily stores programs executed by the CPU 101 and data used for calculations by the CPU 101 . The information processing device 100 may have a type of volatile memory other than RAM.

The HDD 103 is a non-volatile storage that stores an OS (Operating System), middleware, software programs such as application software, and data. The information processing apparatus 100 may have other types of non-volatile storage such as flash memory and SSD (Solid State Drive).

The GPU 104 is a processor that executes program instructions according to instructions from the CPU 101 . The GPU 104 generates images in cooperation with the CPU 101 and outputs the images to the display device 111 connected to the information processing apparatus 100 . The display device 111 is, for example, a CRT (Cathode Ray Tube) display, a liquid crystal display, an organic EL (Electro Luminescence) display, or a projector. Other types of output devices such as printers may be connected to the information processing apparatus 100 .

Also, the GPU 104 has a plurality of cores such as cores 104a, 104b, 104c, and 104d. Multiple cores can execute multiple threads in parallel. GPU 104 may have GPU memory that is different from RAM 102 . GPU memory is a volatile semiconductor memory that temporarily stores programs and data. Note that the information processing apparatus 100 may have a plurality of GPUs. A collection of GPUs or a collection of GPU cores may be referred to as multiprocessors or simply processors. A thread in a second embodiment, which will be described later, is executed by the core of GPU 101 or the core of GPU 104 .

Input interface 105 receives an input signal from input device 112 connected to information processing apparatus 100 . The input device 112 is, for example, a mouse, touch panel, or keyboard. A plurality of input devices may be connected to the information processing apparatus 100 .

The medium reader 106 is a reading device that reads programs and data recorded on the recording medium 113 . The recording medium 113 is, for example, a magnetic disk, an optical disk, or a semiconductor memory. Magnetic disks include flexible disks (FDs) and HDDs. Optical discs include CDs (Compact Discs) and DVDs (Digital Versatile Discs). A medium reader 106 copies the program and data read from the recording medium 113 to another recording medium such as the RAM 102 or HDD 103 . The read program may be executed by CPU 101 .

The recording medium 113 may be a portable recording medium. Recording medium 113 may be used to distribute programs and data. Recording medium 113 and HDD 103 may also be referred to as computer-readable recording media.

The communication interface 107 is connected to the network 114 and communicates with other information processing apparatuses via the network 114 . The communication interface 107 may be a wired communication interface connected to a wired communication device such as a switch or router, or a wireless communication interface connected to a wireless communication device such as a base station or access point.

Next, persistent homology will be explained.
FIG. 3 is a diagram showing an example of a matrix used for persistent homology.
Persistent homology is a topological technique that quantitatively represents the shape features of an object. Persistent homology is sometimes used in technical fields such as material science, life science, and social science, and is sometimes used as a so-called big data analysis method.

Persistent homology expresses the shape of an object as a set of points and quantitatively analyzes the bias of the point distribution. Persistent homology regards a point as a particle of radius r and detects the appearance and disappearance of closed regions while changing the radius r. As long as the radius r is small, the points do not touch each other, so there is no closed region (sometimes called a hole) surrounded by the points. As the radius r increases, nearby points may contact each other and a hole may appear. If the radius r is further increased, the holes are crushed and disappear because distant points also come into contact with each other.

Holes of different sizes may appear at different radii r. The radius r at which the hole appears and the radius r at which the hole disappears depend on the point distribution. The timing of the appearance and disappearance of holes is algebraically analyzed through boundary matrix contraction as described below.

The shape of an object is represented as a simplicial complex, which is a combination of various simplexes. Simplexes include a point as a 0-dimensional simplex, a line segment as a 1-dimensional simplex, a triangle as a 2-dimensional simplex, a tetrahedron as a 3-dimensional simplex, and the like. A simplex of one dimension may have a simplex of lower dimension as its boundary. A line segment may have two points as boundaries that are endpoints. A triangle may have three line segments as boundaries. A tetrahedron may have four triangles as boundaries.

As an example, a triangular shaped object includes simplexes 30,31,32,33,34,35,36. The simplexes 30, 31, 32 are points. Simplexes 33, 34 and 35 are line segments. Simplex 36 is triangular. Simplexes 30, 31, 32 have no boundaries. Simplex 33 has simplex 30, 32 as a boundary. Simplex 34 has simplex 31 and 32 as boundaries. Simplex 35 has simplex 30, 31 as a boundary. Simplex 36 has simplexes 33, 34, and 35 as boundaries.

The information processing apparatus 100 generates a matrix 41, which is a boundary matrix, from the above geometric data. Matrix 41 is a square and upper triangular matrix. Rows 0 to 6 of matrix 41 correspond to simplexes 30, 31, 32, 33, 34, 35, and 36; Similarly, columns 0-6 of matrix 41 correspond to simplexes 30, 31, 32, 33, 34, 35, and 36. A column means a higher-dimensional simplex, and a row means a lower-dimensional simplex that can be a boundary of a higher-dimensional simplex. A matrix 41 is a set of flags indicating whether or not there is a boundary. Element (i, j) of matrix 41 is 1 when simplex j has simplex i as a boundary. Otherwise, element (i,j) is zero.

Therefore, columns 0 to 2 of matrix 41 are zero vectors. The third column of matrix 41 is (1010000). Column 4 of matrix 41 is (0110000). The fifth column of matrix 41 is (1100000). Column 6 of matrix 41 is (0001110). Due to its nature as a boundary matrix, the matrix 41 is square and upper triangular.

FIG. 4 is a diagram showing an execution example of the sweep method for matrices.
The information processing device 100 executes the sweep method on the matrix 41 . The unit operation of the sweep method of the second embodiment is to add a column to another column to the left of the column. Since the elements of matrix 41 are binary 0 or 1, addition is defined as exclusive OR. That is, 0+0=0, 0+1=1, 1+0=1, 1+1=0.

The purpose of this sweeping method is to minimize the row number of the lowest non-zero elements for each column. Below, the row number of the lowest non-zero element in column j is sometimes written as low(j). If the j column contains no non-zero elements, then low(j)=-1. If two columns contain nonzero elements in the same row, adding one column to the other eliminates the nonzero elements in the other column. Therefore, after performing the sweep method, multiple columns each containing at least one non-zero element will have different low(j).

If i=low(j)>−1 holds after executing the sweep method, that is, if the lowest non-zero element in the j column is in the i row, the information processing apparatus 100 performs the element (i, j ) is determined to be a pivot. Pivot (i, j) is interpreted such that i represents the appearance timing of a hole and j represents the disappearance timing of the hole. Therefore, the calculation of persistent homology is performed by transforming the boundary matrix by the sweep method.

Due to the nature of the above sweep method, the information processing apparatus 100 processes the columns included in the matrix 41 in order from left to right. Further, the information processing apparatus 100 processes a plurality of elements included in the same column in order from bottom to top. Since the matrix 41 is an upper triangular matrix, the information processing apparatus 100 processes the plurality of elements in order from the lower left to the upper right.

When processing the j1 column, the information processing apparatus 100 searches for non-zero elements from the bottom to the top of the j1 column. When a non-zero element is detected, the information processing apparatus 100 searches other columns on the left side of that column for the j2 column having the same low as the row number of the detected non-zero element. If there is a corresponding j2 column, the information processing apparatus 100 adds the entire j2 column to the j1 column and searches upward for non-zero elements. If the corresponding j2 column does not exist, the row number of the non-zero element becomes low(j1) and the j1 column pivot is established.

When the pivot of the j1 column is determined, the information processing apparatus 100 does not need to scan the j1 column further upward, and ends the processing of the j1 column. This is because non-zero elements other than the lowest non-zero element are irrelevant to the pivot and need not be deleted.

In the sweep method, it may be determined that the processing of a certain column can be omitted. Among the columns for which processing can be omitted, there are columns that are determined at the beginning of the sweep method, and there are columns that are determined in the middle. Columns with all zero elements in the initial boundary matrix can be skipped and are determined at the start. Further, for columns whose pivots have been determined as described above, subsequent processing can be omitted, and determination is made during the sweeping method. Also, when the pivot (i, j) is determined, all the elements of the i column become zero due to the property of persistent homology. Therefore, it may be determined that the i-column can be skipped, and the determination can be made in the middle of the sweep-out method.

When performing a simple sweep method on the matrix 41, the information processing device 100 selects the 0 column and determines low(0)=-1 because the 0 column is the zero vector. Similarly, the information processing apparatus 100 determines low(1)=low(2)=-1. Next, the information processing apparatus 100 selects 3 columns and detects non-zero elements of (2, 3). The information processing apparatus 100 determines that low(3)=2 because there is no column with low=2 on the left side, and ends the processing of the 3rd column.

Next, the information processing apparatus 100 selects 4 columns and detects non-zero elements of (2, 4). Since low(3)=2, the information processing apparatus 100 adds 3 columns to 4 columns. As a result, column 4 is transformed into (1100000) and matrix 41 is transformed into matrix 42 . Next, the information processing apparatus 100 detects non-zero elements of (1, 4). The information processing apparatus 100 determines that low(4)=1 since there is no column with low=1 on the left side, and ends the processing of the 4th column.

Next, the information processing apparatus 100 selects 5 columns and detects non-zero elements of (1, 5). The information processing apparatus 100 adds 4 columns to 5 columns because low(4)=1. This transforms column 5 into (0000000) and matrix 42 into matrix 43 . Further, the information processing apparatus 100 determines low(5)=−1 because the 5th column is a zero vector.

Next, the information processing apparatus 100 selects 6 columns and detects non-zero elements of (5, 6). The information processing apparatus 100 determines that low(6)=5 since there is no column of low=5 on the left side, and ends the processing of the 6th column. Accordingly, the information processing apparatus 100 determines the elements (2, 3), (1, 4), and (5, 6) as pivots.

FIG. 5 is a diagram showing an example of a column management table.
The information processing apparatus 100 may hold the column management table 131 for controlling the sweep method. The column management table 131 associates column numbers, low and zero flags. The column number identifies the column of the boundary matrix. low is the row number of the row where the lowest non-zero element resides. However, low is -1 for columns in which there are no non-zero elements. The initial value of low is -1. A zero flag indicates whether the column is a zero vector.

If all elements in a column are zero, the zero flag for that column is updated to YES. When the pivot of column j is confirmed, low(j) is updated to an integer greater than or equal to 0. If pivot (i,j) is settled, the zero flag for column i may be updated to YES. A column whose low is 0 or more or whose zero flag is YES is a column whose processing can be omitted.

Next, parallelization of the sweep method for boundary matrices will be described. The information processing apparatus 100 executes a plurality of threads in parallel using a plurality of cores included in the CPU 101 or a plurality of cores included in the GPU 104, and parallelizes the sweep method by the plurality of threads.

FIG. 6 is a diagram showing an example of parallelization of the sweep method using a plurality of threads.
The information processing device 100 divides the matrix 41 into a plurality of blocks. A plurality of blocks is a square submatrix containing the same number of rows and the same number of columns. A plurality of blocks are arranged in a grid. The length of one side of the block may be fixed in advance, specified by the user, or calculated based on the size of the matrix 41 . For example, the information processing apparatus 100 calculates the length of one side of the block as the length of one side of the matrix÷(number of threads×α). α is a constant representing an integer of 1 or more.

For example, the information processing apparatus 100 divides the matrix 41 of 7 rows and 7 columns into blocks of 2 rows and 2 columns to generate blocks 50, 51, 52, 53, 54, 55, 56, 57, 58, and 59. . Blocks 50, 51, 52, 53 are diagonal blocks containing diagonal elements. Block 54 is the right neighbor of block 50 , block 55 is the right neighbor of block 51 , and block 56 is the right neighbor of block 52 . Block 57 is the right neighbor of block 54 and block 58 is the right neighbor of block 55 . Block 59 is right next to block 57 . Note that one blank column is inserted at the right end of the matrix 41 and one blank row is inserted at the bottom end of the matrix 41 for size adjustment. Further, the information processing apparatus 100 does not have to generate blocks in areas outside the upper triangle.

These multiple blocks are processed in order under certain order conditions. If a block has an adjacent unprocessed block to its left or an unprocessed adjacent block below it, processing of that block is not started. This is because the columns to be added are not determined if the left block is unprocessed, and the necessity of erasing non-zero elements is not determined if the lower block is unprocessed. Therefore, in the initial state where all blocks are unprocessed, only diagonal blocks are processable blocks.

The information processing apparatus 100 allocates an empty thread having no block being processed to a processable block having no unprocessed block adjacent to the left and no unprocessed block adjacent to the lower side. When a certain thread finishes processing a block, the information processing apparatus 100 searches for a processable block. As a block becomes processed, a new processable block may occur. The information processing apparatus 100 allocates a thread that has become free after processing a block to any processable block.

The block processing performed in each thread is the same as the sweep method described above. A thread processes columns in a block from left to right. However, the thread skips columns that have already been determined to be optional. The thread scans the elements in the same row from bottom to top. Upon finding a non-zero element, the thread searches the left column for the column with the same low as the row number of the non-zero element.

The other column may be a column within the same block or a column outside the block. If there is a matching partner column, the thread adds the entire partner column to the column being processed. At this time, elements of other blocks above the block being processed may also be updated. If there is no matching partner column, the detected non-zero element remains as the pivot. In this case, the column being processed is determined as a column whose processing can be omitted thereafter.

Here, the following method is also conceivable as an example of a method of specifying processable blocks and allocating free threads. First, the information processing apparatus 100 allocates threads to blocks 50, 51, 52, and 53, which are diagonal blocks. If the number of threads is four, four threads can process blocks 50, 51, 52 and 53 in parallel.

When the processing of blocks 50, 51, 52, and 53 is all completed, information processing apparatus 100 identifies blocks 54, 55, and 56 above the upper right oblique line parallel to the diagonal line as processable blocks. , 56 are assigned threads. In this case, three threads can process blocks 54, 55 and 56 in parallel.

When the processing of blocks 54 , 55 , 56 is all completed, the information processing apparatus 100 further identifies blocks 57 , 58 above the upper right diagonal line as processable blocks, and allocates threads to the blocks 57 , 58 . In this case, two threads can process blocks 57 and 58 in parallel. When the processing of blocks 57 and 58 is completed, the information processing apparatus 100 further identifies block 59 above the upper right diagonal line as a processable block, and assigns a thread to block 59 . In this case, one thread processes block 59 .

However, in the thread allocation method described above, the number of processable blocks decreases step by step to 4, 3, 2, and 1 as the sweep-out method progresses. As a result, the number of threads used is gradually reduced, and the degree of parallelism is reduced. In addition, since blocks may include columns whose processing can be omitted, the calculation time differs depending on the block. Thus, bottleneck blocks with long computation times can slow the progress of the sweep-out method.

Therefore, the information processing apparatus 100 sequentially allocates free threads to blocks that have become processable blocks without being constrained by diagonal lines. In addition, the information processing apparatus 100 estimates the calculation cost of each processable block, and allocates threads to the block with the highest calculation cost first.

FIG. 7 is a diagram illustrating a procedure example of the sweep method according to the second embodiment.
Matrix 61 shows blocks arranged in an upper triangle. The matrix 61 is, for example, obtained by dividing a matrix of 100 rows and 100 columns into blocks of 10 rows and 10 columns. Note that the coordinates (m, n) in the matrix 61 indicate the position of the block and are different from the coordinates (i, j) indicating the position of the element. m is the block row number and n is the block column number.

The information processing apparatus 100 identifies 10 diagonal blocks as processable blocks included in the matrix 61 . The information processing apparatus 100 calculates the calculation costs of these ten blocks as 2, 1, 2, 2, 5, 1, 7, 2, 4, and 3. The calculation cost is, for example, the number of columns other than columns determined to be process-skippable, that is, the number of columns to be processed.

The information processing apparatus 100 inserts information about processable blocks into the waiting block queue 132 . The information of processable blocks includes block names and computational costs. A block name is an identifier for identifying a processable block, and is, for example, coordinates of the processable block. In the waiting block queue 132, information on processable blocks is sorted in descending order of calculation cost. Information of processable blocks having the same calculation cost is sorted in ascending order of block row number m.

Therefore, in the initial state, the head of the waiting block queue 132 is block B (6, 6) with a calculation cost of 7. Next is block B(4,4) with a computational cost of 5. Next is block B(8,8) with a computational cost of four. Next is block B(9,9) with a computational cost of 3. Next is block B(0,0) with a computational cost of two.

Next is block B(2,2) with a computational cost of two. Next is block B(3,3) with a computational cost of two. Next is block B(7,7) with a computational cost of two. Next is block B(1,1) with a computational cost of one. Next is block B(5,5) with a computational cost of one.

The information processing apparatus 100 also holds a thread table 133 that manages the state of threads. The thread table 133 associates thread numbers with states. A thread number is an identifier that identifies a thread. If no blocks are being processed, the state is READY. If there is a block in process, the state is the identifier of the block in process. In the initial state, the state of all threads is READY.

FIG. 8 is a diagram (continuation 1) showing an example of the procedure of the sweeping method according to the second embodiment.
The information processing apparatus 100 extracts block B (6, 6) with the highest priority from the waiting block queue 132 and assigns thread #1 to it. Thread #1 begins processing block B(6,6). Next, the information processing apparatus 100 extracts block B(4, 4) with the highest priority at this point from the waiting block queue 132, and assigns thread #2 to it. Thread #2 begins processing block B(4,4).

Next, the information processing apparatus 100 extracts block B (8, 8) with the highest priority from the waiting block queue 132 and assigns thread #3 to it. Thread #3 begins processing block B(8,8). Next, the information processing apparatus 100 extracts block B (9, 9) with the highest priority from the waiting block queue 132 and assigns thread #4 to it. Thread #4 begins processing block B(9,9). Thus, matrix 61 becomes matrix 62 .

FIG. 9 is a diagram (continuation 2) showing an example of the procedure of the sweeping method according to the second embodiment.
Since the calculation cost of block B (9, 9) is small, processing of thread #4 ends first. Then, the information processing apparatus 100 searches for a block that has newly become processable as the block B (9, 9) has been processed. There are no new processable blocks here. The information processing apparatus 100 extracts block B(0,0) with the highest priority from the waiting block queue 132 and assigns thread #4 to it. Thread #4 begins processing block B(0,0). Thus, matrix 62 becomes matrix 63 .

FIG. 10 is a diagram (continuation 3) showing an example of the procedure of the sweeping method according to the second embodiment.
Following thread #4, processing of thread #3 ends. Then, the information processing apparatus 100 searches for a block that has newly become processable as the block B(8, 8) has been processed. Here, since left block B(8,8) has been processed and lower block B(9,9) has been processed, block B(8,9) is a new processable block. The information processing apparatus 100 calculates the calculation cost of block B (8, 9) as 2, and inserts the information of block B (8, 9) into the waiting block queue 132 .

In the waiting block queue 132, the priority of block B(8,9) is between block B(7,7) and block B(1,1). The information processing apparatus 100 extracts block B(2,2) with the highest priority from the waiting block queue 132 and assigns thread #3 to it. Thread #3 begins processing block B(2,2). Thus, matrix 63 becomes matrix 64 . In this way, the parallel processing of the sweep method proceeds.

FIG. 11 is a diagram illustrating a calculation example of the calculation cost of each block.
Blocks 71 , 72 , 73 , 74 , 75 and 76 are included in matrix 61 . Block 71 is B(5,5), Block 72 is B(6,6), Block 73 is B(7,7), Block 74 is B(5,6), Block 75 is B(6,7), Block 76 is B(5,7). Blocks 71, 72, and 73 are processable blocks.

The computational cost of block 71 is 1, because of the 10 columns included in block 71, 9 are optional columns and 1 is the column to be processed. The computational cost of block 72 is 7, because of the 10 columns included in block 72, 3 are optional columns and 7 are columns to be processed. The computational cost of block 73 is 2, because of the 10 columns included in block 73, 8 are optional columns and 2 are columns to be processed.

The calculation cost of block 74 is calculated after the processing of block 72 is completed, since it is greatly influenced by the processing results of the blocks below block 74 . Similarly, the computational cost of block 75 is calculated after block 73 has been processed, and the computational cost of block 76 is computed after block 75 has been processed. In the second embodiment, the computational cost of block 74 is calculated when block 74 becomes a processable block. Similarly, the computational cost of block 75 is calculated when block 75 becomes a processable block. The computational cost of block 76 is calculated when block 76 becomes a processable block.

Note that the number of columns for which processing can be omitted gradually increases as the sweeping-out method progresses. The number of optional columns at the start of block 74 is the same as at the start of block 72 or is greater than at the start of block 72 . Therefore, the computational cost of block 74 is less than block 72. Similarly, the computational cost of block 75 is less than block 73 and the computational cost of block 76 is less than block 75 .

Next, the effect of processing blocks in descending order of computational cost will be described.
FIG. 12 is a diagram illustrating an example of how block priority affects parallel processing.
Matrix 83 is an upper triangular matrix at the start of the sweep method. Suppose that the computational cost of columns 81 and 82 among the columns included in matrix 83 is relatively high. If multiple threads sequentially process the processable blocks without considering the computational cost, the matrix 83 may become like the matrix 84 during the sweep method.

As shown in matrix 84, the blocks in columns with lower computational costs are processed first, leaving the blocks in columns 81 and 82 with higher computational costs. Due to restrictions on the processing order, between column 81 and column 82, blocks in the same row as the block being processed in column 81 and in rows above it are not processable blocks. Also, on the right side of column 82, the blocks in the same row as the block being processed in column 82 and the rows above it do not become processable blocks.

Therefore, the number of processable blocks is reduced. In matrix 84, the number of processable blocks is limited to two. In that case, even if the information processing apparatus 100 activates a large number of threads, only a small number of the threads process blocks, and the degree of parallelism decreases.

On the other hand, when preferentially processing blocks with high calculation costs, the matrix 83 is expected to become like the matrix 85 during the sweeping method. As shown in the matrix 85, processing of blocks in columns 81 and 82 having high calculation costs is preferentially started, so the number of unprocessed blocks in columns 81 and 82 tends to decrease. As the number of unprocessed blocks in column 81 decreases, processable blocks are more likely to occur between column 81 and column 82 . Also, as the number of unprocessed blocks in the column 82 decreases, processable blocks are more likely to occur on the right side of the column 82 .

Therefore, the decrease in processable blocks is suppressed. As a result, multiple threads activated by the information processing apparatus 100 can be utilized, and parallelism is maintained. Maintaining the degree of parallelism speeds up the matrix computation of the sweep method.

Next, the software structure and processing procedure of the information processing apparatus 100 will be described.
FIG. 13 is a block diagram illustrating an example of software for an information processing device.
The information processing apparatus 100 has a geometric data storage unit 121 , a matrix storage unit 122 , a control information storage unit 123 , a matrix generation unit 124 , a thread initialization unit 125 and a thread processing unit 126 . The thread processing unit 126 has a sweep method execution unit 127 , a block search unit 128 and a calculation cost calculation unit 129 .

The geometric data storage unit 121, the matrix storage unit 122, and the control information storage unit 123 are implemented using storage areas of the RAM 102 or GPU memory, for example. The matrix generation unit 124, the thread initialization unit 125, and the thread processing unit 126 are implemented using, for example, the CPU 101 or GPU 104 and programs.

The geometric data storage unit 121 stores geometric data including multiple points. The matrix storage unit 122 stores a boundary matrix for persistent homology. The control information storage unit 123 stores control information used for contraction of the boundary matrix. The control information includes the column management table 131, waiting block queue 132 and thread table 133 described above.

The matrix generation unit 124 detects simple substances such as points, line segments, triangles, and tetrahedrons from the geometric data stored in the geometric data storage unit 121, and generates a boundary matrix indicating the boundary relationship between the simple substances. Matrix generator 124 stores the generated boundary matrix in matrix storage 122 . Note that different information processing apparatuses may perform the generation of the boundary matrix and the contraction of the boundary matrix.

The thread initialization unit 125 controls parallelization of the sweep method using a plurality of threads. The thread initialization unit 125 activates multiple threads and causes different cores to execute the threads. The number of threads may be fixed, specified by the user, or variable according to the number of processor cores. Also, the thread initialization unit 125 divides the matrix stored in the matrix storage unit 122 into a plurality of blocks.

In addition, the thread initialization unit 125 determines columns for which processing can be omitted from the matrix in the initial state. The thread initialization unit 125 selects diagonal blocks on the diagonal line as processable blocks, and calculates the calculation cost of each processable block. The thread initialization unit 125 inserts information about processable blocks into the waiting block queue 132 in descending order of calculation cost.

When all the threads are stopped, the thread initialization unit 125 outputs the processing result of the boundary matrix. The thread initialization unit 125 may display the processing result on the display device 111, store it in a non-volatile storage, or transmit it to another information processing device. The processing result may include the reduced boundary matrix and may include information on the detected pivots.

The thread processing unit 126 defines processing for each of a plurality of threads. The thread processing unit 126 extracts the highest priority block from the waiting block queue 132 in the READY state. If the waiting block queue 132 is empty and all threads are in the READY state, the thread processing unit 126 stops its own threads.

The sweep-out method execution unit 127 processes blocks extracted from the waiting block queue 132 . The sweep-out method execution unit 127 detects non-zero elements by scanning elements while skipping columns determined to be process-skippable, and tries to eliminate non-zero elements by adding other columns.

The block search unit 128 searches for a new processable block from the matrix each time the sweep-out method execution unit 127 finishes processing one block. Candidates for new processable blocks are the block to the right and the block above the block that has been processed this time. If the lower right block has already been processed, the right block is the new processable block, and if the upper left block has already been processed, the upper block is the new processable block. The block searching unit 128 inserts information on processable blocks into the waiting block queue 132 .

The calculation cost calculator 129 calculates the calculation cost of the block. The computational cost is, for example, the number of columns to be processed. The number of columns to be processed is a value obtained by subtracting the number of columns for which processing can be omitted from the total number of columns included in the block. In the second embodiment, the calculation cost of a certain block is calculated when the block becomes processable.

FIG. 14 is a flowchart illustrating an example of a thread initialization procedure.
(S10) The thread initialization unit 125 divides the matrix into multiple blocks. The length of one side of the block is, for example, the length of one side of the matrix÷(number of threads×α).

(S11) The thread initialization unit 125 determines a column for which processing can be omitted from the matrix in the initial state. Columns for which processing can be omitted include columns that are clearly zero vectors.
(S12) The thread initialization unit 125 identifies diagonal blocks as processable blocks. The thread initialization unit 125 calculates the calculation cost of each diagonal block based on the number of columns determined in step S11. The thread initialization unit 125 sorts the diagonal blocks in descending order of calculation cost, associates the block names of the diagonal blocks with the calculation costs, and inserts them into the waiting block queue 132 .

(S13) The thread initialization unit 125 activates a plurality of threads and causes different cores of the CPU 101 or GPU 104 to execute different threads.
FIG. 15 is a flowchart illustrating an example of a procedure for thread processing according to the second embodiment.

(S20) The block search unit 128 determines whether there is a new processable block in the matrix. A new processable block is an unprocessed block whose left adjacent block and lower adjacent block have been processed and are not registered in the waiting block queue 132 . If there is a block processed immediately before by its own thread, the block searching unit 128 may check only the blocks above and to the right of that block. If there is a new processable block, the process proceeds to step S21, and if there is no new processable block, the process proceeds to step S22.

(S21) The calculation cost calculator 129 calculates the calculation cost of the new processable block detected in step S20. The calculation cost is calculated based on the columns that are currently determined to be process-skippable among the columns included in the new processable block. The block search unit 128 associates the block name of the new processable block with the calculation cost and inserts it into the waiting block queue 132 . At this time, the block searching unit 128 determines the insertion position based on the calculation cost so that the processable blocks are arranged in descending order of the calculation cost.

(S22) The thread processing unit 126 determines whether a block is registered in the waiting block queue 132. FIG. If there is a block in the waiting block queue 132, the process proceeds to step S23, and if the waiting block queue 132 is empty, the process proceeds to step S25.

(S23) The thread processing unit 126 extracts the highest priority block from the waiting block queue 132. FIG. The block with the highest priority is the block with the highest calculation cost, and if there are multiple blocks with the highest calculation cost, the block with the lowest row number among them. The sweep-out method executing unit 127 executes the sweep-out method on the extracted blocks.

(S24) The sweep-out method execution unit 127 determines, from the processing result of step S23, which columns are included in the processed block and whose processing can be omitted. Columns for which processing can be omitted include columns for which the pivot has been determined, ie, columns for which non-zero elements have not been eliminated. Then, the process returns to step S20.

(S25) The thread processing unit 126 determines whether there is another thread processing the block. If there is another thread processing a block, it waits for a certain period of time and returns to step S22, and if all threads are in the READY state, it stops its own thread.

As described above, the information processing apparatus 100 according to the second embodiment divides the boundary matrix for persistent homology into a plurality of blocks, and processes the blocks in parallel using a plurality of threads. This speeds up matrix computation and speeds up big data analysis.

In addition, the information processing apparatus 100 quickly allocates an empty thread that has finished processing one block to any processable block at that time without being constrained by diagonal lines. This allows multiple threads to be utilized to maintain parallelism and speed up matrix calculations. In addition, the information processing apparatus 100 estimates the calculation cost of each block, and preferentially processes blocks in descending order of calculation cost. This reduces the risk of a block with a high computational cost becoming a bottleneck and reducing the number of processable blocks, and suppresses a decrease in parallelism.

Further, the information processing apparatus 100 calculates the calculation cost of the processable block based on the number of omissible columns that changes as the sweep method progresses. Thereby, the calculation cost is accurately estimated so that the calculation cost is proportional to the calculation time.

[Third Embodiment]
Next, a third embodiment will be described. The description will focus on differences from the above-described second embodiment, and descriptions of the same contents as in the second embodiment may be omitted.

The third embodiment differs from the second embodiment in the calculation method of the calculation cost. The information processing apparatus of the third embodiment can be realized by a structure similar to the hardware of the second embodiment shown in FIG. 2 and the software of the second embodiment shown in FIG. Therefore, the third embodiment will be described below using the same reference numerals as in FIGS.

FIG. 16 is a diagram illustrating an example of how the calculation cost of peripheral blocks affects parallel processing.
Matrix 65 is the matrix after continuing the sweep method on matrix 64 shown in FIG. Blocks B(0,0), B(4,4), B(8,8) and B(9,9) have been processed. Blocks B(2,2), B(3,3), B(6,6) and B(8,9) are being processed. Blocks B(1,1), B(5,5), and B(7,7) are processable blocks.

The computational cost of block B(1,1) is 1, the computational cost of block B(5,5) is 1, and the computational cost of block B(7,7) is 2. When the processing of block B(6,6) ends, the information processing apparatus 100 starts processing block B(7,7), which has the highest calculation cost among the processable blocks. Matrix 65 thus becomes matrix 66 .

At this time, the calculation costs of blocks B(3,4), B(5,6), and B(7,8) have not yet been calculated by the method of the second embodiment. However, assume that block B(3,4) has a computational cost of 5, block B(5,6) has a computational cost of 7, and block B(7,8) has a computational cost of 2. Since the computational cost of block B(5,6) is high, it is preferable to process block B(5,5) early and start processing block B(5,6) early.

However, since the calculation cost of block B(5,5) itself is small, the start of processing of block B(5,5) is delayed, and as a result the start of processing of block B(5,6) is delayed. Therefore, in the third embodiment, the information processing apparatus 100 corrects the calculation cost of the processable block based on the calculation cost of the peripheral blocks.

FIG. 17 is a diagram illustrating an example of calculation cost correction with reference to peripheral blocks.
Matrix 67 is the matrix at the time block B(6, 6) has been processed after matrix 65 . In the third embodiment, the information processing apparatus 100 calculates the calculation cost of the adjacent block when the processing of a certain block is completed. A block for calculating a computational cost may not be a processable block. Here, the calculation cost of block B(3,4) is 5, and the calculation cost of block B(7,8) is 2. Further, when the processing of the block B(6,6) is completed, the information processing apparatus 100 calculates the calculation cost of the block B(5,6) as 7.

When the information processing apparatus 100 calculates the calculation cost c1 of a certain block, if there is an adjacent processable block on the left, the information processing apparatus 100 corrects the calculation cost c2 of the adjacent processable block. When the calculation cost c1 is greater than the calculation cost c2, the information processing apparatus 100 takes the arithmetic average of the calculation costs c1 and c2 as the calculation cost of the adjacent processable blocks. Therefore, the calculation cost c2 is updated as c2=(c1+c2)/2.

Here, the information processing apparatus 100 modifies the calculation cost of the block B(5,5) from 1 to 4. Then, the information processing apparatus 100 starts processing the block B(5, 5), which has the highest calculation cost among the processable blocks. Matrix 67 thus becomes matrix 68 . As a result, the processing of block B(5,6) is started earlier.

FIG. 18 is a flowchart illustrating an example of a thread processing procedure according to the third embodiment.
(S30) The block search unit 128 determines whether there is a new processable block in the matrix. If there is a new processable block, the process proceeds to step S31, and if there is no new processable block, the process proceeds to step S32.

(S31) The block searching unit 128 associates the block name and calculation cost of the new processable block with each other and inserts them into the waiting block queue 132 . The block search unit 128 uses the cost calculated in advance in step S36, which will be described later, as the calculation cost.

(S32) The thread processing unit 126 determines whether a block is registered in the waiting block queue 132. FIG. If there is a block in the waiting block queue 132, the process proceeds to step S33, and if the waiting block queue 132 is empty, the process proceeds to step S40.

(S 33 ) The thread processing unit 126 extracts the block with the highest priority from the waiting block queue 132 . The block with the highest priority is the block with the highest calculation cost, and if there are multiple blocks with the highest calculation cost, the block with the lowest row number among them. The sweep-out method executing unit 127 executes the sweep-out method on the extracted blocks.

(S34) The sweep-out method execution unit 127 determines, from the processing result of step S33, columns for which processing can be omitted newly among the columns included in the processed block.
(S35) The calculation cost calculator 129 determines whether the block row number of the block B(n,m) processed in step S33 is 0 (whether n=0). If the conditions are met, the process returns to step S30, and if the conditions are not met, the process proceeds to step S36.

(S36) The calculation cost calculator 129 calculates the calculation cost of the block B(n-1,m) adjacent above the block B(n,m). The calculation cost is calculated based on the columns included in the block B(n−1, m) that are currently determined to be omissible for processing.

(S37) The calculation cost calculator 129 determines that the block B (n-1, m-1) adjacent to the left of the block B (n-1, m) is a waiting block registered in the waiting block queue 132. determine if there is If the block is waiting for processing, the process proceeds to step S38, otherwise the process returns to step S30.

(S38) The computational cost calculator 129 determines whether the computational cost of block B(n−1,m−1) is smaller than the computational cost of block B(n−1,m). If the condition is met, the process proceeds to step S39, and if the condition is not met, the process returns to step S30.

(S39) The calculation cost calculator 129 calculates the calculation cost of block B (n-1, m-1) by combining the calculation cost of block B (n-1, m-1) with the calculation cost of block B (n-1, m). corrected to the arithmetic mean of the computational cost of . Then, the process returns to step S30.

(S40) The thread processing unit 126 determines whether there is another thread processing a block. If there is another thread processing a block, it waits for a certain period of time and returns to step S32, and if all threads are in the READY state, it stops its own thread.

As described above, the information processing apparatus 100 of the third embodiment has the same effects as those of the second embodiment. Further, when a processable block is adjacent to a block with a large computational cost on the right, the information processing apparatus 100 increases the computational cost of the processable block. As a result, among the blocks that can be processed next, a block with a large calculation cost is processed early, suppressing a decrease in parallelism and increasing the speed of matrix calculation.

10 Information Processing Device 11 Storage Unit 12 Processing Unit 13 Matrix Data 13a, 13b, 13c Processable Blocks 14a, 14b, 14c Calculation Cost 15a, 15b Thread

Claims (8)

A second block not adjacent to another unprocessed block in the first direction and orthogonal to the first direction from unprocessed blocks among a plurality of lattice-shaped blocks included in the matrix data. Identify blocks that are not adjacent to other unprocessed blocks in the direction of as processable blocks from which processing can begin, and
When there are a plurality of processable blocks, an empty thread among a plurality of threads to be executed in parallel is assigned with priority in order of higher calculation cost based on the calculated load of each processable block among the plurality of processable blocks. ,
A data analysis program that causes a computer to perform processing. In identifying the processable block, in an initial state, a block on a diagonal line among the plurality of blocks is identified as the processable block;
In the allocation of the free threads, after the processing of some blocks on the diagonal line is completed, the processable blocks on the diagonal line and the processable blocks not on the diagonal line are processed in parallel by different threads. to allow
The data analysis program according to claim 1. calculating the computational cost of the processable block based on the processing result of the block adjacent in the first direction; causing the computer to further perform a process;
The data analysis program according to claim 1. The blocks adjacent in the first direction and the processable blocks include a plurality of columns in common, and processing of the plurality of columns is performed based on the processing result of the blocks adjacent in the first direction. is determined which columns can be omitted, and
The calculation cost is calculated based on the number of columns for which the processing can be omitted,
4. A data analysis program according to claim 3. modifying the computational cost of the processable block based on other computational costs for unprocessed blocks within a certain range from the processable block, further causing the computer to perform a process;
The data analysis program according to claim 1. modifying the computational cost increases the computational cost if the other computational cost for a neighboring unprocessed block in a third direction opposite the second direction is greater than the computational cost;
6. A data analysis program according to claim 5. A second block not adjacent to another unprocessed block in the first direction and orthogonal to the first direction from unprocessed blocks among a plurality of lattice-shaped blocks included in the matrix data. Identify blocks that are not adjacent to other unprocessed blocks in the direction of as processable blocks from which processing can begin, and
When there are a plurality of processable blocks, an empty thread among a plurality of threads to be executed in parallel is assigned with priority in order of higher calculation cost based on the calculated load of each processable block among the plurality of processable blocks. ,
A data analysis method in which the processing is performed by a computer. a storage unit that stores matrix data including a plurality of grid-like blocks;
Among the unprocessed blocks among the plurality of blocks, there is no other unprocessed block adjacent in a first direction and another unprocessed block in a second direction perpendicular to the first direction. Blocks that are not adjacent to each other are specified as processable blocks from which processing can be started, and if there are a plurality of processable blocks, the calculation cost based on the calculation load of each processable block among the plurality of processable blocks is large. a processing unit that preferentially allocates an empty thread among a plurality of threads that are executed in parallel;
Information processing device having

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