JP2023037814A - Noise detection circuit and imaging apparatus - Google Patents

Abstract

To provide a noise detection circuit configured to detect noise entered into a cable.SOLUTION: A reference clock counter 22 counts reference clocks for every line. A reference line counter 23 counts the number of lines in each frame. A detection clock counter 24 counts reference clocks, resets the count value every time a horizontal synchronization pulse is input, and resets the count value when noise is input through a first bidirectional pin 213. The detection line counter 25 counts the number of lines, resets the count value every time a vertical synchronization pulse is input, and resets the count value when noise is input through a second bidirectional pin 212. An anomaly detection unit 26 generates an anomaly detection flag when there is a difference between the count values counted by the reference clock counter 22 and the detection clock counter 24, or when there is a difference between the count values counted by the reference line counter 23 and the detection line counter 25.SELECTED DRAWING: Figure 1

Description

The present invention relates to a noise detection circuit and an imaging device.

A video camera (imaging device) has a viewfinder for checking an image being shot. An image display driving unit installed in the video camera supplies image data generated by photographing an object to the viewfinder, and drives the viewfinder to display an image on the viewfinder.

JP-A-5-167881

The image display driving unit and the viewfinder are often connected by a wiring material (cable) typified by a flexible flat cable. If noise such as static electricity enters the flexible flat cable, the image displayed in the viewfinder may remain distorted, or the image may freeze, making it impossible to check the image being shot. This problem is not limited to the case where the image display unit connected to the image display drive unit via a flexible flat cable is a viewfinder, but can also occur when the image display unit is a liquid crystal panel. .

One or more embodiments include a noise detection circuit capable of detecting noise entering a cable connecting a video display drive unit and a video display unit, and a noise detection circuit capable of detecting noise entering a cable, and an image remaining distorted even if noise enters the cable. An object of the present invention is to provide an image pickup apparatus capable of eliminating anomalies such as image pickup and freezing.

According to a first aspect of one or more embodiments, a video display unit and a video display drive unit that supplies video data to the video display unit and drives the video display unit are connected by a cable. there is According to the first aspect, the video display driving section and the cable output a horizontal synchronization signal of the video data to the cable, and the noise superimposed on the horizontal synchronization signal transmitted through the cable is transmitted to the video. A first bi-directional pin for inputting to a display driving section, a vertical synchronization signal of the video data is output to the cable, and noise superimposed on the vertical synchronization signal transmitted through the cable is transmitted to the video display driving section. It is connected with a second bidirectional pin for input.

A first aspect provides a noise detection circuit including a reference clock counter, a reference line counter, a detection clock counter, a detection line counter, and an anomaly detector.

The reference clock counter counts a reference clock supplied from the image display drive unit to the image display unit through the cable, and counts each time a horizontal synchronization pulse included in the horizontal synchronization signal is input. By resetting the value, the reference clock for each line in each frame of the video data is counted. The reference line counter counts the number of lines of the video data, and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, whereby the lines of each frame of the video data are counted. count the number.

The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and detects noise from the cable through the first bidirectional pin. is input to reset the count value. The detection line counter counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and detects noise from the cable through the second bidirectional pin. When input to the display driver, the count value is reset.

The abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and that an abnormality has occurred in the horizontal synchronization signal when the count value of the reference clock counter and the count value of the detection clock counter are different, When the count value of the reference line counter and the count value of the detection line counter are different, it is determined that noise is superimposed on the vertical synchronizing signal and an abnormality has occurred in the vertical synchronizing signal. When it is determined that at least one of the vertical synchronization signals has an abnormality, an abnormality detection flag is generated.

According to a second aspect of one or more embodiments, a video display unit and a video display drive unit for supplying video data to the video display unit and driving the video display unit are connected by a cable. there is According to the second aspect, the video display driving section and the cable output a horizontal synchronization signal of the video data to the cable, and the noise superimposed on the horizontal synchronization signal transmitted through the cable is transmitted to the video. It is connected by a bidirectional pin that inputs to the display driver.

A second aspect provides a noise detection circuit including a reference clock counter, a detection clock counter, and an anomaly detector.

The reference clock counter counts a reference clock supplied from the image display drive unit to the image display unit through the cable, and counts each time a horizontal synchronization pulse included in the horizontal synchronization signal is input. By resetting the value, the reference clock for each line in each frame of the video data is counted. The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and detects when noise is input from the cable to the video display driving unit via the bidirectional pin. to reset the count value. The abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and that an abnormality has occurred in the horizontal synchronization signal when the count value of the reference clock counter and the count value of the detection clock counter are different, When it is determined that an abnormality has occurred in the horizontal synchronizing signal, an abnormality detection flag is generated.

According to a third aspect of one or more embodiments, a video display unit and a video display drive unit that supplies video data to the video display unit and drives the video display unit are connected by a cable. there is According to the third aspect, the video display driving unit and the cable output a vertical synchronization signal of the video data to the cable, and the noise superimposed on the vertical synchronization signal transmitted through the cable is transmitted to the video. It is connected with a bidirectional pin that inputs to the display driver.

A third aspect provides a noise detection circuit including a reference line counter, a detection line counter, and an anomaly detector.

The reference line counter counts the number of lines of the video data, and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, whereby the lines of each frame of the video data are counted. count the number. The line counter for detection counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and detects noise from the cable through the bidirectional pin to the video display drive unit. is input to reset the count value. The abnormality detection unit determines that noise is superimposed on the vertical synchronization signal and that an abnormality has occurred in the vertical synchronization signal when the count value of the reference line counter and the count value of the detection line counter are different, When it is determined that an abnormality has occurred in the vertical synchronization signal, an abnormality detection flag is generated.

According to a fourth aspect of one or more embodiments, a video display unit, and supplying video data, a horizontal synchronization signal for the video data, a vertical synchronization signal for the video data, and a reference clock to the video display unit a video display drive unit for driving the video display unit; and a cable for transmission from a video display driver to the video display.

According to the fourth aspect, the video display driving section and the cable output the horizontal synchronization signal to the cable, and the noise superimposed on the horizontal synchronization signal transmitted through the cable is transmitted to the video display driving section. and a second bidirectional pin for outputting the vertical synchronization signal to the cable and inputting noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit. It is connected with a directional pin.

According to a fourth aspect, there is provided an imaging device further comprising a reference clock counter, a reference line counter, a detection clock counter, a detection line counter, an abnormality detection section, and a restart control section.

The reference clock counter counts the reference clock, and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, so that each line in each frame of the video data is read. Count the reference clocks. A reference line counter counts the number of lines of the video data, and resets the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input, thereby increasing the number of lines of each frame of the video data. to count.

The detection clock counter counts the reference clock, resets the count value each time the horizontal synchronization pulse is input, and detects noise from the cable through the first bidirectional pin. is input to reset the count value. A detection line counter counts the number of lines of the video data, resets the count value each time the vertical synchronization pulse is input, and detects noise from the cable through the second bidirectional pin to the video display. When input to the drive unit, the count value is reset.

The abnormality detection unit determines that noise is superimposed on the horizontal synchronization signal and that an abnormality has occurred in the horizontal synchronization signal when the count value of the reference clock counter and the count value of the detection clock counter are different, When the count value of the reference line counter and the count value of the detection line counter are different, it is determined that noise is superimposed on the vertical synchronizing signal and an abnormality has occurred in the vertical synchronizing signal. When it is determined that at least one of the vertical synchronization signals has an abnormality, an abnormality detection flag is generated. The restart control section controls the image display section to restart the image display section when the abnormality detection section generates the abnormality detection flag.

According to the noise detection circuit of one or more embodiments, it is possible to detect noise that enters the cable that connects the video display driver and the video display. According to the imaging device of one or more embodiments, even if noise jumps into the cable connecting the image display driving unit and the image display unit, the image remains distorted or freezes. be able to.

1 is a block diagram illustrating noise detection circuitry and an imaging device of one or more embodiments; FIG. 4 is a flow chart illustrating the operation of an imaging device of one or more embodiments; 4 is a timing chart illustrating the operation of the noise detection circuit and imaging device of one or more embodiments when noise is not superimposed on the horizontal sync signal; 5 is a timing chart illustrating the operation of the noise detection circuit and imaging device of one or more embodiments when noise is superimposed on the horizontal sync signal; 4 is a timing chart illustrating the operation of the noise detection circuit and imaging device of one or more embodiments when noise is not superimposed on the vertical synchronization signal; 4 is a timing chart illustrating the operation of the noise detection circuit and imaging device of one or more embodiments when noise is superimposed on the vertical synchronization signal;

One or more embodiments of noise detection circuits and imagers are described below with reference to the accompanying drawings. As shown in FIG. 1, an imaging apparatus (hereinafter referred to as a video camera) of one or more embodiments includes a video signal processing section 1, a video display driving section 2, and a viewfinder 5 as a video display section. The video camera may have a liquid crystal panel as another image display unit.

In FIG. 1, a video signal processing unit 1 processes a video signal generated by imaging a subject with an imaging device (not shown) to generate video data Vdata, a vertical synchronization signal Vsync of the video data Vdata, and a horizontal synchronization signal Vsync of the video data Vdata. and the signal Hsync to the video display driving unit 2 . As an example, the video data Vdata consists of a luminance signal (Y signal) and two color difference signals (Cb and Cr signals). For example, the Y signal is 8-bit digital data, and the Cb and Cr signals are 8-bit digital data time division multiplexed with each other.

The image display driving unit 2 is configured by a hardware integrated circuit. The image display driving unit 2 may be composed of an FPGA (Field Programmable Gate Array) whose circuit configuration can be changed, or may be composed of a CPLD (Complex Programmable Logic Device) having a smaller number of gates than the FPGA. good too. That is, the video display driving section 2 may be composed of an integrated circuit whose circuit configuration cannot be changed, or may be composed of an integrated circuit that is a programmable logic device including FPGA or CPLD.

The image display drive unit 2 is connected to the viewfinder 5 via a flexible flat cable (hereinafter referred to as FFC) 4 . If the video camera has a liquid crystal panel, the video display driver 2 is connected to the liquid crystal panel by the FFC4. The image display driving section 2 drives the viewfinder 5 or the liquid crystal panel. The image display driving section 2 and the viewfinder 5 may be connected by a cable other than the FFC 4. The image display driving section 2 and the viewfinder 5 may be connected by a flexible printed circuit (FPC). A cable connecting the image display drive unit 2 and the viewfinder 5 may have noise caused by static electricity or the like.

The number of lines in one frame and the number of pixels in one line of the viewfinder 5 are often different from the number of lines and pixels in the video data Vdata output from the video signal processing unit 1 . In one or more embodiments, the number of lines in one frame and the number of pixels in one line of the viewfinder 5 are less than the number of lines and pixels in the video data Vdata output from the video signal processing unit 1. explain. Therefore, the format conversion unit 21 converts the video format by reducing the number of lines and the number of pixels of the video data Vdata. The format conversion unit 21 supplies the video data Vdata whose video format has been converted to the driver 201, and supplies the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the drivers 202 and 203, respectively.

The driver 201 supplies the video data Vdata to the viewfinder 5 via the output pin 211 and FFC4. Drivers 202 and 203 supply vertical synchronization signal Vsync and horizontal synchronization signal Hsync, respectively, to viewfinder 5 via bidirectional pins 212 and 213 and FFC4. Bidirectional pin 213 is the first bidirectional pin and bidirectional pin 212 is the second bidirectional pin.

The bidirectional pins 212 and 213 are output pins for outputting the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync from the video display driver 2 to the FFC4, and signals superimposed on the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync for transmitting the FFC4. to the video display drive unit 2. This pin has both functions. Normally, the video display driving section 2 is provided with output pins so that the video display driving section 2 supplies the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the viewfinder 5 via the FFC 4 . In one or more embodiments, bidirectional pins 212 and 213 are provided in place of the output pins normally provided.

One end of pull-up resistor 208 is connected between driver 202 and bidirectional pin 212 . One end of pull-up resistor 207 is connected between driver 203 and bidirectional pin 213 . The other ends of pull-up resistors 207 and 208 are connected to a power supply (not shown).

A clock CLK0 generated by an external clock generator is input to a PLL (Phase Locked Loop) circuit 27 . Based on the clock CLK0, the PLL circuit 27 generates and outputs a clock CLK, which is a reference clock for the operation of the image display driving section 2 and the viewfinder 5. FIG. Driver 204 provides clock CLK to viewfinder 5 via output pin 214 and FFC4. A clock CLK is supplied to the format conversion unit 21 and each circuit block described later.

The image display driving section 2 includes a reference clock counter 22 , a reference line counter 23 , a detection clock counter 24 , a detection line counter 25 and an abnormality detection section 26 . The reference clock counter 22, the reference line counter 23, the detection clock counter 24, the detection line counter 25, and the abnormality detection section 26 constitute a noise detection circuit. The noise detection circuit detects pulse-shaped noise superimposed on the vertical synchronization signal Vsync or horizontal synchronization signal Hsync transmitted through the FFC4, which is generated when noise such as static electricity enters the FFC4.

The clock CLK and the horizontal synchronization signal Hsync supplied to the drivers 204 and 203 are input to the reference clock counter 22, respectively. The reference line counter 23 receives the clock CLK, the count value of the reference clock counter 22, and the vertical synchronization signal Vsync. The clock CLK and vertical synchronization signal Vsync supplied to the reference line counter 23 are the clock CLK and vertical synchronization signal Vsync supplied to the drivers 204 and 202, respectively.

The reference clock counter 22 counts the input clock CLK and resets the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal Hsync is input. That is, the reference clock counter 22 counts the clock CLK for each line in each frame of the video data Vdata. The reference line counter 23 increments the count value when the count value of the reference clock counter 22 reaches the maximum value, and resets the count value each time the vertical synchronization signal Vsync is input. That is, the reference line counter 23 counts the number of lines in each frame of the video data Vdata.

A clock CLK and a horizontal synchronization signal Hsync are input to the detection clock counter 24 . When noise enters the FFC 4 and pulse-like noise is superimposed on the horizontal synchronization signal Hsync transmitted through the FFC 4 , the pulse-like noise is input to the video display driver 2 via the bidirectional pin 213 . When pulse-shaped noise is input to the video display driving section 2 via the bidirectional pin 213 , the noise is input to the detection clock counter 24 .

The detection line counter 25 receives the clock CLK, the count value of the detection clock counter 24, and the vertical synchronization signal Vsync. When noise enters the FFC 4 and pulse noise is superimposed on the vertical synchronization signal Vsync transmitted through the FFC 4 , the pulse noise is input to the video display driver 2 via the bidirectional pin 212 . When pulse-shaped noise is input to the video display driving section 2 via the bidirectional pin 212 , the noise is input to the detection line counter 25 .

Similar to the reference clock counter 22, the detection clock counter 24 counts the input clock CLK and resets the count value each time the horizontal synchronization signal Hsync is input. However, the detection clock counter 24 resets the count value when pulse-shaped noise is input. The detection clock counter 24 counts the clock CLK for each line, but resets the count value and counts the clock CLK again when pulse-shaped noise is input in the middle of one line.

Similar to the reference line counter 23, the detection line counter 25 increments the count value when the count value of the detection clock counter 24 reaches the maximum value, and resets the count value each time the vertical synchronization signal Vsync is input. However, the detection line counter 25 resets the count value when pulse noise is input. The detection line counter 25 counts the number of lines in each frame, but resets the count value and counts the number of lines again when pulse-like noise is input within the frame.

The abnormality detection unit 26 compares the count value of the reference clock counter 22 and the count value of the detection clock counter 24 . The abnormality detection unit 26 detects abnormality of the horizontal synchronization signal Hsync based on whether the count values of both are the same. Specifically, if the two count values are the same, the abnormality detection unit 26 determines that there is no abnormality in the horizontal synchronization signal Hsync. It is determined that an abnormality has occurred in Abnormality of the horizontal synchronizing signal Hsync means that noise is superimposed on the horizontal synchronizing signal Hsync transmitted by FFC4.

The abnormality detection unit 26 compares the count value of the reference line counter 23 and the count value of the detection line counter 25 . The anomaly detection unit 26 detects an anomaly in the vertical synchronization signal Vsync based on whether the count values of both are the same. Specifically, if the two count values are the same, the abnormality detection unit 26 determines that there is no abnormality in the vertical synchronization signal Vsync. It is determined that an abnormality has occurred in Abnormality of the vertical synchronization signal Vsync means that noise is superimposed on the vertical synchronization signal Vsync transmitted by FFC4.

When detecting an abnormality in at least one of the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync, the abnormality detection section 26 generates an abnormality detection flag and supplies it to the processor 3 . Processor 3 may be a central processing unit (CPU) of a microcomputer. As will be described later, the processor 3 instructs the anomaly detection unit 26 to start or stop anomaly detection, or to clear an anomaly detection flag.

As described above, according to the noise detection circuit of one or more embodiments, it is possible to detect noise that enters the FFC 4 that connects the video display driving section 2 and the viewfinder 5 .

When the abnormality detection flag is input from the abnormality detection unit 26 , the processor 3 supplies a restart command to the viewfinder 5 and controls the viewfinder 5 to restart. The processor 3 functions as a restart control unit that controls the viewfinder 5 to restart the viewfinder 5 when the error detection unit 26 generates the error detection flag. In one or more embodiments, the restart control section is provided outside the video display drive section 2 , but the restart control section may be provided inside the video display drive section 2 . That is, the restart controller may be configured as part of an integrated circuit.

When the viewfinder 5 is restarted, the abnormality such as the image being displayed in the viewfinder 5 remaining distorted or frozen is resolved, and the viewfinder 5 can display a normal image again. can. Therefore, according to the video camera of one or more embodiments, it is possible to eliminate anomalies such as the image remaining distorted or freezing even if noise enters the FFC 4 .

Schematic operations of the video display driving unit 2 or the processor 3 will be described with reference to the flowchart shown in FIG. In FIG. 2, when the power of the video camera is turned on, the video camera is started, and processing is started, the video display driving section 2 starts the viewfinder 5 in step S1. The video display drive unit 2 (abnormality detection unit 26) starts abnormality detection of the vertical synchronization signal Vsync or the horizontal synchronization signal Hsync in step S2 in accordance with the instruction to start abnormality detection by the processor 3. FIG.

The video display drive unit 2 (abnormality detection unit 26) determines whether or not an abnormality has occurred in step S3. If no abnormality has occurred (NO), the video display driving section 2 determines whether or not the power of the video camera has been turned off in step S8. If the power of the video camera is turned off (YES), the image display driving section 2 terminates the processing. If the power of the video camera is not turned off (NO), the video display driving section 2 returns the process to step S3.

If an abnormality occurs in step S3 (YES), the video display drive section 2 (abnormality detection section 26) generates an abnormality detection flag in step S4. The image display driving section 2 (abnormality detection section 26) stops the abnormality detection in step S5 according to the instruction to stop the abnormality detection by the processor 3, and clears the abnormality detection flag in step S6.

The reason why the abnormality detection is stopped in step S5 is to avoid the possibility that an unexpected abnormal operation may occur if an abnormality is detected again while the viewfinder 5 is being restarted. The processor 3 restarts the viewfinder 5 in step S7, and the video display driving section 2 returns the process to step S2.

3A, 3B, 4A, and 4B, the operation of the video display driving section 2 will be described in detail. FIG. 3A shows the operation of the video display driving section 2 when noise is not superimposed on the horizontal synchronization signal Hsync. As shown in FIG. 3A, the horizontal sync pulse Hpls included in the horizontal sync signal Hsync is negative. The reference clock counter 22 resets the count value to 0 at the fall of the horizontal sync pulse Hpls. The reference clock counter 22 counts the clock CLK during the period of one line (1H) and sequentially increments the count value from the count value 0 to the maximum value Hmax.

The reference line counter 23 increments the count value when the count value of the reference clock counter 22 reaches the maximum value Hmax. Therefore, the count value of the reference line counter 23 increases by n−1, n, n+1, . . . every 1H.

The detection clock counter 24 resets the count value to 0 at the fall of the horizontal sync pulse Hpls. The detection clock counter 24 counts the clock CLK for a period of 1H and sequentially increments the count value from the count value 0 to the maximum value Hmax. The detection line counter 25 increments the count value when the count value of the detection clock counter 24 reaches the maximum value Hmax. Therefore, the count value of the detection line counter 25 increases by n−1, n, n+1, . . . every 1H.

Although not shown in FIG. 3A, as described in step S2 in FIG. In FIG. 3A, the abnormality detection unit 26 detects that the count value of the reference clock counter 22 and the count value of the detection clock counter 24 are always the same value. Therefore, the abnormality detection unit 26 does not detect an abnormality in the horizontal synchronization signal Hsync, and sets the abnormality detection value of the horizontal synchronization signal Hsync to low (L). The abnormality detection value L indicates a state in which no abnormality of the horizontal synchronization signal Hsync is detected.

The anomaly detection unit 26 does not detect an anomaly in the horizontal synchronization signal Hsync, so it does not generate an anomaly detection flag. That is, the abnormality detection unit 26 continuously outputs L indicating that no abnormality detection flag is generated.

FIG. 3B shows the operation of the video display driving section 2 when noise is superimposed on the horizontal synchronization signal Hsync. As shown in FIG. 3B, when the noise Ns is superimposed on the horizontal synchronization signal Hsync, the count value of the detection clock counter 24 is reset to zero. Here, the noise Ns is an example of a plurality of continuous pulse-shaped noises. On the other hand, since the reference clock counter 22 is not reset, when the count value of the detection clock counter 24 is reset to 0, the count value of the reference clock counter 22 is not 0 but a predetermined value x.

The abnormality detection unit 26 detects that the count value x of the reference clock counter 22 and the count value 0 of the detection clock counter 24 are different. Therefore, the abnormality detection unit 26 detects an abnormality in the horizontal synchronization signal Hsync and sets the abnormality detection value of the horizontal synchronization signal Hsync to high (H). The abnormality detection value H indicates a state in which an abnormality in the horizontal synchronization signal Hsync is detected. Until the count values of the reference clock counter 22 and the detection clock counter 24 are reset at the falling edge of the next horizontal synchronizing pulse Hpls, the count values of both are different. The abnormality detection value H is output until the downstream.

When the abnormality detection value of the horizontal synchronization signal Hsync is set to H, the abnormality detection unit 26 outputs H as an abnormality detection flag. An abnormality detection flag H indicates a state in which an abnormality is detected. Although not shown in FIG. 3B, the abnormality detection unit 26 stops abnormality detection in accordance with an instruction to stop abnormality detection by the processor 3 . After the abnormality detection unit 26 stops abnormality detection, the processor 3 instructs to clear the abnormality detection flag, and the abnormality detection unit 26 sets the abnormality detection flag to L. The abnormality detection flag becomes L at a predetermined timing after the abnormality detection value of the horizontal synchronization signal Hsync becomes L at the falling edge of the next horizontal synchronization pulse Hpls. Subsequently, processor 3 restarts viewfinder 5 .

FIG. 4A shows the operation of the video display driving section 2 when noise is not superimposed on the vertical synchronization signal Vsync. As shown in FIG. 4A, the vertical sync pulse Vpls included in the vertical sync signal Vsync has a negative polarity. The reference line counter 23 and detection line counter 25 reset their count values to 0 at the fall of the vertical sync pulse Vpls. The reference line counter 23 and the detection line counter 25 count the number of lines during the period of one frame (1 V), and sequentially increment the count value from the count value 0 to the maximum value Vmax.

Assume that the abnormality detection unit 26 starts abnormality detection at time t<b>1 in accordance with the instruction to start abnormality detection from the processor 3 . L in the abnormality detection start/stop shown in FIG. 4A indicates a state in which abnormality detection is stopped, and H indicates a state in which abnormality detection is started and an abnormality is detected.

In FIG. 4A, the abnormality detection unit 26 detects that the count value of the reference line counter 23 and the count value of the detection line counter 25 are always the same value. Therefore, the abnormality detection unit 26 does not detect an abnormality in the vertical synchronization signal Vsync, and sets the abnormality detection value of the vertical synchronization signal Vsync to L. The abnormality detection unit 26 detects abnormality of the horizontal synchronization signal Hsync in each 1H within the period of 1V in FIG. 4A, as described with reference to FIGS. 3A and 3B. Here, it is assumed that neither the vertical synchronizing signal Vsync nor the horizontal synchronizing signal Hsync is detected to be abnormal. Therefore, the abnormality detection unit 26 outputs L as the abnormality detection flag.

FIG. 4B shows the operation of the video display driving section 2 when noise is superimposed on the vertical synchronization signal Vsync. As shown in FIG. 4B, when the noise Ns is superimposed on the vertical synchronization signal Vsync, the count value of the detection line counter 25 is reset to zero. On the other hand, since the reference line counter 23 is not reset, when the count value of the detection line counter 25 is reset to 0, the count value of the reference line counter 23 is a predetermined value y which is not 0.

The abnormality detection unit 26 detects that the count value y of the reference line counter 23 and the count value 0 of the detection line counter 25 are different. Therefore, the abnormality detection unit 26 detects an abnormality in the vertical synchronization signal Vsync and sets the abnormality detection value of the vertical synchronization signal Vsync to "H". Since the count values of the reference line counter 23 and the detection line counter 25 are different until the count values of the reference line counter 23 and the detection line counter 25 are reset at the falling edge of the next vertical synchronizing pulse Vpls, the abnormality detecting section 26 detects that the count value is different from that of the next vertical synchronizing pulse Vpls. H is output as the abnormality detection value until the downlink.

When the abnormality detection value of the vertical synchronization signal Vsync is set to H, the abnormality detection unit 26 outputs H as an abnormality detection flag. An abnormality detection flag H indicates a state in which an abnormality is detected. The abnormality detection unit 26 stops abnormality detection at time t<b>2 in accordance with the instruction to stop abnormality detection by the processor 3 . At time t3, the processor 3 instructs to clear the abnormality detection flag, and the abnormality detection unit 26 sets the abnormality detection flag to L. FIG. Subsequently, processor 3 restarts viewfinder 5 .

In this manner, the abnormality detection unit 26 detects an abnormality in the horizontal synchronization signal Hsync in each 1H period and detects an abnormality in the vertical synchronization signal Vsync in each 1V period. When an abnormality is detected in at least one of them, an abnormality detection flag is generated. It is preferable that the abnormality detection section 26 detects whether or not there is an abnormality in both the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync, and generates an abnormality detection flag when detecting an abnormality in at least one of them.

For simplification of the configuration, the abnormality detection unit 26 may detect whether or not there is an abnormality in only the horizontal synchronization signal Hsync, and generate an abnormality detection flag when detecting an abnormality in the horizontal synchronization signal Hsync. In this case, the reference line counter 23 and the detection line counter 25 can be omitted. Alternatively, the abnormality detection unit 26 may detect whether or not there is an abnormality in the vertical synchronization signal Vsync only, and generate an abnormality detection flag when detecting an abnormality in the vertical synchronization signal Vsync. In this case, the reference clock counter 22 and the detection clock counter 24 can be omitted. If the reference clock counter 22 and the detection clock counter 24 are omitted, the reference line counter 23 and the detection line counter 25 can count the horizontal synchronizing pulses Hpls.

As described above, according to the video camera of one or more embodiments, even if noise enters the FFC 4 that connects the image display driving section 2 and the viewfinder 5, the image remains distorted or freezes. It is possible to eliminate abnormalities such as Accordingly, the video camera of one or more embodiments may be free of additional anti-static components or the like. In the video camera of this embodiment, it is not necessary to cover the movable portion of the viewfinder 5 with a case or tape so that the cable is not exposed.

The present invention is not limited to the one or more embodiments described above, and various modifications can be made without departing from the scope of the present invention.

1 video signal processing unit 2 video display driving unit 3 processor (restart control unit)
4 flexible flat cable 5 viewfinder 21 format conversion unit 22 reference clock counter 23 reference line counter 24 detection clock counter 25 detection line counter 26 abnormality detection unit 201 to 204 drivers 207, 208 pull-up resistors 211, 214 output pins 212, 213 bidirectional pins

Claims (4)

an image display unit and an image display driving unit that supplies image data to the image display unit and drives the image display unit are connected by a cable,
The video display driving section and the cable output a horizontal synchronization signal of the video data to the cable, and input noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving section. 1 bidirectional pin, and a second bidirectional pin for outputting a vertical synchronization signal of the video data to the cable and inputting noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving section. are connected with
By counting the reference clock supplied from the video display drive unit to the video display unit via the cable and resetting the count value each time a horizontal sync pulse included in the horizontal sync signal is input , a reference clock counter for counting the reference clock for each line in each frame of the video data;
A reference line for counting the number of lines of each frame of the video data by counting the number of lines of the video data and resetting the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input. a counter;
counting the reference clock, resetting the count value each time the horizontal synchronization pulse is input, and resetting the count value when noise is input from the cable to the video display driving unit via the first bidirectional pin; a detection clock counter for resetting the
The number of lines of the video data is counted, the count value is reset each time the vertical synchronization pulse is input, and noise is input from the cable to the video display driver via the second bidirectional pin. and a line counter for detection that resets the count value,
When the count value of the reference clock counter and the count value of the detection clock counter are different, it is determined that noise is superimposed on the horizontal synchronizing signal and an abnormality has occurred in the horizontal synchronizing signal, and the reference line counter counts. When the value and the count value of the detection line counter are different, it is determined that noise is superimposed on the vertical synchronization signal and an abnormality has occurred in the vertical synchronization signal, and an anomaly detection unit that generates an anomaly detection flag when it is determined that an anomaly has occurred in at least one of the
a noise detection circuit. an image display unit and an image display driving unit that supplies image data to the image display unit and drives the image display unit are connected by a cable,
The video display driving section and the cable output a horizontal synchronization signal of the video data to the cable, and input noise superimposed on the horizontal synchronization signal transmitted through the cable to the video display driving section. are connected by directional pins,
By counting the reference clock supplied from the video display drive unit to the video display unit via the cable and resetting the count value each time a horizontal sync pulse included in the horizontal sync signal is input , a reference clock counter for counting the reference clock for each line in each frame of the video data;
The reference clock is counted, the count value is reset each time the horizontal synchronization pulse is input, and the count value is reset when noise is input from the cable to the video display driver via the bidirectional pin. a detection clock counter;
When the count value of the reference clock counter and the count value of the detection clock counter are different, it is determined that noise is superimposed on the horizontal synchronizing signal and an abnormality has occurred in the horizontal synchronizing signal, and the horizontal synchronizing signal is abnormal. an anomaly detection unit that generates an anomaly detection flag when it is determined that
a noise detection circuit. an image display unit and an image display driving unit that supplies image data to the image display unit and drives the image display unit are connected by a cable,
The video display driving unit and the cable output a vertical synchronization signal of the video data to the cable, and input noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit. It is connected with a directional pin,
A reference line for counting the number of lines of each frame of the video data by counting the number of lines of the video data and resetting the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input. a counter;
The number of lines of the video data is counted, the count value is reset each time the vertical synchronization pulse is input, and the count value is received when noise is input from the cable to the video display driving unit via the bidirectional pin. a line counter for detection that resets the
When the count value of the reference line counter and the count value of the detection line counter are different, it is determined that noise is superimposed on the vertical synchronizing signal and an abnormality has occurred in the vertical synchronizing signal, and the vertical synchronizing signal is abnormal. an anomaly detection unit that generates an anomaly detection flag when it is determined that
a noise detection circuit. a video display unit;
a video display driving unit that supplies video data, a horizontal synchronization signal of the video data, a vertical synchronization signal of the video data, and a reference clock to the video display unit to drive the video display unit;
a cable that connects the video display driving unit and the video display unit and transmits the video data, the horizontal synchronization signal, the vertical synchronization signal, and the reference clock from the video display driving unit to the video display unit;
with
The video display driving section and the cable output the horizontal synchronizing signal to the cable, and input noise superimposed on the horizontal synchronizing signal transmitted through the cable to the video display driving section. and a second bidirectional pin for outputting the vertical synchronization signal to the cable and inputting noise superimposed on the vertical synchronization signal transmitted through the cable to the video display driving unit,
By counting the reference clock and resetting the count value each time a horizontal synchronization pulse included in the horizontal synchronization signal is input, the reference clock for each line in each frame of the video data is counted. a reference clock counter;
A reference line for counting the number of lines of each frame of the video data by counting the number of lines of the video data and resetting the count value each time a vertical synchronization pulse included in the vertical synchronization signal is input. a counter;
counting the reference clock, resetting the count value each time the horizontal synchronization pulse is input, and resetting the count value when noise is input from the cable to the video display driving unit via the first bidirectional pin; a detection clock counter for resetting the
The number of lines of the video data is counted, the count value is reset each time the vertical synchronization pulse is input, and noise is input from the cable to the video display driver via the second bidirectional pin. and a line counter for detection that resets the count value,
When the count value of the reference clock counter and the count value of the detection clock counter are different, it is determined that noise is superimposed on the horizontal synchronizing signal and an abnormality has occurred in the horizontal synchronizing signal, and the reference line counter counts. When the value and the count value of the detection line counter are different, it is determined that noise is superimposed on the vertical synchronizing signal and an abnormality has occurred in the vertical synchronizing signal. an anomaly detection unit that generates an anomaly detection flag when it is determined that an anomaly has occurred in at least one of the
a restart control unit that controls the image display unit to restart the image display unit when the abnormality detection unit generates the abnormality detection flag;
An imaging device further comprising:

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