JP2023031578A - Battery monitoring device - Google Patents

Abstract

To provide a battery monitoring device allowing reduction in measurement time of impedance.SOLUTION: An application part 20 simultaneously applies to a monitor current-carrying part 32, a signal generated using a drive signal generation part 21 by superimposing signals of a plurality of single frequencies different to each other. A plurality of lock-in detection parts 22 are provided for the plurality of single frequencies, respectively, when the signal is applied from the application part 20 to the monitor current-carrying part 32, feedback inputs signals generated in a detection resistor 32 and a battery cell 3 as measuring object, and inputs signals of the plurality of single frequencies generated by the drive signal generation part 21 to be mixed in mixers 23i, 23q, 24i and 24q for lock-in detection. A signal processing part 14 measures impedance for each of the plurality of single frequencies on the basis of detection results of the plurality of lock-in detection parts 22.SELECTED DRAWING: Figure 1

Description

The present invention relates to battery monitoring devices.

Generally, a battery monitoring device is provided to monitor the state of battery cells that constitute a storage battery or assembled battery. A battery monitoring device monitors the state of a battery cell by measuring the complex impedance of the battery cell that constitutes the assembled battery (see Patent Document 1, for example). According to the technique described in Patent Document 1, the state of the battery cell is monitored by constantly performing complex impedance measurement at a single frequency.

Japanese Patent Application Laid-Open No. 2021-18946

When the technique described in Patent Document 1 is used, the impedance measurement of the battery cell is constantly repeated, so it is necessary to perform the measurement for a long period of time in order to obtain the necessary data. Long-term measurement may change the condition of the battery cell being measured, leading to deterioration in the accuracy of measurement results. In addition, if the measurement result update interval such as the fault tolerant time interval (FTTI) or the total measurement time is limited in order to comply with so-called functional safety, it becomes difficult to satisfy this condition.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a battery monitoring device capable of shortening the impedance measurement time.

According to the first aspect of the present invention, the applying section superimposes a plurality of different single-frequency signals and simultaneously applies the signals generated by the driving signal generating section to the monitoring energizing section. The monitoring energization unit energizes some or all of the battery cells to be measured in the assembled battery and the detection resistors connected in series to the battery cells to be measured.

A plurality of lock-in detection units are provided for each of a plurality of single frequencies, and when applied from the application unit to the monitoring energization unit, the signal generated in the detection resistance and the battery cell to be measured is fed back and input by the drive signal generation unit. A plurality of single-frequency signals are input and mixed by a mixer to detect lock-in. The measuring section measures impedances at a plurality of single frequencies based on the detection results of the plurality of lock-in detecting sections. According to the first aspect of the invention, the impedance can be measured at a plurality of single frequencies based on the detection results of the plurality of lock-in detectors, so that the impedance measurement time can be shortened.

Electrical configuration diagram of the battery monitoring device in the first embodiment Electrical configuration diagram of the battery monitoring device in the second embodiment Electrical configuration diagram of the application section in the third embodiment Electrical configuration diagram of the battery monitoring device in the fourth embodiment Electrical configuration diagram of drive signal generator Electrical configuration diagram of the drive signal generator in the fifth embodiment

Several embodiments of the battery monitoring device 1 will be described below with reference to the drawings. The same reference numerals may be given to the same parts among the respective embodiments, and the description thereof may be omitted as necessary.

(First embodiment)
A first embodiment will be described with reference to FIG. The battery monitoring device 1 is a device that monitors the state of the assembled battery 2 . The assembled battery 2 is a chargeable/dischargeable secondary battery that supplies power to, for example, a power converter that supplies a three-phase current to the main motor, although not shown. The battery module is based on a lithium-ion storage battery, a nickel-metal hydride storage battery, or the like. The assembled battery 2 is configured by combining battery modules in which battery cells 3 are stacked and connected in series, and the voltage across the terminals as a whole reaches 100 V or more. The battery monitoring device 1 is a device that monitors the state of charge (SOC) and the state of deterioration (SOH) of the battery cell 3 to be measured.

The battery monitoring device 1 of this embodiment includes a plurality of blocks 4a, 4b, 4c, one adder 5, one waveform shaping section 6, one driver 7, two A/D converters 8, 9, and one multiplexer. 10, one on/off switch 11, two digital filters 12 and 13, a signal processing unit 14, and a communication unit 15 are configured using an ASIC connected in the illustrated form, and are configured to be controllable by a control unit 16. ASIC is an abbreviation for Application Specific Integrated Circuit. The communication unit 15 indicates a communication circuit that communicates with the outside of the ASIC. The control unit 16 executes switch switching control of the multiplexer 10 configured in the ASIC.

A drive signal generation section 21 and a lock-in detection section 22 are respectively configured in the plurality of blocks 4a, 4b, and 4c in this embodiment. The drive signal generators 21 are configured in the same number as the lock-in detectors 22 in each of the blocks 4a to 4c. Since the drive signal generation unit 21 and the lock-in detection unit 22 have the same configuration among the blocks 4a to 4c, only the configuration of a part of the block 4a is shown and the configuration of the other blocks 4b and 4c is omitted. ing. The drive signal generators 21 of the respective blocks 4a to 4c generate different single-frequency signals as drive signals. The lock-in detector 22 is configured by connecting four mixers 23i, 23q, 24i, 24q and digital filters 25i, 25q, 26i, 26q in the form shown.

The drive signal generator 21 of each of the blocks 4a to 4c is configured by, for example, a frequency synthesizer, and generates a sine wave drive frequency signal that is, for example, an odd multiple (eg, 1, 3, or 5 times) of the fundamental frequency. They are output in a phase-locked state with each other. Here, a form in which odd multiples of the fundamental frequency are used as signals of the driving frequencies of the respective blocks 4a to 4c will be described, but the present invention is not limited to this. An arbitrary single frequency for testing that is different from each other may be used as the driving frequency for each of the blocks 4a to 4c. The drive signal generator 21 outputs the I signal of the basic phase to the adder 5 and simultaneously outputs the IQ signals having phases different from each other by 90° to the mixers 23 i, 23 q, 24 i, and 24 q of the lock-in detector 22 .

The adder 5 adds the outputs of the drive signal generators 21 of the blocks 4a to 4c. In this embodiment, the adder 5 superimposes and adds the signals of the driving frequencies that are odd multiples of the fundamental frequency, and outputs the result to the waveform shaping section 6 . The application section 20 in this embodiment is composed of a drive signal generation section 21 , an adder 5 and a waveform shaping section 6 .

The waveform shaping section 6 of this embodiment is composed of a D/A converter. When the waveform shaping section 6 is composed of a D/A converter, the signal added by the adder 5 is analog-converted and directly applied to the monitoring energization section 32 through the driver 7 . The driver 7 amplifies the input signal and applies the amplified signal to the monitor energization section 32 .

On the other hand, a current-limiting resistor 31, a monitoring current-carrying part 32 for excitation, and a detection resistor 33 are connected in series to the current path between the positive terminal and the negative terminal of the assembled battery 2. FIG. The monitor energization unit 32 is composed of a switching element 32a such as a MOSFET, for example, and is used when the assembled battery 2 is monitored. The switching element 32 a is connected between its drain and source to the conducting path between the positive terminal and the negative terminal of the assembled battery 2 .

When a plurality of single-frequency signals are superimposed and applied simultaneously from the driver 7, the switching element 32a is turned on and off based on the driving frequency signal. In this embodiment, an on/off operation is performed based on a signal of a drive frequency obtained by superimposing three single frequencies, and current is supplied from the assembled battery 2 to the detection resistor 33 based on this operation. The detection resistor 33 detects the voltage based on the energized current.

<Description of Feedback Configuration of Detected Voltage by Detection Resistor 33>
An on/off switch 11 is connected to both terminals of the detection resistor 33 , and connected to the A/D converter 8 via the on/off switch 11 . The on/off switch 11 is normally kept off and is turned on by the controller 16 during battery monitoring. During battery monitoring, the battery monitoring device 1 acquires the voltage across the terminals of the detection resistor 33 through the A/D converter 8 . An amplifier may be provided in the preceding stage of the A/D converter 8, although it is shown in the drawing in a simplified manner. A digital filter 13 is arranged in the rear stage of the A/D converter 8, and outputs the processed signal that has passed through the low frequency band to each of the blocks 4a to 4c.

The lock-in detector 22 of each block 4a-4c feeds back the signal generated at the detection resistor 33 through the A/D converter 8 and the digital filter 13. FIG. The lock-in detector 22 inputs the input signal to two mixers 24i and 24q. On the other hand, the two mixers 24i and 24q receive and mix single-frequency signals generated by the driving signal generators 21 of the blocks 4a to 4c.

The mixers 24i and 24q of the respective blocks 4a to 4c mix the signals of the odd multiples of the fundamental frequency, which are different from each other, so that the corresponding single-frequency signals are mixed. Digital filters 26i and 26q are provided downstream of the mixers 24i and 24q, and output the processed signals to the signal processing section 14 after passing through the low frequency band. Therefore, the input signal to the signal processing unit 14 has a value corresponding to the real part/imaginary part of the absolute value of the current flowing through the assembled battery 2 detected by the detection resistor 33 .

<Explanation of Feedback Structure of Voltage of Battery 2>
On the other hand, both terminals of each battery cell 3 of the assembled battery 2 are connected to a multiplexer 10 and connected to an A/D converter 9 via the multiplexer 10 . The multiplexer 10 is configured by combining a plurality of switches respectively connected to the positive terminal and negative terminal of each battery cell 3 .

By switching the switch of the multiplexer 10 by the control unit 16 , the battery monitoring device 1 can acquire information on the voltage of the battery cells 3 to be measured in whole or in part of the assembled battery 2 through the A/D converter 9 . Although shown in the drawing for simplification, an amplifier may be provided in the preceding stage of the A/D converter 9 . A digital filter 12 is arranged in the subsequent stage of the A/D converter 9, and outputs a processed signal which passes through a low frequency band to each of the blocks 4a to 4c.

The lock-in detector 22 of each block 4a-4c feeds back the signal generated in the assembled battery 2 through the A/D converter 9 and the digital filter 12. FIG. The lock-in detector 22 inputs the input signal to two mixers 23i and 23q. On the other hand, the two mixers 23i and 23q receive and mix single-frequency signals generated by the driving signal generators 21 of the blocks 4a to 4c.

Since the mixers 23i and 23q of the respective blocks 4a to 4c mix different odd-numbered multiples of the fundamental frequency, they can mix corresponding single-frequency signals. Digital filters 25i and 25q are provided downstream of the mixers 23i and 23q, and output to the signal processing section 14 the processed signals that have passed through the low frequency band. Here, the input signal to the signal processing unit 14 has a value corresponding to the real part and the imaginary part of the absolute value of the voltage generated in the assembled battery 2, respectively.

As a result, the signal processing unit 14 inputs the real and imaginary parts of the absolute values of the current and voltage flowing through the assembled battery 2, and based on these values, calculates the complex impedance at each drive frequency based on voltage/current calculation. to measure. Thereby, the signal processing section 14 has a function as a measuring section. The signal processing unit 14 inputs the real part and the imaginary part of the absolute values of the current and voltage flowing through the assembled battery 2 for each odd multiple of the fundamental frequency different from each other from the blocks 4a to 4c. A complex impedance at a single frequency can be calculated respectively.

<Summary>
According to this embodiment, a plurality of single-frequency signals are superimposed by the adder 5 and simultaneously applied to the switching element 32a of the monitor energization section 32. FIG. Similarly, down-conversion mixers 23i, 23q, 24i, and 24q are provided in the lock-in detector 22 for a plurality of blocks 4a to 4c for each single frequency. This allows the signal processing unit 14 to measure impedances at a plurality of single frequencies simultaneously or in a time-division manner, thereby shortening the total measurement time.

Each of the blocks 4a to 4c including the drive signal generator 21 and the lock-in detector 22, the adder 5, the signal processor 14, and the digital filters 12 and 13 can be configured by digital circuits using low voltage elements and can be operated at low voltage. can.

In addition, the monitor energization unit 32, the driver 7, the A/D converters 8 and 9, the multiplexer 10, and the on/off switch 11 are composed of analog circuits with relatively medium and high voltage elements compared to the logic circuit described above. Blocks 4a to 4c can share an analog circuit, and even when complex impedance is measured at a plurality of frequencies for testing, the mounting area can be suppressed as much as possible and power consumption can be suppressed.

(Second embodiment)
A second embodiment will be described with reference to FIG. The difference of this embodiment from the first embodiment is that the digital filters 25i, 25q, 26i, and 26q, which are configured in the respective blocks 4a to 4c, are configured outside the respective blocks 204a to 204c, and the respective blocks 204a to 204c 204c in common.

As shown in FIG. 2, in this embodiment, the digital filters 25i, 25q, 26i, and 26q are not configured in the respective blocks 204a to 204c, and the digital filters 25i, 25q, 26i, 26i, 26i, 26i, 26i 26q is configured one for all blocks 204a to 204c.

As shown in FIG. 2, multiplexers 34i, 34q, 36i, and 36q for selectively inputting the outputs of the respective blocks 204a to 204c are configured as selection units, and the outputs of the digital filters 25i, 25q, 26i, and 26q are selectively output. Multiplexers 35i, 35q, 37i, and 37q are configured. The control unit 16 switches and controls the multiplexers 34i to 37i and 34q to 37q.

Then, the signal processing unit 14 can use the outputs of the digital filters 25i, 25q, 26i, and 26q in a time division manner. Impedance at multiple single frequencies can be calculated.

According to this embodiment, by using the digital filters 25i, 25q, 26i, and 26q in a time-sharing manner, the digital filters 25i, 25q, 26i, and 26q configured after the mixers 23i, 23q, 24i, and 24q are The processing signals of blocks 204a to 204c can be shared, and an increase in mounting area can be suppressed.

(Third embodiment)
A third embodiment will be described with reference to FIG. In this embodiment, a modification will be described in which a rectangular wave is generated by the PWM modulator 6a as a pulse modulator and applied to the monitor energization section 32. FIG. The application section 320 of this embodiment includes a plurality of drive signal generation sections 21 and a PWM modulator 6 a as the waveform shaping section 6 .

As shown in FIG. 3, the drive signal generator 21 is composed of a frequency synthesizer that outputs a sine wave signal of odd multiples (eg, 1, 3, 5 times) of the fundamental frequency for each of the blocks 4a to 4c. Each frequency synthesizer is configured to output a sinusoidal signal to the mixers 23i, 23q, 24i, 24q of each block 4a-4c.

Further, the drive signal generator 21 of the block 4 a outputs a sine wave signal having a frequency one times the fundamental frequency to the PWM modulator 6 a forming the waveform shaping section 6 . Waveform shaping section 6 outputs an H level when the signal input from PWM modulator 6a is positive and an L level when the signal is negative, so that it outputs a rectangular wave of the fundamental frequency.

The rectangular wave signal contains the sine wave of the fundamental frequency as well as harmonic components of odd multiples such as three times and five times the fundamental frequency. Therefore, when the waveform shaping section 6 applies this pulse signal to the MOSFET of the monitoring energizing section 32 through the driver 7, it becomes possible to simultaneously apply not only the fundamental frequency but also odd-numbered harmonic frequencies thereof. Multiple single frequency voltages can be energized.

The mixers 23i, 23q, 24i, and 24q of the blocks 4a to 4c receive sine wave signals of odd multiples of the fundamental frequency from the drive signal generators 21 of the blocks 4a to 4c, respectively. can be measured simultaneously or time-divisionally.

As a result, this embodiment also has the same effects as those of the above-described embodiment. In addition, the drive signal generator 21 outputs a rectangular wave to the monitor energizer 32 using the PWM modulator 6a, and the drive signal generator 21 outputs sine waves to the mixers 23i, 23q, 24i, and 24q of the blocks 4a to 4c. It emits a wave signal. Therefore, it becomes possible to measure the voltage, the real part of the current, and the imaginary part of the current at each single frequency that is an odd multiple of the fundamental frequency. It can be measured in divisions. The waveform shaping section 6 may be configured by a PDM modulator as a pulse modulator.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. 4 and 5. FIG. The difference between the battery monitoring device 401 of this embodiment and the battery monitoring device 1 of the first embodiment is that instead of the drive signal generators 21 of the blocks 4a to 4c, the blocks 404a to 404c are shared. It is where the drive signal generator 421 is configured. The application section 420 of the present embodiment is composed of the drive signal generation section 421 and the waveform shaping section 6 .

As shown in FIG. 4, in this embodiment, the drive signal generator 21 is not configured in each of the blocks 404a to 404c, and the drive signal generator 421 is provided outside the blocks 404a to 404c corresponding to all the blocks 404a to 404c. constitutes one. The drive signal generator 421 is configured by a DDS frequency synthesizer. DDS is an abbreviation for Direct Digital Synthesizer and is a digital direct synthesis oscillator.

As shown in FIG. 5, the DDS frequency synthesizer of the drive signal generation unit 421 includes a plurality of phase accumulators 51a to 51c each having an adder 52 and a latch 53 in the illustrated form, and synchronizes with the reference clock to generate the withdrawal speed K1. , K2, and K3, digital data in sawtooth waveforms are output at pull-out velocities K1, K2, and K3 proportional to the set values of a plurality of single frequencies, respectively.

In the sine wave table 54, digital information of sine waves corresponding to the number of data points corresponding to the minimum frequency and maximum period is prepared in advance. The drive signal generator 421 uses the sawtooth digital data as the phase of the output waveform, refers to the sine wave table 54, and outputs the corresponding m-bit data.

A sine wave table 54 of this type generally requires a relatively large storage area. data points can be viewed. Therefore, there is no need to secure a storage area for individually storing sine wave data for a plurality of single frequencies, and the sine wave table 54 can be prevented from becoming large. These m-bit data outputs for a plurality of single frequencies are input to mixers 23i, 23q, 24i and 24q of blocks 4a to 4c as shown in FIG.

The adder 55 adds m-bit data outputs for a plurality of drive frequencies and outputs the result to the waveform shaping section 6 . A waveform shaping section 6 subjects the added data to waveform shaping and outputs the result as a drive frequency signal.

If the waveform shaping section 6 is a D/A converter, the m-bit data output is added and input and converted into an analog signal. It will be.

In this way, even if a DDS frequency synthesizer is used as the drive signal generator 421, it becomes possible to simultaneously or time-divisionally measure the impedance at a plurality of single frequencies. It works and has the same effect.

By configuring the drive signal generator 421 with a DDS frequency synthesizer, it is possible to share hardware and avoid parallelization of the frequency synthesizer, which can be realized with a single circuit. In addition, when the drive signal generation unit 421 generates the signal of the drive frequency, the sine wave table 54 of the DDS frequency synthesizer can be used in common, thereby suppressing an increase in circuit scale.

<Modification of Fourth Embodiment>
Further, as described in the third embodiment, if the reference output of the sine wave table 54 by the phase accumulator 51a is input to the PWM modulator 6a without providing the adder 55 shown in FIG. The device 6a will output a square wave at the fundamental frequency. This output pulse signal contains a harmonic signal as well as a sine wave signal of the fundamental frequency.

Therefore, by applying the pulse signal, the switching element 32a can be energized and driven by a plurality of signals that can be regarded as having a single frequency. If the lock-in detection unit 22 detects lock-in as in the above embodiment, the signal processing unit 14 can simultaneously measure the impedance at the fundamental frequency and its harmonic frequency. As the waveform shaping section 6, a PDM modulator may be configured as a pulse modulator. As a result, effects similar to those of the third embodiment can be obtained.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. This embodiment differs from the fourth embodiment in that only one phase accumulator 551 is provided in the configuration of the DDS frequency synthesizer as the drive signal generator 521 .

As shown in FIG. 6, the drive signal generator 521 configures one phase accumulator 551 including an adder 52 and a latch 53, and includes multipliers 56 and 57 that multiply the output of the phase accumulator 551 by an odd number. . The phase accumulator 551 accumulates the set value of the withdrawal speed K1 in synchronization with the reference clock, and outputs sawtooth digital data at the withdrawal speed K1 proportional to the set value of the fundamental frequency. Multipliers 56 and 57 multiply the output digital data of phase accumulator 551 by an odd number, refer to sine wave table 54, and output sine wave data to mixers 23i, 23q, 24i, and 24q of blocks 4a to 4c. .

In the sine wave table 54, digital information of sine waves corresponding to the number of data points corresponding to the minimum frequency and maximum period is prepared in advance. The drive signal generator 521 uses the sawtooth digital data as the phase of the output waveform, refers to the sine wave table 54, and outputs the corresponding m-bit data. As in the above-described embodiment, there is no need to secure a storage area for individually storing sine wave data for a plurality of single frequencies, and an increase in the size of the sine wave table 54 can be suppressed.

The fundamental frequency sine wave data is output to the waveform shaping section 6 . The waveform shaping unit 6 of the present embodiment is composed of a PWM modulator 6a, and the PWM modulator 6a outputs a PWM signal as a pulse signal in order to shape the m-bit data output with reference to the sine wave table 54 into a rectangular wave shape. will do.

As described in the third and fourth embodiments, the pulse signal includes a sine wave signal of the fundamental frequency and a harmonic signal, and the impedance can be simultaneously measured at the frequency included in the pulse signal. become. The waveform shaping section 6 may use a PDM modulator as a pulse modulator.

As a result, this embodiment also has the same effects as those of the above-described embodiment. In addition, when the drive signal generation unit 521 generates a plurality of single-frequency signals, the sine wave table 54 of the DDS frequency synthesizer can be shared, thereby suppressing an increase in circuit scale.

(Other embodiments)
The present invention is not limited to the above-described embodiments, but can be implemented in various modifications, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions are possible. A mode has been described in which the signal processing unit 14 measures the impedance by dividing the voltage of the battery cell 3 to be measured in the assembled battery 2 by the current that flows. You may make it measure.

The battery monitoring device 1, 201, 401, controller 16 approach described in this disclosure configures a processor and memory programmed to perform one or more functions embodied by a computer program. may be implemented by a dedicated computer provided by Alternatively, the battery monitoring devices 1, 201, 401, the control unit 16, and the techniques thereof described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. good. Alternatively, the battery monitoring devices 1, 201, 401, controller 16, and techniques described in the present disclosure may be implemented by a processor and memory programmed to perform one or more functions and one or more hardware logic It may also be implemented by one or more dedicated computers in combination with a processor made up of circuits. The computer program may also be stored as computer-executable instructions on a computer-readable non-transitional tangible storage medium.

Although the present invention has been described with reference to the embodiments described above, it is understood that the invention is not limited to such embodiments or constructions. The present invention includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of the invention.

In the drawings, 1, 201 and 401 are battery monitoring devices, 2 is an assembled battery, 3 is battery cells, 6a is a PWM modulator (pulse modulator), 14 is a signal processing section (measurement section), 16 is a control section, 20 , 320 and 420 denote application units, 21, 421 and 521 denote drive signal generation units, and 34i, 34q, 35i and 35q denote multiplexers (selection units).

Claims (6)

a monitoring energization unit (33) that energizes a part or all of the battery cells (3) to be measured in the assembled battery (2) and a detection resistor that is connected in series to the battery cells (3) to be measured;
an application unit (20; 320; 420) for simultaneously applying signals generated by a drive signal generation unit (21; 421; 521) by superimposing a plurality of single frequency signals different from each other to the monitoring energization unit;
A signal that is provided for each of the plurality of single frequencies and that is generated in the detection resistor and the battery cell to be measured when applied from the applying unit to the monitoring energizing unit is fed back, and the plurality of a plurality of lock-in detectors (22) for inputting single-frequency signals of and mixing them by mixers (23i, 23q, 24i, 24q) for lock-in detection;
measurement units (14, 16) for measuring respective impedances at the plurality of single frequencies based on the detection results of the plurality of lock-in detection units;
A battery monitoring device comprising: The application unit (20)
the drive signal generator (21) for generating a plurality of single-frequency signals;
an adder (5) for adding the plurality of single-frequency signals;
2. The battery monitoring device according to claim 1, wherein the signals obtained by superimposing the signals by the adder are simultaneously applied to the monitoring current-carrying unit. The drive signal generation unit and the lock-in detection unit are configured in parallel by a digital circuit,
3. The battery monitoring device according to claim 1, wherein the monitoring energizing section to which the outputs of the plurality of driving signal generating sections are applied is shared by an analog circuit. a selection unit (34i, 34q, 35i, 35q) that selects from signals mixed for each of the plurality of single frequencies by the mixers of the plurality of lock-in detection units;
a digital filter (25i, 25q, 26i, 26q) for filtering the selected signal;
4. The battery according to any one of claims 1 to 3, wherein the measurement unit measures the impedance in a time division manner for each of the plurality of single frequencies using the signal selected by the selection unit and processed by the digital filter. surveillance equipment. 5. The drive signal generation unit (421, 521) uses a DDS (Direct Digital Synthesizer) frequency synthesizer to share hardware to generate the plurality of single-frequency signals. The battery monitoring device according to claim 1. A pulse modulator (6a) that generates a rectangular wave by shaping a single-frequency signal generated by the drive signal generator (21),
The application unit (320) uses the pulse modulator to generate a fundamental frequency signal and a harmonic at the same time, and applies the same to the monitoring current-carrying unit, thereby supplying the plurality of single-frequency signals to the monitoring current-carrying unit. 2. The battery monitoring device according to claim 1, wherein the voltage is applied.

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