JP2023023342A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that functions as a protection element and that easily forms a semiconductor integrated circuit having a low parasitic capacitance at normal operation time of a protected circuit.SOLUTION: A diode array in which a first pn junction diode D1a and a second pn junction diode D2a are connected in a forward direction, and a diode array in which another first pn junction diode D1b and another second pn junction diode D2b are connected in an opposite direction are connected in parallel between a first terminal T1 and a second terminal T2. Diodes having small capacitances are connected by making pieces of forward direction voltage of pn junction diodes constituting the diode array to have different values. As a result, synthetic capacitance is made small, and parasitic capacitance having a state not functioning as a protection element can be made small. Connection for forming the diode array can be formed only using connection between semiconductor substrate surfaces.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having a pn junction diode that serves as a transient voltage protection element.

Semiconductor devices have been miniaturized and the impurity concentration has been increased in order to meet the demands for performance improvement and miniaturization. Such semiconductor devices have reduced resistance to electrostatic discharge (ESD) and the like. Therefore, a pn junction diode in which a p-type semiconductor region and an n-type semiconductor region are joined is used as a protective element (Patent Document 1). In this type of semiconductor device, by appropriately setting the impurity concentrations of the p-type semiconductor region and the n-type semiconductor region, it is possible to form a protective element having desired characteristics.

By the way, when a protection element is connected to a signal line to which a circuit to be protected is connected, the pn junction diode becomes a parasitic capacitance when the circuit to be protected operates normally (when the protection element does not operate). If this parasitic capacitance is large, the loss of the signal propagating through the signal line will increase. Therefore, a semiconductor device using a low-capacity pn diode has been proposed (Patent Document 2).

In this type of semiconductor device, as shown in FIG. 3, a lightly doped n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1. A high-concentration n-type buried layer 3 is formed. A p-type region 4 and an n-type region 5 are formed on the surface of the n-type epitaxial layer 2 and partitioned by isolation trenches 6 .

With such a structure, the p-type semiconductor substrate 1 and the n-type buried layer 3 form a Zener diode ZD, and the pn junction of the p-type region 4 and the n-type epitaxial layer 2 forms a low-capacity pn junction diode. DA is formed. A pn junction of the p-type semiconductor substrate 1 and the n-type epitaxial layer 2 forms a low-capacity pn junction diode DB. FIG. 4 shows its circuit configuration.

A semiconductor device having such a structure is used as a protection element by connecting a first terminal T1 to a signal line to which a circuit to be protected is connected and grounding the substrate 1, which serves as a second terminal T2. . For example, when a positive transient voltage is applied to the first terminal T1, the transient current flows forward through the low-capacitance pn junction diode DA and reverse through the Zener diode ZD from the second terminal T2. flow to ground. At this time, the clamp voltage VCL1 of the first terminal T1 is the sum of the forward voltage VF _(DA) of the low-capacity pn junction diode DA and the reverse breakdown voltage VBR _(ZD) of the Zener diode ZD (VCL1=VF _{(DA )} +VBR _(ZD) ).

When a negative transient voltage is applied to the first terminal T1, the transient current flows forward through the low-capacity pn junction diode DB. At this time, the clamp voltage VCL2 of the first terminal T1 can be represented by the forward voltage VF _(DB) (VCL2=VF _(DB) ) of the low-capacity pn junction diode DB.

On the other hand, in recent years, the operating voltage of semiconductor devices, which are circuits to be protected, has been reduced, and the demand for lower operating voltages of protection elements has increased.

JP-A-11-8841 JP 2014-175325 A

In the conventional semiconductor device as shown in FIG. 3, when a positive transient voltage is applied and when a negative transient voltage is applied to a signal line to which a circuit to be protected is connected, the first terminal T1 A difference occurs in the clamp voltage. Therefore, its application was limited to the protection of a circuit to be protected from an abnormal surge voltage caused by lightning or induced lightning. In other words, in this type of semiconductor device, desired protection cannot be expected when a signal that swings about GND like an analog signal is propagated through the signal line. Furthermore, as the operating voltage of a circuit to be protected is becoming lower in recent years, it is also necessary to lower the operating voltage of a protective element. Furthermore, a circuit configuration in which the semiconductor substrate 1 is grounded cannot be formed in a normal semiconductor integrated circuit. In view of such circumstances, the present invention provides a semiconductor device that functions as a protective element and has a low parasitic capacitance during normal operation of a circuit to be protected, and that can be easily formed in a general semiconductor integrated circuit. An object is to provide a semiconductor device.

In order to achieve the above object, the invention according to claim 1 of the present application provides a semiconductor device having a plurality of pn junction diode forming regions in a semiconductor region stacked on a semiconductor substrate, wherein the pn junction diode forming region is a first diode forming region. and a second diode forming region, wherein the first diode forming region is formed by stacking a first semiconductor region having a first conductivity type and a first impurity concentration on the semiconductor substrate; In the diode forming region, a second semiconductor region of a first conductivity type and having a second impurity concentration lower than the first impurity concentration is laminated on the semiconductor substrate, and the surface of the first semiconductor region and the first semiconductor region are laminated. A third semiconductor region of a second conductivity type is provided on the surface of each of the semiconductor regions of 2, and a first pn is formed in the first diode forming region by the third semiconductor region and the first semiconductor region. A junction diode is formed, a second pn junction diode is formed in the second diode formation region by the third semiconductor region and the second semiconductor region, and the first pn junction diode and the second semiconductor region are formed in the second diode formation region. pn junction diodes connected in series in the forward direction, and a diode array in which the first pn junction diode and the second pn junction diode are both connected in series in the reverse direction. The diode string connected in series in the forward direction and the diode string connected in series in the reverse direction are connected in parallel between the first terminal and the second terminal.

The invention according to claim 2 of the present application is the semiconductor device according to claim 1, wherein the forward voltage of the first pn junction diode is higher than the forward voltage of the second pn junction diode, and the second pn junction diode has a forward voltage higher than that of the second pn junction diode. The capacitance of the junction diode is smaller than the capacitance of the first pn junction diode.

The invention according to claim 3 of the present application is the semiconductor device according to claim 1 or claim 2, wherein the first terminal is connected to a signal line of a circuit to be protected and the second terminal is grounded. A transient current flows in the forward direction of the diode array connected in series in the forward direction and connected to the first terminal, thereby protecting the circuit to be protected.

INDUSTRIAL APPLICABILITY The semiconductor device of the present invention can protect a protected circuit with a low operating voltage from a transient voltage, and can realize a low-capacity protective element. Also, it can be formed as a general semiconductor integrated circuit.

1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention; FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention; FIG. 1 is an explanatory diagram of a conventional semiconductor device of this type; FIG. 1 is an explanatory diagram of a conventional semiconductor device of this type; FIG.

The semiconductor device of the present invention functions as a protection element that is connected to a signal line connected to a circuit to be protected and protects the circuit to be protected from transient voltages such as electrostatic discharge. In particular, the semiconductor device of the invention provides sufficient protection even when the circuit to be protected operates at a low operating voltage or when a loss increases when a parasitic capacitance is connected to a signal line connected to the circuit to be protected. It has a configuration that can achieve low loss. Embodiments of the present invention will be described below.

(embodiment)
FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention, schematically showing a cross-sectional view of a semiconductor device composed of four pn junction diodes formed at different positions on a semiconductor substrate 1. FIG. there is As shown in FIG. 1, a low-concentration n-type epitaxial layer 2 is laminated on a semiconductor substrate 1, and part of the n-type epitaxial layer 2 has an impurity concentration higher than that of the n-type epitaxial layer 2. An n-type well 7a is formed. An isolation trench 6 separates the n-type epitaxial layer 2a of the n-type epitaxial layer 2 and the region where the n-type well 7a is formed. Of the regions defined by the isolation trenches 6, the n-type well 7a (corresponding to the first semiconductor region) serves as the first diode formation region in which the first pn junction diode D1a is formed, and serves as the n-type epitaxial layer. 2a (corresponding to a second semiconductor region) is a second diode formation region in which a second pn junction diode D2a is formed.

A p-type region 8a and an n-type region 9a are formed on the surface of the n-type well 7a serving as the first diode forming region. A pn junction between the p-type region 8a (corresponding to a third semiconductor region) and the n-type well 7a forms a first pn junction diode D1a. A p-type region 8b and an n-type region 9b are also formed on the surface of the n-type epitaxial layer 2a serving as the second diode formation region. Here, a second pn junction diode D2a is formed by a pn junction between p type region 8b (corresponding to a third semiconductor region) and n type epitaxial layer 2a.

By forming the p-type region 8a and the p-type region 8b at the same time, it becomes possible to form them with the same impurity concentration and depth, and it becomes easy to control the characteristics of the pn junction.

The n-type region 9a formed on the surface of the n-type well 7a in the first diode forming region is a contact region for the n-type well 7a, and is formed on the surface of the n-type epitaxial layer 2a in the second diode forming region. The n-type region 9b becomes a contact region for the n-type epitaxial layer 2a. Therefore, the n-type region 9a is arranged so that the first pn junction diode D1a has desired characteristics, and the n-type region 9b is arranged so that the second pn junction diode D2a has desired characteristics.

In addition, on the semiconductor substrate 1, pn junction diodes are simultaneously formed in different sets of first diode forming regions and second diode forming regions. Specifically, as shown in FIG. 1, in a portion of n-type epitaxial layer 2 on semiconductor substrate 1, n-type well 7b having a higher impurity concentration than n-type epitaxial layer 2 is formed. An isolation trench 6 separates the n-type epitaxial layer 2b, which is a part of the n-type epitaxial layer 2, and the region where the n-type well 7b is formed. Of the regions defined by the isolation trenches 6, the n-type well 7b (corresponding to the first semiconductor region) serves as another first diode formation region in which another first pn junction diode D1b is formed, The n-type epitaxial layer 2b (corresponding to the second semiconductor region) becomes another second diode forming region in which another second pn junction diode D2b is formed.

A p-type region 8c and an n-type region 9c are formed on the surface of the n-type well 7b, which is another first diode forming region. Another first pn junction diode D1b is formed by the pn junction between the p-type region 8c (corresponding to the third semiconductor region) and the n-type well 7b. A p-type region 8d and an n-type region 9d are also formed on the surface of the n-type epitaxial layer 2b, which is another second diode forming region. Here, another second pn junction diode D2b is formed by the pn junction of the p-type region 8d (corresponding to the third semiconductor region) and the n-type epitaxial layer 2b.

The first pn junction diode D1a and the further first pn junction diode D1b can be formed at the same time. Similarly, the second pn junction diode D2a and another second pn junction diode D2b can be formed at the same time.

Therefore, by connecting as shown in FIG. 1, the first pn junction diode D1a and the second pn junction diode D2a are connected in the forward direction between the first terminal T1 and the second terminal T2. A diode string and a diode string in which another first pn junction diode D1b and another second pn junction diode D2b are connected in opposite directions are connected in parallel. FIG. 2 shows the connection state of the diode string. This connection can be formed only by wiring on the surface of the semiconductor substrate 1 .

When using the semiconductor device of this embodiment as a protective element, for example, the first terminal T1 is connected to the signal line to which the circuit to be protected is connected. Also, the second terminal T2 is connected to the ground potential.

When a positive transient voltage is applied to the first terminal T1, a transient current flows through a diode string in which the first pn junction diode D1a and the second pn junction diode D2a are connected in series in the forward direction. 2 terminal T2 to ground. At this time, the clamp voltage VCL1 of the first terminal T1 is the sum of the forward voltage VF _(D1a) of the first pn junction diode D1a and the forward voltage VF _(D2a) of the second pn junction diode D2a (VCL1=VF _(D1a) + VF _(D2a) ).

Further, when a negative transient voltage is applied to the first terminal T1, the transient current is a diode in which another first pn junction diode D1b and another second pn junction diode D2b are connected in series in the forward direction. It flows through the column and from the second terminal T2 to ground. At this time, the clamp voltage VCL2 of the first terminal T1 is the sum of the forward voltage VF _(D1b) of another first pn junction diode D1b and the forward voltage VF _(D2b) of another second pn junction diode D2b. (VCL2=VF _(D1b) +VF _(D2b) ).

As described above, the first pn junction diode D1a and another first pn junction diode D1b are pn junction diodes having the same characteristics, and the second pn junction diode D2a and another second pn junction diode D2b are made to have the same characteristics. By using a pn junction diode, it is possible to configure so that there is no difference in the clamp voltage of the first terminal T1 when a positive transient voltage is applied to the signal line and when a negative transient voltage is applied to the signal line. can.

Furthermore, since the transient current flows in the forward direction of the pn junction diode, even if the circuit to be protected operates at a low voltage, the protective element can be configured to operate at a low voltage, thereby enabling the desired protection. Become.

By the way, in order to set a desired clamp voltage, the characteristics of the first pn junction diode D1a and the second pn junction diode D2a are appropriately set. In the case of this embodiment, the impurity concentration of the n-type well 7a forming the pn junction of the first pn junction diode D1a is higher than the impurity concentration of the n-type epitaxial layer 2a forming the pn junction of the second pn junction diode D2a. set high. By setting in this way, not only can the forward voltage of the diode string described above be reduced, but also the parasitic capacitance can be reduced.

Specifically, the characteristics of the first pn junction diode are the forward voltage VF=1.0 V and the capacitance C1=1.0 pF, and the characteristics of the second pn junction diode are the forward voltage VF=0.6 V and the capacitance C2. =0.04 pF will be described. Here, the combined forward voltage Vf is Vf=1.0V+0.6V=1.6V.

For comparison, when two pn junction diodes having characteristics of forward voltage VF=0.8V and capacitance C=0.4pF are connected in series, the combined forward voltage vf is vf=0.8V+0.8V=1. 6 V, and the same characteristics can be obtained.

However, when the combined capacitance is compared, there is a difference in characteristics. Specifically, since the combined capacitance can be represented by the sum of reciprocals, the combined capacitance C of the semiconductor device of this embodiment is C=(C1×C2)/(C1+C2)=(1.0×0.04 )/(1.0+0.04)=0.038 pF. On the other hand, the combined capacitance c of the comparative example is c=(0.4×0.4)/(0.4+0.4)=0.2 pF. Thus, it can be seen that the semiconductor device of this embodiment has a small capacitance (parasitic capacitance) when it does not operate as a protective element.

As described above, the semiconductor device of this embodiment starts operating when a transient current flows in the forward direction, so it is possible to protect a circuit to be protected with a low operating voltage. In addition, the capacitance (parasitic capacitance) is small when not operating as a protective element, and loss of signals propagating through the signal line is not caused when connected to the signal line of the circuit to be protected. Furthermore, since each pn junction diode can be connected to each other on the surface of the semiconductor substrate, it is easy to form a semiconductor integrated circuit.

It should be noted that the present invention is not limited to the above embodiments. For example, in the example shown in FIG. 1, a first pn junction diode D1a and a second pn junction diode D2a are connected in this order between a first terminal T1 and a second terminal T2. Although an example in which another second pn junction diode D2b and another first pn junction diode D1b are connected in this order is shown, the connection order of the first pn junction diode and the second pn junction diode is Similar characteristics can be obtained by reversing the connection order of the second pn junction diode and the other first pn junction diode.

Also, in order to shorten the manufacturing process, the formation of the n-type wells 7a and 7b and the formation of the p-type regions 8a to 8d have been described as being formed at the same time. Variations in the impurity concentration, etc. of the region 1 are allowed, and there is no problem even if they are formed separately.

1: semiconductor substrate, 2, 2a, 2b: n-type epitaxial layer, 3: n-type buried layer, 4: p-type region, 5: n-type region, 6: isolation trench, 7a, 7b: n-type well, 8a-8d: p-type regions, 9a-9d: n-type regions

Claims (3)

In a semiconductor device having a plurality of pn junction diode forming regions in a semiconductor region laminated on a semiconductor substrate,
The pn junction diode forming region includes a first diode forming region and a second diode forming region,
the first diode formation region is formed by stacking a first semiconductor region having a first conductivity type and a first impurity concentration on the semiconductor substrate;
the second diode formation region is formed by stacking a second semiconductor region having a first conductivity type and a second impurity concentration lower than the first impurity concentration on the semiconductor substrate;
A third semiconductor region of a second conductivity type is provided on the surface of the first semiconductor region and the surface of the second semiconductor region, respectively;
a first pn junction diode is formed in the first diode forming region by the third semiconductor region and the first semiconductor region;
a second pn junction diode is formed in the second diode formation region by the third semiconductor region and the second semiconductor region;
a diode string in which both the first pn junction diode and the second pn junction diode are connected in series in the forward direction; A string of diodes connected in series is formed,
A semiconductor device, wherein the diode array connected in series in the forward direction and the diode array connected in series in the reverse direction are connected in parallel between a first terminal and a second terminal. The semiconductor device according to claim 1,
the forward voltage of the first pn junction diode is greater than the forward voltage of the second pn junction diode;
A semiconductor device, wherein the capacitance of the second pn junction diode is smaller than the capacitance of the first pn junction diode. 3. In the semiconductor device according to claim 1 or 2,
When the first terminal is connected to a signal line of a circuit to be protected and the second terminal is grounded,
A semiconductor device, wherein a transient current flows in the forward direction of the diode array connected in series in the forward direction and connected to the first terminal, thereby protecting the circuit to be protected.

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