JP2023023298A - Power source semiconductor integrated circuit and power source regulator circuit - Google Patents

Abstract

To provide a power source semiconductor integrated circuit capable of detecting occurrence of an open-circuit failure in any one or more loads of plural loads.SOLUTION: A power source semiconductor integrated circuit includes: an output transistor connected between a voltage input terminal, to which a dc voltage is inputted, and a voltage output terminal; and a control circuit that controls the output transistor according to a feedback voltage of an output. The power source semiconductor integrated circuit further includes: an open-circuit failure detection circuit that includes plural voltage comparison circuits each of which compares each voltage of threshold voltages on predetermined plural stages with a voltage proportional to a voltage at the voltage output terminal, and that detects an open-circuit condition of the voltage output terminal; and plural detection result output terminals through which a result of detection by the open-circuit failure detection circuit is outputted to outside. The threshold voltages on the plural stages are designated so that the open-circuit failure detection circuit can detect the open-circuit condition of some of the plural loads or all of the loads connected to the voltage output terminal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power supply semiconductor integrated circuit (power supply IC) that constitutes a DC power supply device such as a voltage regulator or a DC-DC converter that converts a DC voltage, and more particularly to an open output terminal to which loads of multiple channels are connected. It relates to effective technology for detection.

2. Description of the Related Art A series regulator (hereinafter abbreviated as a regulator) is a power supply device that controls a transistor provided between a DC voltage input terminal and an output terminal to output a DC voltage of a desired potential.
In a car equipped with a terrestrial digital broadcasting (terrestrial digital television broadcasting) tuner, an in-vehicle regulator supplies power to in-vehicle electronic devices such as a terrestrial digital antenna. In addition, in the terrestrial digital tuner for vehicles that support full seg, the tuner adjusts the reception sensitivity and switches between full seg and one seg, and in order to optimize the reception situation, a 4ch (channel) equivalent is used as a terrestrial digital antenna. Diversity antennas, which are antennas, are commonly used.

On the other hand, tuners and antennas for automobiles are connected to the in-vehicle regulator via a connector, so vibrations from the car body can cause the connector to come off and open the output terminal of the power supply, or cause a short circuit inside the load. Sometimes. Therefore, some automotive regulators have a function to detect such an abnormal state.
Therefore, an open abnormality detection comparator for detecting the open state of the output terminal and a short abnormality detection comparator for detecting the short state of the output terminal are provided, and an abnormality detection signal is generated and output from the output terminal. Inventions relating to integrated circuits (regulator ICs) have been proposed (eg, Patent Documents 1 and 2).

JP 2017-45096 A JP 2018-55545 A

Conventionally, in an in-vehicle terrestrial digital system equipped with multiple antennas, it was common to supply power to the multiple antennas from a common regulator. In this case, even if one of the 1ch antennas is open, the signal is received by the other channel, so the operation is performed without detecting an abnormality. On the other hand, in order to detect that any one of the 1ch antennas is open, it is conceivable to provide a regulator having an open abnormality detection function for each antenna as a load. However, doing so requires a plurality of regulators, which poses the problem of a significant increase in cost and an increase in mounting area.

The present invention has been made in view of the above-mentioned problems, and its object is to supply power to a plurality of loads and, at the same time, to prevent the occurrence of an open failure in one of the loads or a plurality of loads. It is an object of the present invention to provide a power supply semiconductor integrated circuit and a power supply regulator circuit capable of detecting and outputting .

In order to achieve the above object, the present invention
A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit for controlling the output transistor in accordance with an output feedback voltage. ,
An open abnormality detection circuit that detects an open state of the voltage output terminal, and has a plurality of voltage comparison circuits that compare a voltage proportional to the voltage of the voltage output terminal and each voltage of a plurality of predetermined threshold voltages. and,
a plurality of detection result output terminals for outputting a detection result by the open abnormality detection circuit to the outside,
The plurality of stages of threshold voltages are set so that the open abnormality detection circuit can detect the open state of any one of the plurality of loads connected to the voltage output terminal and the open state of all the loads. It is configured as described.

According to the power supply semiconductor integrated circuit having the above configuration, power can be supplied from one semiconductor integrated circuit to a plurality of loads connected to the voltage output terminal, resulting in a significant increase in cost and a reduction in mounting area. In addition, the open abnormality detection circuit can distinguish and detect the open state of any of the plurality of loads connected to the voltage output terminal and the open state of all the loads.

A power supply regulator circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit for controlling the output transistor in accordance with an output feedback voltage. and
An open abnormality detection circuit that detects an open state of the voltage output terminal, and has a plurality of voltage comparison circuits that compare a voltage proportional to the voltage of the voltage output terminal and each voltage of a plurality of predetermined threshold voltages. and,
A detection result by the open abnormality detection circuit can be output to the outside,
The plurality of stages of threshold voltages are set so that the open abnormality detection circuit can detect the open state of any one of the plurality of loads connected to the voltage output terminal and the open state of all the loads. It may be configured as shown.

According to the present invention, a power supply semiconductor integrated circuit (regulator IC, There is an effect that it is possible to provide a DC-DC converter IC) and a power supply regulator circuit.

1 is a circuit configuration diagram showing one embodiment of a regulator IC to which the present invention is applied; FIG. FIG. 10 is a diagram showing the relationship between the current consumption of 2ch antennas and the state of the output terminal when the variation a of the current consumption of each antenna is 33%.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a series regulator as a DC power supply device to which the present invention is applied. In FIG. 1, a portion surrounded by a dashed line is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as single crystal silicon, and a capacitor Co is connected to an output terminal OUT of the regulator IC 10. function as a DC power supply that supplies a stable DC voltage.

In the regulator IC 10 of this embodiment, as shown in FIG. 1, a voltage control transistor Q1 made up of a P-channel MOS transistor is connected between a voltage input terminal IN to which a DC voltage VDD is applied and an output terminal OUT. Bleeder resistors R1 and R2 for dividing the output voltage Vout are connected in series between the output terminal OUT and the ground line to which the ground potential GND is applied.

The voltage VFB divided by the output voltage dividing resistors R1 and R2 is fed back to the non-inverting input terminal of an error amplifier 11 as an error amplifier circuit for controlling the gate terminal of the voltage control transistor Q1. Then, the error amplifier 11 controls the voltage control transistor Q1 according to the potential difference between the output feedback voltage VFB and the predetermined reference voltage Vref to control the output voltage Vout to a desired potential.
In the regulator IC 10 of the present embodiment, even when two antennas ANT1 and ANT2 are connected as loads to the output terminal OUT, a voltage control circuit is provided so that a required current can flow to each load. The characteristics and size of the transistor Q1 are designed.

Further, the regulator IC 10 of this embodiment includes a reference voltage circuit 12 for generating a reference voltage Vref applied to the inverting input terminal of the error amplifier 11, and an operating current flowing through the error amplifier 11 and the reference voltage circuit 12. A bias circuit 13, a current limit circuit 14 connected to the gate terminal of the voltage control transistor Q1 for limiting the output current, and operation of the error amplifier 11 when the temperature of the chip rises above a predetermined temperature. A thermal shutdown (TSD) circuit 15 is provided which shuts down and turns off transistor Q1. CE is an external terminal to which a signal for turning on/off the operation of the IC is input.

The reference voltage circuit 12 may consist of a bandgap reference, a series resistor, a Zener diode, or the like. The bias circuit 13 has a function of supplying or cutting off a bias current to the error amplifier 11 according to a control signal input to the external terminal CE from an external microcomputer (CPU) or the like. When the error amplifier 11 attempts to lower the gate voltage so as to allow more current to flow through the transistor Q1 due to an increase in the output current Iout due to an abnormality in the load, etc., the current limit circuit 14 reduces the output voltage beyond a predetermined level. The output current Iout is limited by applying a clamp so that the drain current does not increase. This output current Iout flows as the consumption current Icc of the antennas ANT1 and ANT2 as loads connected to the output terminal OUT.

Further, in the regulator IC 10 of the present embodiment, transistors Q2, Q3, and Q4 forming a current mirror circuit with Q1 are provided in parallel with the voltage control transistor Q1. The same voltage as that applied to the gate terminal of the transistor Q1 for voltage control is applied to the gate terminal of Q1. As a result, a current proportional to the drain current of Q1 (a current of 1/N) flows through Q2 to Q4 according to the size ratio N of the elements. When the transistor Q1 is configured by connecting N transistors of the same size in parallel and each of Q2 to Q4 is configured by one transistor, a current proportional to the number of elements is set to flow. .

Further, the regulator IC 10 of this embodiment is provided with an external terminal P1 for connecting a resistor Rop for current-voltage conversion outside the chip and an external terminal P2 for connecting a resistor Rsc. The drain terminal of mirror transistor Q2 is connected to external terminal P1, and the drain terminal of current mirror transistor Q3 is connected to external terminal P2.
Furthermore, comparators CMP1 and CMP2 for open abnormality detection, in which the inverting input terminal is connected to the external terminal P1 and the reference voltages Vop_1 and Vop_2 (Vop_1>Vop_2) are applied to the non-inverting input terminal, and the non-inverting input terminal is connected to the external terminal P2. , and a comparator CMP3 for short-circuit abnormality detection, to which the reference voltage Vsc is applied to the inverting input terminal. Although not particularly limited, the comparators CMP1 and CMP2 for open-circuit abnormality detection and the comparator CMP3 for short-circuit abnormality detection have hysteresis characteristics.

The resistance value of the external resistor Rop is set so that the voltage between both terminals of the resistor becomes the same value as the reference voltages Vop_1 and Vop_2 when a relatively small open fault detection current flows through the current mirror transistor Q2. set. How to set the reference voltages Vop_1 and Vop_2 will be described later in detail. On the other hand, the resistance value of the external resistor Rsc is set so that the voltage between both terminals of the resistor becomes the same value as the reference voltage Vsc when a relatively large short-circuit abnormality detection current flows through the current mirror transistor Q3. set.

Therefore, when one of the two antennas connected to the output terminal OUT is disconnected or disconnected and the current flowing through the voltage control transistor Q1 and the current mirror transistor Q2 decreases, the output OP_OUT1 of the comparator CMP1 becomes low level (L). to a high level (H), and when both are disconnected and the current flowing through the voltage control transistor Q1 and the current mirror transistor Q2 further decreases, the outputs OP_OUT1 and OP_OUT2 of the comparators CMP1 and CMP2 both change from L to H. can be used to detect open abnormalities.
As described above, in this embodiment, the external resistors Rop and Rsc set the current values for detecting the open and short abnormalities, so the detection current values (threshold values) can be arbitrarily set according to the system used. . The same voltage value can be used as one of the reference voltages Vop_1 and Vop_2 used for the comparators CMP1 and CMP2 and the reference voltage Vsc used for the comparator CMP3.

Further, the regulator IC 10 of this embodiment is provided with a logic circuit 16 that inputs the outputs OP_OUT1 and OP_OUT2 of the open-circuit abnormality detection comparators CMP1 and CMP2 and the output SC_OUT of the short-circuit abnormality detection comparator CMP3.
Furthermore, there are provided N-channel MOS transistors Q5 and Q6, to whose gate terminals the output of the logic circuit 16 is input. The regulator IC is provided with external terminals P3 and P4 for outputting abnormality detection signals Err_1 and Err_2 to an external CPU or the like in an open drain format, and the drain terminal of the transistor Q5 is connected to the external terminal P3. and the drain terminal of the transistor Q6 is connected to the external terminal P4.

Table 1 shows a truth table showing the relationship between the state of the output terminal OUT, the outputs OP_OUT1, OP_OUT2 and SC_OUT of the comparators CMP1 to CMP3, and the abnormality detection signals Err_1 and Err_2. The logic circuit 16 drives the transistors Q5 and Q6 so that when OP_OUT1, OP_OUT2 and SC_OUT having the relationship shown in Table 1 are input, the abnormality detection signals Err_1 and Err_2 having the relationship shown in Table 1 are output. The logic is configured to output a signal that It should be noted that the truth table of Table 1 is an example, and the present invention is not limited to this.

As can be seen from Table 1 above, in the regulator IC 10 of the present embodiment, either one of the antennas ANT1 and ANT2 connected to the output terminal OUT is disconnected, and both antennas ANT1 and ANT2 are in a one-channel open state. 2-channel open state in which the antennas ANT1 and ANT2 are disconnected from each other, and short-circuited state in which one of the antennas ANT1 and ANT2 is short-circuited are output separately by 2-bit error detection signals Err_1 and Err_2, and notified to the CPU, etc. can be done. Therefore, when an output terminal open abnormality detection circuit and an output terminal short abnormality detection circuit are provided, it is possible to distinguish and output abnormality detection results with a small number of external terminals.

Next, how to set the reference voltages Vop_1 and Vop_2 of the open-circuit abnormality detection comparators CMP1 and CMP2 in the regulator IC 10 of this embodiment that performs the above-described abnormality detection will be described.
When the two comparators CMP1 and CMP2 are used to detect the 1-channel open state and the 2-channel open state, if there is a large variation in the consumption current Icc flowing through the antennas ANT1 and ANT2 as loads, these abnormalities are distinguished. It is difficult to detect. Therefore, first, the variation range of the consumption current Icc for distinguishing and detecting the two open states is considered.

表２に示すように、アンテナが２個の場合（２ｃｈ）はアンテナが１個の場合（１ｃｈ）の２倍の消費電流が流れる。 Table 2 shows the variation in current consumption Icc for one antenna as ±a%, and the minimum value (Min) of current consumption for one antenna (1ch) and two antennas (2ch). The relationship between the median value (Typ) and the maximum value (Max) is shown.

As shown in Table 2, when there are two antennas (2ch), twice as much current is consumed as when there is one antenna (1ch).

Further, FIG. 2 shows the relationship between the current consumption of the 2ch antenna and the state of the output terminal when the variation a of the current consumption of each antenna is 33%. As can be seen from FIG. 2, the maximum current consumption (Icc+a%) for one antenna (1ch) is greater than the minimum value (Icc-a%)×2 for two antennas (2ch). If it is smaller, by setting the threshold value (Vop_1) to the voltage corresponding to the boundary between (Icc+a%) and (Icc-a%)×2, the output terminal is in a normal state and one of the antennas is disconnected. It is possible to distinguish and detect an abnormal state (1ch open).
Specifically, a current that is 1/N of the current flowing through the voltage control transistor Q1 flows through the current mirror transistor Q2 to which the external resistor Rop is connected in series. By setting it to N, it is possible to distinguish and detect the normal state of the output terminal and the 1ch open state.

Here, the above variation a is obtained by the following formula Icc(1+a/100)=Icc(1-a/100)×2
Solving for gives a=100/3≈33.3%. From this, in the case of 2ch antennas, if the variation in the consumption current Icc is within ±33.3%, the output terminal is normal and the abnormal state (1ch open) in which one of the antennas is disconnected is detected. know that it can be done.

Also, from FIG. 2, Vop_2 is set to a voltage corresponding to the current consumption (Icc-a%). Specifically, by setting Vop_2=Rop×(Icc−a%)/N, an abnormal state in which one antenna is disconnected (1ch open) and an abnormal state in which two antennas are disconnected (2ch open) can be distinguished and detected.
If the antenna used changes and the current consumption Icc of the antenna changes, by adjusting the resistance value of the external resistor Rop connected to the external terminal P1, the open state of the output terminal can be achieved by the same principle as above. can be detected.

Here, the above variation a≈33.3% is obtained when there are two loads (antennas) connected to the output terminal OUT, and when there are n antennas (nch), the following equation a= 100÷{n×(n+1)÷2}
can be generalized and represented by From this formula, the range of variation in current consumption that can distinguish an open error when there are three antennas (3ch) is within about ±16.6%, and an error when there are four antennas (4ch) can be distinguished. It can be seen that the variation range of the current consumption is within ±10%. Also, in that case, three and four comparators are required for detecting an open abnormality, respectively. It is preferable that the abnormality detection signal is composed of 3 bits or more and output.

Therefore, if the variation a of the current consumption satisfies the above condition, a plurality of arbitrary antennas having the same current consumption can be connected to the output terminal OUT of the regulator IC of the present embodiment, and current can flow. Therefore, it is possible to detect an open state caused by disconnection of one of the antennas or disconnection of the antenna while avoiding an increase in cost associated with providing a plurality of regulator ICs corresponding to the plurality of antennas. .

As described above, in the regulator IC 10 of this embodiment, two antennas can be connected to the output terminal OUT to allow current to flow. 2-channel open state in which both two antennas are disconnected, and short-circuit state in which one of the two antennas is short-circuited are distinguished by 2-bit error detection signals Err_1 and Err_2. It can be output and notified to the CPU or the like.

Therefore, the cost, the mounting area, and the power consumption of the IC can be reduced compared to the case where a regulator is provided for each antenna while maintaining the open-circuit abnormality and short-circuit abnormality detection functions. Therefore, when configuring a 4-channel terrestrial digital antenna compatible with a vehicle-mounted full-segment system, only two regulator ICs need to be provided. In addition, since three abnormal states can be determined by a 2-bit abnormality detection signal, the number of terminals provided in the regulator IC can be reduced, and a small and inexpensive package can be used to achieve cost reduction.

Instead of providing the comparators CMP1 and CMP2 for open-circuit abnormality detection in the regulator IC, an A/D converter is provided on the microcomputer side to supply the voltage of the external terminal P1 to which the resistor Rop is connected to the microcomputer. Although it is possible to detect an open abnormality on the side, by configuring to output 2-bit abnormality detection signals Err_1 and Err_2 as in the above embodiment, the I/O section of the microcomputer can detect an open abnormality. There is no need to provide an A/D converter and no need to set a threshold value for discrimination, which has the advantage of facilitating system design.

In addition, if the load connected to the output terminal is an antenna connected to a terrestrial digital TV broadcast tuner mounted on a vehicle, the antenna is relatively likely to come off due to the vibration of the vehicle body in the terrestrial digital broadcast tuner mounted on the vehicle. By supplying a current to the antenna from the power supply device using the semiconductor integrated circuit for power supply of the above embodiment, it is possible to distinguish between the open state of any of the plurality of antennas and the open state of all the loads.

(Modification)
In the regulator IC (FIG. 1) of the above embodiment, the 1-channel open state, 2-channel open state, and short-circuit state are detected and output separately by 2-bit abnormality detection signals Err_1 and Err_2. The short detection function (comparator CMP3) may be omitted. Further, when the short-circuit detection function is omitted, the logic circuit 16 may be omitted and the outputs of the comparators CMP1 and CMP2 for detecting open failure may be directly input to the gate terminals of the transistors Q5 and Q6. Alternatively, instead of the logic circuit 16, a simple circuit such as a delay circuit or a buffer may be provided to input to the gate terminals of Q5 and Q6.

If the short-circuit detection function is omitted, the output TSD_OUT of the thermal shutdown (TSD) circuit 15 is input to the logic circuit 16 to generate a signal that is logically combined with the outputs of the comparators CMP1 and CMP2 for open abnormality detection. and output as 2-bit abnormality detection signals Err_1 and Err_2. In this case, "short" in Table 1 should be read as "TSD operation".

Furthermore, in the regulator IC (FIG. 1) of the above-described embodiment, an example was described in which an antenna was connected as a load to the output terminal OUT and configured as a vehicle-mounted terrestrial digital power supply device, but the load is not limited to the antenna. It can also be applied to a power supply device to which two or more loads with the same current consumption are connected. Also, for example, when there are two loads, the difference between the minimum variation of the total current consumption when the two loads are normally connected and the current consumption when one is disconnected (including disconnection) If the condition that the maximum variation and , and , do not overlap, it can be used as a power supply device when two loads of different types, ie, different consumption currents, are connected to the output terminal OUT.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment. For example, in the above embodiment, MOS transistors are used as transistors forming the internal circuit of the regulator IC 10, but bipolar transistors may be used instead of MOS transistors.
Further, in the above-described embodiments, the case where the present invention is applied to a regulator IC has been described, but the present invention is not limited to a regulator IC, and can be applied to an IC that constitutes an isolated DC-DC converter. is also possible.

DESCRIPTION OF SYMBOLS 10... Regulator IC, 11... Error amplifier, 12... Reference voltage circuit, 13... Bias circuit, 14... Current limit circuit, 15... Thermal shutdown circuit, 16... Logic circuit, CMP1, CMP2... Open abnormality detection comparator, CMP3... Short circuit abnormality detection comparator, Q1: voltage control transistor (output transistor), Q2, Q3, Q4: current mirror transistor, Q5, Q6: abnormality detection signal output transistor, P3, P4: external terminal (detection result output terminal) )

Claims (7)

A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit for controlling the output transistor in accordance with an output feedback voltage. There is
An open abnormality detection circuit that detects an open state of the voltage output terminal, having a plurality of voltage comparison circuits that compare a voltage proportional to the voltage of the voltage output terminal and each voltage of a plurality of predetermined threshold voltages. and,
a plurality of detection result output terminals for outputting a detection result by the open abnormality detection circuit to the outside,
The plurality of stages of threshold voltages are set so that the open abnormality detection circuit can detect the open state of any one of the plurality of loads connected to the voltage output terminal and the open state of all the loads. A semiconductor integrated circuit for power supply, characterized by: the plurality of loads connected to the voltage output terminal are two antennas, the plurality of voltage comparison circuits are two;
The plurality of threshold voltages are set in two stages, and one of the two voltages is the maximum current consumption when there is one antenna and the minimum current consumption when there are two antennas. , and the other voltage of the two voltages is a voltage corresponding to the minimum current consumption when there is only one antenna. 3. The semiconductor integrated circuit for power supply according to . 3. The semiconductor integrated circuit for power supply according to claim 2, wherein the antenna has a variation of current consumption within ±33.3%. a first transistor forming a current mirror circuit with the output transistor;
a resistive element connected in series with the first transistor;
an external terminal to which the resistive element is connected as an external element,
4. The voltage comparison circuit according to claim 1, wherein said plurality of voltage comparison circuits compare the voltage current-voltage converted by said resistive element with each voltage of said plurality of stages of threshold voltages. power supply semiconductor integrated circuit. The plurality of detection result output terminals are two;
a second transistor forming a current mirror circuit with the output transistor;
a short-circuit abnormality detection circuit that detects a short-circuit state of the voltage output terminal based on the voltage of the resistive element connected in series with the second transistor;
The outputs of the two voltage comparison circuits and the output of the short circuit abnormality detection circuit are used as inputs to generate and output a 2-bit signal representing one of four states: 1-channel open, 2-channel open, short, and normal. a logic circuit;
5. The apparatus according to claim 1, wherein a 2-bit signal corresponding to a 2-bit output signal of said logic circuit is output from said plurality of detection result output terminals. Power supply semiconductor integrated circuit. 6. The semiconductor integrated circuit for power supply according to claim 1, wherein said load is an antenna connected to a terrestrial digital television broadcasting tuner mounted on a vehicle. A power supply regulator circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; and a control circuit for controlling the output transistor according to an output feedback voltage. hand,
An open abnormality detection circuit that detects an open state of the voltage output terminal, and has a plurality of voltage comparison circuits that compare a voltage proportional to the voltage of the voltage output terminal and each voltage of a plurality of predetermined threshold voltages. and,
A detection result by the open abnormality detection circuit can be output to the outside,
The plurality of stages of threshold voltages are set so that the open abnormality detection circuit can detect the open state of any one of the plurality of loads connected to the voltage output terminal and the open state of all the loads. A power supply regulator circuit, characterized in that:

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