JP2023019807A - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a nitride semiconductor device capable of suppressing occurrence of a breakdown voltage reduction phenomenon such as rapid flowing of current between a drain electrode and a source electrode.SOLUTION: A nitride semiconductor device includes a first nitride semiconductor layer constituting an electron transit layer, a second nitride semiconductor layer formed above the first nitride semiconductor layer, having a larger bandgap than the first nitride semiconductor layer, and constituting an electron supply layer, and a source electrode arranged above the first nitride semiconductor layer. The source electrode includes a main electrode in Ohmic contact with the second nitride semiconductor layer, and a sub-electrode which is electrically connected to the main electrode and at least a part of which is in contact with the first nitride semiconductor layer. A p-type region extending from a surface of the first nitride semiconductor layer in a downward direction and including a second p-type impurity is formed in a lower region of the sub-electrode in the first nitride semiconductor layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to a nitride semiconductor device made of a group III nitride semiconductor (hereinafter sometimes simply referred to as "nitride semiconductor") and a method for manufacturing the same.

A group III nitride semiconductor is a semiconductor in which nitrogen is used as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as _{AlxInyGa1 -x-yN} (0≤x≤1, 0≤y≤1, 0≤x+y≤1) _.
FIG. 3 of Patent Document 1 discloses a HEMT (High Electron Mobility Transistor) using a nitride semiconductor. The HEMT described in FIG. 3 of Patent Document 1 includes a silicon substrate, a buffer layer formed on the silicon substrate, an electron transit layer made of GaN formed on the buffer layer, and an electron transit layer formed on the electron transit layer. an electron supply layer made of AlGaN; a gate portion formed on the electron supply layer; and a drain electrode and a source electrode formed in contact with the electron supply layer. The gate portion includes a ridge-shaped p-type GaN layer formed on the electron supply layer and a gate electrode formed on the p-type GaN layer.

JP 2018-160668 A

In the HEMT described in FIG. 3 of Patent Document 1, when a high voltage is continuously applied between the drain and source electrodes when the transistor is turned off, a phenomenon occurs in which a current suddenly flows between the drain and source electrodes. Sometimes.
The reason for this is as follows. That is, when a high voltage is continuously applied between the drain and source electrodes while the transistor is off, electrons and holes are generated in the electron transit layer. Electrons are extracted by the drain electrode.

On the other hand, holes move to the vicinity of the source electrode in the electron transit layer. However, since the source electrode is in ohmic contact with the electron supply layer, there is a barrier against holes at the interface between the source electrode and the electron supply layer. Therefore, holes cannot move to the source electrode side and are accumulated in the electron transit layer. As holes are accumulated in the electron transit layer, the barrier against electrons at the interface between the source electrode and the electron supply layer is lowered, making it easier for electrons to move from the source electrode to the electron transit layer. As a result, a decrease in breakdown voltage occurs, such as a sudden current flow between the drain and source electrodes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device and a method of manufacturing the same that can suppress the occurrence of a breakdown voltage reduction phenomenon such as a sudden current flow between the drain and source electrodes.

An embodiment of the present disclosure includes a substrate, a first nitride semiconductor layer disposed on the substrate and constituting an electron transit layer, and the first nitride semiconductor layer formed above the first nitride semiconductor layer, a second nitride semiconductor layer having a bandgap larger than that of the semiconductor layer and forming an electron supply layer; three nitride semiconductor layers, a gate electrode formed on at least part of an upper surface of the third nitride semiconductor layer, a source electrode arranged above the first nitride semiconductor layer, and the third nitride and a drain electrode arranged to face the source electrode with a semiconductor layer interposed therebetween, the source electrode being electrically connected to a main electrode in ohmic contact with the second nitride semiconductor layer and the main electrode. and a sub-electrode at least partially in contact with the first nitride semiconductor layer, and a region below the sub-electrode in the first nitride semiconductor layer has a surface extending downward from the surface of the first nitride semiconductor layer. and a p-type region containing a second p-type impurity is provided.

With this configuration, it is possible to suppress the occurrence of a decrease in withstand voltage, such as a sudden current flow between the drain and source electrodes.
An embodiment of the present disclosure includes steps of forming a first nitride semiconductor layer constituting an electron transit layer on a substrate, and forming a p-type region extending downward from a portion of the surface of the first nitride semiconductor layer. forming, on the first nitride semiconductor layer, a second semiconductor layer material film which is a material film of the second nitride semiconductor layer constituting the electron supply layer, and a nitride semiconductor containing p-type impurities. forming a third semiconductor layer material film, which is a material film of a third nitride semiconductor layer, in that order; and forming a gate electrode film, which is a material film of a gate electrode, on the third semiconductor layer material film. and patterning the gate electrode film and the third semiconductor layer material film to form a ridge-shaped third nitride semiconductor layer and the third nitride semiconductor layer on the second semiconductor layer material film. forming a gate portion formed on a conductive layer and comprising a gate electrode; and selectively removing the second semiconductor layer material film so as to expose at least a portion of the surface of the p-type region, forming a second nitride semiconductor layer; forming a source sub-electrode on the first nitride semiconductor layer in contact with at least a portion of an exposed surface of the p-type region; forming a source-main electrode and a drain electrode in ohmic contact with the surface of the second nitride semiconductor layer and electrically connected to the source sub-electrode, on the nitride semiconductor layer. to provide a method of manufacturing

With this manufacturing method, a nitride semiconductor device can be obtained that can suppress the occurrence of a voltage drop phenomenon such as a sudden current flow between the drain and source electrodes.

FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a first embodiment of the invention. 2A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device of FIG. 1. FIG. FIG. 2B is a cross-sectional view showing the next step of FIG. 2A. FIG. 2C is a cross-sectional view showing the next step of FIG. 2B. FIG. 2D is a cross-sectional view showing the next step of FIG. 2C. FIG. 2E is a cross-sectional view showing the next step of FIG. 2D. FIG. 2F is a cross-sectional view showing the next step of FIG. 2E. FIG. 2G is a cross-sectional view showing the next step of FIG. 2F. FIG. 2H is a cross-sectional view showing the next step of FIG. 2G. FIG. 2I is a cross-sectional view showing the next step of FIG. 2H. FIG. 2J is a cross-sectional view showing the next step after FIG. 2I. FIG. 3 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to a second embodiment of the invention. FIG. 4 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a third embodiment of the invention. FIG. 5 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to a fourth embodiment of the invention. 6A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device of FIG. 5. FIG. FIG. 6B is a cross-sectional view showing the next step of FIG. 6A.

[Description of Embodiments of the Present Disclosure]
An embodiment of the present disclosure includes a substrate, a first nitride semiconductor layer disposed on the substrate and constituting an electron transit layer, and the first nitride semiconductor layer formed above the first nitride semiconductor layer, a second nitride semiconductor layer having a bandgap larger than that of the semiconductor layer and forming an electron supply layer; three nitride semiconductor layers, a gate electrode formed on at least part of an upper surface of the third nitride semiconductor layer, a source electrode arranged above the first nitride semiconductor layer, and the third nitride and a drain electrode arranged to face the source electrode with a semiconductor layer interposed therebetween, the source electrode being electrically connected to a main electrode in ohmic contact with the second nitride semiconductor layer and the main electrode. and a sub-electrode at least partially in contact with the first nitride semiconductor layer, and a region below the sub-electrode in the first nitride semiconductor layer has a surface extending downward from the surface of the first nitride semiconductor layer. and a p-type region containing a second p-type impurity is provided.

With this configuration, it is possible to suppress the occurrence of a decrease in withstand voltage, such as a sudden current flow between the drain and source electrodes.
In one embodiment of the present disclosure, the sub-electrode is made of a different material than the main electrode.
In one embodiment of the present disclosure, the sub-electrode is arranged separately from the main electrode.

In one embodiment of the present disclosure, the sub-electrode is in contact with the main electrode.
In one embodiment of the present disclosure, the sub-electrode is a laminated film of a Ni layer formed on the first nitride semiconductor layer and an Au layer laminated on the Ni layer, or the first nitride semiconductor It is composed of a laminated film of a V layer formed on a layer and an Au layer laminated on the V layer.
In one embodiment of the present disclosure, the sub-electrode is made of the same material as the main electrode.

In one embodiment of the present disclosure, the sub-electrode is formed integrally with the main electrode.
In one embodiment of the present disclosure, the main electrode is a laminated film of a Ti layer formed on the second nitride semiconductor layer and an Al layer laminated on the Ti layer, or the second nitride A laminated film comprising a Ti layer formed on a semiconductor layer, an Al layer formed on the Ti layer, a Ni layer formed on the Al layer, and an Au layer formed on the Ni layer. .

In one embodiment of the present disclosure, the first nitride semiconductor layer includes a high resistance nitride semiconductor layer disposed on the substrate and a conductive nitride semiconductor layer formed on the high resistance nitride semiconductor layer. and the p-type region extends from the surface of the conductive nitride semiconductor layer through the conductive nitride semiconductor layer and into the interior of the high resistance nitride semiconductor layer.
In an embodiment of the present disclosure, when the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is d ₂ <t<(d ₁ +d ₂ ).

In an embodiment of the present disclosure, when the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is { (d ₁ /4)+d ₂ }<t<{(3· _d 1/4)+d ₂ }.
In an embodiment of the present disclosure, when the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is t = {( _d1 /2)+ _d2 }.

In one embodiment of the present disclosure, in a surface layer portion of the p-type region, a second impurity having a concentration of the second p-type impurity higher than a concentration of the second p-type impurity below the surface portion of the p-type region is provided. A density region is formed.
In one embodiment of the present disclosure, the concentration of the second p-type impurity in the second high concentration region is 1×10 ¹⁷ cm ³ to 1×10 ²¹ cm ³ , and the second high concentration in the p-type region. The concentration of the second p-type impurity in the region other than the region is 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ .

In one embodiment of the present disclosure, the surface layer portion of the third nitride semiconductor layer has a concentration of the first p-type impurity higher than the concentration of the first p-type impurity below the surface layer portion of the third nitride semiconductor layer. A first high-concentration region having a high concentration is formed.
In one embodiment of the present disclosure, the concentration of the first p-type impurity in the first high-concentration region is 1×10 ¹⁷ cm ³ to 1×10 ²¹ cm ³ , and the third The concentration of the first p-type impurity in the regions other than the first high-concentration region is 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ .

In one embodiment of the present disclosure, the gate electrode is a laminated film of a Ni layer formed on the third nitride semiconductor layer and an Au layer laminated on the Ni layer, or the third nitride It is composed of a laminated film of a V layer formed on a semiconductor layer and an Au layer laminated on the V layer.
In one embodiment of the present disclosure, a buffer layer made of a nitride semiconductor is included between the semiconductor substrate and the semi-insulating nitride layer.

In one embodiment of the present disclosure, the drain electrode is in ohmic contact with the second nitride semiconductor layer.
An embodiment of the present disclosure includes steps of forming a first nitride semiconductor layer constituting an electron transit layer on a substrate, and forming a p-type region extending downward from a portion of the surface of the first nitride semiconductor layer. forming, on the first nitride semiconductor layer, a second semiconductor layer material film which is a material film of the second nitride semiconductor layer constituting the electron supply layer, and a nitride semiconductor containing p-type impurities. forming a third semiconductor layer material film, which is a material film of a third nitride semiconductor layer, in that order; and forming a gate electrode film, which is a material film of a gate electrode, on the third semiconductor layer material film. and patterning the gate electrode film and the third semiconductor layer material film to form a ridge-shaped third nitride semiconductor layer and the third nitride semiconductor layer on the second semiconductor layer material film. forming a gate portion formed on a conductive layer and comprising a gate electrode; and selectively removing the second semiconductor layer material film so as to expose at least a portion of the surface of the p-type region, forming a second nitride semiconductor layer; forming a source sub-electrode on the first nitride semiconductor layer in contact with at least a portion of an exposed surface of the p-type region; forming a source-main electrode and a drain electrode in ohmic contact with the surface of the second nitride semiconductor layer and electrically connected to the source sub-electrode, on the nitride semiconductor layer. to provide a method of manufacturing

With this manufacturing method, a nitride semiconductor device can be obtained that can suppress the occurrence of a voltage drop phenomenon such as a sudden current flow between the drain and source electrodes.
[Detailed Description of Embodiments of the Present Disclosure]
BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a first embodiment of the invention.

A nitride semiconductor device 1 includes a substrate 2, a buffer layer 3 formed on the surface (upper surface) of the substrate 2, a first nitride semiconductor layer 4 epitaxially grown on the buffer layer 3, and a first nitride semiconductor layer. 4 and a second nitride semiconductor layer 5 epitaxially grown thereon. Further, nitride semiconductor device 1 includes a gate portion 20 formed on second nitride semiconductor layer 5 .
Further, nitride semiconductor device 1 includes source electrode 8 in contact with first nitride semiconductor layer 4 and second nitride semiconductor layer 5 and drain electrode 9 in contact with second nitride semiconductor layer 5 . The source electrode 8 and the drain electrode 9 are opposed to each other with the gate portion 20 interposed therebetween. Further, nitride semiconductor device 1 includes a substrate electrode 10 formed on the rear surface (lower surface) of substrate 2 .

The substrate 2 may be, for example, a low resistance silicon substrate. The low resistance silicon substrate may be, for example, a p-type silicon substrate having an electrical resistivity of 0.001Ωmm to 0.5Ωmm. Further, the substrate 2 may be a low-resistance SiC substrate, a low-resistance GaN substrate, or the like, in addition to the low-resistance silicon substrate. The thickness of the substrate 2 is, for example, about 650 .mu.m during the semiconductor process, and is ground to about 350 .mu.m or less at the stage prior to chipping.

The buffer layer 3 is a buffer layer for relaxing strain caused by a difference between the lattice constant of the first nitride semiconductor layer 4 formed on the buffer layer 3 and the lattice constant of the substrate 2 . In this embodiment, the buffer layer 3 is composed of a multi-layered buffer layer in which a plurality of nitride semiconductor films are laminated. In this embodiment, the buffer layer 3 includes a first buffer layer 31 made of an AlN film in contact with the surface of the substrate 2 and AlGaN laminated on the surface of the first buffer layer 31 (the surface opposite to the substrate 2). and a second buffer layer 32 consisting of layers. The film thickness of the first buffer layer 31 is approximately 100 nm to 500 nm. The film thickness of the second buffer layer 32 is approximately 500 nm to 2000 nm. The buffer layer 3 may be composed of, for example, an AlGaN single film, an AlGaN/GaN superlattice film, an AlN/AlGaN superlattice film, a film having an AlN/GaN superlattice structure, or the like.

The first nitride semiconductor layer 4 constitutes an electron transit layer. In this embodiment, the first nitride semiconductor layer 4 is formed on the high resistance nitride semiconductor layer (semi-insulating nitride layer) 41 formed on the buffer layer 3 and on the high resistance nitride semiconductor layer 41. and a conductive nitride semiconductor layer 42 .
The high resistance nitride semiconductor layer 41 is provided to suppress leakage current. The high resistance nitride semiconductor layer 41 is composed of an impurity-doped GaN layer (high resistance GaN layer) and has a thickness of about 1 μm to 2 μm. In this embodiment, the thickness of the high resistance nitride semiconductor layer 41 is approximately 1.5 μm. Impurities are, for example, C (carbon). The impurity concentration is preferably 4×10 ¹⁶ cm ⁻³ or higher. The impurity may be Fe (iron).

In this embodiment, the conductive nitride semiconductor layer 42 is made of a GaN layer (conductive GaN layer) and has a thickness of about 0.2 μm to 1 μm. In this embodiment, the thickness of the conductive nitride semiconductor layer 42 is approximately 0.5 μm. The thickness of the first nitride semiconductor layer 4 is about 0.5 μm to 2 μm.
In this embodiment, the second nitride semiconductor layer 5 is formed in a region of the upper surface of the first nitride semiconductor layer 4 excluding one side (the left side in FIG. 1). Therefore, a stepped portion is formed between the top surface of one side portion of the second nitride semiconductor layer 5 (the left side in FIG. 1) and the one side portion of the top surface of the first nitride semiconductor layer 4 . there is

The second nitride semiconductor layer 5 constitutes an electron supply layer. The second nitride semiconductor layer 5 is made of a nitride semiconductor having a bandgap larger than that of the first nitride semiconductor layer 4 . Specifically, the second nitride semiconductor layer 5 is made of a nitride semiconductor having a higher Al composition than the first nitride semiconductor layer 4 . In nitride semiconductors, the higher the Al composition, the larger the bad gap. In this embodiment, the second nitride semiconductor layer 5 consists of an Al _x Ga _1-x N layer (0.1<x≦0.3). The Al composition of the second nitride semiconductor layer 5 is preferably 20% or more and 30% or less, more preferably 24% or more and 25% or less. That is, x is preferably 0.2 to 0.3, more preferably 0.24 to 0.25. The thickness of the second nitride semiconductor layer 5 is preferably 5 nm to 15 nm.

As described above, the first nitride semiconductor layer (electron transit layer) 4 and the second nitride semiconductor layer (electron supply layer) 5 are made of nitride semiconductors having different band gaps (Al composition). has lattice mismatch. Spontaneous polarization of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 and piezoelectric polarization caused by lattice mismatch between them cause the first nitride semiconductor layer 4 and the second nitride semiconductor The energy level of the conduction band of first nitride semiconductor layer 4 at the interface with layer 5 is lower than the Fermi level. As a result, in the first nitride semiconductor layer 4, two-dimensional electrons are formed at a position close to the interface between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 (for example, at a distance of several angstroms from the interface). A gas (2DEG) 12 is spreading.

The gate portion 20 includes a ridge-shaped third nitride semiconductor layer 6 selectively formed on the second nitride semiconductor layer 5 and a gate electrode 7 formed on the third nitride semiconductor layer 6 .
The cross-sectional shape of the third nitride semiconductor layer 6 is rectangular. The third nitride semiconductor layer 6 is made of a nitride semiconductor doped with p-type impurities (acceptor-type impurities). More specifically, the third nitride semiconductor layer 6 is composed of an Al _y Ga _1-y N (0≦y<1, y<x) layer doped with a p-type impurity.

In this embodiment, the third nitride semiconductor layer 6 is composed of a GaN layer doped with p-type impurities (p-type GaN layer). In this embodiment, the p-type impurity is Zn (zinc). The p-type impurity may be a p-type impurity other than Zn, such as Mo (molybdenum). The film thickness of the third nitride semiconductor layer 6 is preferably 50 nm or more and 100 nm or less.
A high-concentration region 6 a having a high p-type impurity concentration is formed in the surface layer portion of the third nitride semiconductor layer 6 . The p-type impurity concentration in the region other than the high-concentration region 6a in the third nitride semiconductor layer 6 is preferably 1×10 ¹⁶ cm ³ or more and 1×10 ²⁰ cm ^{3 or} less. The p-type impurity concentration of the high-concentration region 6a is preferably 1×10 ¹⁷ cm ³ or more and 1×10 ²¹ cm ^{3 or} less.

The third nitride semiconductor layer 6 is formed at the interface formed between the first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer) in the region immediately below the gate portion 20 . It is provided to change the conduction band so that the two-dimensional electron gas 12 is not generated in the region immediately below the gate section 20 when no gate voltage is applied.
The cross section of gate electrode 7 is rectangular. In this embodiment, the gate electrode 7 is in Schottky contact with the top surface of the third nitride semiconductor layer 6 . The gate electrode 7 is preferably made of a material having a low hole barrier at the interface between the gate electrode 7 and the third nitride semiconductor layer 6 . In this embodiment, the gate electrode 7 is composed of a laminated film (Ni/Au laminated film) of a Ni layer formed on the third nitride semiconductor layer 6 and an Au layer laminated on the Ni layer. The gate electrode 7 may be composed of a laminated film (V/Au laminated film) of a V (vanadium) layer formed on the third nitride semiconductor layer 6 and an Au layer laminated on the V layer. . The Ni/Au laminated film and the V/Au laminated film are examples of materials having a low hole barrier at the interface between the gate electrode 7 and the third nitride semiconductor layer 6 . The film thickness of the gate electrode 7 is preferably 50 nm or more and 150 nm or less.

The source electrode 8 includes a main electrode (source main electrode) 8A and a sub-electrode (source sub-electrode) 8B. In this embodiment, the sub-electrode 8B is formed separately from the main electrode 8A. In this embodiment, the sub-electrode 8B is spaced apart from the main electrode 8A. In this embodiment, the sub-electrode 8B is electrically connected to the main electrode 8A by wiring 15. As shown in FIG.

In this embodiment, the main electrode 8A is formed so as to cover the upper and side surfaces of one side portion of the second nitride semiconductor layer 5 and the corner connecting them. Therefore, the main electrode 8A is in contact with the top surface and the side surface of one side of the second nitride semiconductor layer 5 and the corner connecting them, and is also in contact with the top surface of the first nitride semiconductor layer 4. . The main electrode 8A is composed of a laminated film (Ti/Al laminated film) of a lower Ti layer and an upper Al layer laminated on the Ti layer. The main electrode 8A is formed on the lowermost Ti layer, the first intermediate layer Al layer laminated on the Ti layer, the second intermediate layer Ni layer formed on the Al layer, and the Ni layer. It may also be composed of a laminated film (Ti/Al/Ni/Au laminated film) with an uppermost Au layer. The main electrode 8A is in ohmic contact with the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 . The film thickness of the main electrode 8A is approximately 100 nm to 500 nm.

In this embodiment, the sub-electrode 8B is arranged on one side of the main electrode 8A and spaced apart from the main electrode 8A. Sub-electrode 8B is formed on one side of the upper surface of first nitride semiconductor layer 4 . Therefore, sub-electrode 8B is in contact with the upper surface of first nitride semiconductor layer 4 .
As will be described later, a p-type region 16 is formed below the sub-electrode 8B in the first nitride semiconductor layer 4 . Sub-electrode 8B is preferably made of a material having a low hole barrier at the interface between sub-electrode 8B and p-type region 16 . In this embodiment, the sub-electrode 8B is made of, for example, a laminated film (Ni/Au laminated film) of a Ni layer formed on the first nitride semiconductor layer 4 and an Au layer laminated on the Ni layer. . The sub-electrode 8B may be composed of a laminated film (V/Au laminated film) of a V layer formed on the first nitride semiconductor layer 4 and an Au layer laminated on the V layer. The Ni/Au laminated film and the V/Au laminated film are examples of materials having a low hole barrier at the interface between the sub-electrode 8B and the p-type region 16 . The film thickness of the sub-electrode 8B is about 50 nm to 150 nm.

The drain electrode 9 is composed of a laminated film (Ti/Al laminated film) of a Ti layer formed on the second nitride semiconductor layer 5 and an Al layer laminated on the Ti layer. The drain electrode 9 includes a Ti layer formed on the second nitride semiconductor layer 5, an Al layer laminated on the Ti layer, a Ni layer formed on the Al layer, and an Au layer formed on the Ni layer. It may be composed of a layered film (Ti/Al/Ni/Au layered film). The drain electrode 9 is in ohmic contact with the second nitride semiconductor layer 5 . The film thickness of the drain electrode 9 is about 100 nm to 500 nm.

The substrate electrode 10 is composed of a laminated film (Ti/Al laminated film) of a Ti layer formed on the back surface of the substrate 2 and an Al layer laminated on the Ti layer. The substrate electrode 10 is a laminate of a Ti layer formed on the back surface of the substrate 2, an Al layer laminated on the Ti layer, a Ni layer formed on the Al layer, and an Au layer formed on the Ni layer. It may be composed of a film (Ti/Al/Ni/Au laminated film). The film thickness of the substrate electrode 10 is about 100 nm to 500 nm. A substrate electrode 10 is electrically connected to the source electrode 8 .

A p-type region 16 is formed in a region of the first nitride semiconductor layer 4 below the sub-electrode 8B. In this embodiment, the p-type region 16 extends from the surface of the conductive nitride semiconductor layer 42 through the conductive nitride semiconductor layer 42 and into the high resistance nitride semiconductor layer 41 . A high-concentration region 16 a having a high p-type impurity concentration is formed in the surface layer portion of the p-type region 16 .
The p-type impurity of the p-type region 16 is, for example, Zn (zinc). The p-type impurity of p-type region 16 may be Mo (molybdenum). The p-type impurity concentration in the p-type region 16 other than the high-concentration region 16a is preferably 1×10 ¹⁶ cm ³ or more and 1×10 ²⁰ cm ^{3 or} less. The p-type impurity concentration of the high-concentration region 16a is preferably 1×10 ¹⁷ cm ³ or more and 1×10 ²¹ cm ^{3 or} less.

Assuming that the thickness of the high resistance nitride semiconductor layer 41 is _d1 and the thickness of the conductive nitride semiconductor layer 42 is _d2 , the depth t of the p-type region 16 is _d2 <t<( _d1 +d ₂ ) is preferred. More specifically, the depth t of the p-type region 16 is more preferably {(d ₁ /4)+d ₂ }<t<{(3·d _1/4 )+d ₂ }, where t= More preferably {(d ₁ /2)+d ₂ }.

In this nitride semiconductor device 1, a second nitride semiconductor layer 5 (electron supply layer) having a different bandgap (Al composition) is formed on a first nitride semiconductor layer 4 (electron transit layer) to form a heterojunction. It is As a result, the two-dimensional electron gas 12 is formed in the first nitride semiconductor layer 4 near the interface between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5, and the two-dimensional electron gas 12 is used as a channel. A utilized HEMT (transistor) is formed. The gate electrode 7 faces the second nitride semiconductor layer 5 with the third nitride semiconductor layer 6 interposed therebetween.

Below gate electrode 7 , the energy levels of first nitride semiconductor layer 4 and second nitride semiconductor layer 5 are raised by acceptors contained in third nitride semiconductor layer 6 made of p-type GaN. Therefore, the energy level of the conduction band at the heterojunction interface between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 is higher than the Fermi level. Therefore, immediately below the gate electrode 7 (gate portion 20), the two-dimensional electron gas 12 is generated due to the spontaneous polarization of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 and the piezoelectric polarization due to their lattice mismatch. not formed.

Therefore, when no bias is applied to the gate electrode 7 (at zero bias), the channel formed by the two-dimensional electron gas 12 is cut off immediately below the gate electrode 7 . Thus, a normally-off HEMT is realized. When an appropriate on-voltage (for example, 5 V) is applied to the gate electrode 7, a channel is induced in the first nitride semiconductor layer 4 immediately below the gate electrode 7, and the two-dimensional electron gas 12 on both sides of the gate electrode 7 is connected. be. This allows conduction between the source and the drain.

During use, for example, a predetermined voltage (eg, 50 V to 100 V) is applied between the source electrode 8 and the drain electrode 9 such that the drain electrode 9 side is positive. In this state, an off voltage (0 V) or an on voltage (5 V) is applied to the gate electrode 7 with the source electrode 8 as a reference potential (0 V).
2A to 2J are cross-sectional views for explaining an example of the manufacturing method of nitride semiconductor device 1 described above, showing cross-sectional structures at a plurality of stages in the manufacturing method.

First, as shown in FIG. 2A, a first buffer layer 31, a second buffer layer 3, a high resistance nitride semiconductor layer 41 and a conductive nitride semiconductor are formed on a substrate 2 by MOCVD (Metal Organic Chemical Vapor Deposition). Layer 42 is epitaxially grown. Thereby, the buffer layer 3 composed of the first buffer layer 31 and the second buffer layer 32 is formed on the substrate 2 . A first nitride semiconductor layer (electron transit layer) 4 composed of a high resistance nitride semiconductor layer 41 and a conductive nitride semiconductor layer 42 is formed on the buffer layer 3 .

Next, as shown in FIG. 2B, a p-type impurity is implanted into the first nitride semiconductor layer 4 from the formation region of the p-type region 16 on the surface of the first nitride semiconductor layer 4 by ion implantation, for example. be. Then, an activation annealing process is performed. Thereby, the p-type region 16 extending from the surface of the conductive nitride semiconductor layer 42 to the inside of the high resistance nitride semiconductor layer 41 is formed. However, at this time, the high-concentration region 16a is not formed in the surface layer of the p-type region 16. Next, as shown in FIG.

Next, as shown in FIG. 2C, a second semiconductor layer material film 105, which is a material film of the second nitride semiconductor layer (electron supply layer) 5, and a second semiconductor layer material film 105 are formed on the first nitride semiconductor layer 4 by MOCVD. A third semiconductor layer material film 106, which is a material film of the trinitride semiconductor layer 6, is epitaxially grown.
Next, as shown in FIG. 2D, a p-type impurity (for example, Zn) is diffused into a region including a region where the high-concentration region 6a is to be formed in the surface layer portion of the third semiconductor layer material film 106 by laser doping. be. As a result, a high-concentration region 106 a is formed in part of the surface layer of the third semiconductor layer material film 106 .

Next, as shown in FIG. 2E, a gate electrode film 107, which is a material film of the gate electrode 7, is formed on the entire surface of the third semiconductor layer material film 106 by sputtering.
Next, as shown in FIG. 2F, the gate electrode film 107 and the third semiconductor layer material film 106 are patterned by photolithography and dry etching. Etching of the gate electrode film 107 uses, for example, an oxygen-free etching gas (Cl ₂ /BCl ₃ , BCl ₃ , CF ₄ , Cl ₂ /SiCl _{4 ,} etc.). An etching gas containing chlorine and oxygen (Cl ₂ /O ₂ /N ₂ , Cl ₂ /O ₂ /Ar, etc.) is used for etching the third semiconductor layer material film 106 .

Thereby, the ridge-shaped third nitride semiconductor layer 6 having the high-concentration region 6a in the surface layer portion and the gate electrode 7 formed on the third nitride semiconductor layer 6 are obtained. Thereby, the gate portion 20 composed of the third nitride semiconductor layer 6 and the gate electrode 7 is obtained.
Next, as shown in FIG. 2G, the second semiconductor layer material film 105 is patterned by photolithography and dry etching. For etching the second semiconductor layer material film 105, for example, an etching gas containing chlorine and not containing oxygen ( _Cl2 / _BCl3 , _BCl3 , _CF4 , _Cl2 / _SiCl4, etc.) is used. Thereby, the second nitride semiconductor layer 5 is obtained.

Next, as shown in FIG. 2H, p-type impurities (for example, Zn) are diffused into the surface layer of the p-type region 16 by photolithography and laser doping. As a result, a high-concentration region 16 a is formed in the surface layer of the p-type region 16 .
Next, as shown in FIG. 2I, a sub-electrode 8B of the source electrode 8 is formed on the p-type region 16 by photolithography and sputtering. In this embodiment, the sub-electrode 8B is made of, for example, a Ni/Au laminated film or a V/Au laminated film.

Next, as shown in FIG. 2J, the main electrode 8A of the source electrode 8 and the drain electrode 9 are formed on the second nitride semiconductor layer 5 by photolithography and sputtering. The main electrode 8A and the drain electrode 9 are made of, for example, a Ti/Al laminated film or a Ti/Al/Ni/Au laminated film.
Finally, a substrate electrode 10 is formed on the back surface of the substrate 2 by sputtering. Thereby, nitride semiconductor device 1 as shown in FIG. 1 is obtained. The substrate electrode 10 is made of, for example, a Ti/Al laminated film or a Ti/Al/Ni/Au laminated film.

When a high voltage is continuously applied between the drain electrode 9 and the source electrode 8 while the transistor is off, electrons and holes are generated in the first nitride semiconductor layer (electron transit layer) 4 . Electrons generated in the first nitride semiconductor layer 4 are taken out by the drain electrode 9 .
On the other hand, holes generated in the first nitride semiconductor layer 4 move to the vicinity of the source electrode 8 in the first nitride semiconductor layer 4 . As in the nitride semiconductor device shown in FIG. 3 of Patent Document 1, when the source electrode is composed only of the source electrode in ohmic contact with the electron supply layer, the source electrode is in ohmic contact with the electron supply layer. Since they are in contact, there is a barrier to holes at the interface between the source electrode and the electron supply layer. Therefore, holes cannot move to the source electrode side and are accumulated in the electron transit layer.

Even when the source electrode is in ohmic contact with the electron transit layer, a hole barrier exists at the interface between the source electrode and the electron transit layer. Therefore, holes cannot move to the source electrode side and are accumulated in the electron transit layer.
As holes accumulate in the electron transit layer, the barrier against electrons at the interface between the source electrode, the electron supply layer, and the electron transit layer is lowered, making it easier for electrons to move from the source electrode to the electron transit layer. As a result, a breakdown voltage drop phenomenon occurs such that a current suddenly flows between the drain and source electrodes.

In the first embodiment described above, the source electrode 8 includes the main electrode 8A in ohmic contact with the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5, and the main electrode in contact with the first nitride semiconductor layer 4 and in ohmic contact with the second nitride semiconductor layer 5. and a sub-electrode 8B electrically connected to 8A. A p-type region 16 is formed in the first nitride semiconductor layer 4 directly below the sub-electrode 8B.
There is no barrier against holes at the interface between first nitride semiconductor layer 4 and p-type region 16 . As a result, holes are extracted from the first nitride semiconductor layer 4 through the p-type region 16 by the sub-electrode 8B. Thereby, accumulation of holes in the first nitride semiconductor layer 4 can be suppressed. As a result, it is possible to suppress the occurrence of a breakdown voltage reduction phenomenon in which a current suddenly flows between the drain and source electrodes when the transistor is turned off.

Furthermore, in the above-described first embodiment, the sub-electrode 8B is made of a material (Ni/Au laminated film, V/Au laminated film, etc.) having a low hole barrier at the interface between the sub-electrode 8B and the p-type region 16. used. This makes it easier for holes to be taken out by the sub-electrode 8B, so that it is possible to effectively suppress the occurrence of the breakdown voltage reduction phenomenon when the transistor is turned off.
Furthermore, in the above-described first embodiment, the high-concentration region 16 a having a high p-type impurity concentration is formed in the surface layer portion of the p-type region 16 . As a result, the contact resistance between the p-type region 16 and the sub-electrode 8B is reduced, and holes are more likely to move from the p-type region 16 to the sub-electrode 8B. can be suppressed more effectively.

By the way, holes generated in the first nitride semiconductor layer 4 may accumulate in the third nitride semiconductor layer 6 via the second nitride semiconductor layer (electron supply layer) 5 . In the first embodiment described above, the gate electrode 7 is made of a material (Ni/Au laminated film, V/Au laminated film, etc.) is used. As a result, the holes accumulated in the third nitride semiconductor layer 6 are taken out by the gate electrode 7 when the transistor is turned off, so that the breakdown voltage reduction phenomenon when the transistor is turned off can be further suppressed.

Furthermore, in the first embodiment described above, the high-concentration region 6 a having a high p-type impurity concentration is formed in the surface layer portion of the third nitride semiconductor layer 6 . As a result, the contact resistance between the third nitride semiconductor layer 6 and the gate electrode 7 is reduced, and holes are easily moved from the third nitride semiconductor layer 6 to the gate electrode 7. The occurrence of the breakdown voltage reduction phenomenon can be suppressed more effectively.

FIG. 3 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to a second embodiment of the invention. In FIG. 3, the same reference numerals as in FIG. 1 denote the parts corresponding to the parts in FIG. 1 described above.
In the nitride semiconductor device 1A according to the second embodiment, the main electrode 8A is formed so as to straddle one side portion of the second nitride semiconductor layer 5 and the sub-electrode 8B. The main electrode 8A is formed on the upper surface and side surface of one side portion of the second nitride semiconductor layer 5, the upper surface of the first nitride semiconductor layer 4, the upper surface of the sub-electrode 8B, and the side surface of the sub-electrode 8B on the gate portion 20 side. in contact. Other configurations are the same as those of the nitride semiconductor device 1 according to the first embodiment.

In the nitride semiconductor device 1A according to the second embodiment, since the main electrode 8A is in contact with the sub-electrode 8B, it is not necessary to connect the sub-electrode 8B to the main electrode 8A by wiring.
When manufacturing the nitride semiconductor device 1A according to the second embodiment, the main electrode 8A is formed so as to straddle one side portion of the second nitride semiconductor layer 5 and the sub-electrode 8B in the step of FIG. 2J described above. should be formed. In other words, one side portion of the second nitride semiconductor layer 5, the upper surface of the sub-electrode 8B and the side surface on the side of the gate portion 20, and the second nitride semiconductor layer 5 and the sub-electrode on the upper surface of the first nitride semiconductor layer 4 The main electrode 8A may be formed so as to cover the portion between and 8B.

Also in the second embodiment, the same effects as in the first embodiment are obtained.
FIG. 4 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a third embodiment of the invention. In FIG. 4, the same reference numerals as in FIG. 1 denote the parts corresponding to the parts in FIG. 1 described above.
In the nitride semiconductor device 1B according to the third embodiment, the sub-electrode 8B is made of the same material as the main electrode 8A and is formed integrally with the main electrode 8A. That is, the source electrode 8 includes one side portion of the second nitride semiconductor layer 5, the main electrode 8A covering the vicinity of one side of the second nitride semiconductor layer 5 on the upper surface of the first nitride semiconductor layer 4, and the main electrode 8A. Sub-electrode 8B extends outward from one side of 8A and covers one side of the surface of first nitride semiconductor layer 4 (including the surface of p-type region 16). Sub-electrode 8B is in contact with the surface of p-type region 16 . Other configurations are the same as those of the nitride semiconductor device 1 according to the first embodiment.

In the nitride semiconductor device 1B according to the third embodiment, since the main electrode 8A is in contact with the sub-electrode 8B, it is not necessary to connect the sub-electrode 8B to the main electrode 8A by wiring.
When manufacturing the nitride semiconductor device 1B according to the third embodiment, the step of FIG. 2I described above is omitted, and in the step of FIG. The source electrode 8 may be formed so as to cover the exposed upper surface of the nitride semiconductor layer 5 .

In the third embodiment, the sub-electrode 8B is made of the same material as the main electrode 8A and is formed integrally with the main electrode 8A. , substantially the same as the first embodiment, it is possible to suppress the occurrence of the breakdown voltage reduction phenomenon when the transistor is turned off.
FIG. 5 is a cross-sectional view for explaining a nitride semiconductor device according to a fourth embodiment of the invention. A nitride semiconductor device 1C according to the fourth embodiment is similar to the nitride semiconductor device 1B according to the third embodiment. In FIG. 5, the same reference numerals as in FIG. 4 denote the parts corresponding to the parts in FIG. 4 described above.

A nitride semiconductor device 1C according to the fourth embodiment differs from the nitride semiconductor device 1B according to the third embodiment in that a passivation film 50 is provided. The passivation film 50 covers the exposed surface of the first nitride semiconductor layer 4 (excluding a region facing a second source contact hole 52 described later) and the exposed surface of the second nitride semiconductor layer 5 (first source contact hole 52 described later). It covers the exposed surface of the gate portion 20 (excluding the regions facing the hole 51 and the drain contact hole 53).

As a result, the side surfaces of the third nitride semiconductor layer 6 and the side surfaces and surfaces of the gate electrode 7 are covered with the passivation film 50 . The film thickness of the passivation film 50 is approximately 50 nm to 200 nm. In this embodiment, the passivation film 50 consists of a SiN film. The passivation film 50 may be composed of a single film of any one of SiN film, _SiO2 film, SiON film, and AlN film, or a composite film of any combination of two or more thereof.

A first source contact hole 51 , a second source contact hole 52 and a drain contact hole 53 are formed in the passivation film 50 . The first and second source contact holes 51 and 52 and the drain contact hole 53 are arranged with the gate portion 20 interposed therebetween. Specifically, the first and second source contact holes 51 and 52 are arranged on one side (the left side in FIG. 5) of the gate section 20, and the drain contact hole 53 is arranged on the other side of the gate section 20 (the left side in FIG. 5). 5). The second source contact hole 52 is arranged on one side (left side in FIG. 5) with respect to the first source contact hole 51 .

Source electrode 8 is formed on passivation film 50 so as to cover first source contact hole 51 and second source contact hole 52 . The source electrode 8 includes a main electrode 8A including a portion in ohmic contact with the surface of the second nitride semiconductor layer 5 through a first source contact hole 51, and a p-type region 16 through a second source contact hole 52. and a sub-electrode 8B including a portion in contact with the surface of the . The main electrode 8A and the sub-electrode 8B are integrally formed.

A drain electrode 9 is formed on the passivation film 50 so as to cover the drain contact hole 53 . A portion of the drain electrode 9 is in ohmic contact with the surface of the second nitride semiconductor layer 5 through the drain contact hole 53 .
To manufacture the nitride semiconductor device 1C according to the fourth embodiment, first, steps similar to those shown in FIGS. 2A to 2H are performed. Next, as shown in FIG. 6A, a passivation film 50 is formed over the entire surface by plasma CVD or sputtering, for example.

Next, as shown in FIG. 6B, a first source contact hole 51, a second source contact hole 52 and a drain contact hole 53 are formed in the passivation film 50 by photolithography and etching.
After that, the source electrode 8 is formed to cover the first source contact hole 51 and the second source contact hole 52, and the drain electrode 9 is formed to cover the drain contact hole 53, thereby forming the structure shown in FIG. A nitride semiconductor device 1C as shown is obtained.

Also in the fourth embodiment, the same effects as in the third embodiment are obtained.
Although the first to fourth embodiments of the present disclosure have been described above, the present invention can also be implemented in other embodiments. For example, in the above-described first and second embodiments, the sub-electrode 8B is made of, for example, a Ni/Au laminated film or It is composed of a V/Au laminated film. However, the sub-electrode 8B may be composed of a Ti film, a TiN film, or the like.

In the first to fourth embodiments described above, the high-concentration region 16a having a high p-type impurity concentration is formed in the surface layer portion of the p-type region 16, but the high-concentration region 16a is formed in the surface layer portion of the p-type region 16. It does not have to be.
In the first to fourth embodiments described above, from the viewpoint of lowering the barrier against holes at the interface between the gate electrode 7 and the third nitride semiconductor layer 6, the gate electrode 7 is made of, for example, a Ni/Au laminated film. Alternatively, it is composed of a V/Au laminated film. However, the gate electrode 7 may be composed of a Ti film, a TiN film, or the like.

In the first to fourth embodiments described above, the high-concentration region 6a having a high p-type impurity concentration is formed in the surface layer portion of the third nitride semiconductor layer 6. The high-concentration region 6a may not be formed.
Although the embodiments of the present disclosure have been described in detail, these are only specific examples used to clarify the technical content of the present disclosure, and the present disclosure is interpreted as being limited to these specific examples. should not, the scope of the present disclosure is limited only by the appended claims.

Reference Signs List 1, 1A, 1B, 1C nitride semiconductor device 2 substrate 3 buffer layer 4 first nitride semiconductor layer 5 second nitride semiconductor layer 6 third nitride semiconductor layer 6a high concentration region 7 gate electrode 8 source electrode 8A main electrode 8B sub-electrode 9 drain electrode 10 substrate electrode 12 two-dimensional electron gas 15 wiring 16 p-type region 16a high concentration region 31 first buffer layer 32 second buffer layer 41 high resistance nitride semiconductor layer 42 conductive nitride semiconductor layer 500 passivation Film 51 First source contact hole 52 Second source contact hole 53 Drain contact hole 105 Second semiconductor layer material film 106 Third semiconductor layer material film 106a High concentration region 107 Gate electrode film

Claims (20)

a substrate;
a first nitride semiconductor layer disposed on the substrate and constituting an electron transit layer;
a second nitride semiconductor layer formed above the first nitride semiconductor layer, having a bandgap larger than that of the first nitride semiconductor layer and forming an electron supply layer;
a third nitride semiconductor layer selectively formed above the second nitride semiconductor layer and having a ridge shape and containing a first p-type impurity;
a gate electrode formed on at least part of the upper surface of the third nitride semiconductor layer;
a source electrode disposed above the first nitride semiconductor layer;
a drain electrode arranged to face the source electrode with the third nitride semiconductor layer interposed therebetween;
The source electrode includes a main electrode in ohmic contact with the second nitride semiconductor layer, and a sub-electrode electrically connected to the main electrode and at least partially in contact with the first nitride semiconductor layer,
A nitride semiconductor device, wherein a p-type region extending downward from the surface of the first nitride semiconductor layer and containing a second p-type impurity is formed in a region of the first nitride semiconductor layer below the sub-electrode. . 2. The nitride semiconductor device according to claim 1, wherein said sub-electrode is made of a material different from that of said main electrode. 3. The nitride semiconductor device according to claim 2, wherein said sub-electrode is arranged separately from said main electrode. 3. The nitride semiconductor device according to claim 2, wherein said sub-electrode is in contact with said main electrode. The sub-electrode is a laminated film of a Ni layer formed on the first nitride semiconductor layer and an Au layer laminated on the Ni layer, or a V layer formed on the first nitride semiconductor layer. and an Au layer laminated on the V layer. 2. The nitride semiconductor device according to claim 1, wherein said sub-electrode is made of the same material as said main electrode. 7. The nitride semiconductor device according to claim 6, wherein said sub-electrode is formed integrally with said main electrode. The main electrode is a laminated film of a Ti layer formed on the second nitride semiconductor layer and an Al layer laminated on the Ti layer, or Ti formed on the second nitride semiconductor layer. a layer, an Al layer laminated on said Ti layer, a Ni layer formed on said Al layer, and an Au layer formed on said Ni layer. 1. The nitride semiconductor device according to claim 1. the first nitride semiconductor layer includes a high resistance nitride semiconductor layer disposed on the substrate and a conductive nitride semiconductor layer formed on the high resistance nitride semiconductor layer;
9. The p-type region according to claim 1, wherein said p-type region extends from the surface of said conductive nitride semiconductor layer through said conductive nitride semiconductor layer and into said high resistance nitride semiconductor layer. 3. The nitride semiconductor device according to claim 1. Assuming that the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is _d2 <t<( _d1 +d ₂ ), the nitride semiconductor device according to claim 9. Assuming that the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is {( _d1 /4)+ _d2 }<t<{(3·d ₁ /4)+d ₂ }, the nitride semiconductor device according to claim 9 . Assuming that the thickness of the high resistance nitride semiconductor layer is _d1 and the thickness of the conductive nitride semiconductor layer is _d2 , the depth t of the p-type region is t={( _d1 /2) +d ₂ }, the nitride semiconductor device according to claim 9 . A second high-concentration region having a higher concentration of the second p-type impurity than the second p-type impurity concentration lower than the surface layer portion of the p-type region is formed in the surface layer portion of the p-type region. The nitride semiconductor device according to any one of claims 1 to 12. The concentration of the second p-type impurity in the second high-concentration region is 1×10 ¹⁷ cm ³ to 1×10 ²¹ cm ³ , and the second p-type impurity in the region other than the second high-concentration region in the p-type region. 14. The nitride semiconductor device according to claim 13, wherein the concentration of the type impurity is 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ . a first high-concentration region in a surface layer portion of the third nitride semiconductor layer, the concentration of the first p-type impurity being higher than the concentration of the first p-type impurity in the third nitride semiconductor layer below the surface layer portion; 15. The nitride semiconductor device according to any one of claims 1 to 14, wherein The concentration of the first p-type impurity in the first high-concentration region is 1×10 ¹⁷ cm ³ to 1×10 ²¹ cm ³ , and the concentration of the first p-type impurity in the third nitride semiconductor layer other than the first high-concentration region 16. The nitride semiconductor device according to claim 15, wherein said first p-type impurity has a concentration of 1×10 ¹⁶ cm ³ to 1×10 ²⁰ cm ³ . The gate electrode is a laminated film of a Ni layer formed on the third nitride semiconductor layer and an Au layer laminated on the Ni layer, or V formed on the third nitride semiconductor layer. 17. The nitride semiconductor device according to claim 1, comprising a laminated film of a layer and an Au layer laminated on said V layer. 18. The nitride semiconductor device according to claim 1, further comprising a buffer layer made of a nitride semiconductor arranged between said semiconductor substrate and said semi-insulating nitride layer. 19. The nitride semiconductor device according to claim 1, wherein said drain electrode is in ohmic contact with said second nitride semiconductor layer. forming a first nitride semiconductor layer constituting an electron transit layer on a substrate;
forming a p-type region extending downward from a portion of the surface of the first nitride semiconductor layer;
a second semiconductor layer material film which is a material film of the second nitride semiconductor layer constituting the electron supply layer; and a third nitride semiconductor layer made of a nitride semiconductor containing p-type impurities, on the first nitride semiconductor layer. a step of forming a third semiconductor layer material film, which is a material film of the conductive layer, in that order;
forming a gate electrode film, which is a material film of a gate electrode, on the third semiconductor layer material film;
By patterning the gate electrode film and the third semiconductor layer material film, a ridge-shaped third nitride semiconductor layer is formed on the second semiconductor layer material film, and a ridge-shaped third nitride semiconductor layer is formed on the third nitride semiconductor layer. forming a gate portion comprising the formed gate electrode;
forming the second nitride semiconductor layer by selectively removing the second semiconductor layer material film so as to expose at least part of the surface of the p-type region;
forming a source sub-electrode on the first nitride semiconductor layer in contact with at least part of the exposed surface of the p-type region;
forming, on the second nitride semiconductor layer, a source main electrode and a drain electrode that are in ohmic contact with the surface of the second nitride semiconductor layer and are electrically connected to the source sub-electrode; A method for manufacturing a nitride semiconductor device.

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