JP2023018166A - Imaging device - Google Patents

Abstract

To provide an imaging device capable of achieving both the low resistance of the ITO electrode and the improvement of the controllability of the current-voltage characteristics of the photoelectric conversion part.SOLUTION: The imaging device is an imaging device that includes: a pixel electrode 122; a counter electrode 127; and a photoelectric conversion layer 126 located between the pixel electrode 122 and the counter electrode 127. The counter electrode 127 includes a first ITO layer 127a and a second ITO layer 127b laminated on the main surface of the first ITO layer 127a opposite to the photoelectric conversion layer 126. The crystallite size of the second ITO layer 127b is larger than that of the first ITO layer 127a.SELECTED DRAWING: Figure 6

Description

The present disclosure relates to imaging devices.

2. Description of the Related Art In imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors, a structure using an organic photoelectric conversion layer in a photoelectric conversion section has been proposed. For example, in Patent Document 1, a plurality of pixel electrodes arranged in a matrix on a substrate, an organic layer including a photoelectric conversion layer provided in common to the plurality of pixel electrodes on the plurality of pixel electrodes, and an organic layer A configuration of an imaging device is disclosed that includes a translucent counter electrode that is provided in common with a plurality of pixel electrodes. The imaging device absorbs light incident from the translucent counter electrode in the photoelectric conversion layer and converts the light into electrons and holes. At this time, by applying a voltage between the pixel electrode and the counter electrode, carriers generated in the photoelectric conversion layer can be efficiently extracted. Indium tin oxide (ITO) is widely used for the translucent counter electrode because it preferably has high transmittance and low resistance.

Japanese Patent No. 5946132 Japanese Patent No. 4607767 Japanese Patent No. 6128020

Masao Mizuno, "Influence of Impurities on Electronic State of Indium Oxide," KOBE STEEL ENGINEERING REPORTS, December 1998, Vol. 48, No. 3

ITO, which is widely used as a transparent conductive film, is known to have significantly different optical and electrical properties depending on its composition or film quality. For example, according to Patent Document 2, the specific resistance, which is one of the electrical properties, is defined as the reciprocal of carrier concentration and mobility. Therefore, the specific resistance can be lowered by lowering the carrier concentration.

On the other hand, in Patent Document 3, in an amorphous oxide composed of a quaternary compound of indium, gallium and/or aluminum, zinc, and oxygen, the work function is controlled by the oxygen concentration during film formation. It reveals what it can do. Furthermore, Non-Patent Document 1 shows that localized oxygen vacancies form donor levels, and carrier electrons emitted from the donor levels provide conductivity.

From these facts, when an ITO film is used as a counter electrode of a photoelectric conversion element, a low resistance can be realized by adjusting the carrier concentration. current-voltage characteristics change. In other words, there is a problem that it is not possible to achieve both a reduction in the resistance of the ITO electrode and an improvement in the controllability of the current-voltage characteristics of the photoelectric conversion element.

Accordingly, the present disclosure provides an imaging device capable of achieving both a reduction in the resistance of the ITO electrode and an improvement in the controllability of the current-voltage characteristics of the photoelectric conversion unit.

In order to solve the above problems, an imaging device according to one aspect of the present disclosure is an imaging device including a pixel electrode, a counter electrode, and a photoelectric conversion layer positioned between the pixel electrode and the counter electrode. The counter electrode includes a first ITO layer and a second ITO layer laminated on the main surface of the first ITO layer opposite to the photoelectric conversion layer. The crystallite size of the second ITO layer is larger than the crystallite size of the first ITO layer.

According to one aspect of the present disclosure, it is possible to provide an imaging device capable of achieving both a reduction in the resistance of an ITO electrode and an improvement in controllability of current-voltage characteristics of a photoelectric conversion unit.

FIG. 1 is a cross-sectional view of a sample element used for analyzing the crystallite size of an ITO layer according to an embodiment. FIG. 2 is a graph showing the relationship between the sheet resistance of the ITO layer and the crystallite size according to the embodiment. FIG. 3 is a graph showing the relationship between the oxygen concentration in the deposition gas for the ITO layer and the crystallite size according to the embodiment. FIG. 4 is a cross-sectional view of a sample element used for evaluating the sheet resistance of the laminated structure of ITO layers according to the embodiment. FIG. 5 is a graph showing an example of sheet resistance for each lamination structure of ITO layers according to the embodiment. FIG. 6 is a cross-sectional view showing an example of a photoelectric conversion unit according to the embodiment; FIG. 7 is a graph showing an example of current-voltage characteristics of the photoelectric conversion unit according to the embodiment. FIG. 8 is a cross-sectional view showing another example of the photoelectric conversion unit according to the embodiment. FIG. 9 is a circuit diagram showing the circuit configuration of the imaging device according to the embodiment. FIG. 10 is a cross-sectional view of a unit pixel in the imaging device according to the embodiment.

(Summary of this disclosure)
An imaging device according to an aspect of the present disclosure is an imaging device including a pixel electrode, a counter electrode, and a photoelectric conversion layer positioned between the pixel electrode and the counter electrode. The counter electrode includes a first ITO layer and a second ITO layer laminated on the main surface of the first ITO layer opposite to the photoelectric conversion layer. The crystallite size of the second ITO layer is larger than the crystallite size of the first ITO layer.

As a result, by using a laminated structure of two ITO layers with different crystallite sizes as a counter electrode (ITO electrode), it is possible to reduce the resistance of the ITO electrode and improve the controllability of the current-voltage characteristics of the photoelectric conversion section. can do.

Further, for example, the imaging device according to one aspect of the present disclosure further includes an electrode terminal electrically connected to the first ITO layer. The main surface of the electrode terminal and the main surface of the pixel electrode may be positioned at the same height in the stacking direction.

This makes it possible to easily supply power to the counter electrode. For example, a power supply circuit for supplying power to the counter electrode and a signal processing circuit for signal charges collected by the pixel electrodes can be collectively formed on the substrate side.

Also, for example, the sheet resistance of the second ITO layer may be lower than the sheet resistance of the first ITO layer.

As a result, since the counter electrode includes the second ITO layer having a low sheet resistance, it is possible to reduce the resistance of the counter electrode.

Also, for example, the work function of the second ITO layer may be greater than the work function of the first ITO layer.

As a result, the work function of the first ITO layer on the side of the photoelectric conversion layer becomes small, so that when a voltage is applied to the counter electrode, current easily flows through the photoelectric conversion layer. Therefore, it is possible to improve the controllability of the current-voltage characteristics of the photoelectric conversion unit, such as driving the photoelectric conversion unit with a driving voltage having a small absolute value.

Also, for example, the film thickness of the second ITO layer may be greater than the film thickness of the first ITO layer.

As a result, the thickness of the second ITO layer having a low sheet resistance is large, so that the resistance of the counter electrode can be further reduced.

Also, for example, the imaging device according to one aspect of the present disclosure may further include a first functional layer positioned between the photoelectric conversion layer and the first ITO layer.

Accordingly, by providing, for example, a hole blocking layer or the like as the first functional layer, the function of photoelectric conversion can be improved.

Also, for example, the imaging device according to one aspect of the present disclosure may further include a second functional layer located between the photoelectric conversion layer and the pixel electrode.

Accordingly, by providing an electron blocking layer or the like as the second functional layer, for example, the function of photoelectric conversion can be improved.

Embodiments will be specifically described below with reference to the drawings.

It should be noted that the embodiments described below are all comprehensive or specific examples. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are examples, and are not intended to limit the present disclosure. Further, among the constituent elements in the following embodiments, constituent elements not described in independent claims will be described as optional constituent elements.

Each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, for example, scales and the like do not necessarily match in each drawing. Moreover, in each figure, substantially the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted or simplified.

Also, in this specification, terms that indicate the relationship between elements such as vertical or horizontal, terms that indicate the shape of elements, and numerical ranges are not expressions that express only strict meanings, but substantially equivalent It is an expression that means to include a wide range, for example, a difference of about several percent.

In this specification, the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking structure. It is used as a term defined by a relative positional relationship. Also, the terms "above" and "below" are used only when two components are spaced apart from each other and there is another component between them, as well as when two components are spaced apart from each other. It also applies when two components are in contact with each other and are placed in close contact with each other.

(Embodiment)
[1. Features of ITO layer]
First, the ITO layer used as the counter electrode of the photoelectric conversion unit of the imaging device according to the embodiment will be described.

FIG. 1 is a cross-sectional view of a sample element used for analyzing the crystallite size of an ITO layer according to an embodiment.

The inventors fabricated a sample device 100 shown in FIG. 1 in order to clarify the relationship between the sheet resistance of the ITO layer and the crystallite size. As shown in FIG. 1, sample device 100 comprises silicon wafer 101 and ITO layer 102 . The ITO layer 102 is laminated directly on top of the silicon wafer 101 . A method of manufacturing the sample device 100 is as follows.

First, an ITO layer 102 having a film thickness of 50 nm was formed on a silicon wafer 101 using a sputtering method. Then, the sample element 100 was produced by performing heat treatment at 200° C. for 50 minutes in a nitrogen atmosphere.

At this time, the composition of the target used in the sputtering method was InO:SnO=9:1. As for the film forming atmosphere of the ITO layer 102, a film forming gas containing a mixture of argon and oxygen was introduced into the chamber, and the pressure inside the chamber was adjusted to 0.3 Pa. Sample elements 100 according to Comparative Examples 1 to 4 were manufactured by varying the oxygen concentration in the film forming gas. Specifically, the oxygen concentrations in the film formation gas of the sample elements 100 according to Comparative Examples 1 to 4 are 0.2%, 0.4%, 0.7%, and 1.1%. .

The inventors analyzed the crystallite size of the ITO layer 102 for each of the sample devices 100 according to Comparative Examples 1 to 4. FIG. Specifically, the X-ray diffraction (Xray Diffraction: XRD) method is used to measure the X-ray diffraction spectrum, and the half width of the measured X-ray diffraction spectrum is used to determine the crystal of the ITO layer 102 using Scherrer's formula. Child size was calculated. Here, a crystallite is a group of crystals that can be regarded as a single crystal. Also, a group consisting of a single or a plurality of crystallites is defined as a crystal grain boundary, and the amount of crystal grain boundaries occupying a certain region is defined as a crystal grain boundary density. Furthermore, the inventors measured the sheet resistance of the ITO layer 102 using a four-probe measuring instrument. The analysis results of the ITO layer 102 are shown in Table 1, FIGS. 2 and 3 below.

FIG. 2 is a graph showing the relationship between the sheet resistance of the ITO layer and the crystallite size according to the embodiment. In FIG. 2 , the horizontal axis represents the sheet resistance of the ITO layer 102 and the vertical axis represents the crystallite size of the ITO layer 102 .

FIG. 3 is a graph showing the relationship between the oxygen concentration in the deposition gas for the ITO layer and the crystallite size according to the embodiment. In FIG. 3 , the horizontal axis represents the oxygen concentration in the film forming gas for the ITO layer 102 and the vertical axis represents the crystallite size of the ITO layer 102 .

As shown in Table 1, the lower the oxygen concentration, the lower the sheet resistance. On the other hand, as shown in Table 1 and FIG. 3, the lower the oxygen concentration, the larger the crystallite size. Therefore, as shown in FIG. 2, the smaller the crystallite size, the higher the sheet resistance. Thus, it can be seen from the results shown in Table 1, FIGS. 2 and 3 that the sheet resistance of the ITO layer 102 can be adjusted by adjusting the crystallite size.

As the crystallite size of the ITO layer 102 increases, the grain boundary density, which causes trapping or scattering of carriers, tends to increase. In addition, since oxygen defects tend to increase, the carrier concentration tends to increase. From these facts, it is inferred that the sheet resistance of the ITO layer 102 is lowered by increasing the crystallite size.

As described above, the sheet resistance of the ITO layer 102 can be lowered by increasing the crystallite size of the ITO layer 102 . On the other hand, when the ITO layer 102 is used alone as the counter electrode of the photoelectric conversion section of the imaging device, the controllability of the current-voltage characteristics of the photoelectric conversion section deteriorates. For this reason, the present inventors have considered using a laminated structure of two ITO layers with different crystallite sizes as a counter electrode. The controllability of the current-voltage characteristics of the photoelectric conversion units will be described later.

FIG. 4 is a cross-sectional view of a sample element used for evaluating the sheet resistance of the laminated structure of ITO layers according to the embodiment. As shown in FIG. 4, sample device 110 comprises silicon wafer 101 , first ITO layer 111 and second ITO layer 112 . A first ITO layer 111 is directly laminated on the top surface of the silicon wafer 101 . The second ITO layer 112 is laminated directly on top of the first ITO layer 111 .

The method for fabricating the sample element 110 is the same as the method for fabricating the sample element 100 shown in FIG. Specifically, first, a first ITO layer 111 and a second ITO layer 112 were formed in order on a silicon wafer 101 using a sputtering method. After that, a heat treatment at 200° C. was performed for 50 minutes in a nitrogen atmosphere to fabricate the sample element 110 .

Here, the film formation conditions for the first ITO layer 111 and the film formation conditions for the second ITO layer 112 are the same except that the oxygen concentration in the film formation gas and the film thickness are different. The oxygen concentration in the deposition gas for the first ITO layer 111 is 20%, and the oxygen concentration in the deposition gas for the second ITO layer 112 is 3%. The thickness of the first ITO layer 111 and the thickness of the second ITO layer 112 were adjusted so that the total thickness of the first ITO layer 111 and the second ITO layer 112 was 50 nm. The inventors produced five sample elements 110 having different film thicknesses as Examples 1 to 3 and Comparative Examples 5 and 6. FIG. The film thickness of each sample element 110 is as shown in Table 2 below.

Note that the sample element 110 according to Comparative Example 5 has the same structure as the sample element 100 having the first ITO layer 111 as the ITO layer 102 because the film thickness of the second ITO layer 112 is 0 nm. Similarly, the sample device 110 according to Comparative Example 6 has the same structure as the sample device 100 having the second ITO layer 112 as the ITO layer 102 because the film thickness of the first ITO layer 111 is 0 nm.

The present inventors measured the sheet resistance of the laminated structure of the first ITO layer 111 and the second ITO layer 112 for each of the five sample elements 110 produced using a four-probe measuring instrument. For Comparative Examples 5 and 6, the sheet resistance of the first ITO layer 111 or the second ITO layer 112 was measured.

FIG. 5 is a graph showing an example of sheet resistance for each lamination structure of ITO layers according to the embodiment. In FIG. 5, the horizontal axis represents Examples 1 to 3 and Comparative Examples 5 and 6, and the vertical axis represents sheet resistance. Note that Examples 1 to 3 and Comparative Examples 5 and 6 are arranged in the order in which the film thickness of the second ITO layer 112 increases toward the right side of the horizontal axis.

From the results shown in Table 2 and FIG. 5, when the total film thickness of the laminated structure of the ITO layers is the same, by adjusting the film thickness ratio between the first ITO layer 111 and the second ITO layer 112, the laminated structure sheet It can be seen that the resistance can be adjusted. Specifically, if the total thickness of the laminated structure of the ITO layers is the same, the sheet resistance decreases as the thickness of the second ITO layer 112 formed in a film formation gas with a low oxygen concentration increases. I understand. That is, as the thickness of the second ITO layer 112 having a lower sheet resistance than that of the first ITO layer 111 increases, the sheet resistance of the laminated structure of the ITO layers decreases.

Note that when Table 1 and Table 2 are compared, the sheet resistance of the sample element 110 according to Comparative Example 6 is lower than that of the sample element 100 according to Comparative Example 4, although the oxygen concentration is high. ing. This is because the sample elements 100 according to Comparative Examples 1 to 4 and the sample elements 110 according to Comparative Examples 5 and 6 use different deposition apparatuses for forming the ITO layers. This is because the conditions were different.

[2. Characteristics of Photoelectric Conversion Section]
Next, a photoelectric conversion section including a laminated structure of ITO layers as a counter electrode will be described.

[2-1. structure]
First, the structure of the photoelectric conversion unit will be described with reference to FIG. FIG. 6 is a cross-sectional view showing an example of a photoelectric conversion unit according to this embodiment. As shown in FIG. 6 , the photoelectric conversion unit 120 includes pixel electrodes 122 , photoelectric conversion layers 126 and counter electrodes 127 . The photoelectric conversion section 120 is provided on the insulating layer 121 . Connection wires 123 , electrode terminals 124 and connection wires 125 are formed on the insulating layer 121 .

The insulating layer 121 is an insulating layer formed over a substrate (not shown). Note that transistors included in a signal processing circuit that processes signal charges generated by the photoelectric conversion unit 120, for example, are formed on the substrate. The insulating layer 121 has a single-layer structure or a laminated structure such as a silicon oxide film or a silicon nitride film, but is not particularly limited.

The pixel electrode 122 is an electrode for collecting signal charges generated in the photoelectric conversion layer 126 . As a material for the pixel electrode 122, a conductive material such as metal, metal oxide, metal nitride, or conductive polysilicon is used. Metals are, for example, aluminum, silver, copper, titanium or tungsten. Metal nitrides are, for example, titanium nitride or tantalum nitride. Conductive polysilicon is polysilicon to which conductivity is imparted by adding impurities.

The connection wiring 123 is part of the wiring that electrically connects the pixel electrode 122 and the signal processing circuit. As a material of the connection wiring 123, a conductive material such as metal, metal oxide, metal nitride, or conductive polysilicon is used.

The electrode terminal 124 is a power supply terminal for supplying power to the counter electrode 127 . The electrode terminal 124 is electrically connected to the counter electrode 127 . As a material of the electrode terminal 124, a conductive material such as metal, metal oxide, metal nitride, or conductive polysilicon is used.

The main surface of the electrode terminal 124 and the main surface of the pixel electrode 122 are located at the same height in the stacking direction. Specifically, the upper surface 124a of the electrode terminal 124 and the upper surface 122a of the pixel electrode 122 are positioned at the same height in the stacking direction. In this embodiment, the upper surface 124a of the electrode terminal 124, the upper surface 122a of the pixel electrode 122, and the upper surface 121a of the insulating layer 121 are flush with each other.

The connection wiring 125 is a part of wiring that electrically connects the electrode terminal 124 and a power supply circuit (not shown) that supplies a voltage to be applied to the counter electrode 127 . As a material of the connection wiring 125, a conductive material such as metal, metal oxide, metal nitride, or conductive polysilicon is used.

The photoelectric conversion layer 126 is positioned between the pixel electrode 122 and the counter electrode 127 . The photoelectric conversion layer 126 generates electron-hole pairs inside upon being irradiated with light. The electron-hole pairs are separated into electrons and holes by the electric field applied to the photoelectric conversion layer 126, and each moves toward the pixel electrode 122 side or the counter electrode 127 side.

The photoelectric conversion layer 126 is formed using a known photoelectric conversion material. The photoelectric conversion material is, for example, an organic material, but may be an inorganic material. As inorganic photoelectric conversion materials, hydrogenated amorphous silicon, compound semiconductor materials, metal oxide semiconductor materials, and the like can be used. A compound semiconductor material is, for example, CdSe. The metal oxide semiconductor material is for example ZnO.

When the photoelectric conversion material is an organic material, the molecular design of the photoelectric conversion material can be relatively freely designed so as to obtain desired photoelectric conversion characteristics. When the photoelectric conversion material is an organic material, the photoelectric conversion layer 126 with excellent planarization can be easily formed by a coating process using a solution containing the photoelectric conversion material. The organic semiconductor material can be formed by, for example, a vacuum deposition method or a coating method.

When an organic semiconductor material is used as the photoelectric conversion material, the photoelectric conversion layer 126 may be composed of a laminated film of a donor material and an acceptor material, or may be composed of a mixed film of these materials. A laminated film structure of a donor material and an acceptor material is called a heterojunction type. A mixed film structure of donor and acceptor materials is called a bulk heterojunction type.

A p-type semiconductor of an organic compound is a donor organic semiconductor, and is mainly represented by a hole-transporting organic compound, and refers to an organic compound having a property of easily donating electrons. Specifically, the p-type semiconductor of an organic compound refers to an organic compound having a smaller ionization potential when two organic materials are used in contact with each other. Therefore, any organic compound can be used as the donor organic semiconductor as long as it is an electron-donating organic compound. For example, donor organic semiconductors include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, cyanine compounds, merocyanine compounds, and oxonol. compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, condensed aromatic carbocyclic compounds, or nitrogen-containing heterocyclic compounds as ligands. The condensed aromatic carbocyclic compounds are, for example, naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives and the like. Any organic compound having a smaller ionization potential than the organic compound used as the acceptor organic semiconductor can be used as the donor organic semiconductor.

An n-type semiconductor of an organic compound is an acceptor organic semiconductor, which is mainly represented by an electron-transporting organic compound, and refers to an organic compound having a property of easily accepting electrons. Specifically, the n-type semiconductor of an organic compound refers to an organic compound having a larger electron affinity when two organic compounds are used in contact with each other. Therefore, as the acceptor organic compound, any organic compound can be used as long as it is an electron-accepting organic compound. For example, as the acceptor organic compound, a metal complex having a ligand such as fullerene, fullerene derivative, condensed aromatic carbocyclic compound, polyarylene compound, fluorene compound, cyclopentadiene compound, silyl compound, nitrogen-containing heterocyclic compound, or the like is used. be able to. Alternatively, a metal complex having a 5- or 7-membered heterocyclic compound containing a nitrogen atom, an oxygen atom or a sulfur atom as a ligand can be used as the acceptor organic compound. 5- or 7-membered heterocyclic compounds containing a nitrogen atom, an oxygen atom or a sulfur atom include, for example, pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine , pyralidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine or tribenzazepine. As described above, any organic compound having a higher electron affinity than the organic compound used as the donor organic compound can be used as the acceptor organic semiconductor.

The counter electrode 127 collects charges of opposite polarity to the signal charges collected by the pixel electrodes 122 . A predetermined voltage is applied to the counter electrode 127 . Thereby, a potential difference is generated between the counter electrode 127 and the plurality of pixel electrodes 122 , and an electric field is applied to the photoelectric conversion layer 126 . The counter electrode 127 collects charges that move to the counter electrode 127 side due to the electric field among the holes and electrons generated in the photoelectric conversion layer 126 .

The counter electrode 127 has a laminated structure of ITO layers. Specifically, as shown in FIG. 6, the counter electrode 127 includes a first ITO layer 127a and a second ITO layer 127b.

The first ITO layer 127a is provided closer to the photoelectric conversion layer 126 than the second ITO layer 127b. Specifically, the first ITO layer 127 a is directly laminated on the upper surface of the photoelectric conversion layer 126 .

The second ITO layer 127b is stacked on the main surface of the first ITO layer 127a opposite to the photoelectric conversion layer 126 . Specifically, the second ITO layer 127b is directly laminated on the upper surface of the first ITO layer 127a.

The first ITO layer 127 a and the second ITO layer 127 b cover the end surface of the photoelectric conversion layer 126 and the portion of the insulating layer 121 not covered with the photoelectric conversion layer 126 . Specifically, the first ITO layer 127 a is in contact with the end surface of the photoelectric conversion layer 126 and the portion of the insulating layer 121 not covered with the photoelectric conversion layer 126 . The first ITO layer 127 a is in contact with the electrode terminal 124 and electrically connected to the electrode terminal 124 .

The crystallite size of the second ITO layer 127b is larger than the crystallite size of the first ITO layer 127a. As can be seen from the relationship between the crystallite size and the sheet resistance described above, the sheet resistance of the second ITO layer 127b is smaller than the sheet resistance of the first ITO layer 127a. Also, the work function of the second ITO layer 127b is greater than the work function of the first ITO layer 127a.

In this embodiment, the thickness of the second ITO layer 127b is greater than the thickness of the first ITO layer 127a. For example, the film thickness of the second ITO layer 127b is 1.5 times or more the film thickness of the first ITO layer 127a, but may be 2 times or more or 4 times or more.

[2-2. Current-voltage characteristics]
Next, the current-voltage characteristics of the photoelectric conversion unit 120 will be described.

In order to measure current-voltage characteristics, the inventors fabricated a photoelectric conversion unit 120 shown in FIG. 6 as a sample element according to Example 4. FIG. The present inventors further produced sample elements according to Comparative Examples 7 and 8, which had the same configuration as that of Example 4 except that the counter electrode 127 had a single-layer structure of an ITO layer. .

In the sample element according to Example 4, a titanium nitride (TiN) film with a thickness of 50 nm was formed by sputtering as the pixel electrode 122 and the electrode terminal 124 . As the photoelectric conversion layer 126, an organic photoelectric conversion film, which is a mixed film containing Sn( _OSiHex3 ) _2Nc and fullerene ₍ C60) at a volume ratio of 1:9, was formed by vacuum deposition. The first ITO layer 127a is an ITO layer with a film thickness of 20 nm formed in a film formation gas with an oxygen concentration of 1.1%. The second ITO layer 127b is an ITO layer with a film thickness of 30 nm formed in a film formation gas with an oxygen concentration of 0.4%.

A sample element according to Comparative Example 7 has a single-layer structure of an ITO layer having a thickness of 50 nm formed in a film forming gas having an oxygen concentration of 0.4% as the counter electrode 127 . A sample element according to Comparative Example 8 has a single-layer structure of an ITO layer with a thickness of 50 nm formed in a film forming gas having an oxygen concentration of 1.1% as the counter electrode 127 . The sheet resistance of the counter electrode 127 of the sample element according to Comparative Example 7 is lower than the sheet resistance of the counter electrode 127 of the sample element according to Comparative Example 8. Specifically, the sheet resistance of the counter electrode 127 according to Comparative Example 7 is the same as that of Comparative Example 2, which is 71Ω/sq. The sheet resistance of the counter electrode 127 according to Comparative Example 8 is the same as that of Comparative Example 4, which is 372Ω/sq.

The present inventors measured the current-voltage characteristics of the sample devices according to Example 4, Comparative Example 7 and Comparative Example 8, respectively. Specifically, the voltage applied to the counter electrode 127 was swept from -0.2 V to 0 V, and the current value of the current flowing between the counter electrode 127 and the pixel electrode 122 was measured.

A semiconductor parameter analyzer B1500A manufactured by Keysight was used to measure the current-voltage characteristics. During the measurement, a xenon light source MAX-303 manufactured by Asahi Spectrosco Co., Ltd. was used to irradiate the photoelectric conversion layer 126 of the sample element with light.

FIG. 7 is a graph showing an example of current-voltage characteristics of the photoelectric conversion unit according to the embodiment. In FIG. 7, the horizontal axis represents the applied voltage applied to the counter electrode 127 and the vertical axis represents the current flowing between the pixel electrode 122 and the counter electrode 127 . Since the potential of the pixel electrode 122 is constant, the horizontal axis corresponds to the potential difference between the counter electrode 127 and the pixel electrode 122 .

As shown in FIG. 7, the applied voltage when the current value becomes 1.0×10 ⁻¹¹ A is −0.195 V, −0.195 V, -0.135V, -0.145V. As a result, in the sample element according to Comparative Example 7, which has a low sheet resistance, the applied voltage is 0.05 V higher on the negative side than the sample element according to Comparative Example 8, which has a high sheet resistance, when the current starts to flow. Here, the time when the current value reaches 1.0×10 ⁻¹¹ A is regarded as the time when the current starts to flow. When the current starts to flow, the electron-hole pairs generated in the photoelectric conversion layer 126 can be separated into electrons and holes and moved, and can be detected as signal charges, that is, photoelectric conversion. This is when the unit 120 can be driven. Therefore, the applied voltage applied to the counter electrode 127 when the current starts to flow is the driving voltage of the photoelectric conversion section 120 .

From the results shown in FIG. 7, it can be seen that the sample element according to Comparative Example 7, which has a low sheet resistance, requires a driving voltage with a larger absolute value than the sample element according to Comparative Example 8, which has a high sheet resistance. In other words, when a single ITO layer having a low sheet resistance is used as the counter electrode 127, a driving voltage having a large absolute value is required, so it can be said that the controllability of the current-voltage characteristics of the photoelectric conversion section 120 is poor.

On the other hand, in the sample element according to Example 4, as shown in FIG. 7, the photoelectric conversion unit 120 can be driven with a drive voltage approximately equal to that of the sample element according to Comparative Example 8 having a high sheet resistance. I understand. Therefore, by utilizing the laminated structure of the ITO layers, it is possible to improve the controllability of the current-voltage characteristics.

It should be noted that the difference in the work function of the ITO layer in contact with the photoelectric conversion layer 126 has an effect on the change in drive voltage that accompanies such a shift in current-voltage characteristics. The difference in work function between the ITO layer of the sample device according to Comparative Example 7 and the ITO layer of the sample device according to Comparative Example 8 is the difference in drive voltage shown in FIG. 7, which is about −0.05V. That is, the work function of the ITO layer with a small crystallite size according to Comparative Example 8 is smaller than the work function of the ITO layer with a large crystallite size according to Comparative Example 7.

In the sample element according to Example 4, the first ITO layer 127a on the photoelectric conversion layer 126 side is the same as the ITO layer of the sample element according to Comparative Example 8, and is an ITO layer having a high sheet resistance and a small work function. Since the current-voltage characteristics of the sample element according to Example 4 are equivalent to those of Comparative Example 8, the controllability of the current-voltage characteristics depends not on the counter electrode 127 as a whole, but on the first ITO layer 127a on the photoelectric conversion layer 126 side. It can be seen that the functions can be adjusted. Specifically, the smaller the work function of the first ITO layer 127a on the photoelectric conversion layer 126 side, the easier it is for the current to flow through the photoelectric conversion layer 126 between the counter electrode 127 and the pixel electrode 122. controllability can be improved.

As described above, in the photoelectric conversion body 120 according to the present embodiment, the crystallite size of the second ITO layer 127b is smaller than that of the first ITO layer 127a. The sheet resistance is lower than that of 127a. Thereby, the sheet resistance of the entire counter electrode 127 can be reduced.

Also, since the crystallite size of the first ITO layer 127a on the photoelectric conversion layer 126 side is smaller than the crystallite size of the second ITO layer 127b, the work function of the first ITO layer 127a is smaller than the work function of the second ITO layer 127b. Thereby, the controllability of the current-voltage characteristics of the photoelectric conversion unit 120 can be improved.

The conditions for forming the ITO layer are not limited to the conditions described above as long as the crystallite size of the ITO layer can be adjusted. For example, deposition of the ITO layer may be performed using a wet method. Moreover, the heating temperature after film formation may be any temperature at which crystallization of the ITO layer proceeds, and may be 150° C., for example. The atmosphere during heating may be a vacuum reduced pressure atmosphere, a rare gas atmosphere such as argon, or an oxygen atmosphere. In addition, the deposition gas may contain a gas such as hydrogen or nitrogen. The composition of the sputtering target may be InO:SnO=9.5:0.5. Also, the film thickness of each layer is not limited to the examples described above.

[2-3. Modification]
Here, a modification of the photoelectric conversion unit will be described with reference to FIG. 8 . FIG. 8 is a cross-sectional view showing another example of the photoelectric conversion unit according to the embodiment.

The photoelectric conversion section 130 shown in FIG. 8 is different from the photoelectric conversion section 120 shown in FIG. 6 in newly including an electron blocking layer 128 and a hole blocking layer 129 . The following description focuses on the differences from the structure shown in FIG. 6, and omits or simplifies the description of the common points.

The electron blocking layer 128 is an example of a second functional layer located between the photoelectric conversion layer 126 and the pixel electrode 122 . The electron blocking layer 128 has a function of suppressing movement of electrons into the pixel electrode 122 in the photoelectric conversion layer 126 by photoelectric conversion. Electron blocking layer 128 inhibits the passage of electrons and allows the passage of holes.

As a material for forming the electron blocking layer 128, a p-type semiconductor or a hole-transporting organic compound can be used. Examples of such materials are TPD (N,N'-bis(3-methylphenyl)-(1,1'-biphenyl)-4,4'-diamine), α-NPD (4,4'-bis aromatic diamine compounds such as [N-(naphthyl)-N-phenyl-amino]biphenyl), oxazoles, oxadiazoles, triazoles, imidazoles, imidazolones, stilbene derivatives, pyrazoline derivatives, tetrahydroimidazoles, polyarylalkanes, butadiene, m - MTDATA (4,4′,4″-tris(N-(3-methylphenyl)N-phenylamino)triphenylamine), perylene, and porphine, tetraphenylporphine copper, phthalocyanine, copper phthalocyanine and titanium phthalocyanine Porphyrin compounds such as oxides, triazole derivatives, oxazizazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, annealamine derivatives, amino-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazones derivatives, silazane derivatives, etc. Alternatively, materials for forming the electron block layer 128 include polymers such as phenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, picoline, thiophene, acetylene, and diacetylene, or These derivatives can be used.The material for forming the electron blocking layer 128 can be selected from the above materials in consideration of the electron affinity of the material constituting the photoelectric conversion layer 126. The electron blocking layer 128 is It may be formed using not only an organic material but also an inorganic material.

The film thickness of the electron blocking layer 128 is not particularly limited. From the viewpoint of sufficiently reducing the tunneling probability of electrons, the thickness of the electron blocking layer 128 may be 5 nm or more. The upper limit of the film thickness of the electron blocking layer 128 is, for example, 100 nm.

The hole blocking layer 129 is an example of a first functional layer positioned between the photoelectric conversion layer 126 and the first ITO layer 127a. The hole blocking layer 129 has a function of suppressing movement of holes from the counter electrode 127 to the photoelectric conversion layer 126 . The hole-blocking layer 129 suppresses passage of holes and allows passage of electrons.

As a material for forming the hole blocking layer 129, an n-type semiconductor or an electron-transporting organic compound can be used. Examples of such materials are fullerenes such as C60 and C70, fullerene derivatives such as indene- _C60 bis-adduct ₍ ICBA), carbon nanotubes and their derivatives, OXD- ₇ (1,3-bis(4- tert-butylphenyl-1,3,4-oxadiazolyl)phenylene), anthraquinodimethane derivatives, diphenylquinone derivatives, bathocuproine (BCP), bathophenanthroline and its derivatives, distyrylarylene derivatives, triazole compounds , silole compound, tris(8-hydroxyquinolinato)aluminum complex, bis(4-methyl-8-quinolinato)aluminum complex, acetylacetonate complex, copper phthalocyanine, 3,4,9,10-perylenetetracarboxylic acid di Anhydrides (PTCDA), organics or organo-metallic compounds such as Alq, or inorganics such as MgAg, MgO. A material for forming the hole blocking layer 129 can be selected from the above materials in consideration of the ionization potential of the material forming the photoelectric conversion layer 126 .

As described above, the photoelectric conversion section 130 includes the electron blocking layer 128 and the hole blocking layer 129, so that the photoelectric conversion function can be enhanced.

In this modified example, the pixel electrode 122 collects holes as signal charges, but the pixel electrodes 122 may collect charges as signal charges. In this case, the hole blocking layer 129 is positioned between the pixel electrode 122 and the photoelectric conversion layer 126 , and the electron blocking layer 128 is positioned between the photoelectric conversion layer 126 and the counter electrode 127 .

Further, the photoelectric conversion section 130 may include either one of the electron blocking layer 128 and the hole blocking layer 129, or may not include the other. Further, the photoelectric conversion section 130 may include functional layers for enhancing the photoelectric conversion function, such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, in addition to the layer having the charge blocking function. .

[3. Imaging device]
Next, an imaging device according to this embodiment will be described with reference to FIGS. 9 and 10. FIG.

FIG. 9 is a circuit diagram showing the circuit configuration of the imaging device 200 according to this embodiment. FIG. 10 is a cross-sectional view of a unit pixel 210 in the imaging device 200 according to this embodiment.

[3-1. circuit configuration]
First, the circuit configuration of the imaging device 200 according to the present embodiment will be described below. The imaging device 200 includes a plurality of unit pixels 210 and peripheral circuits, as shown in FIG. A plurality of unit pixels 210 includes charge detection circuit 25 , photoelectric conversion section 120 , and charge accumulation node 24 electrically connected to charge detection circuit 25 and photoelectric conversion section 120 .

The imaging device 200 is, for example, an organic image sensor realized by a one-chip integrated circuit, and has a pixel array including a plurality of unit pixels 210 arranged two-dimensionally. A plurality of unit pixels 210 are arranged two-dimensionally, that is, in row and column directions to form a photosensitive region, which is a pixel region. FIG. 9 shows an example in which the unit pixels 210 are arranged in a matrix of 2 rows and 2 columns. The imaging device 200 may be a line sensor. In that case, the plurality of unit pixels 210 may be arranged one-dimensionally. In this specification, row direction and column direction refer to directions in which rows and columns extend, respectively. That is, the vertical direction is the column direction and the horizontal direction is the row direction.

Each unit pixel 210 includes a charge storage node 24 electrically connected to the photoelectric conversion section 120 and the charge detection circuit 25 . Charge detection circuit 25 includes amplification transistor 11 , reset transistor 12 , and address transistor 13 .

The photoelectric conversion unit 120 includes pixel electrodes 122 , a photoelectric conversion layer 126 and a counter electrode 127 . A predetermined voltage is applied to the counter electrode 127 from the voltage control circuit 30 via the counter electrode signal line 16 .

The pixel electrode 122 is connected to the gate electrode 39B of the amplification transistor 11 (see FIG. 10). The signal charge collected by the pixel electrode 122 is stored in the charge storage node 24 located between the pixel electrode 122 and the gate electrode 39B of the amplification transistor 11. FIG. In this embodiment, the signal charges are holes, but the signal charges may be electrons.

The signal charge accumulated in the charge accumulation node 24 is applied to the gate electrode 39B of the amplification transistor 11 as a voltage corresponding to the amount of signal charge. The amplification transistor 11 amplifies this voltage. The amplified voltage is selectively read out by the address transistor 13 as a signal voltage. The reset transistor 12 has one of its source electrode and drain electrode connected to the pixel electrode 122 and resets the signal charge accumulated in the charge accumulation node 24 . In other words, the reset transistor 12 resets the potentials of the gate electrode 39B of the amplification transistor 11 and the pixel electrode 122 .

In order to selectively perform the above-described operations in a plurality of unit pixels 210, the imaging device 200 includes power supply wirings 21, vertical signal lines 17, address signal lines 26, and reset signal lines, as shown in FIG. 27. These lines are connected to each unit pixel 210 respectively. Specifically, the power supply wiring 21 is connected to one of the source electrode and the drain electrode of the amplification transistor 11 . A vertical signal line 17 is connected to one of a source electrode and a drain electrode of the address transistor 13 . The address signal line 26 is connected to the gate electrode 39C of the address transistor 13 (see FIG. 10). The reset signal line 27 is connected to the gate electrode 39A of the reset transistor 12 (see FIG. 10).

The peripheral circuits include a vertical scanning circuit 15 , a horizontal signal readout circuit 20 , multiple column signal processing circuits 19 , multiple load circuits 18 , multiple differential amplifiers 22 , and a voltage control circuit 30 . The vertical scanning circuit 15 is also called a row scanning circuit. The horizontal signal readout circuit 20 is also called a column scanning circuit. The column signal processing circuit 19 is also called a row signal storage circuit. Differential amplifier 22 is also referred to as a feedback amplifier.

The vertical scanning circuit 15 is connected to address signal lines 26 and reset signal lines 27 . The vertical scanning circuit 15 selects a plurality of unit pixels 210 arranged in each row for each row, reads signal voltages, and resets the potentials of the pixel electrodes 122 . A power supply line 21 that is a source follower power supply supplies a predetermined power supply voltage to each unit pixel 210 . The horizontal signal readout circuit 20 is electrically connected to a plurality of column signal processing circuits 19 . The column signal processing circuit 19 is electrically connected to the unit pixels 210 arranged in each column via the vertical signal lines 17 corresponding to each column. A load circuit 18 is electrically connected to each vertical signal line 17 . The load circuit 18 and the amplification transistor 11 form a source follower circuit.

A plurality of differential amplifiers 22 are provided corresponding to each column. A negative input terminal of the differential amplifier 22 is connected to the corresponding vertical signal line 17 . The output terminal of the differential amplifier 22 is connected to the unit pixel 210 via the feedback line 23 corresponding to each column.

The vertical scanning circuit 15 applies a row selection signal for controlling ON/OFF of the address transistor 13 to the gate electrode 39C of the address transistor 13 through the address signal line 26 . This scans and selects the row to be read. A signal voltage is read out to the vertical signal line 17 from the unit pixel 210 in the selected row. The vertical scanning circuit 15 applies a reset signal for controlling ON/OFF of the reset transistor 12 to the gate electrode 39A of the reset transistor 12 via the reset signal line 27 . Thereby, the row of the unit pixels 210 to be reset is selected. The vertical signal line 17 transmits the signal voltage read from the unit pixel 210 selected by the vertical scanning circuit 15 to the column signal processing circuit 19 .

The column signal processing circuit 19 performs noise suppression signal processing typified by correlated double sampling, analog-to-digital conversion (AD conversion), and the like.

The horizontal signal readout circuit 20 sequentially reads signals from the plurality of column signal processing circuits 19 to the horizontal common signal line 28 .

The differential amplifier 22 is connected via a feedback line 23 to the other of the source and drain electrodes of the reset transistor 12 , which is not connected to the pixel electrode 122 . Therefore, differential amplifier 22 receives the output value of address transistor 13 at its negative input terminal when address transistor 13 and reset transistor 12 are in a conducting state. The differential amplifier 22 performs a feedback operation so that the gate potential of the amplification transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is 0V or a positive voltage near 0V. Feedback voltage means the output voltage of the differential amplifier 22 .

The voltage control circuit 30 may generate a constant control voltage, or may generate a plurality of control voltages with different values. For example, the voltage control circuit 30 may generate control voltages having two or more different values, or may generate control voltages that vary continuously within a predetermined range. The voltage control circuit 30 determines the value of the control voltage to be generated based on the command of the operator who operates the imaging device 200 or the command of another control unit provided in the imaging device 200, and determines the control voltage of the determined value. to generate The voltage control circuit 30 is provided outside the photosensitive area as part of the peripheral circuitry. Note that the photosensitive area is substantially the same as the pixel area.

For example, the voltage control circuit 30 generates two or more different control voltages and applies the control voltages to the counter electrode 127 to change the spectral sensitivity characteristics of the photoelectric conversion layer 126 . In addition, the change in the spectral sensitivity characteristic includes the spectral sensitivity characteristic in which the photoelectric conversion layer 126 has zero sensitivity to the light to be detected. As a result, for example, in the imaging device 200, while the unit pixels 210 are reading the detection signals for each row, the voltage control circuit 30 applies a control voltage to the counter electrode 127 so that the sensitivity of the photoelectric conversion layer 126 becomes zero. Thus, it is possible to substantially eliminate the influence of incident light when reading the detection signal. Therefore, the global shutter operation can be realized even if the detection signal is read substantially row by row.

In the present embodiment, as shown in FIG. 9, the voltage control circuit 30 applies a control voltage to the counter electrodes 127 of the unit pixels 210 arranged in the row direction via the counter electrode signal line 16 . Thereby, the voltage between the pixel electrode 122 and the counter electrode 127 is changed to switch the spectral sensitivity characteristics of the photoelectric conversion section 120 . Alternatively, the voltage control circuit 30 realizes an electronic shutter operation by applying a control voltage so as to obtain a spectral sensitivity characteristic in which the sensitivity to light becomes zero at a predetermined timing during imaging. Note that the voltage control circuit 30 may apply a control voltage to the pixel electrode 122 .

The pixel electrode 122 is set to a potential higher than that of the counter electrode 127 so that the photoelectric conversion unit 120 is irradiated with light and the pixel electrode 122 collects electrons as signal charges. This causes electrons to move toward the pixel electrode 122 . At this time, the direction of movement of electrons is opposite to the direction of current flow, so current flows from the pixel electrode 122 toward the counter electrode 127 . Further, the pixel electrode 122 is set to a potential lower than that of the counter electrode 127 so that the photoelectric conversion unit 120 is irradiated with light and the pixel electrode 122 collects holes as signal charges. At this time, current flows from the counter electrode 127 toward the pixel electrode 122 .

[3-2. Cross-sectional configuration]
Next, an example of a specific cross-sectional configuration of the unit pixel 210 of the imaging device 200 will be described with reference to FIG. 10 . As shown in FIG. 10, the unit pixel 210 includes a semiconductor substrate 31, a charge detection circuit 25, a photoelectric conversion section 120, and a charge storage node 24. As shown in FIG. A plurality of unit pixels 210 are formed on the semiconductor substrate 31 . For example, the photoelectric conversion section 120 is provided above the semiconductor substrate 31 . The charge detection circuit 25 is provided inside and above the semiconductor substrate 31 .

The semiconductor substrate 31 is an insulating substrate or the like having a semiconductor layer provided on the surface on which the photosensitive region is formed, and is, for example, a p-type silicon substrate. The semiconductor substrate 31 has impurity regions 41A, 41B, 41C, 41D, and 41E, and an isolation region 42 for electrical isolation between the unit pixels 210 . Here, the element isolation region 42 is also provided between the impurity regions 41B and 41C. This suppresses leakage of the signal charges accumulated in the charge accumulation node 24 . The element isolation region 42 is formed, for example, by implanting acceptor ions under predetermined implantation conditions.

The impurity regions 41A, 41B, 41C, 41D and 41E are diffusion layers formed in the semiconductor substrate 31, for example. Here, the impurity regions 41A, 41B, 41C, 41D and 41E are n-type impurity regions. As shown in FIG. 10, the amplification transistor 11 includes an impurity region 41C, an impurity region 41D, a gate insulating film 38B, and a gate electrode 39B. Impurity region 41C and impurity region 41D function as a source region and a drain region of amplifying transistor 11, respectively. A channel region of the amplification transistor 11 is formed between the impurity regions 41C and 41D.

Similarly, address transistor 13 includes impurity region 41D, impurity region 41E, gate insulating film 38C, and gate electrode 39C. In the example shown in FIG. 10, amplifying transistor 11 and address transistor 13 are electrically connected to each other by sharing impurity region 41D. Impurity region 41D and impurity region 41E function as a source region and a drain region of address transistor 13, respectively. Impurity region 41E is connected to vertical signal line 17 shown in FIG.

The reset transistor 12 includes an impurity region 41A, an impurity region 41B, a gate insulating film 38B, and a gate electrode 39A. Impurity region 41A and impurity region 41B function as a source region and a drain region of reset transistor 12, respectively. Impurity region 41A is connected to reset signal line 27 shown in FIG.

The gate insulating film 38A, the gate insulating film 38B, and the gate insulating film 38C are insulating films each formed using an insulating material. The insulating film has, for example, a single layer structure or a laminated structure such as a silicon oxide film or a silicon nitride film.

Gate electrode 39A, gate electrode 39B, and gate electrode 39C are each formed using a conductive material. The conductive material is, for example, conductive polysilicon.

An interlayer insulating layer 43 is laminated on the semiconductor substrate 31 so as to cover the amplifying transistor 11 , the address transistor 13 and the reset transistor 12 . A wiring layer (not shown) may be arranged in the interlayer insulating layer 43 . The wiring layer is made of metal such as copper, and may include wiring such as the vertical signal lines 17 described above. The number of insulating layers in the interlayer insulating layer 43 and the number of layers included in the wiring layers arranged in the interlayer insulating layer 43 can be set arbitrarily.

In the interlayer insulating layer 43, a contact plug 45A connected to the impurity region 41B of the reset transistor 12, a contact plug 45B connected to the gate electrode 39B of the amplification transistor 11, a contact plug 47 connected to the pixel electrode 122, and , wirings 46 for connecting the contact plugs 47, the contact plugs 45A, and the contact plugs 45B. As a result, the impurity region 41B of the reset transistor 12 is electrically connected to the gate electrode 39B of the amplification transistor 11 .

A photoelectric conversion unit 120 is arranged on the interlayer insulating layer 43 . A specific configuration of the photoelectric conversion unit 120 is the same as in FIG. Note that the interlayer insulating layer 43 and the contact plug 47 correspond to the insulating layer 121 and the connection wiring 123 shown in FIG. 6, respectively. The electrode terminals 124 and the connection wirings 125 shown in FIG. 6 are provided, for example, not in the unit pixel 210 but in the periphery of the photosensitive region.

Note that the photoelectric conversion section 120 may include at least one of a plurality of functional layers including an electron blocking layer 128 and a hole blocking layer 129, like the photoelectric conversion section 130 shown in FIG. For example, the imaging device 200 may include a photoelectric conversion section 130 instead of the photoelectric conversion section 120 .

A color filter 60 is provided above the photoelectric conversion unit 120 . A microlens 61 is provided above the color filter 60 . The color filter 60 is formed as an on-chip color filter by patterning, for example, and a photosensitive resin in which dyes or pigments are dispersed is used. The microlens 61 is provided as an on-chip microlens, for example, and an ultraviolet photosensitive material or the like is used.

The imaging device 200 can be manufactured using a general semiconductor manufacturing process. In particular, when a silicon substrate is used as the semiconductor substrate 31, it can be manufactured by utilizing various silicon semiconductor processes.

As described above, the counter electrode 127 of the photoelectric conversion unit 120 included in the imaging device 200 has a laminated structure of the first ITO layer 127a and the second ITO layer 127b. Therefore, as described above, the imaging device 200 can achieve both a reduction in the resistance of the counter electrode 127 and an improvement in controllability of the current-voltage characteristics of the photoelectric conversion section 120 .

In addition, a transparent and insulating protective film may be provided between the photoelectric conversion section 130 and the color filter 60 .

(Other embodiments)
Although the imaging device according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, modifications that can be made by those skilled in the art to the present embodiment, and forms constructed by combining the components of different embodiments are also included within the scope of the present disclosure. be

For example, in the above embodiments, counter electrode 127 may include three or more ITO layers. In this case, the ITO layer closest to the photoelectric conversion layer 126 is the first ITO layer 127a. The second ITO layer 127b is one of two or more ITO layers excluding the first ITO layer 127a. For example, the second ITO layer 127 b may be the ITO layer farthest from the photoelectric conversion layer 126 . That is, another ITO layer may be included between the first ITO layer 127a and the second ITO layer 127b. Alternatively, an ITO layer that is farther from the photoelectric conversion layer 126 than the second ITO layer 127b may be provided.

Further, for example, the electrode terminal 124 and the pixel electrode 122 may have the lower surfaces positioned at the same height in the stacking direction. For example, the electrode terminal 124 and the pixel electrode 122 may be provided on the top surface of the insulating layer 121 whose top surface is flat.

Further, for example, the film thickness of the first ITO layer 127a and the film thickness of the second ITO layer 127b may be equal. Alternatively, the film thickness of the first ITO layer 127a may be greater than the film thickness of the second ITO layer 127b.

In addition, various changes, replacements, additions, and omissions can be made to each of the above-described embodiments within the scope of claims or equivalents thereof.

INDUSTRIAL APPLICABILITY The present disclosure can be used, for example, in cameras, rangefinders, or the like.

11 Amplification transistor 12 Reset transistor 13 Address transistor 15 Vertical scanning circuit 16 Counter electrode signal line 17 Vertical signal line 18 Load circuit 19 Column signal processing circuit 20 Horizontal signal readout circuit 21 Power supply wiring 22 Differential amplifier 23 Feedback line 24 Charge storage node 25 Charge detection circuit 26 Address signal line 27 Reset signal line 28 Horizontal common signal line 30 Voltage control circuit 31 Semiconductor substrates 38A, 38B, 38C Gate insulating films 39A, 39B, 39C Gate electrodes 41A, 41B, 41C, 41D, 41E Impurity regions 42 Element isolation region 43 Interlayer insulating layers 45A, 45B, 47 Contact plug 46 Wiring 60 Color filter 61 Microlens 100, 110 Sample element 101 Silicon wafer 102 ITO layers 111, 127a First ITO layers 112, 127b Second ITO layers 120, 130 Photoelectric conversion Part 121 insulating layers 121a, 122a, 124a upper surface 122 pixel electrodes 123, 125 connection wiring 124 electrode terminal 126 photoelectric conversion layer 127 counter electrode 128 electron blocking layer 129 hole blocking layer 200 imaging device 210 unit pixel

Claims (7)

An imaging device comprising a pixel electrode, a counter electrode, and a photoelectric conversion layer positioned between the pixel electrode and the counter electrode,
The counter electrode is
a first ITO (Indium Tin Oxide) layer;
and a second ITO layer laminated on the main surface of the first ITO layer opposite to the photoelectric conversion layer,
the crystallite size of the second ITO layer is larger than the crystallite size of the first ITO layer;
Imaging device. further comprising an electrode terminal electrically connected to the first ITO layer,
the main surface of the electrode terminal and the main surface of the pixel electrode are positioned at the same height in the stacking direction;
The imaging device according to claim 1 . the sheet resistance of the second ITO layer is lower than the sheet resistance of the first ITO layer;
The imaging device according to claim 1 or 2. the work function of the second ITO layer is greater than the work function of the first ITO layer;
The imaging device according to any one of claims 1 to 3. The film thickness of the second ITO layer is greater than the film thickness of the first ITO layer,
The imaging device according to any one of claims 1 to 4. Further comprising a first functional layer located between the photoelectric conversion layer and the first ITO layer,
The imaging device according to any one of claims 1 to 5. Further comprising a second functional layer positioned between the photoelectric conversion layer and the pixel electrode,
The imaging device according to any one of claims 1 to 6.

Images