JP2023013292A - Light-receiving device, electronic equipment, and light-receiving method - Google Patents

Abstract

To make it possible to remove reset noise.SOLUTION: A light-receiving device includes: a photoelectric conversion unit; two or more floating diffusions that accumulate, at different timings, electric charges photoelectrically converted by the photoelectric conversion unit; a plurality of pixels that, on the basis of the electric charges accumulated by the two or more floating diffusions, output four or more types of pixel signals having different phases for each pixel; and an AD conversion unit that outputs, in a frame unit and for each phase of the four or more types of pixel signals, a digital signal according to a reset level of the pixel signal and a digital signal according to the pixel signal level.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD The present disclosure relates to a light receiving device, an electronic device, and a light receiving method.

A ranging sensor using an indirect ToF (Time of Flight) method is known. In the indirect ToF distance measuring sensor, the light signal emitted from the light emitting unit is reflected by the object, and the signal charges obtained by photoelectrically converting the reflected light are received by, for example, two gate electrodes that are driven at high speed. The distance is calculated from the distribution ratio of the signal charges distributed to the two charge accumulation regions (see Patent Document 1).

WO2007/026777

The potential of the floating diffusion in which photoelectrically converted charges are accumulated fluctuates due to reset noise. For this reason, it is common to perform correlated double sampling (CDS) that cancels reset noise by taking the difference between the reset level and the pixel signal level.

However, since the distance measurement sensor starts the readout operation in a state in which electric charges are distributed to a plurality of floating diffusions, after reading out the D (Data) phase that detects the pixel signal level, reset is applied once and then the reset level is detected. Therefore, the P (Pre-charge) phase reading is performed.

The D-phase potential depends on the previous reset level of the P-phase. That is, the reset level is not necessarily the same between the D phase and the P phase. Therefore, even if the difference between the D-phase signal level and the P-phase signal level is detected, the reset noise cannot be completely removed.

As described above, the conventional indirect ToF distance measuring sensor may not be able to remove the reset noise.

Therefore, the present disclosure provides a light receiving device, an electronic device, and a light receiving method capable of removing reset noise.

In order to solve the above problems, according to the present disclosure, a photoelectric conversion unit, two or more floating diffusions that accumulate charges photoelectrically converted by the photoelectric conversion unit at different timings, and the two or more floating diffusions a plurality of pixels that output four or more types of pixel signals with different phases for each pixel based on the charge accumulated in the
an AD conversion unit that outputs a digital signal corresponding to the reset level of the pixel signal and a digital signal corresponding to the pixel signal level for each phase of the four or more types of pixel signals in frame units. is provided.

The AD conversion section may output the digital signal obtained by synthesizing the reset level and the pixel signal level having different phases from each other.

a counter that outputs a count value corresponding to a period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level;
The AD converter may generate the digital signal according to the count value of the counter.

The counter continues counting without resetting the count value of the counter at some switching timings among a plurality of switching timings at which the phases of the four or more types of pixel signals are switched, and at the remaining switching timings, A count value of the counter may be reset.

The partial switching timing is a switching timing for counting count values for pixel signals with phases different by 180°,
The rest of the switching timings may be switching timings for counting count values for pixel signals having phases different by 90°.

When X is an arbitrary angle value, the partial switching timing is the switching timing between the pixel signal level of X° and the reset level of X+180°, and the switching timing of the pixel signal level of X+90° and the reset level of X+270°. may include

The counter resets the count value when a first reset signal instructing resetting of all the floating diffusions for all pixels is input, and instructs resetting of some of the floating diffusions. The count value may be held when the second reset signal is input.

The second reset signal is input at the partial switching timing,
The first reset signal may be input at the remaining switching timings.

The counter may switch between counting up and counting down based on an external control signal.

When the control signal is the first logic, the counter reverses the count direction when the phase of the input pixel signal is switched, and counts when the control signal is the second logic. Counting may be continued without changing the counting direction of the counter when the phase of the input pixel signal is switched.

The pixels switch between a reset level and a pixel signal level of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase, and sequentially output the pixel signals;
Based on the control signal, the counter counts a count value corresponding to the reset level of one pixel signal and a count value corresponding to the pixel signal level of the other pixel signal out of two pixel signals having phases different from each other by 180°. A count value may be generated by summing the values.

The counter outputs a count value corresponding to the reset level of the first phase based on the control signal, then outputs a count value corresponding to the pixel signal level of the first phase and the reset level of the second phase. Then output a count value corresponding to the pixel signal level of the second phase, and then output a count value corresponding to the reset level of the third phase. Then, a count value obtained by summing the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase is output, and then the pixel signal level of the fourth phase is output. You may output the count value according to.

The counter does not change the direction of counting up or down when adding the count value corresponding to the pixel signal level of the first phase and the count value corresponding to the reset level of the second phase. When adding the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase, it is not necessary to change the count-up or count-down direction.

Before the counter starts counting for the period until the reset level of the first phase crosses the reference signal level, and for the period until the reset level of the third phase crosses the reference signal level. and resetting the count value before starting the counting of the reference signal. Counting may be continued without resetting the count value before starting counting for each period until the level is crossed.

The first phase and the second phase are different in phase by 180°, the second phase and the third phase are different in phase by 90°, and the third phase and the fourth phase are different by 180°. ° may be out of phase.

The control signal is a first logic pulse signal after the counter generates a count value corresponding to the reset level of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase. is output, and the rest is the second logic,
When the control signal is the first logic, the counter switches the counting direction to count, and when the control signal is the second logic, the counter continues counting while maintaining the counting direction. good.

The pixel may have a CAPD (Current Assisted Photonic Demodulator) structure or a gate electrode structure.

According to the present disclosure, a light emitting unit that emits an optical signal toward an object;
the light receiving device described above, including the photoelectric conversion unit that receives the reflected light of the optical signal reflected by the object;
An electronic device is provided, comprising: a distance measuring unit that measures a distance to the object based on the digital signal output from the light receiving device and the optical signal.

The distance measurement unit generates an I signal and a Q signal based on the reset level and pixel signal level of the four or more types of pixel signals, and measures the distance to the object based on the ratio of the I signal and the Q signal. You can measure the distance.

According to the present disclosure, four or more types of pixel signals with different phases are generated for each pixel based on charges accumulated in two or more floating diffusions that accumulate charges photoelectrically converted by the photoelectric conversion unit at different timings. output and
When counting the length of the period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level with a counter, a plurality of switching in which the phases of the four or more types of pixel signals are switched. Provided is a light receiving method that continues counting without resetting the count value of the counter at part of switching timings, and resets the count value of the counter at the remaining switching timings.

1 is a block diagram showing a schematic configuration example of a light receiving device to which the present technology is applied; FIG. FIG. 2 is a cross-sectional view showing a first configuration example of pixels arranged in a pixel array section; FIG. 2 is a diagram showing a circuit configuration of pixels two-dimensionally arranged in a pixel array section; FIG. 4 is a plan view showing an arrangement example of the pixels shown in FIG. 3; FIG. 4 is a signal waveform diagram of four types of pixel signals output from pixels and having different phases. Timing diagram of 4Tap-4Phase method. FIG. 10 is a diagram for explaining a readout method of Only; FIG. 4 is a diagram for explaining a DDS read method; FIG. 4 is a diagram for explaining a method of reading a frame CDS; FIG. 4 is a diagram showing a read sequence according to the embodiment; FIG. 4 is a diagram showing information read out in a frame CDS according to the embodiment; The figure which generalized FIG. 9 is a detailed timing diagram of the read sequence shown in FIG. 8; FIG. FIG. 2 is a cross-sectional view of one pixel provided in a pixel array section; A plan view of a pixel. FIG. 14 is a block diagram showing a schematic configuration of an electronic device 2 that includes the light receiving device shown in FIGS. 1 to 13 and performs distance measurement by the indirect ToF method; 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; FIG. FIG. 2 is an explanatory diagram showing an example of installation positions of an information detection unit outside the vehicle and an imaging unit;

Embodiments of a light receiving device, an electronic device, and a light receiving method will be described below with reference to the drawings. Although the main components of the light-receiving device, electronic equipment, and light-receiving method will be mainly described below, the light-receiving device, electronic equipment, and light-receiving method may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.

<Configuration example of light receiving device>
FIG. 1 is a block diagram showing a schematic configuration example of a light receiving device 1 to which the present technology is applied. Note that the light receiving device 1 can also be called an imaging device.

A light receiving device 1 shown in FIG. 1 is an element that outputs distance measurement information by the indirect ToF method.

The light receiving device 1 receives light (reflected light) emitted from a predetermined light source (irradiation light) and reflected by an object, and outputs a depth image in which distance information to the object is stored as a depth value. The irradiation light emitted from the light source is, for example, infrared light with a wavelength in the range of 780 nm to 1000 nm, and is pulsed light that is repeatedly turned on and off at a predetermined cycle.

The light receiving device 1 has a pixel array section 21 formed on a semiconductor substrate and a peripheral circuit section integrated on the same semiconductor substrate as the pixel array section 21 . The peripheral circuit section includes, for example, a vertical driving section 22, a column processing section 23, a horizontal driving section 24, a system control section 25, a reference signal generating section 18, a tap driving section 12, and the like.

The light receiving device 1 is further provided with a signal processing section 26 and a data storage section 27 . The signal processing unit 26 and the data storage unit 27 may be mounted on the same board as the light receiving device 1 or may be arranged on a board in a module separate from the light receiving device 1 .

The pixel array section 21 has a configuration in which the pixels 10 that generate electric charges corresponding to the amount of received light and output signals corresponding to the electric charges are two-dimensionally arranged in rows and columns. That is, the pixel array section 21 has a plurality of pixels 10 that photoelectrically convert incident light and output a signal corresponding to the charge obtained as a result. Details of the pixel 10 will be described later with reference to FIG.

Here, the row direction is the direction in which the pixels 10 are arranged in the horizontal direction, and the column direction is the direction in which the pixels 10 are arranged in the vertical direction. The row direction is the horizontal direction in the drawing, and the column direction is the vertical direction in the drawing.
The tap drive unit 12 performs control for distributing charges photoelectrically converted by the photodiode in the pixel to a plurality of floating diffusions. The tap drive unit 12 outputs control signals GDA and GDB for controlling charge distribution. These control signals GDA and GDB are supplied to each pixel.

In the pixel array section 21, pixel drive lines 28 are wired along the row direction for each pixel row, and vertical signal lines 29 are wired along the column direction for each pixel column. It is For example, the pixel drive line 28 transmits a drive signal for driving when reading a signal from the pixel 10 . The pixel drive lines 28 may include multiple types of drive lines supplied to each pixel row.

The vertical driving section 22 is composed of a shift register, an address decoder, and the like, and drives all the pixels 10 of the pixel array section 21 simultaneously or in units of rows. That is, the vertical drive section 22 constitutes a drive section that controls the operation of each pixel 10 of the pixel array section 21 together with the system control section 25 that controls the vertical drive section 22 .

A pixel signal, which is a detection signal output from each pixel 10 in a pixel row according to drive control by the vertical drive unit 22 , is input to the column processing unit 23 through the vertical signal line 29 . The column processing unit 23 performs predetermined signal processing on the pixel signal output from each pixel 10 through the vertical signal line 29, and temporarily holds the pixel signal after the signal processing. Specifically, the column processor 23 has an AD converter 30 .

The AD conversion section 30 has a comparison circuit section 31 and a counter section 32 . The comparison circuit section 31 has a plurality of comparison circuits 31a. A corresponding vertical signal line 29 is connected to each comparison circuit 31a. The comparison circuit 31a compares the reference signal RAMP supplied from the reference signal generator 18 with the pixel signal VSL, which is the detection signal of the pixel PX. The signal level of the pixel signal VSL is the reset level of the pixel signal or the pixel signal level. The comparison circuit 31a detects whether or not the signal level of the reference signal RAMP (hereinafter referred to as reference signal level) crosses the reset level or the pixel signal level.

The counter unit 32 has a plurality of counters (CNT) 32a that count based on the comparison result of the comparison circuit 31a. The comparison circuit section 31 and the counter section 32 constitute an ADC (Analog-Digital Converter).

The reference signal generator 18 generates a reference signal RAMP to be compared with the pixel signal VSL from the pixel PX, and supplies it to the comparator circuit 31 a of the comparator circuit unit 31 . The reference signal RAMP is a signal whose level (voltage) changes stepwise or linearly over time.

The horizontal driving section 24 is composed of a shift register, an address decoder, and the like, and selects unit circuits corresponding to the pixel columns of the column processing section 23 in order. By selective scanning by the horizontal driving section 24, pixel signals that have undergone signal processing for each unit circuit in the column processing section 23 are sequentially output.

The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the vertical driving unit 22, the column processing unit 23, and the horizontal driving unit 24 based on the various timing signals generated by the timing generator. and other drive control.

The system control unit 25 outputs a CN inversion pulse signal (control signal) PS as described later. The CN inversion pulse signal PS is a signal that instructs switching of the count direction of the counter 32 a in the AD conversion section 30 . For example, when the counter 32a is counting up, when the CN inversion pulse signal PS becomes the first logic (for example, high level), the counter 32a switches the counting operation to count down. Further, when the counter 32a is counting down, when the CN inversion pulse signal PS becomes the first logic, the counter 32a switches the counting operation to the counting up direction.

Thus, the counter 32a switches between counting up and counting down based on the CN inversion pulse signal PS. When the CN inversion pulse signal PS is at the first logic level (for example, high level), the counter 32a reverses the counting direction when the phase of the input pixel signal is switched, and counts the CN inversion pulse signal. When PS is the second logic, the counter 32a continues counting without changing the counting direction when the phase of the input pixel signal is switched.

For example, the pixels switch the reset level and the pixel signal level of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase, and output them in order. Based on the CN inversion pulse signal PS, the counter 32a calculates a count value according to the reset level of one pixel signal and a pixel signal level of the other pixel signal out of two pixel signals that are 180° out of phase with each other. Generates a count value that is the sum of the count value obtained. The first phase is, for example, 0°, the second phase is, for example, 180°, the third phase is, for example, 90°, and the fourth phase is, for example, 270°.

More specifically, the counter 32a outputs a count value corresponding to the reset level of the first phase based on the CN inversion pulse signal PS, and then outputs a count value corresponding to the pixel signal level of the first phase and the first phase. A count value obtained by summing the count values corresponding to the reset levels of the two phases is output, then the count value corresponding to the pixel signal level of the second phase is output, and then the count value corresponding to the reset level of the third phase is output. Next, the count value obtained by summing the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase is output, and then the pixel signal level of the fourth phase is output. Outputs the count value according to

More specifically, the counter 32a changes the direction of counting up or down when adding the count value corresponding to the pixel signal level of the first phase and the count value corresponding to the reset level of the second phase. First, when adding the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase, the direction of count-up or count-down is not changed.

In addition, the counter 32a counts the period before the reset level of the first phase crosses the reference signal level and the period until the reset level of the third phase crosses the reference signal level. until the pixel signal level of the first phase, the reset level and pixel signal level of the second phase, and the pixel signal level of the third phase cross the reference signal level. Counting is continued without resetting the count value before starting counting for each period.

The first phase differs from the second phase by 180°, the second phase differs from the third phase by 90°, and the third phase differs from the fourth phase by 180°. .

The signal processing section 26 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing based on the pixel signals output from the column processing section 23 . The data storage unit 27 temporarily stores data required for signal processing in the signal processing unit 26 .

The light-receiving device 1 configured as described above outputs a depth image in which pixel values include distance information to an object as depth values. The light-receiving device 1 is, for example, a vehicle-mounted system that measures the distance to an object outside the vehicle, or a system that measures the distance to an object such as a user's hand and measures the distance to the user's hand based on the measurement result. It can be installed in a gesture recognition device for recognizing gestures.

Note that the depth value may be detected by an application processor (AP) or the like external to the light receiving device. In this case, the light receiving device outputs the pixel signal output from the column processing section 23 to the AP or the like.

<Sectional View of First Configuration Example of Pixel>
FIG. 2 is a cross-sectional view showing a first configuration example of the pixels 10 arranged in the pixel array section 21. As shown in FIG.

The light receiving device 1 includes a semiconductor substrate 41 and a multilayer wiring layer 42 formed on the surface side (lower side in the drawing).

The semiconductor substrate 41 is made of silicon (Si), for example, and has a thickness of 1 to 6 μm, for example. In the semiconductor substrate 41, for example, an N-type (second conductivity type) semiconductor region 52 is formed in each pixel in a P-type (first conductivity type) semiconductor region 51, thereby forming a photodiode PD in each pixel. formed. The P-type semiconductor regions 51 provided on both front and back surfaces of the semiconductor substrate 41 also serve as hole charge accumulation regions for suppressing dark current.

The upper surface of the semiconductor substrate 41, which is the upper side in FIG. 2, is the rear surface of the semiconductor substrate 41 and serves as a light incident surface on which light is incident. An antireflection film 43 is formed on the upper surface of the back surface of the semiconductor substrate 41 .

The antireflection film 43 has, for example, a laminated structure in which a fixed charge film and an oxide film are laminated. can. Specifically, hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), STO (Strontium Titan Oxide), or the like can be used. In the example of FIG. 2, the antireflection film 43 is configured by stacking a hafnium oxide film 53, an aluminum oxide film 54, and a silicon oxide film 55. As shown in FIG.

An inter-pixel light shielding film for preventing incident light from entering the adjacent pixels is provided on the upper surface of the antireflection film 43 and at a boundary portion 44 (hereinafter also referred to as a pixel boundary portion 44) between the pixels 10 adjacent to each other on the semiconductor substrate 41. A membrane 45 is formed. The material of the inter-pixel light shielding film 45 may be any material that blocks light, and for example, metal materials such as tungsten (W), aluminum (Al), and copper (Cu) can be used.

A flattening film 46 is formed on the upper surface of the antireflection film 43 and the upper surface of the inter-pixel light shielding film 45, for example, an insulating film such as silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon oxynitride (SiON). Alternatively, it is made of an organic material such as resin.

An on-chip lens 47 is formed on the upper surface of the planarizing film 46 for each pixel. The on-chip lens 47 is made of, for example, a resin material such as styrene resin, acrylic resin, styrene-acrylic copolymer resin, or siloxane resin. The light condensed by the on-chip lens 47 is efficiently incident on the photodiode PD.

Further, in the pixel boundary portion 44 on the back side of the semiconductor substrate 41 , adjacent pixels in the depth direction of the semiconductor substrate 41 are provided from the back side of the semiconductor substrate 41 (on-chip lens 47 side) to a predetermined depth in the substrate depth direction. An inter-pixel separation portion 61 is formed to separate the pixels from each other. A peripheral portion including the bottom surface and side walls of the inter-pixel isolation portion 61 is covered with a hafnium oxide film 53 that is part of the antireflection film 43 . The inter-pixel separation section 61 prevents incident light from penetrating into the adjacent pixel 10 , confines the incident light within its own pixel, and prevents incident light from leaking from the adjacent pixel 10 .

In the example of FIG. 2, the silicon oxide film 55 and the inter-pixel isolation part 61 are simultaneously formed by embedding the silicon oxide film 55, which is the uppermost layer material of the antireflection film 43, into a trench (groove) dug from the back side. Therefore, although the silicon oxide film 55 that is part of the laminated film as the antireflection film 43 and the inter-pixel separation portion 61 are made of the same material, they do not necessarily have to be the same material. The material embedded in the trench (groove) dug from the rear surface side as the inter-pixel isolation section 61 may be, for example, a metal material such as tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiN).

On the other hand, two transfer transistors TRG1 and TRG2 are formed for one photodiode PD formed in each pixel 10 on the surface side of the semiconductor substrate 41 on which the multilayer wiring layer 42 is formed. In addition, on the surface side of the semiconductor substrate 41, floating diffusions FD1 and FD2 as charge storage portions for temporarily holding charges transferred from the photodiodes PD are formed of high-concentration N-type semiconductor regions (N-type diffusion regions). It is

The multilayer wiring layer 42 is composed of a plurality of metal films M and an interlayer insulating film 62 therebetween. FIG. 2 shows an example composed of three layers of a first metal film M1 to a third metal film M3.

Among the plurality of metal films M of the multilayer wiring layer 42, the region of the first metal film M1 closest to the semiconductor substrate 41 located below the formation region of the photodiode PD, in other words, in plan view, the photodiode PD A metal wiring made of copper, aluminum, or the like is formed as a light shielding member 63 in a region at least partially overlapping with the formation region of .

The light shielding member 63 is configured to block infrared light that enters the semiconductor substrate 41 from the light incident surface through the on-chip lens 47 and passes through the semiconductor substrate 41 without being photoelectrically converted in the semiconductor substrate 41. The light is shielded by the first metal film M1 closest to 41 and is not transmitted to the second metal film M2 and the third metal film M3 below it. Due to this light shielding function, infrared light that has passed through the semiconductor substrate 41 without being photoelectrically converted in the semiconductor substrate 41 is scattered by the metal film M below the first metal film M1 and enters the neighboring pixels. It can be suppressed. This can prevent erroneous detection of light by neighboring pixels.

In addition, the light shielding member 63 impinges on the semiconductor substrate 41 from the light incident surface through the on-chip lens 47 and passes through the semiconductor substrate 41 without being photoelectrically converted in the semiconductor substrate 41. It also has a function of reflecting the light by the light shielding member 63 and making it enter the semiconductor substrate 41 again. Therefore, it can be said that the light shielding member 63 is also a reflecting member. This reflection function increases the amount of infrared light that is photoelectrically converted within the semiconductor substrate 41, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel 10 to infrared light.

The light shielding member 63 may be made of polysilicon, oxide film, or the like, instead of a metal material, to form a structure that reflects or shields light.

Further, the light shielding member 63 is not composed of a single layer of metal film M, but is composed of a plurality of metal films M, for example, formed in a lattice pattern by a first metal film M1 and a second metal film M2. may

Among the plurality of metal films M of the multilayer wiring layer 42, a predetermined metal film M, for example, the second metal film M2, is patterned, for example, in a comb-teeth shape to form a wiring capacitance 64. there is The light shielding member 63 and the wiring capacitance 64 may be formed in the same layer (metal film M). It is formed. In other words, the light blocking member 63 is formed closer to the semiconductor substrate 41 than the wiring capacitor 64 is.

As described above, the light-receiving device 1 arranges the semiconductor substrate 41, which is a semiconductor layer, between the on-chip lens 47 and the multilayer wiring layer 42, and emits incident light from the back side where the on-chip lens 47 is formed to the photodiode. It has a back-illuminated structure that makes it incident on the PD.

In addition, the pixel 10 includes two transfer transistors TRG1 and TRG2 for the photodiode PD provided in each pixel. It is configured to be able to be distributed to FD2.

Further, the pixel 10 according to the first configuration example has the inter-pixel separation portion 61 formed in the pixel boundary portion 44 to prevent the incident light from penetrating into the adjacent pixel 10, confine the incident light within the own pixel, and prevent the incident light from penetrating into the adjacent pixel. This prevents incident light from leaking from the pixels 10 that By providing the light shielding member 63 on the metal film M below the formation region of the photodiode PD, the infrared light that has passed through the semiconductor substrate 41 without being photoelectrically converted in the semiconductor substrate 41 is blocked by the light shielding member 63 . to be reflected again into the semiconductor substrate 41 .

With the above configuration, the amount of infrared light photoelectrically converted in the semiconductor substrate 41 can be increased, and the quantum efficiency QE, that is, the sensitivity of the pixel 10 to infrared light can be improved.

<Example of pixel circuit configuration>
FIG. 3 shows the circuit configuration of the pixels 10 two-dimensionally arranged in the pixel array section 21. As shown in FIG.

The pixel 10 has a photodiode PD as a photoelectric conversion element. The pixel 10 also has two transfer transistors TRG, two floating diffusions FD, two additional capacitors FDL, two switching transistors FDG, two amplifier transistors AMP, two reset transistors RST, and two selection transistors SEL. Furthermore, the pixel 10 has a charge drain transistor OFG.

Here, when distinguishing each of the transfer transistor TRG, the floating diffusion FD, the additional capacitor FDL, the switching transistor FDG, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL, which are provided in the pixel 10 by two, as shown in FIG. As shown, transfer transistors TRG1 and TRG2, floating diffusions FD1 and FD2, additional capacitances FDL1 and FDL2, switching transistors FDG1 and FDG2, amplification transistors AMP1 and AMP2, reset transistors RST1 and RST2, and select transistors SEL1 and SEL2. called.

The transfer transistor TRG, the switching transistor FDG, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the charge discharge transistor OFG are composed of, for example, N-type MOS transistors.

The transfer transistor TRG1 becomes conductive in response to the activation of the transfer drive signal GDA supplied to its gate electrode, thereby transferring the charge accumulated in the photodiode PD to the floating diffusion FD1. The transfer transistor TRG2 becomes conductive in response to the activation of the transfer drive signal GDB supplied to the gate electrode, thereby transferring the charge accumulated in the photodiode PD to the floating diffusion FD2.

The floating diffusions FD1 and FD2 are charge storage units that temporarily hold charges transferred from the photodiodes PD.

The switching transistor FDG1 becomes conductive in response to the activation of the FD drive signal FDG1g supplied to the gate electrode, thereby connecting the additional capacitance FDL1 to the floating diffusion FD1. The switching transistor FDG2 connects the additional capacitance FDL2 to the floating diffusion FD2 by becoming conductive in response to the activation of the FD drive signal FDG2g supplied to the gate electrode. Additional capacitances FDL1 and FDL2 are formed by wiring capacitance 64 in FIG.

The reset transistor RST1 resets the potential of the floating diffusion FD1 by becoming conductive in response to the active state of the reset drive signal RSTg supplied to the gate electrode. The reset transistor RST2 resets the potential of the floating diffusion FD2 by becoming conductive in response to the active state of the reset drive signal RSTg supplied to the gate electrode. When the reset transistors RST1 and RST2 are activated, the switching transistors FDG1 and FDG2 are activated at the same time, and the additional capacitors FDL1 and FDL2 are also reset.

For example, when the illuminance is high and the amount of incident light is large, the vertical driving unit 22 activates the switching transistors FDG1 and FDG2 to connect the floating diffusion FD1 and the additional capacitor FDL1, and also connects the floating diffusion FD2 and the additional capacitor FDL2. do. As a result, more charges can be accumulated under high illuminance.

On the other hand, when the incident light intensity is low and the illuminance is low, the vertical driving section 22 deactivates the switching transistors FDG1 and FDG2 to separate the additional capacitors FDL1 and FDL2 from the floating diffusions FD1 and FD2, respectively. Thereby, conversion efficiency can be improved.

The charge discharge transistor OFG discharges the charge accumulated in the photodiode PD by becoming conductive in response to the activation of the discharge drive signal OFG1g supplied to the gate electrode.

The amplification transistor AMP1 is connected to a constant current source (not shown) by connecting the source electrode to the vertical signal line 29A via the selection transistor SEL1, thereby forming a source follower circuit. The amplification transistor AMP2 is connected to a constant current source (not shown) by connecting the source electrode to the vertical signal line 29B via the selection transistor SEL2, thereby forming a source follower circuit.

The selection transistor SEL1 is connected between the source electrode of the amplification transistor AMP1 and the vertical signal line 29A. The selection transistor SEL1 becomes conductive in response to the activation of the selection signal SEL1g supplied to the gate electrode, and outputs the pixel signal VSL1 output from the amplification transistor AMP1 to the vertical signal line 29A.

The selection transistor SEL2 is connected between the source electrode of the amplification transistor AMP2 and the vertical signal line 29B. The selection transistor SEL2 becomes conductive in response to the activation of the selection signal SEL2g supplied to the gate electrode, and outputs the pixel signal VSL2 output from the amplification transistor AMP2 to the vertical signal line 29B.

Transfer transistors TRG 1 and TRG 2 , switching transistors FDG 1 and FDG 2 , amplification transistors AMP 1 and AMP 2 , selection transistors SEL 1 and SEL 2 , and discharge transistor OFG of pixel 10 are controlled by vertical drive section 22 .

In the pixel of FIG. 2, the additional capacitors FDL1 and FDL2 and the switching transistors FDG1 and FDG2 for controlling their connection may be omitted. can be ensured.

The operation of pixel 10 will be briefly described.

First, before starting light reception, a reset operation for resetting the charges of the pixels 10 is performed in all pixels. That is, the charge discharge transistor OFG, the reset transistors RST1 and RST2, and the switching transistors FDG1 and FDG2 are turned on, and the charges accumulated in the photodiode PD, the floating diffusions FD1 and FD2, and the additional capacitors FDL1 and FDL2 are discharged.

After the accumulated charges are discharged, all pixels start receiving light.

During the light receiving period, the transfer transistors TRG1 and TRG2 are alternately driven. That is, in the first period, the transfer transistor TRG1 is controlled to be ON and the transfer transistor TRG2 is controlled to be OFF. In this first period, charges generated in the photodiode PD are transferred to the floating diffusion FD1. In the second period following the first period, the transfer transistor TRG1 is turned off and the transfer transistor TRG2 is turned on. During this second period, charges generated in the photodiode PD are transferred to the floating diffusion FD2. As a result, charges generated in the photodiode PD are distributed to the floating diffusions FD1 and FD2 and accumulated.

Here, the transfer transistor TRG and the floating diffusion FD from which charges (electrons) obtained by photoelectric conversion are read out are also called active taps. Conversely, the transfer transistor TRG and the floating diffusion FD from which charges obtained by photoelectric conversion are not read out are also called inactive taps.

Then, when the light receiving period ends, each pixel 10 of the pixel array section 21 is selected line-sequentially. In the selected pixel 10, select transistors SEL1 and SEL2 are turned on. As a result, the charge accumulated in the floating diffusion FD1 is output as the pixel signal VSL1 to the column processing section 23 via the vertical signal line 29A. The charge accumulated in the floating diffusion FD2 is output to the column processing section 23 via the vertical signal line 29B as the pixel signal VSL2.

As described above, one light-receiving operation is completed, and the next light-receiving operation starting from the reset operation is executed.

The reflected light received by the pixel 10 is delayed according to the distance to the object from the timing of irradiation by the light source. Since the distribution ratio of the charges accumulated in the two floating diffusions FD1 and FD2 changes depending on the delay time according to the distance to the object, the distribution ratio of the charges accumulated in the two floating diffusions FD1 and FD2 indicates that the object You can find the distance to

<Plan view of pixel>
FIG. 4 is a plan view showing an arrangement example of pixels shown in FIG.

The horizontal direction in FIG. 4 corresponds to the row direction (horizontal direction) in FIG. 1, and the vertical direction corresponds to the column direction (vertical direction) in FIG.

As shown in FIG. 4, a photodiode PD is formed of an N-type semiconductor region 52 in the central region of the rectangular pixel 10 .

A transfer transistor TRG1, a switching transistor FDG1, a reset transistor RST1, an amplification transistor AMP1, and a selection transistor SEL1 are arranged linearly along one of the four sides of the rectangular pixel 10 outside the photodiode PD. A transfer transistor TRG2, a switching transistor FDG2, a reset transistor RST2, an amplification transistor AMP2, and a selection transistor SEL2 are linearly arranged along the other four sides of the rectangular pixel 10 .

Further, a charge discharge transistor OFG is arranged on a side other than the two sides of the pixel 10 on which the transfer transistor TRG, switching transistor FDG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are formed.

Note that the arrangement of the pixels shown in FIG. 3 is not limited to this example, and other arrangements may be used.

<Overview of Frame CDS>
The light receiving device 1 according to the present embodiment outputs four or more types of pixel signals having different phases from each pixel 10 for the purpose of performing distance measurement by the indirect ToF method. Then, the AD conversion section 30 in the light receiving device 1 outputs a digital signal corresponding to the reset level of the pixel signal and a digital signal corresponding to the pixel signal level in units of frames for each phase. By taking the difference between the digital signal corresponding to the reset level and the digital signal corresponding to the pixel signal level, the CDS operation for canceling the reset noise can be performed on a frame-by-frame basis. Such CDS operations are referred to herein as frame CDS.

In the frame CDS, first, with the floating diffusion reset, a digital signal corresponding to the period until the reset level of the pixel signal of the first phase intersects the reference signal level is generated in units of frames. A digital signal corresponding to the period until the pixel signal level of the pixel signal crosses the reference signal level is generated, and the difference between these digital signals is taken to cancel the reset noise. The above operation is repeated for each phase. In the indirect ToF method, distance measurement is performed based on four types of digital signals corresponding to four phases obtained by performing frame CDS.

<Light receiving timing>
FIG. 5 is a signal waveform diagram of four types of pixel signals output from the pixel 10 and having different phases. The signal waveform diagram of FIG. 5 shows an example in which two taps A and B are provided within one pixel 10 . Taps A and B correspond to floating diffusions FD1 and FD2 shown in FIG. FIG. 5 shows the timing of irradiation light emitted by a light emitting unit (not shown) toward an object, the timing of reflected light from the object received by the light receiving device 1, and the charge accumulation timing of taps A and B. is shown.

FIG. 5 shows an example in which taps A and B accumulate electric charges at four different phases of 0°, 90°, 180° and 270°. In the first frame, the charge accumulation timings of the taps A and B are determined based on the timing waveform having a phase of 0° with respect to the timing waveform of the irradiation light. More specifically, the tap A accumulates the charge received from the timing of receiving the reflected light to the timing of ending the irradiation of the irradiation light. The tap B accumulates the charges received during the period from the irradiation end timing of the irradiation light to the reception end timing of the reflected light.

In the second frame, the charge accumulation timings of the taps A and B are determined based on the timing waveform that is out of phase with the timing waveform of the irradiation light by 90°. More specifically, the tap A accumulates the charge received during the period from the rising timing of the timing waveform obtained by shifting the phase of the irradiation light timing waveform by 90° to the end timing of receiving the reflected light. The tap B accumulates charges received during a period from the start timing of receiving the reflected light to the rising timing of the timing waveform whose phase is shifted by 90° from the timing waveform of the irradiation light.

In the third frame, the charge accumulation timings of the taps A and B are determined based on the timing waveform that is 180° out of phase with the timing waveform of the irradiation light. More specifically, the tap A accumulates the electric charges received during the period from the irradiation end timing of the irradiation light to the reception end timing of the reflected light. The tap B accumulates charges received during the period from the start timing of receiving the reflected light to the end timing of the irradiation light.

In the fourth frame, the charge accumulation timings of the taps A and B are determined based on the timing waveform that is 180° out of phase with the timing waveform of the irradiation light. More specifically, the tap A accumulates the charges received during the period from the start timing of receiving the reflected light to the timing shifted by 270° from the end timing of the irradiation light. The tap B accumulates the charge received during the period from the timing when the irradiation end timing of the irradiation light is shifted by 270° to the reception end timing of the reflected light.

The charge A0 accumulated in the tap A of the first frame is expressed by equation (1), and the charge B0 accumulated in the tap B is expressed by equation (2). KA and KB are gains, OA and OB are dark offsets, and ΦG is ambient light.
Ａ0＝KA(Φ0＋ΦG)＋OA …(1)
Ｂ0＝KB(Φ180＋ΦG)＋OB …（2）

A charge A90 accumulated in the tap A of the second frame is expressed by equation (3), and a charge B90 accumulated in the tap B is expressed by equation (4).
Ａ90＝KA(Φ90＋ΦG)＋OA …(3)
Ｂ90＝KB(Φ270＋ΦG)＋OB …(4)

A charge A180 accumulated in the tap A of the third frame is expressed by equation (5), and a charge B180 accumulated in the tap B is expressed by equation (6).
Ａ180＝KA(Φ180＋ΦG)＋OA …（5）
Ｂ180＝KB(Φ0＋ΦG)＋OB …(6)

A charge A180 accumulated in the tap A of the fourth frame is expressed by equation (7), and a charge B180 accumulated in the tap B is expressed by equation (8).
Ａ270＝KA(Φ270＋ΦG)＋OA …（7）
Ｂ270＝KB(Φ90＋ΦG)＋OB …（8）

Here, the I signal and Q signal on the IQ plane used for measuring the distance to the object are represented by the following equations (9) and (10), respectively.
I=(A0-B0)-(A180-B180)=(KA+KB)(Φ0-Φ180) (9)
Q=(A90-B90)-(A270-B270)=(KA+KB)(Φ90-Φ270) (10)

Therefore, the phase shift amount θ between I and Q is calculated by the following equation (11).

The distance D to the object is represented by Equation (12) using Equation (11). Note that Tp is the pulse width.

In this way, by using pixel signals of four phases, the distance to the object can be measured by the equations (11) and (12).

FIG. 5 shows an example of a 2Tap-4Phase scheme that generates four phase signals using two taps A and B. In this embodiment, four taps are used to generate four phase signals. It can also be applied to the light receiving device 1 of the 4Tap-4Phase system. The 4Tap-4Phase type light receiving device 1 has four taps in one pixel 10 . FIG. 6 is a timing chart of the 4Tap-4Phase method. FIG. 6 shows the timing of irradiation light, the timing of reflected light, and the charge accumulation timing of the four taps TRT1 to TRT4.

The tap TRT1 accumulates charges from the reception start timing of the reflected light to the phase timing shifted by 90° from the irradiation start timing of the irradiation light. The tap TRT2 accumulates electric charges from the irradiation end timing of the irradiation light to the reception end timing of the reflected light. The tap TRT3 accumulates charges from the timing of the phase shifted by 90° from the irradiation start timing of the irradiation light to the irradiation end timing of the irradiation light. The tap TRT4 accumulates charges from the timing of the phase shifted by 90° from the irradiation end timing of the irradiation light to the irradiation start timing of the irradiation light.

As described above, the light receiving device 1 according to the present embodiment employs the improved frame CDS as a pixel signal readout method, and there are a plurality of pixel signal readout methods. 7A, 7B, and 7C are diagrams for comparing pixel signal readout methods. FIG. 7A is a diagram for explaining the readout method for only the D phase, FIG. 7B is for DDS, and FIG. 7C is a diagram for explaining the frame CDS readout method. is

Only in FIG. 7A is a method of reading only the D phase. In Only, after performing a global reset (GRST) for resetting the floating diffusion of all the pixels 10, the pixel signal level (D phase) of the first phase (for example, 0°) is read out. Thereafter, similarly, after global reset is performed, the process of reading out the D phase of each phase is repeated four times in total.

The DDS in FIG. 7B resets the floating diffusion after reading the D phase of the first phase (eg, 0°), and then reads the P phase. This process is repeated four times. As described above, the DDS reads the P phase after resetting the floating diffusion after reading the D phase. Reset levels are not always the same. Therefore, even if the difference between the P phase and the D phase is taken, there is a possibility that the reset noise cannot be completely canceled.

In the frame CDS of FIG. 7C, after the global reset is performed, the P-phase readout of the first phase (eg, 0°) is performed, and then the D-phase readout is performed. This series of operations is repeated four times. In the frame CDS, the reset level can be offset by taking the difference between the P phase and the immediately following D phase, but it is necessary to read the pixel signal from the pixel 10 eight times in total.

As described above, the number of readings from the AD converter 30 is four in the DDS, while the number of readings is doubled to eight in the frame CDS. While the integration time for allocating the charge photoelectrically converted by the photodiode PD to the floating diffusion is several hundred microseconds, the readout time from the AD converter 30 requires several milliseconds. Therefore, as the number of readings increases, the time required for distance measurement increases. Thus, an increase in the number of times of reading becomes a rate-limiting issue for the frame rate. Specific measures for solving the above-described problems will be described below.

The I signal and Q signal on the IQ plane are represented by the following equations (13) and (14), respectively.

Here, assuming that equation (15) holds true, the I signal and the Q signal are represented by the following equations (16) and (17), respectively.

The calculation of the I signal and the Q signal shown in equations (16) and (17) may be performed inside the photodetector 1, or may be performed by an application processor (AP) or the like connected to the photodetector 1. .

In the light receiving device 1 according to the present embodiment, part of the calculations of formulas (16) and (17) are performed within the light receiving device 1 . This reduces the number of times the pixel signal is read out from the AD converter 30 . As described above, the normal frame CDS requires eight readouts, while the frame CDS according to this embodiment only requires six readouts.

FIG. 8 is a diagram showing a read sequence according to this embodiment. First, do a global reset. In global reset, all floating diffusions of all pixels 10 are reset. Next, as shown in (1) of FIG. 8, the reset level (P phase) of the pixel signal of the first phase (for example, 0°) is read. Here, a digital signal is generated according to the period until the reset level, which is the signal level of the P-phase signal, crosses the reference signal level, and this digital signal is read out. In the subsequent integration period, the object is irradiated with an optical signal, the reflected light from the object is photoelectrically converted by the photodiode PD in FIG.

After that, as shown in (2) of FIG. 8, the charge is transferred from the photodiode to the floating diffusion corresponding to the first phase, and the D phase is read out. Here, a digital signal is generated according to the period until the pixel signal level crosses the reference signal level, and this digital signal is read out.

Next, reset the floating diffusion corresponding to the second phase (eg, 180°). This reset is called a rolling reset because the floating diffusion is reset for each pixel row (horizontal direction). In this specification, the signal instructing the above-described global reset may be called the first reset signal, and the signal instructing the rolling reset may be called the second reset signal.

The counter 32a in the AD conversion unit 30 resets the count value when the first reset signal is input (at the time of global reset), and resets the count value when the second reset signal is input (at the time of rolling reset). Hold the value.

Next, as shown in (3) of FIG. 8, the reset level (P phase) of the second phase is read. Here, as in (1), a digital signal corresponding to the reset level of the second phase is read.

When performing the processes (2) and (3), the count direction of the counter 32a is made common (for example, the count-up direction), and the length of the period until the pixel signal level or reset level intersects the reference signal level is counted. Measure at 32a. In the frame CDS shown in FIG. 7C, after operating the counter 32a to read out the D phase of the first phase, the count value of the counter 32a is once reset, and then the P phase of the second phase is read out. To do so, run counter 32a. On the other hand, in FIG. 8, while the processes (2) and (3) are being performed, the counting operation of the counter 32a is continued, and after the process (3) is completed, (2) and (3) are output as a digital signal.

As a result, it is not necessary to output a digital signal corresponding to the count value when the process (2) is completed, and the number of readings from the pixels 10 can be reduced.

After the processing of (3) is completed, the charge is transferred from the photodiode PD to the floating diffusion corresponding to the second phase, and the D phase is read out as shown in (4). Then do a global reset.

Next, as shown in (5), the reset level (P phase) of the third phase (for example, 90°) is read. Next, the electric charge is transferred from the photodiode PD to the floating diffusion corresponding to the third phase, and the reading of the D phase shown in (6) is performed. After resetting the floating diffusion corresponding to the fourth phase while leaving the count value of the counter 32a operated for reading the D phase in (6) as it is, the reset level (P phase). At this time, the counter 32a continues counting from the count value after the process of (6). When the processing of (7) is completed, a digital signal obtained by combining the processing of (6) and (7) is output. As a result, there is no need to output a digital signal when the processing of (6) is completed, and the number of times of reading can be reduced.

Next, the electric charge is transferred from the photodiode PD to the floating diffusion corresponding to the fourth phase, and the reading of the D phase of (8) is performed.

Thus, by adopting the readout sequence of FIG. 8, the number of readouts from the AD converter 30 can be reduced by two compared to the frame CDS of FIG. Therefore, the time required for distance measurement can be shortened.

In FIG. 8, the first phase is 0°, the second phase is 180°, the third phase is 90°, and the fourth phase is 270°. Multiple variations are possible.

1. Phase (0°) → Phase (180°) → Phase (90°) → Phase (270°)
2. Phase (180°) → Phase (0°) → Phase (90°) → Phase (270°)
3. Phase (0°) → Phase (180°) → Phase (270°) → Phase (90°)
4. Phase (180°) → Phase (0°) → Phase (270°) → Phase (90°)
5. Phase (90°) → Phase (270°) → Phase (0°) → Phase (180°)
6. Phase (270°) → Phase (90°) → Phase (0°) → Phase (180°)
7. Phase (90°) → Phase (270°) → Phase (180°) → Phase (0°)
8. Phase (270°) → Phase (90°) → Phase (180°) → Phase (0°)

In any one of the above 1 to 8, the frame CDS can be performed with 6 readouts. FIG. 9 is a diagram showing information read by each of the above-mentioned 1 to 8 by reading six times. The above 1 is similar to FIG.

In the case of 2 above, the counter 32a is continuously operated when reading the pixel signal level of phase 180° and the reset level of phase 0° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), the counter 32a is continuously operated when reading the pixel signal level of phase 90° and the reset level of phase 270°, and the processing results of (6) and (7) are summarized. output.

In the case of 3 above, the counter 32a is continuously operated when reading the pixel signal level of phase 0° and the reset level of phase 180° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase 270° and the reset level of phase 90° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 4 above, the counter 32a is continuously operated when reading the pixel signal level of phase 180° and the reset level of phase 0° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase 270° and the reset level of phase 90° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 5 above, the counter 32a is continuously operated when reading the pixel signal level of phase 90° and the reset level of phase 270° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, the counter 32a is continuously operated when reading out the pixel signal level of phase 0° and the reset level of phase 180° in (6) and (7), and the processing results of (6) and (7) are summarized. output.

In the case of 6 above, the counter 32a is continuously operated when reading the pixel signal level of phase 270° and the reset level of phase 90° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, the counter 32a is continuously operated when reading out the pixel signal level of phase 0° and the reset level of phase 180° in (6) and (7), and the processing results of (6) and (7) are summarized. output.

In the case of 7 above, the counter 32a is continuously operated when reading the pixel signal level of phase 90° and the reset level of phase 270° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), the counter 32a is continuously operated when reading the pixel signal level of phase 180° and the reset level of phase 0°, and the processing results of (6) and (7) are summarized. output.

In the case of 8 above, the counter 32a is continuously operated when reading the pixel signal level of phase 270° and the reset level of phase 90° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), the counter 32a is continuously operated when reading the pixel signal level of phase 180° and the reset level of phase 0°, and the processing results of (6) and (7) are summarized. output.

FIGS. 8 and 9 illustrate examples in which the four phases are 0°, 90°, 180°, and 270°, but the phase difference between the four phases may be 90° or 180°, and each phase is not necessarily It need not be a multiple of 90. Therefore, generalizing the above 1 to 8 results in the following 1' to 8'. X is an arbitrary angle.

1'. Phase (X) → Phase (X+180°) → Phase (X+90°) → Phase (X+270°)
2'. Phase (X+180°) → Phase (X) → Phase (X+90°) → Phase (X+270°)
3'. Phase (X) → Phase (X+180°) → Phase (X+270°) → Phase (X+90°)
4'. Phase (X+180°) → Phase (X) → Phase (X+270°) → Phase (X+90°)
5'. Phase (X+90°) → Phase (X+270°) → Phase (X) → Phase (X+180°)
6'. Phase (X+270°) → Phase (X+90°) → Phase (X) → Phase (X+180°)
7'. Phase (X＋90°) → Phase (X+270°) → Phase (X+180°) → Phase (X)
8'. Phase (X+270°) → Phase (X+90°) → Phase (X+180°) → Phase (X)

FIG. 10 is a diagram showing information read by each of 1' to 8' described above in six readings.
In the case of 1′ above, the counter 32a is continuously operated when reading out the pixel signal level of phase X and the reset level of phase X+180° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase X+90° and the reset level of phase X+270° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 2′ above, the counter 32a is continuously operated when reading the pixel signal level of phase X+180° and the reset level of phase X in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase X+90° and the reset level of phase X+270° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 3′ above, the counter 32a is continuously operated when reading out the pixel signal level of phase X and the reset level of phase X+180° in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase X+270° and the reset level of phase X+90° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 4′ above, the counter 32a is continuously operated when reading out the pixel signal level of phase X+180° and the reset level of phase X in (2) and (3), and the processing results of (2) and (3) are are collectively output. Similarly, in (6) and (7), when the pixel signal level of phase X+270° and the reset level of phase X+90° are read out, the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. output.

In the case of 5′ above, when reading out the pixel signal level of phase X+90° and the reset level of phase X+270° in (2) and (3), the counter 32a is continuously operated, and the processing of (2) and (3) is performed. Output the results collectively. Similarly, when reading out the pixel signal level of phase X and the reset level of phase X + 180° in (6) and (7), the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. Output.

In the case of 6′ above, the counter 32a is continuously operated when reading the pixel signal level of phase X+270° and the reset level of phase X+90° in (2) and (3), and the processing of (2) and (3) is performed. Output the results collectively. Similarly, when reading out the pixel signal level of phase X and the reset level of phase X + 180° in (6) and (7), the counter 32a is continuously operated, and the processing results of (6) and (7) are summarized. Output.

In the case of 7′ above, when reading out the pixel signal level of phase X+90° and the reset level of phase X+270° in (2) and (3), the counter 32a is continuously operated, and the processing of (2) and (3) is performed. Output the results collectively. Similarly, when reading out the pixel signal level of phase X+180° and the reset level of phase X in (6) and (7), the counter 32a is continuously operated, and the processing results of (6) and (7) are collectively Output.

In the case of 8′ above, the counter 32a is continuously operated when reading out the pixel signal level of phase X+270° and the reset level of phase X+90° in (2) and (3), and the processing of (2) and (3) is performed. Output the results collectively. Similarly, when reading out the pixel signal level of phase X+180° and the reset level of phase X in (6) and (7), the counter 32a is continuously operated, and the processing results of (6) and (7) are collectively Output.

In this manner, the counter 32a in the AD conversion unit 30 continues to count in the same count direction when reading out the pixel signal level and the reset level that are out of phase by 180°.

FIG. 11 is a detailed timing diagram of the read sequence shown in FIG. The timing diagram of FIG. 11 shows the timing of the first half of FIG. The same timing as in FIG. 11 is repeated in the second half of FIG.

A global reset is performed between times t1 and t2 in FIG. As a result, all floating diffusions in all pixels 10 are set to the reset level. After that, at time t3, the reference signal level, which is a ramp waveform, begins to decrease linearly with time. At this time, the signal line voltage VSL is the reset level (P phase) of the floating diffusion corresponding to the first phase (eg, 0°). The voltage level of the reference signal changes substantially linearly from time t3 to time t5. After time t3, the counter 32a continues counting at a predetermined clock cycle. In this state, the reference signal level is higher than the reset level, so the counter 32a counts down.

When the reset level and the reference signal level cross at time t4, the counter 32a stops counting and outputs a digital signal corresponding to the count value at the time of crossing.

At time t5, the signal level of the reference signal level becomes constant, and the reading of the P-phase signal of the first phase ends.

After that, the CN inversion pulse signal PS output from the system control unit 25 becomes high level during time t6 to t7. When the CN inversion pulse signal PS becomes high level, the counter 32a switches the counting direction when restarting the counting operation thereafter. Since the counter 32a counted down from time t3 to t4, the CN inversion pulse signal PS becomes high level at time t6, so that the counter 32a counts up when restarting the counting operation thereafter. count to.

Between times t8 and t9, the transistors TRG1 and TRG2 in the pixel 10 in FIG. 3 are alternately turned on/off in opposite phases, and charges are distributed from the photodiode to the floating diffusion. Specifically, during the period from time t8 to t9, the pixel signal level of the first phase (eg, 0°) is transferred to each floating diffusion.

After that, the pixel signal level in the first phase is compared with the reference signal level in the comparison circuit section 31 of FIG. 1 based on the accumulated charge of the floating diffusion. The counter 32a continues counting up from time t10 until the pixel signal level crosses the reference signal level.

At time t11, when the pixel signal level crosses the reference signal level, the counter 32a stops counting up. The count value of the counter 32a is not output to the outside at this time. As a result, the number of reading times of pixel data from the light receiving device 1 can be reduced.

Time t13 to t14 is a rolling reset period. During this period, the floating diffusion corresponding to the second phase (eg 180°) is reset. Since the CN inversion pulse signal PS is not output immediately before the rolling reset period, the counting direction of the counter 32a does not change.

After that, during the period from time t15 to t17, reading of the reset level of the second phase is performed. Specifically, the comparison circuit unit 31 compares the reset level and the reference signal level, and the counter 32a counts up from time t15 until the reset level crosses the reference signal level (t15 to t16). take action. Since the CN inversion pulse signal PS did not become the first logic (high level) at the time when the readout of the pixel signal level of the first phase is completed (time t12), the counter 32a continues counting up. Therefore, the count value of the counter 32a is the sum of the pixel signal level of the first phase from time t10 to t11 and the reset level of the second phase from time t15 to t16.

At time t16, the counter 32a stops counting and outputs the count value to the outside as a digital signal.

After that, the CN inversion pulse signal PS goes high during the period from time t18 to t19. Thereby, the counter 32a switches the counting direction. Specifically, the counter 32a switches to the countdown direction.

After that, during time 20 to t21, the transistors TRG1 and TRG2 in the pixels 10 in FIG. 3 are turned on in order for each pixel row, and the charge is distributed from the photodiode PD to the floating diffusion for each pixel row. . Specifically, during the period from time t20 to t21, the pixel signal level of the second phase (eg, 180°) is transferred to the corresponding floating diffusion.

After that, the pixel signal level in the second phase is compared with the reference signal level in the comparison circuit section 31 of FIG. 1 based on the accumulated charge of the floating diffusion. The counter 32a continues the countdown operation from time t22 until the pixel signal level crosses the reference signal level (t22 to t23).

At time t23, when the pixel signal level crosses the reference signal level, the counter 32a stops counting down. A count value of the counter 32 a is output from the light receiving device 1 . After that, at time t24, the reading of the pixel signal level of the second phase (D phase) ends.

In the light receiving device 1 described above, the pixel 10 has a gate structure as shown in FIG. 3, but the pixel 10 may have a CAPD (Current Assisted Photonic Demodulator) structure.

12 shows a cross-sectional view of one pixel 10 provided in the pixel array section 21, and FIG. 13 shows a plan view of the pixel 10. As shown in FIG. 12A shows a cross-sectional view taken along line A-A' of FIG. 13, and B of FIG. 12 shows a cross-sectional view taken along line B-B' of FIG.

As shown in FIG. 12, the pixel 10 has, for example, a silicon substrate, specifically a semiconductor substrate 34 made of a P-type semiconductor layer, and an on-chip lens 35 formed on the semiconductor substrate 34. there is

Further, an inter-pixel light shielding film 36 for preventing color mixture between adjacent pixels 10 is formed on the boundary portion of the pixels 10 on the light incident surface of the semiconductor substrate 34 . The inter-pixel light shielding film 36 prevents the light incident on the pixel 10 from entering another pixel 10 provided adjacently.

A signal extracting portion 37-1 and a signal extracting portion 37-2 are formed on the surface of the semiconductor substrate 34 opposite to the light incident surface, that is, on the inner portion of the lower surface in the figure. The signal extractor 37-1 corresponds to the first tap A in FIG. 1, and the signal extractor 37-2 corresponds to the second tap B in FIG.

The signal extracting portion 37-1 includes an N+ semiconductor region 71-1 that is an N-type semiconductor region, an N- semiconductor region 72-1 that has a lower donor impurity concentration, and a P+ semiconductor region 73- that is a P-type semiconductor region. 1 and a P- semiconductor region 74-1 with a lower acceptor impurity concentration. Here, the donor impurities include, for example, elements belonging to Group 5 of the periodic table of elements such as phosphorus (P) and arsenic (As) for Si, and the acceptor impurities include, for example, Elements belonging to Group 3 in the periodic table of elements such as boron (B) can be mentioned. An element that serves as a donor impurity is called a donor element, and an element that serves as an acceptor impurity is called an acceptor element.

The N− semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 so as to cover (enclose) the N+ semiconductor region 71-1. Similarly, the P− semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 so as to cover (enclose) the P+ semiconductor region 73-1.

In plan view, as shown in FIG. 13, the N+ semiconductor region 71-1 is formed around the P+ semiconductor region 73-1 so as to surround the P+ semiconductor region 73-1. Similarly, the N− semiconductor region 72-1 formed above the N+ semiconductor region 71-1 is formed so as to surround the P− semiconductor region 74-1 with the P− semiconductor region 74-1 as the center. ing.

Similarly, the signal extracting portion 37-2 of FIG. 12 is composed of an N+ semiconductor region 71-2, which is an N-type semiconductor region, an N- semiconductor region 72-2 having a lower donor impurity concentration, and a P-type semiconductor region. It has a P+ semiconductor region 73-2 and a P- semiconductor region 74-2 with a lower acceptor impurity concentration.

The N− semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 so as to cover (enclose) the N+ semiconductor region 71-2. Similarly, the P− semiconductor region 74-2 is formed above the P+ semiconductor region 73-2 so as to cover (enclose) the P+ semiconductor region 73-2.

In plan view, as shown in FIG. 13, the N+ semiconductor region 71-2 is formed around the P+ semiconductor region 73-2 so as to surround the P+ semiconductor region 73-2. Similarly, the N− semiconductor region 72-2 formed above the N+ semiconductor region 71-2 is formed so as to surround the P− semiconductor region 74-2 with the P− semiconductor region 74-2 as the center. ing.

Hereinafter, the signal extraction section 37-1 and the signal extraction section 37-2 are also simply referred to as a signal extraction section 65 when there is no particular need to distinguish between them.

Further, hereinafter, when there is no particular need to distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, the N+ semiconductor region 71 is also simply referred to as the N− semiconductor region 72-1 and the N− semiconductor region 72-2. The N− semiconductor region 72 is also simply referred to when there is no particular need to distinguish it.

Further, hereinafter, when there is no particular need to distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, the P+ semiconductor region 73 is simply referred to as the P− semiconductor region 74-1 and the P− semiconductor region 74-2. The P- semiconductor region 74 is also simply referred to when there is no particular need to distinguish it.

A fixed charge film 75 composed of a single-layer film or a laminated film having a positive fixed charge is formed at the interface of the semiconductor substrate 34 on the light incident surface side. The fixed charge film 75 suppresses generation of dark current on the incident surface side of the semiconductor substrate 34 .

On the other hand, a multilayer wiring layer 91 is formed on the side opposite to the light incident surface side of the semiconductor substrate 34 on which the on-chip lens 35 is formed for each pixel 10 . In other words, the semiconductor substrate 34 as a semiconductor layer is arranged between the on-chip lens 35 and the multilayer wiring layer 91 . The multilayer wiring layer 91 is composed of five layers of metal films M1 to M5 and an interlayer insulating film 92 therebetween. 12A, the outermost metal film M5 of the five metal films M1 to M5 of the multilayer wiring layer 91 is not shown because it is not visible, but it is shown in FIG. 12B. ing.

Among the five metal films M1 to M5 of the multilayer wiring layer 91, the metal film M1 closest to the semiconductor substrate 34 is provided with a predetermined voltage GDA or GDB for applying a predetermined voltage GDA or GDB to the P+ semiconductor region 73-1 or 73-2. A voltage application wiring 93 and a reflecting member 94, which is a member that reflects incident light, are included.

In addition, the metal film M1 is connected to a part of the N+ semiconductor region 71, which is the charge detection portion, in addition to the voltage application wiring 93 for applying a predetermined voltage GDA or GDB to the P+ semiconductor region 73, which is the voltage application portion. A signal take-out wiring 95 is formed. The signal output wiring 95 transmits charges detected in the N+ semiconductor region 71 to the FD 102 .

As shown in FIG. 12B, the signal extraction part 37-2 (second tap B) is connected to the voltage application wiring 93 of the metal film M1, and the voltage application wiring 93 is connected to the metal film M4 through vias. is electrically connected to the wiring 96-2 of . The wiring 96-2 of the metal film M4 is connected via a via to the control line 23B of the metal film M5, and the control line 23B of the metal film M5 is connected to the tap driving section 12. FIG. As a result, a predetermined voltage GDB is applied from the tap driving section 12 via the control line 23B of the metal film M5, the wiring 96-2 of the metal film M4, and the voltage applying wiring 93 to the P+ semiconductor region 73- as the voltage applying section. 2.

Similarly, in a region (not shown) of the pixel 10, a predetermined voltage GDA is applied from the tap drive unit 12 via the control line 23A of the metal film M5, the wiring 96-1 of the metal film M4, and the voltage application wiring 93 to the signal It is supplied to the P+ semiconductor region 73-1 as the voltage application section of the lead-out section 37-1 (first tap A).

The N+ semiconductor region 71 provided on the semiconductor substrate 34 functions as a charge detection unit for detecting the amount of light incident on the pixel 10 from the outside, that is, the amount of signal charge generated by photoelectric conversion by the semiconductor substrate 34. . In addition to the N+ semiconductor region 71, the N- semiconductor region 72 having a low donor impurity concentration can also be regarded as the charge detection portion.

In addition, the P+ semiconductor region 73 functions as a voltage application section for injecting a large number of carrier currents into the semiconductor substrate 34, that is, for applying a voltage directly to the semiconductor substrate 34 to generate an electric field in the semiconductor substrate 34. . In addition to the P+ semiconductor region 73, the P− semiconductor region 74 having a low acceptor impurity concentration can also be regarded as the voltage applying portion.

In a plan view of FIG. 13, the signal extracting portion 65 has a P+ semiconductor region 73 as a voltage application portion arranged in the center and an N+ semiconductor region 71 as a charge detection portion arranged so as to surround it. .

As shown in FIG. 13, the signal extraction units 37-1 and 37-2 are arranged in the pixel 10 at symmetrical positions with respect to the center of the pixel 10. As shown in FIG. In FIG. 13, the planar shapes of the N+ semiconductor region 71 and the P+ semiconductor region 73 are octagonal, but they may be square, rectangular, circular, or other planar shapes.

<Technical Effects of Photodetector 1>
As described above, in the light receiving device 1 according to the present embodiment, when the digital signals corresponding to the pixel signals of four phases or more are output from the AD converter 30, the number of times of outputting the digital signals from the AD converter 30 is reduced. , a digital signal of four or more phases can be used to rapidly measure a distance.

In this embodiment, part of the processing for calculating the I signal and the Q signal used for distance measurement is performed within the AD converter 30, so the number of digital signals output from the AD converter 30 is reduced. be able to.

More specifically, in the light-receiving device 1 according to the present embodiment, the reset level and the pixel signal level of the pixel signals that are 180° out of phase are continuous in order to solve the problem of the large number of readouts in the frame CDS. When the data is read out, the counting direction of the counter 32a for generating the digital signal is set to be the same, and the counting operation is continuously performed. Accordingly, each time a digital signal of the reset level or pixel signal level of each phase is generated, the generated digital signal is not output, but a digital signal combining the reset level and the pixel signal level is output. Therefore, it is possible to output from the AD conversion unit 30 a digital signal that is the result of part of the calculation processing for obtaining the I signal and the Q signal inside the AD conversion unit 30. Distance measurement on the side can be performed quickly.

<Electronic device for distance measurement>
FIG. 14 is a block diagram showing a schematic configuration of an electronic device 2 that includes the light receiving device 1 shown in FIGS. 1 to 13 and performs distance measurement by the indirect ToF method. The electronic device 2 of FIG. 14 includes the light emitting section 3, the light receiving device 1 shown in FIGS. 1 to 13, and the distance measuring section 4. The electronic device 2 in FIG. 14 is, for example, a smart phone. Alternatively, the electronic device 2 in FIG. 14 may be a mobile phone, a tablet, a mobile PC (Personal Computer) carried by the user, or a vehicle.

The light emitting unit 3 intermittently transmits an irradiation light pulse signal at a predetermined cycle. When the irradiation light pulse signal is reflected by the object 5, the light receiving device 1 receives the reflected light. The light receiving device 1 outputs a digital signal by the frame CDS shown in FIG. 8, as described above. The distance measurement unit 4 measures the distance to the object 5 by the indirect ToF method based on the digital signal output from the light receiving device 1 .

<Example of application to a moving object>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may

FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

Vehicle control system 12000 comprises a plurality of electronic control units connected via communication network 12001 . In the example shown in FIG. 15 , vehicle control system 12000 includes drive system control unit 12010 , body system control unit 12020 , vehicle exterior information detection unit 12030 , vehicle interior information detection unit 12040 , and integrated control unit 12050 . Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.

Drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.

Body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

External information detection unit 12030 detects information external to the vehicle in which vehicle control system 12000 is mounted. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.

The vehicle interior information detection unit 12040 detects vehicle interior information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.

The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicle, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of

In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12030 based on information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.

The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 15, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 16 is a diagram showing an example of the installation position of the imaging unit 12031. As shown in FIG.

In FIG. 16, imaging units 12101, 12102, 12103, 12104, and 12105 are provided as the imaging unit 12031. In FIG.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

Note that FIG. 16 shows an example of the imaging range of the imaging units 12101 to 12104 . The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the light receiving device 1 of the present disclosure can be applied to the imaging unit 12031 . By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a clearer captured image, thereby reducing driver fatigue.

In addition, this technique can take the following structures.
(1) A photoelectric conversion unit, two or more floating diffusions for accumulating charges photoelectrically converted by the photoelectric conversion units at different timings, and a charge accumulated in the two or more floating diffusions. a plurality of pixels that output four or more types of pixel signals with different phases;
an AD conversion unit that outputs a digital signal corresponding to the reset level of the pixel signal and a digital signal corresponding to the pixel signal level for each phase of the four or more types of pixel signals in frame units. .
(2) The light receiving device according to (1), wherein the AD converter outputs the digital signal obtained by synthesizing part of the reset level and the pixel signal level that are out of phase with each other.
(3) a counter that outputs a count value corresponding to a period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level;
The light receiving device according to (1) or (2), wherein the AD converter generates the digital signal according to the count value of the counter.
(4) The counter continues counting without resetting the count value of the counter at some switching timings among a plurality of switching timings at which the phases of the four or more types of pixel signals are switched, and at remaining switching timings. The light receiving device according to (3), wherein the count value of the counter is reset at the timing.
(5) the partial switching timing is a switching timing for counting count values for pixel signals with phases different by 180°;
The light-receiving device according to (4), wherein the remaining switching timings are switching timings for counting count values for pixel signals having phases different by 90°.
(6) The partial switching timings are, where X is an arbitrary angle value, the switching timing between the pixel signal level of X° and the reset level of X+180°, and the pixel signal level of X+90° and the reset level of X+270°. The light receiving device according to (5), including the switching timing of.
(7) The counter resets the count value and resets a part of the floating diffusions when a first reset signal instructing resetting of all the floating diffusions for all pixels is input. The light receiving device according to any one of (4) to (6), which holds the count value when a second reset signal instructing is input.
(8) the second reset signal is input at the partial switching timing;
The light receiving device according to (7), wherein the first reset signal is input at the remaining switching timing.
(9) The light receiving device according to any one of (3) to (8), wherein the counter switches between counting up and counting down based on an external control signal.
(10) When the control signal is the first logic, the counter reverses the count direction when the phase of the input pixel signal is switched, and the control signal is the second logic. In the case of , the light receiving device according to (9), wherein when the phase of the input pixel signal is switched, the counter continues counting without changing the counting direction.
(11) the pixel switches between reset levels and pixel signal levels of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase, and sequentially outputs the pixel signals;
Based on the control signal, the counter counts a count value corresponding to the reset level of one pixel signal and a count value corresponding to the pixel signal level of the other pixel signal out of two pixel signals having phases different from each other by 180°. The light receiving device according to (9) or (10), which generates a count value by summing the value.
(12) The counter outputs a count value corresponding to the reset level of the first phase based on the control signal, and then outputs a count value corresponding to the pixel signal level of the first phase and the second phase. Then, the count value corresponding to the pixel signal level of the second phase is output, and then the count value corresponding to the reset level of the third phase is output. Next, a count value obtained by summing the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase is output, and then the count value of the fourth phase is output. The light receiving device according to (11), which outputs a count value corresponding to a pixel signal level.
(13) The counter changes the direction of counting up or down when adding the count value corresponding to the pixel signal level of the first phase and the count value corresponding to the reset level of the second phase. (12) without changing the count-up or count-down direction when adding the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase; A photodetector as described.
(14) before the counter starts counting the period until the reset level of the first phase crosses the reference signal level and until the reset level of the third phase crosses the reference signal level; resetting the count value before starting counting for the period of the first phase, the reset level and pixel signal level of the second phase, and the pixel signal level of the third phase The light receiving device according to (12) or (13), wherein the counting is continued without resetting the count value before starting counting for each period until the reference signal level is crossed.
(15) The first phase and the second phase are different in phase by 180°, the second phase and the third phase are different in phase by 90°, and the third phase and the fourth phase are different. The light receiving device according to any one of (11) to (14), which is 180° out of phase with the .
(16) The control signal is applied to the first logic after the counter generates count values corresponding to the reset levels of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase. output the pulse signal of, other than that is the second logic,
The counter switches the count direction to count when the control signal is the first logic, and continues counting while maintaining the count direction when the control signal is the second logic. 11) The light receiving device according to any one of items 15 to 15.
(17) The light receiving device according to any one of (1) to (16), wherein the pixel has a CAPD (Current Assisted Photonic Demodulator) structure and a gate electrode structure.
(18) a light emitting unit that emits an optical signal toward an object;
The optical signal has the photoelectric conversion unit that receives reflected light reflected by the object (the light receiving device according to any one of 1 to 17;
An electronic device, comprising: a distance measuring unit that measures a distance to the object based on the digital signal output from the light receiving device and the optical signal.
(19) The distance measurement unit generates an I signal and a Q signal based on the reset level and the pixel signal level of the four or more types of pixel signals, and calculates the target based on the ratio of the I signal and the Q signal. The electronic device according to (18), which measures a distance to an object.
(20) outputting four or more types of pixel signals with different phases for each pixel based on the charges accumulated in two or more floating diffusions that accumulate charges photoelectrically converted by the photoelectric conversion unit at different timings;
When counting the length of the period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level with a counter, a plurality of switching in which the phases of the four or more types of pixel signals are switched. A method of receiving light, comprising continuing counting without resetting the count value of the counter at part of switching timings, and resetting the count value of the counter at remaining switching timings.

Aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.

1 light receiving device, 2 electronic device, 3 light emitting unit, 4 distance measuring unit, 5 object, 10 pixels, 11 pixel array unit, 12 tap driving unit, 18 reference signal generating unit, 21 pixel array unit, 22 vertical driving unit, 23 column processing unit, 23A control line, 23B control line, 24 horizontal driving unit, 25 system control unit, 26 signal processing unit, 27 data storage unit, 28 pixel driving line, 29 vertical signal line, 30 AD conversion unit, 31 comparison Circuit part 31a Comparison circuit 32 Counter part 32a Counter (CNT) 34 Semiconductor substrate 35 On-chip lens 36 Inter-pixel light shielding film 41 Semiconductor substrate 42 Multilayer wiring layer 43 Antireflection film 44 Pixel boundary part , 45 inter-pixel light-shielding film, 46 planarizing film, 47 on-chip lens, 51 semiconductor region, 52 semiconductor region, 53 hafnium oxide film, 54 aluminum oxide film, 55 silicon oxide film, 61 inter-pixel separation section, 62 interlayer insulating film , 63 light shielding member 64 wiring capacitance 71 semiconductor region 75 fixed charge film 91 multilayer wiring layer 92 interlayer insulating film 93 voltage application wiring 94 reflecting member

Claims (20)

a photoelectric conversion unit; two or more floating diffusions for accumulating charges photoelectrically converted by the photoelectric conversion units at different timings; and a phase based on the charges accumulated in the two or more floating diffusions. a plurality of pixels that output four or more different types of pixel signals;
an AD conversion unit that outputs a digital signal corresponding to the reset level of the pixel signal and a digital signal corresponding to the pixel signal level for each phase of the four or more types of pixel signals in frame units. . 2. The light receiving device according to claim 1, wherein said AD converter outputs said digital signal obtained by synthesizing part of a reset level and a pixel signal level having phases different from each other. a counter that outputs a count value corresponding to a period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level;
2. The light receiving device according to claim 1, wherein said AD converter generates said digital signal corresponding to the count value of said counter. The counter continues counting without resetting the count value of the counter at some switching timings among a plurality of switching timings at which the phases of the four or more types of pixel signals are switched, and at the remaining switching timings, 4. The light receiving device according to claim 3, wherein the count value of said counter is reset. The partial switching timing is a switching timing for counting count values for pixel signals with phases different by 180°,
5. The light-receiving device according to claim 4, wherein said remaining switching timings are switching timings for counting count values for pixel signals having phases different by 90 degrees. When X is an arbitrary angle value, the partial switching timing is the switching timing between the pixel signal level of X° and the reset level of X+180°, and the switching timing of the pixel signal level of X+90° and the reset level of X+270°. 6. The photodetector of claim 5, comprising: The counter resets the count value when a first reset signal instructing resetting of all the floating diffusions for all pixels is input, and instructs resetting of some of the floating diffusions. 5. The light receiving device according to claim 4, which holds the count value when the second reset signal is input. The second reset signal is input at the partial switching timing,
8. The light receiving device according to claim 7, wherein said first reset signal is input at said remaining switching timing. 4. The light receiving device according to claim 3, wherein said counter switches between counting up and counting down based on an external control signal. When the control signal is the first logic, the counter reverses the count direction when the phase of the input pixel signal is switched, and counts when the control signal is the second logic. 10. The light receiving device according to claim 9, wherein the counter continues counting without changing the counting direction when the phase of the input pixel signal is switched. The pixels switch between a reset level and a pixel signal level of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase, and sequentially output the pixel signals;
Based on the control signal, the counter counts a count value corresponding to the reset level of one pixel signal and a count value corresponding to the pixel signal level of the other pixel signal out of two pixel signals having phases different from each other by 180°. 10. The light receiving device according to claim 9, wherein a count value is generated by summing the values. The counter outputs a count value corresponding to the reset level of the first phase based on the control signal, then outputs a count value corresponding to the pixel signal level of the first phase and the reset level of the second phase. Then output a count value corresponding to the pixel signal level of the second phase, and then output a count value corresponding to the reset level of the third phase. Then, a count value obtained by summing the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase is output, and then the pixel signal level of the fourth phase is output. 12. The light-receiving device according to claim 11, which outputs a count value according to . The counter does not change the direction of counting up or down when adding the count value corresponding to the pixel signal level of the first phase and the count value corresponding to the reset level of the second phase. 13. The light receiving according to claim 12, wherein when adding the count value corresponding to the pixel signal level of the third phase and the count value corresponding to the reset level of the fourth phase, the direction of counting up or counting down is not changed. Device. Before the counter starts counting for the period until the reset level of the first phase crosses the reference signal level, and for the period until the reset level of the third phase crosses the reference signal level. and resetting the count value before starting the counting of the reference signal. 13. The light receiving device according to claim 12, wherein counting is continued without resetting the count value before starting counting for each period until the level crosses. The first phase and the second phase are different in phase by 180°, the second phase and the third phase are different in phase by 90°, and the third phase and the fourth phase are different by 180°. 12. The photodetector of claim 11, wherein the phases are different. The control signal is a first logic pulse signal after the counter generates a count value corresponding to the reset level of the pixel signals of the first phase, the second phase, the third phase, and the fourth phase. is output, and the rest is the second logic,
The counter switches the counting direction to count when the control signal is the first logic, and continues counting while maintaining the counting direction when the control signal is the second logic. Item 12. The light receiving device according to item 11. 2. The light receiving device according to claim 1, wherein said pixel has a CAPD (Current Assisted Photonic Demodulator) structure and a gate electrode structure. a light emitting unit that emits an optical signal toward an object;
18. The light receiving device according to any one of claims 1 to 17, wherein the optical signal includes the photoelectric conversion unit that receives reflected light reflected by the object;
An electronic device, comprising: a distance measuring unit that measures a distance to the object based on the digital signal output from the light receiving device and the optical signal. The distance measuring unit generates an I signal and a Q signal based on the reset level and the pixel signal level of the four or more types of pixel signals, and measures the distance to the object based on the ratio of the I signal and the Q signal. 19. The electronic device according to claim 18, which measures distance. outputting four or more types of pixel signals having different phases for each pixel based on charges accumulated in two or more floating diffusions that accumulate charges photoelectrically converted by the photoelectric conversion unit at different timings;
When counting the length of the period until the reset level or pixel signal level of each of the four or more types of pixel signals crosses the reference signal level with a counter, a plurality of switching in which the phases of the four or more types of pixel signals are switched. A method of receiving light, comprising continuing counting without resetting the count value of the counter at part of switching timings, and resetting the count value of the counter at remaining switching timings.

Images