JP2023002041A - Switching power supply device - Google Patents

Abstract

To adjust drive capability of a drive circuit according to electrical characteristics of a switching element in a switching power supply device.SOLUTION: A switching power supply device according to an embodiment comprises a switching transistor and a gate driver circuit. The gate driver circuit is connected to a gate of the switching transistor, and when the switching transistor is turned on, gate current is supplied to the switching transistor. The gate driver circuit is configured such that on-resistance of an output transistor flowing the gate current can be changed.SELECTED DRAWING: Figure 1

Description

Embodiments of the present specification relate to switching power supplies.

2. Description of the Related Art Conventionally, a switching power supply device is known as a synchronous rectification type DC-DC converter. For example, a switching power supply uses a PWM (Pulse Width Modulation) method and drives a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a switching element by a drive circuit.

JP-A-6-053800

However, when the driving capability of the drive circuit becomes excessive with respect to the electrical characteristics of the switching element such as the gate capacitance of the MOSFET, switching noise may occur as the gate capacitance is rapidly charged. When switching noise occurs, the EMI (ElectroMagnetic Interference) performance of the switching power supply deteriorates.

For example, by inserting a resistor in series with the bootstrap capacitor, the power supply output capability of the drive circuit is adjusted, and the rise of the gate-source voltage when the MOSFET is on, that is, the drive capability of the drive circuit is relaxed. EMI performance can be improved. On the other hand, when trying to relax the driving capability of the drive circuit by inserting a resistor into the bootstrap circuit, EMI countermeasures for each electrical characteristic of the switching element, such as selecting a resistor according to the electrical characteristics of the switching element. was necessary.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching power supply device capable of adjusting the drive capability of a drive circuit in accordance with the electrical characteristics of switching elements.

To solve the above-described problems and achieve the object, a switching power supply device according to an embodiment includes a switching transistor and a gate driver circuit. The gate driver circuit is connected to the gate of the switching transistor and supplies a gate current to the switching transistor when turning on the switching transistor. The gate driver circuit is configured such that the ON resistance of the output transistor through which the gate current flows can be changed.

According to the present invention, in the switching power supply device, it is possible to adjust the drive capability of the drive circuit according to the electrical characteristics of the switching element.

FIG. 1 is a diagram showing an example of the configuration of a switching power supply device according to an embodiment. FIG. 2 is a diagram showing an example of gate drive waveforms of the NMOS main power transistor in the switching power supply device of FIG. FIG. 3 is a diagram for explaining the drive mechanism of the NMOS main power transistor in the switching power supply device of FIG. FIG. 4 is a diagram showing an example of the configuration of a switching power supply device that adjusts the drive capability of a high-side driver circuit by inserting a resistor connected in series with a bootstrap capacitor, unlike the switching power supply device according to the embodiment. be. FIG. 5 is a diagram for explaining adjustment of the drive capability of the high side driver circuit by the switching power supply device of FIG.

Hereinafter, embodiments of a switching power supply device will be described in detail with reference to the drawings. In the following embodiments, it is assumed that parts denoted by the same reference numerals perform the same operations, and overlapping descriptions will be omitted as appropriate. In the following embodiments, "connection" means "electrical connection".

FIG. 1 is a diagram showing an example of a configuration of a switching power supply device 1 according to an embodiment. A switching power supply device 1 in FIG. 1 is a switching power supply circuit as a synchronous rectification step-down DC-DC converter.

The switching power supply device 1 has a control circuit 3, a main circuit 5 and a bootstrap circuit 7, as shown in FIG. The switching power supply device 1 outputs a DC output voltage VOUT set according to a load connected to an output terminal OUT using an input voltage VIN which is a DC voltage supplied from a power supply 9 to an input terminal IN. configured to supply to

A power supply 9 is an external power supply for supplying an input voltage VIN to the input terminal IN of the switching power supply device 1 . One end of the power supply 9 is connected to the terminal VDD and the terminal VPIN via the input terminal IN. The other end of power supply 9 is connected to the ground potential.

The load connected to the output terminal OUT is a circuit that operates using the output voltage VOUT from the output terminal OUT, and arbitrary circuit elements or circuit configurations can be used as appropriate. A load is connected in parallel with the capacitor COUT of the main circuit 5 .

The control circuit 3 alternately controls conduction of the NMOS main power transistor _THS1 and the NMOS rectification power transistor _TLS1 , so that when power is supplied to the load using the input voltage VIN input from the terminal VPIN, Based on the feedback output voltage VOUT, control is performed to maintain the output voltage VOUT at a predetermined voltage value. A terminal GND and a terminal PGND of the control circuit 3 are each connected to a ground potential.

As shown in FIG. 1, the control circuit 3 includes a regulator circuit 31, a PWM (Pulse Width Modulation) conversion circuit 32, a dead time control circuit 33, an OTPROM 34, a driver capability selection circuit 38, a bootstrap diode DIO, a level shift circuit 35H, 35L and main driver circuits 36H and 36L.

The regulator circuit 31 is a power supply circuit that supplies two constant voltages to the internal circuit of the control circuit 3 using the input voltage VIN supplied from the terminal VDD. One end of the regulator circuit 31 is connected to the terminal VDD.

The PWM conversion circuit 32 adjusts the duty for controlling the operations of the NMOS main power transistor _THS1 and the NMOS rectification power transistor _TLS1 so that the output voltage VOUT of the output terminal OUT fed back to the terminal FB becomes the target voltage. PWM signal is output. The PWM conversion circuit 32 is connected to the output end of the regulator circuit 31, the output end of the OTPROM 34, and the terminal GND.

The dead time control circuit 33 outputs a signal added with dead time as a delay time based on the PWM signal from the PWM conversion circuit 32 . Here, the dead time is a period during which both the NMOS main power transistor _THS1 and the NMOS rectifying power transistor _TLS1 are turned off simultaneously. The dead time control circuit 33 is connected to the output end of the regulator circuit 31, the output end of the PWM signal of the PWM conversion circuit 32, and the terminal GND.

The OTPROM 34 sets the oscillation frequency of the PWM signal output from the PWM conversion circuit 32 and the voltage value of the output voltage VOUT according to the adjustment data set via the terminal DATA from the outside of the switching power supply device 1. The on/off control of the plurality of switches DSW is adjustable via the driver capability selection circuit 38 . The OTPROM 34 is connected to the terminal DATA, the input end of the driver capability selection circuit 38 and the input end of the PWM conversion circuit 32 .

The driver capability selection circuit 38 outputs signals for controlling a plurality of switches DSW, which will be described later, according to signals from the OTPROM 34 . The driver capability selection circuit 38 is connected to the cathode of the bootstrap diode DIO, the output terminal of the OTPROM 34 and the terminal SW.

The bootstrap diode DIO charges the capacitor CBOOT from the regulator circuit 31 via the terminal BOOT when the voltage of the terminal SW is Low, and reverses the current from the terminal BOOT to the regulator circuit 31 when the voltage of the terminal SW is High. It is a diode that prevents The anode of the bootstrap diode DIO is connected to the output terminal of the regulator circuit 31 . The cathode of bootstrap diode DIO is connected to terminal BOOT of control circuit 3 .

The high-side level shift circuit 35H outputs a signal corresponding to the signal from the dead time control circuit 33 based on the voltage across the capacitor CBOOT. The high-side level shift circuit 35H is connected to the cathode of the bootstrap diode DIO, the output terminal of the dead time control circuit 33, and the terminal SW.

The low-side level shift circuit 35L outputs a signal corresponding to the signal from the dead time control circuit 33 based on one voltage of the regulator circuit 31 . The low-side level shift circuit 35L is connected to the two output terminals of the regulator circuit 31, the output terminal of the dead time control circuit 33, the anode of the bootstrap diode DIO, the terminal GND and the terminal PGND.

The high-side main driver circuit 36H outputs a signal corresponding to the signal from the high-side level shift circuit 35H to the gate of the NMOS main power transistor _THS1 of the main circuit 5 via the terminal GATE_HS. Specifically, the high-side main driver circuit 36H supplies gate current to the NMOS main power transistor _THS1 when turning on the NMOS main power transistor _THS1 . Here, as an example of a gate driver circuit, the high-side main driver circuit 36H includes a high-side pre-driver circuit 37H, a plurality of PMOS transistors T _HS2 , a plurality of switches DSW and an NMOS transistor T _HS3 as shown in FIG. have

The high-side pre-driver circuit 37H outputs a signal corresponding to the signal from the high-side level shift circuit 35H to the gates of the plurality of PMOS transistors _THS2 and the gate of the NMOS transistor _THS3 through the plurality of switches DSW. do. The high-side predriver circuit 37H is connected to the output end of the high-side level shift circuit 35H, the cathode of the bootstrap diode DIO, and the terminal SW.

The plurality of PMOS transistors _THS2 are high-side transistors in the high-side main driver circuit 36H. The plurality of PMOS transistors _THS2 includes three PMOS transistors, a first PMOS transistor _THS21 , a second PMOS transistor _THS22 and a third PMOS transistor _THS23 , in the example shown in FIG. A plurality of PMOS transistors _THS2 are connected in parallel with each other. Each of the plurality of PMOS transistors _THS2 can be enabled or disabled independently of each other by a plurality of switches DSW. That is, it is possible to individually set whether or not each of the plurality of PMOS transistors _THS2 is driven by the high-side predriver circuit 37H.

Each of the plurality of switches DSW can be set to ON/OFF by the OTPROM 34, for example. The multiple switches DSW include three switches, a first switch DSW1, a second switch DSW2, and a third switch DSW3, in the example shown in FIG. One end of each switch DSW is connected to the gates of the first PMOS transistor _THS21 , the second PMOS transistor _THS22 and the third PMOS transistor _THS23 , and the other end of the three switches DSW is a high-side pre-driver circuit. 37H output terminal.

It will be described later which one of the plurality of PMOS transistors _THS2 is selected as the output transistor through which the gate current flows when the NMOS main power transistor _THS1 is turned on by turning on/off the plurality of switches DSW. , the on-resistance is appropriately determined according to the electrical characteristics of the NMOS main power transistor _THS1 , for example. In this way, the high-side main driver circuit 36H can change the on-resistance of the output transistor composed of the selected PMOS transistor by appropriately determining the PMOS transistor through which the gate current flows among the plurality of PMOS transistors _THS2 . configured to

As an example, the plurality of PMOS transistors _THS2 have different on-resistance values.

As another example, at least two PMOS transistors among the plurality of PMOS transistors _THS2 have different on-resistance values.

As another example, the plurality of PMOS transistors _THS2 have the same on-resistance.

In this embodiment, as shown in FIG. 1, three PMOS transistors _THS21 , _THS22 , and _THS23 are illustrated as the plurality of PMOS transistors _THS2 , but the present invention is not limited to this. The number of PMOS transistors included in the plurality of PMOS transistors _THS2 may be two, or may be four or more.

Each gate of the plurality of PMOS transistors _THS2 is connected to the output terminal of the high-side pre-driver circuit 37H via a plurality of switches DSW. Each source of a plurality of PMOS transistors _THS2 is connected to the cathode of bootstrap diode DIO and terminal BOOT. Each drain of a plurality of PMOS transistors _THS2 is connected to the drain of NMOS transistor _THS3 and terminal GATE_HS.

The gate of the NMOS transistor _THS3 is connected to the output terminal of the high side pre-driver circuit 37H. The source of NMOS transistor _THS3 is connected to terminal SW.

The low-side main driver circuit 36L outputs a signal corresponding to the signal from the low-side level shift circuit 35L to the gate of the NMOS rectifying power transistor _TLS1 of the main circuit 5 via the terminal GATE_LS. The low-side main driver circuit 36L, as shown in FIG. 1, has a low-side pre-driver circuit 37L, a PMOS transistor _TLS2 and an NMOS transistor _TLS3 .

The low-side pre-driver circuit 37L outputs a signal corresponding to the signal from the low-side level shift circuit 35L to the gates of the PMOS transistor _TLS2 and the NMOS transistor _TLS3 . The low-side pre-driver circuit 37L is connected to the output terminal of the low-side level shift circuit 35L, the output terminal of the regulator circuit 31, and the terminal PGND.

The gate of the PMOS transistor _TLS2 is connected to the output terminal of the low-side pre-driver circuit 37L. The source of PMOS transistor _TLS2 is connected to the output terminal of regulator circuit 31 . The drain of PMOS transistor _TLS2 is connected to the drain of NMOS transistor _TLS3 and terminal GATE_LS.

The gate of the NMOS transistor _TLS3 is connected to the output end of the low-side predriver circuit 37L. The source of NMOS transistor _TLS3 is connected to terminal PGND.

The main circuit 5 is the main circuit of the switching power supply device 1 as a synchronous rectification step-down DC-DC converter. The main circuit 5, as shown in FIG. 1, has an NMOS main power transistor _THS1 , an NMOS rectifying power transistor _TLS1 , an inductor LOUT and a capacitor COUT. Here, the NMOS main power transistor _THS1 is an example of a switching transistor.

The gate of NMOS main power transistor _THS1 is connected to terminal GATE_HS of control circuit 3 . The source of NMOS main power transistor _THS1 is connected to the drain of NMOS rectifier power transistor _TLS1 . The source of the NMOS main power transistor _THS1 and the drain of the NMOS rectifying power transistor _TLS1 are connected to the output terminal OUT through the inductor LOUT and to the terminal SW. The drain of NMOS main power transistor _THS1 is connected to input terminal IN through terminal VPIN.

The gate of NMOS rectifying power transistor _TLS1 is connected to terminal GATE_LS of control circuit 3 . The source of NMOS rectifier power transistor _TLS1 is connected to terminal PGND.

The inductor LOUT is a choke coil that accumulates power and releases the accumulated power to the terminal SW side of the control circuit 3 or the output terminal OUT side. The capacitor COUT is a capacitive element that stores charge supplied from the terminal SW of the control circuit 3 via the inductor LOUT. One end of the capacitor COUT is connected to the terminal SW through the inductor LOUT and also to the output terminal OUT. The other end of capacitor COUT is connected to terminal PGND. The output voltage VOUT is provided to a load connected across the capacitor COUT.

The bootstrap circuit 7 has a capacitor CBOOT. The capacitor CBOOT is a capacitive element that stores charge supplied from the regulator circuit 31 via the bootstrap diode DIO when the voltage of the terminal SW is Low. A gate-source voltage Vgs higher than the drain voltage can be obtained in the NMOS main power transistor _THS1 by the capacitor CBOOT, so that the NMOS main power transistor _THS1 can be reliably turned on. One end of the capacitor CBOOT is connected to the terminal BOOT. The other end of the capacitor CBOOT is connected to the source of the NMOS main power transistor _THS1 and one end of the inductor LOUT on the terminal SW side.

Here, an example of the operation of the switching power supply device 1 according to the embodiment will be described with reference to the drawings. FIG. 2 is a diagram showing an example of gate drive waveforms of the NMOS main power transistor _THS1 in the switching power supply device 1 of FIG. FIG. 2 further illustrates the operating waveforms of the signal at terminal SW. FIG. 2 magnifies and illustrates when the NMOS main power transistor _THS1 transitions from off to on. FIG. 3 is a diagram for explaining the drive mechanism of the NMOS main power transistor _THS1 in the switching power supply device 1 of FIG.

FIG. 3 illustrates capacitors CHS11 and CHS12 as gate capacitances of NMOS main power transistor _THS1 . Capacitor CHS11 is a parasitic capacitance between the gate and drain of NMOS main power transistor _THS1 . Capacitor CHS12 is a parasitic capacitance between the gate and source of NMOS main power transistor _THS1 . In FIG. 3, it is assumed that the source of the NMOS main power transistor _THS1 is at the GND potential for the sake of simplicity of explanation.

First, the first stage S1 in FIG. 2 will be described. The first region, as shown in FIG. 3, is the stage of charging the gate capacitance of the NMOS main power transistor _THS1 by the high side main driver circuit 36H. At this time, the NMOS main power transistor _THS1 is off and the drain voltage remains High.

The second stage S2 is the stage when the gate-source voltage Vgs of the NMOS main power transistor _THS1 exceeds the threshold. That is, the NMOS main power transistor _THS1 is turned on, so that the drain voltage transitions from high to low. At this time, due to the Miller effect of the capacitor CHS11 between the gate and the drain, the charge charged in the gate capacitance increases. In this way, since the charge charged in the gate capacitance increases, the gate voltage does not increase and remains constant.

The third stage S3 is the stage in which the gate capacitance of the NMOS main power transistor _THS1 is further charged from the second stage S2 and the gate voltage is maximized. When the gate voltage reaches the maximum, charging of the gate capacitance by the high-side main driver circuit 36H is stopped.

Here, unlike the switching power supply device 1 according to the present embodiment, in the high-side main driver circuit 36H, among the first PMOS transistor _THS21 , the second PMOS transistor _THS22 , and the third PMOS transistor _THS23 , Consider the case where only one PMOS transistor is provided.

Unlike the switching power supply device 1 according to the embodiment, FIG. 4 shows a switching power supply device 2 intended to relax the driving capability of a high-side main driver circuit 36H by inserting a resistor RBOOT in series with a bootstrap capacitor CBOOT. It is a figure which shows an example of a structure of. In the switching power supply device 2 of FIG. 4, in the bootstrap circuit 7, the resistor RBOOT is inserted between the capacitor CBOOT and the terminal BOOT, and the plurality of PMOS transistors _THS2 are changed to one PMOS transistor _THS2 . 1 except that the driver capability selection circuit 38 and the plurality of switches DSW connected to the gates of the plurality of PMOS transistors _THS2 are not provided.

In the configuration of FIG. 4, the gate drive waveform of the NMOS main power transistor _THS1 when the resistor RBOOT is not inserted in the bootstrap circuit 7 is shown as gate drive waveform A1 in FIG. In such a case, if the driving capability of the high-side main driver circuit 36H becomes excessive with respect to the electrical characteristics such as the gate capacitance of the NMOS main power transistor _THS1 , the gate capacitance is rapidly charged in the second step S2. and the NMOS main power transistor _THS1 sharply transitions from off to on. Therefore, as shown in FIG. 2, the terminal SW may cause ringing due to overshoot, resulting in switching noise. That is, if the driving capability of the high-side main driver circuit 36H becomes excessive with respect to the electrical characteristics such as the gate capacitance of the NMOS main power transistor _THS1 , the EMI (ElectroMagnetic Interference) performance of the switching power supply 1 may deteriorate. be.

Therefore, in the switching power supply device 2 of FIG. 4, it is required to adjust the output capability of the driver power supply of the main driver circuit 36H on the high side as an EMI countermeasure. For example, in the switching power supply device 2 of FIG. 4, by inserting the resistor RBOOT into the bootstrap circuit 7, the impedance of the capacitor CBOOT operating as a driver power supply is equivalently increased to increase the output capability of the high-side main driver circuit 36H. is adjusted to relax the driving capability of the high-side main driver circuit 36H.

However, when inserting the resistor RBOOT into the bootstrap circuit 7 as shown in FIG. 4, it is necessary to determine the resistance value of the resistor RBOOT for each electrical characteristic such as the gate capacitance of the NMOS main power transistor _THS1 . In other words, in the configuration of FIG. 4, it was necessary to take measures against EMI such as adjusting the output capability of the driver power supply of the high-side main driver circuit 36H for each electrical characteristic of the NMOS main power transistor _THS1 .

On the other hand, in the switching power supply device 1 according to the present embodiment, a plurality of PMOS transistors _THS2 and a plurality of switches DSW are provided in the high-side main driver circuit 36H. Each PMOS transistor included in the plurality of PMOS transistors _THS2 can individually set whether or not to operate by controlling the plurality of switches DSW, as described above. In other words, by arbitrarily selecting which PMOS transistor to operate from among the PMOS transistors _THS2 , the ON resistance of the PMOS transistor _THS2 as a whole can be arbitrarily set. Therefore, by simply selecting the PMOS transistor to be operated according to the electrical characteristics of the NMOS main power transistor _THS1 , there is no need to prepare a different circuit configuration for each electrical characteristic. Output capability can be adjusted.

FIG. 5 is a diagram for explaining adjustment of the drive capability of the high-side main driver circuit 36H by the switching power supply device 1 of FIG. FIG. 5 shows an example of gate drive waveforms B1, B2, and B3 of the NMOS main power transistor _THS1 in the switching power supply device 1 according to this embodiment shown in FIG. The gate drive waveforms B1, B2 and B3 are different from each other in the on-resistance of the PMOS transistor _THS2 as a whole. 5 shows an example of the gate drive waveform A2 of the NMOS main power transistor _THS1 in the switching power supply device 2 of FIG.

For example, by arbitrarily selecting the PMOS transistor to be operated and varying the gate current, the gate drive waveform of the NMOS main power transistor _THS1 can be changed as shown by waveforms B1, B2, and B3 in FIG. . Similarly, by arbitrarily selecting the PMOS transistor to be operated, the operating waveform of the signal at the terminal SW can be changed.

Further, as shown in FIG. 5, by appropriately selecting the PMOS transistor to be operated, the high-side main driver can be operated similarly to the case where the resistor RBOOT is inserted into the bootstrap circuit 7 as in the switching power supply device 2 of FIG. The drive capability of circuit 36H can be changed. In other words, in the switching power supply device 1 according to the present embodiment, it is possible to change the driving capability of the high-side main driver circuit 36H without preparing a different circuit configuration for each electrical characteristic of the NMOS main power transistor _THS1 . can be done.

Specifically, according to the switching power supply device 1 according to the embodiment, it is not necessary to adjust the output capability of the driver power supply of the high-side main driver circuit _36H . Therefore, it is not necessary to insert a resistor RBOOT having a similar resistance value into the bootstrap circuit 7 to adjust the current supply capability. Therefore, according to the switching power supply device 1 according to the embodiment, it is possible to eliminate the need for the resistor RBOOT for adjusting the current supply capability of the driver power supply of the high-side main driver circuit 36H.

Further, according to the switching power supply device 1 according to the embodiment, the number of stages of the PMOS transistors in the plurality of PMOS transistors _THS2 of the high-side main driver circuit 36H can be adjusted to any number. Therefore, the number of driver stages corresponding to the electrical characteristics of the NMOS main power transistor _THS1 connected to the high-side main driver circuit 36H can be set. In other words, according to the switching power supply device 1 according to the embodiment, EMI countermeasures can be taken for each electrical characteristic of the NMOS main power transistor _THS1 .

Further, according to the switching power supply device 1 according to the embodiment, the number of driver stages to be operated can be set by writing adjustment data supplied from the outside to the OTPROM 34 from the terminal DATA. An increase in the number of terminals can also be avoided.

In the above-described embodiment, the switching power supply device 1 in which the number of stages of PMOS transistors can be arbitrarily adjusted by providing a plurality of PMOS transistors _THS2 in the high-side main driver circuit 36H was exemplified, but the present invention is not limited to this. . In the high-side main driver circuit 36H, instead of or in addition to the PMOS transistor _THS2 , the NMOS transistor _{THS3 may} be divided into a plurality of NMOS transistors. Even with these configurations, effects similar to those of the above-described embodiments can be obtained.

Further, in the above-described embodiments, the switching power supply device 1 as a step-down DC-DC converter was exemplified, but the present invention is not limited to this. The technology according to the above embodiments can also be applied to a switching power supply device as a step-up DC-DC converter. In this case, in the low-side main driver circuit 36L, at least one of the PMOS transistor _TLS2 and the NMOS transistor _TLS3 can be divided into a plurality of MOS transistors as in the above embodiments. Even with these configurations, effects similar to those of the above-described embodiments can be obtained.

As described above, according to the switching power supply device 1 according to the embodiment, the drive capability of the drive circuit of the NMOS main power transistor _THS1 as a switching element is changed according to the electrical characteristics of the NMOS main power transistor _THS1 . be able to.

Although the embodiment of the present invention has been described above, the above embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiments described above can be embodied in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

Reference Signs List 1, 2 switching power supply device 3 control circuit 5 main circuit 7 bootstrap circuit 9 power supply 31 regulator circuit 32 PWM conversion circuit 33 dead time control circuit 34 OTPROM
35H, 35L Level shift circuit 36H, 36L Main driver circuit 37H, 37L Pre-driver circuit 38 Driver capability selection circuit BOOT, GATE_HS, GATE_LS, GND, IN, OUT, PGND, SW, VDD, VPIN Terminals CBOOT, CHS11, CHS12, COUT Capacitor DIO Bootstrap diode LOUT Inductor RBOOT Resistor T _HS1 NMOS main power transistor T _LS1 NMOS rectification power transistor T _HS2 , T _HS21 , T _HS22 , T _HS23 PMOS transistor T _HS3 , T _LS3 NMOS transistor

Claims (4)

a switching transistor;
a gate driver circuit connected to the gate of the switching transistor and supplying a gate current to the switching transistor when turning on the switching transistor;
and
The gate driver circuit is configured such that the on-resistance of the output transistor through which the gate current flows can be changed.
switching power supply. The gate driver circuit has a plurality of transistors connected in parallel,
At least one of the plurality of transistors can be selected as the output transistor,
The switching power supply device according to claim 1. 3. The switching power supply device according to claim 2, wherein said gate driver circuit is configured to be able to select at least one of said plurality of transistors as said output transistor according to adjustment data supplied from the outside. . The switching transistor is a high-side switching transistor,
wherein the output transistor is a high-side transistor in the gate driver circuit;
The switching power supply device according to any one of claims 1 to 3.

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