JP2023000223A - Manufacturing method of hard mask, manufacturing method of solar battery, and ion implantation device - Google Patents

Abstract

To provide a manufacturing method of a hard mask, a manufacturing method of a solar battery, and an ion implantation device, which can suppress an increase of a cost in each manufacturing line of the solar battery.SOLUTION: In a manufacturing method of a hard mask, a concave part 13 is formed on a first main surface 11 of a plate-like substrate having the first main surface 11 and a second main surface 12 which is opposite to the first main surface 11 is formed, a reinforcement plate is housed in a concave part 13 via an adhesive layer. A pattern region part 15 having an open 15h penetrated to the concave part 13 in the second main surface 12 opposite to the concave part 13 is formed, and the reinforcement plate and the adhesive layer are removed from the concave part 13.SELECTED DRAWING: Figure 3

Description

The present invention relates to a hard mask manufacturing method, a solar cell manufacturing method, and an ion implanter.

In recent years, among solar cells using crystalline silicon as a substrate (hereinafter also referred to as crystalline solar cells), the structure that has received the most attention due to its improved power generation efficiency is a passivation layer in which silicon oxide (SiO) is used. _x ) and a TOPCon (Tunnel Oxide Passivating Contacts) structure using an amorphous silicon (a-Si) layer.

At EUPVSEC2018, POLO (polycrystalline silicon on oxide), which is similar to the TOPCon-IBC (Tunnel Oxide Passivating Contact-Interdigitated Back Contact) structure, has a power generation efficiency of 26.1% (a record within the EU) from ISFH, Germany. reported (Non-Patent Document 1). In addition, Germany's Fraunhofer ISE reported a power generation efficiency of 26.0% in the TOPCon structure (Non-Patent Document 2). The mass production of crystalline solar cells adopting the TOPCon structure is now under consideration in China and other countries.

In the TOPCon-IBC solar cell, an n-type silicon region and a p-type silicon region are arranged on the back surface of the silicon substrate (the surface opposite to the light receiving surface) so as to be separated from each other. In order to obtain a configuration in which the n-type region and the p-type region are arranged in the same silicon layer, the TOPCon-IBC type crystalline solar cell repeats the film formation process, the masking process using photolithography, and the etching process multiple times. be Also in the TOPCon structure, the p-layer or n-layer is selectively formed with a high concentration only under the electrode on the light receiving surface side, so the same process as described above is used.

"Laser contact openings for local poly-Si-metal contacts enabling 26.1%-efficient POLO-IBC solar cells", Solar Energy Materials and Solar Cells186(2018)184-193 "Design rules for high-efficiency both-sides contacted silicon solar cells with balanced charge carrier transport and recombination losses", Nature energy VOL 6 April 2021 429-438

However, in the case of locally forming the p and n layers, or in the step of locally manufacturing the p or n layer with a high concentration, the number of manufacturing steps increases, which may lead to an increase in the cost of the manufacturing line. In TOPCon-IBC, the gap between the p and n layers on the back surface must be aligned within ±30 μm of alignment accuracy.

In view of the circumstances as described above, it is an object of the present invention to provide a method of manufacturing a hard mask, a method of manufacturing a solar cell, and an ion implantation apparatus that suppress cost increases in a solar cell manufacturing line.

In order to achieve the above object, in a method for manufacturing a hard mask according to one aspect of the present invention,
A concave portion is formed in the first main surface of a plate-shaped substrate having a first main surface and a second main surface opposite to the first main surface,
A reinforcing plate is accommodated in the recess via an adhesive layer,
A pattern region portion having an opening penetrating to the recess is formed on the second main surface opposite to the recess,
The reinforcing plate and the adhesive layer are removed from the recess.

According to such a hard mask manufacturing method, it is possible to suppress an increase in the cost of the solar cell manufacturing line and to accurately control the ion-implanted region in the solar cell.

In the hard mask manufacturing method described above, a silicon substrate may be used as the substrate.

In the method for manufacturing a hard mask, the auxiliary plate and the first main surface may be aligned before forming the pattern region portion on the second main surface.

According to such a hard mask manufacturing method, a hard mask free from cracks and chips can be manufactured.

In the above hard mask manufacturing method, the pattern region may be formed by a dicing blade.

According to such a hard mask manufacturing method, a hard mask can be manufactured at low cost.

In the hard mask manufacturing method, a crystalline silicon substrate may be used as the silicon substrate.

According to such a hard mask manufacturing method, it is possible to manufacture a hard mask with small variations in the width of the opening pattern.

In order to achieve the above object, in a method for manufacturing a solar cell according to one aspect of the present invention,
It has a first principal surface and a second principal surface opposite to the first principal surface, the first principal surface is provided with a recess, and the second principal surface opposite to the recess is provided with a recess. preparing a hard mask provided with a pattern region portion having an opening penetrating to the recess;
A first conductivity type impurity element or a second conductivity type impurity element is selectively implanted into a silicon layer formed on the main surface of a crystalline silicon substrate by ion implantation using a hard mask on the main surface side of the crystalline silicon substrate. .

According to such a solar cell manufacturing method, the p and n layers can be selectively implanted, or the concentration of one dopant can be selectively increased. In addition, it is possible to suppress an increase in cost for the production line of the solar cell, and to accurately control the ion-implanted region in the solar cell.

In the above solar cell manufacturing method, the hard mask may be made of silicon.

In the above solar cell manufacturing method, at least two hard masks are prepared,
selectively implanting a first conductivity type impurity element into the silicon layer using one of the hard masks to form a first region of the first conductivity type in the silicon layer; A second conductivity type second region may be formed in the silicon layer by selectively implanting a second conductivity type impurity element into the silicon layer where the first region is not formed.

According to such a solar cell manufacturing method, the widths of the first region and the second region can be changed independently.

In the method for manufacturing a solar cell described above, the second region may be arranged in parallel with the first region, and the distance between the first region and the second region may be set to 5 μm or more and 100 μm.

According to such a solar cell manufacturing method, it is possible to accurately control the interval between the first region and the second region.

In order to achieve the above object, an ion implanter according to one aspect of the present invention comprises:
a support base capable of supporting the substrate;
the hard mask;
an ion implantation source for implanting ions into the substrate through the hard mask.

According to such an ion implantation apparatus, it is possible to suppress an increase in cost for the production line of the solar cell, and to accurately control the ion implantation region in the solar cell.

In the above ion implanter, the hard mask may be made of silicon.

As described above, according to the present invention, there are provided a hard mask manufacturing method, a solar cell manufacturing method, and an ion implantation apparatus that suppress cost increases in a solar cell manufacturing line.

1 is a schematic configuration diagram of a solar cell manufactured by a method for manufacturing a solar cell according to this embodiment; FIG. 1 is a schematic configuration diagram of an ion implanter applied to a method for manufacturing a solar cell according to this embodiment; FIG. FIG. (a) is a schematic plan view of a hard mask according to this embodiment. FIGS. (b) and (c) are schematic cross-sectional views of the hard mask according to this embodiment. 4A to 4C are schematic cross-sectional views for explaining the manufacturing process of the hard mask according to the present embodiment; 4A to 4C are schematic cross-sectional views for explaining the manufacturing process of the hard mask according to the present embodiment; FIG. 4 is a schematic plan view for explaining the manufacturing process of the hard mask according to this embodiment; It is a schematic cross-sectional view for explaining the method for manufacturing the solar cell of the present embodiment. It is a schematic cross-sectional view for explaining the method for manufacturing the solar cell of the present embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. XYZ axis coordinates may be introduced in each drawing. Also, the same reference numerals may be given to the same members or members having the same function, and the description may be omitted as appropriate after the description of the members. Also, the numerical values shown below are examples, and the present invention is not limited to these examples.

[Solar cell]

FIG. 1 is a schematic configuration diagram of a solar cell manufactured by a method for manufacturing a solar cell according to this embodiment.

The solar cell 100 shown in FIG. 1 is a TOPCon-IBC type crystalline solar cell. The solar cell 100 includes an n-type (first conductivity type) crystalline silicon substrate 110, a silicon layer 111, an n-type region (first region) 111n, a p-type region (second region) 111p, and a protective layer. 112, a protective layer 120, an n-side electrode 130n, and a p-side electrode 130p.

An n-side electrode 130n is connected to the n-type region 111n. A p-side electrode 130p is connected to the p-type region 111p. The n-side electrode 130n or the p-side electrode 130p is made of, for example, at least one of silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), etc., or a mixture of these metals. include.

In solar cell 100 , the light-receiving surface is located on the side opposite to back surface 110 a of crystalline silicon substrate 110 . For example, the surface 110b of the crystalline silicon substrate 110 has an uneven structure (texture structure) to efficiently take in sunlight. The surface 110b is provided with protective layers 112 and 120 along the uneven surface of the surface 110b, which also function as antireflection films for suppressing loss of light amount due to reflection of sunlight.

In solar cell 100, sunlight is received from surface 110b of crystalline silicon substrate 110, and an electrode structure (back electrode structure) is provided on the side opposite to surface 110b. As a result, the solar cell 100 has a structure in which the electrode does not exist on the light receiving surface, thereby suppressing the shadow loss of the sunlight due to the electrode.

A silicon layer 111 is provided on the back surface 110 a of the crystalline silicon substrate 110 . The thickness d1 of the silicon layer 111 is, for example, 5 nm or more and 200 nm or less. In addition, in this embodiment, a non-mass separation ion implantation method (plasma doping method) is used to form the n-type region 111n and the p-type region 111p in the silicon layer 111 . The non-mass-separated ion implantation method can implant the impurity element over a large area, thereby improving the throughput in the production of solar cells.

As long as the impurity element is introduced into the silicon layer 111 in the form of ions, the method is not limited to the non-mass-separated ion implantation method, and a mass-separated ion implantation method or the like is also possible. In the following description, a non-mass-separated ion implantation method is used as a representative example of the impurity introduction method. For the sake of simplicity, non-mass-separated ion implantation is referred to as "ion implantation." Next, an apparatus for ion implantation will be described.

[Ion implanter]

FIG. 2 is a schematic configuration diagram of an ion implanter applied to the method for manufacturing a solar cell according to this embodiment.

The ion implanter 1000 includes a vacuum chamber 1001 (lower vacuum chamber), a vacuum chamber 1002 (upper vacuum chamber), an insulating member 1003, a support base 1004, a gas supply source 1005, and a hard mask 10. . Further, the ion implanter 1000 includes an RF introduction coil 1100 , a permanent magnet 1101 , an RF introduction window (quartz window) 1102 , an electrode 1200 , an electrode 1201 , a DC power supply 1300 and an AC power supply 1301 .

The vacuum chamber 1002 has a smaller diameter than the vacuum chamber 1001 and is provided above the vacuum chamber 1001 via an insulating member 1003 . A vacuum chamber 1002 is an ion implantation source that implants ions into the substrate S1 through the hard mask 10 . The vacuum chamber 1001 and the vacuum chamber 1002 can be maintained in a reduced pressure state by vacuum evacuation means such as a turbomolecular pump. A support table 1004 is provided in the vacuum chamber 1001 . The support base 1004 can support the substrate S1. A heating mechanism for heating the substrate S1 may be provided in the support table 1004 . The substrate S1 is a semiconductor wafer for manufacturing the solar cell 100, a glass substrate, or the like. A gas for ion implantation is introduced into the vacuum chamber 1002 by a gas supply source 1005 .

The support base 1004 can support the substrate S1. The substrate S1 is placed on the support base 1004 with the rear surface 110a shown in FIG. A hard mask 10 is arranged between the substrate S1 and the vacuum chamber 1002 . The ion implantation apparatus 1000 may be provided with a mask moving mechanism (not shown) that replaces the hard mask 10 with another hard mask or changes the distance between the hard mask 10 and the substrate S1. For example, the distance between the hard mask 10 and the substrate S1 can be set to 0 mm to 5 mm.

RF introduction coil 1100 is arranged on RF introduction window 1102 to surround permanent magnet 1101 . The shape of the permanent magnet 1101 is ring-shaped. The shape of the RF introduction coil 1100 is coiled. The diameter of the RF introduction coil 1100 can be appropriately set according to the size of the substrate S1. When ion implantation gas is introduced into the vacuum chamber 1002 and predetermined power is supplied from the AC power source 1301 to the RF introduction coil 1100, plasma 1010 is generated in the vacuum chamber 1002 by ICP (Inductively Coupled Plasma) discharge. do.

Electrode 1200 is an electrode (for example, mesh electrode) having a plurality of openings and is supported by insulating member 1003 . The potential of electrode 1200 is a floating potential. Thereby, a stable plasma 1010 is generated in the space surrounded by the vacuum chamber 1002 and the electrodes 1200 .

Underneath electrode 1200 is another electrode (eg, mesh electrode) 1201 having multiple openings. The electrode 1201 faces the substrate S1. A DC power supply 1300 is connected between the electrode 1201 and the RF introduction coil 1100 , and a negative potential (acceleration voltage) is applied to the electrode 1201 . As a result, positive ions in plasma 1010 are extracted from plasma 1010 by electrode 1201 .

The extracted positive ions can pass through the mesh electrodes 1200 and 1201 and reach the substrate S1 (silicon layer 111). In the ion implanter 1000, the acceleration voltage of positive ions can be set within a range of, for example, 1 kV or more and 30 kV or less. Also, a bias power supply capable of adjusting the acceleration voltage may be connected to the support base 1004 .

A gas containing an impurity element (n-type impurity element or p-type impurity element) to be implanted into the substrate S1 is introduced into the vacuum chamber 1002 . This gas forms plasma 1010 in vacuum chamber 1002, and n-type impurity ions or p-type impurity ions in plasma 1010 are implanted into substrate S1. The n-type impurity ion is, for example, at least one of P, PX ⁺ , PX ₂ ⁺ , PX ₃ ⁺ and the like. Here, "X" is either hydrogen or halogen (F, Cl). The p-type impurity ion is, for example, at least one of B ⁺ , BY ⁺ , BY ₂ ⁺ , BY ₃ ⁺ , B ₂ Y ₂ ⁺ , B ₃ Y ₂ ⁺ , B ₄ Y ₂ ⁺ and the like. Here, "Y" is either hydrogen or halogen (F, Cl).

The concentrations of the impurity element in the n-type region 111n and the impurity element in the p-type region 111p are adjusted so that the conductivity of the n-type region 111n and the p-type region 111p are optimized. However, the concentration of the impurity element implanted into the n-type region 111n is set higher than the concentration of the n-type impurity element in the crystalline silicon substrate 110. FIG.

In this embodiment, means for forming the plasma 1010 is not limited to the ICP method, but may be an electron cyclotron resonance plasma method, a helicon wave excited plasma method, or the like.

In this embodiment, when the impurity element is implanted into the silicon layer 111, a gas containing hydrogen ₍ for example, PH3 _, BH2, etc.) may be added to the ion implantation gas. As a result, hydrogen is implanted into the silicon layer 111 and structural defects in the silicon layer 111 are repaired. This suppresses recombination of carriers at structural defects and increases the total amount of carriers reaching the n-type region 111n and the p-type region 111p. This improves the photoelectric conversion efficiency and increases the open-circuit voltage (V _oc ).

[Hard mask]

FIG. 3A is a schematic plan view of the hard mask according to this embodiment. 3B and 3C are schematic cross-sectional views of the hard mask according to this embodiment. FIG. 3(b) shows a cross section along line A1-A2 in FIG. 3(a). FIG. 3(c) shows a cross section along line A3-A4 in FIG. 3(a).

The hard mask 10 is made of crystalline silicon. The hard mask 10 is not limited to crystalline silicon and may be made of graphite. The hard mask 10 will be described below using crystalline silicon as an example.

The planar shape of the hard mask 10 is, for example, an octagon. The planar shape is not limited to an octagon, and may be a polygon such as a quadrangle or a hexagon. The hard mask 10 includes a main surface 11 (first main surface), a main surface 12 (second main surface) opposite to the main surface 11, a concave portion (counterbore) 13 provided in the main surface 11, and a main surface 12 (second main surface). It has a pattern region portion 15 provided on the surface 12 and a thick peripheral portion 14 surrounding the pattern region portion 15 and the recess 13 .

The recess 13 is dug down from the main surface 11 and is located, for example, in the central portion of the hard mask 10 . The planar shape of the concave portion 13 is a rectangular shape surrounded by a pair of opposing long sides 13La and 13Lb and a pair of opposing short sides 13Sa and 13Sb. The depth of the recess 13 is shallower than the thickness of the hard mask 10 . Here, the direction in which the long sides 13La and 13Lb extend is the first direction, and the direction in which the short sides 13Sa and 13Sb extend is the second direction. The first direction and the second direction are substantially orthogonal.

A pattern region portion 15 having an opening 15h penetrating to the recess 13 is provided on the main surface 12 opposite to the recess 13 . A plurality of openings 15 h are provided in the pattern region portion 15 . Each line width of the plurality of openings 15h is substantially the same. The plurality of openings 15h are arranged side by side in the first direction. For example, the plurality of openings 15h are arranged periodically in the first direction. Moreover, each of the plurality of openings 15h extends linearly along the second direction. In the hard mask 10, a plurality of openings 15h form a line-and-space opening pattern.

10 to 1700 openings 15 h are arranged in the pattern region portion 15 . The line width of the opening 15h is set to 10 μm to 600 μm, for example. When the plurality of openings 15h are arranged periodically in the first direction, the pitch of the openings 15h is set to 300 μm to 4000 μm, for example. Also, the thickness of the pattern region portion 15 (or the depth of the opening 15h) is set to, for example, 0.2 mm to 10.0 mm, for example, 0.4 mm.

Further, each of the plurality of openings 15 h communicates with grooves 15 ta and 15 tb provided in the peripheral portion 14 surrounding the pattern region portion 15 . Each of the plurality of openings 15h is provided between groove 15ta and groove 15tb in the second direction. Each of grooves 15ta and 15tb extends in the second direction. The groove 15ta extends from the pattern region portion 15 to the end portion 10ea of the hard mask 10 facing the long side 13La. The groove 15tb extends from the pattern region portion 15 to the end portion 10eb of the hard mask 10 facing the long side 13Lb.

The grooves 15ta and 15tb do not penetrate from the main surface 12 to the main surface 11 of the hard mask 10, but are bottomed grooves in the peripheral portion . The depth and line width of the opening 15h and the grooves 15ta and 15tb are substantially the same. That is, when an arbitrary opening 15h is selected from the pattern region portion 15, a single linear space groove 15s is formed by the opening 15h and a pair of grooves 15ta and 15tb communicating with both ends of the opening 15h. be. A plurality of space grooves 15s are arranged side by side in the hard mask 10 in the first direction.

4A to 5C are schematic cross-sectional views explaining the manufacturing process of the hard mask according to this embodiment, and FIG. 6 explains the manufacturing process of the hard mask according to this embodiment. It is a schematic plan view.

As shown in FIG. 4A, after preparing a plate-like substrate having a main surface 11 and a main surface 12 opposite to the main surface 11, for example, a silicon substrate 10s, the main surface of the silicon substrate 10s is prepared. A recess 13 is formed in the surface 11 . A crystalline silicon substrate such as a silicon wafer is used as the original plate of the silicon substrate 10s in which the recesses 13 are formed. The planar shape of the silicon substrate 10s is the same as the planar shape of the hard mask 10 shown in FIG. 3(a). A graphite substrate may be used as the plate-like substrate.

The concave portion 13 is formed by a technique such as grind polishing, dry etching, or wet etching. The thickness of the silicon substrate 10s (crystalline silicon substrate) is, for example, 0.5 mm to 20 mm. The depth of the recess 13 is 0.2 mm to 10 mm. By forming the concave portion 13 in the silicon substrate 10s, a peripheral portion 14 surrounding the concave portion 13 and a region portion 15a thinner than the peripheral portion 14 are formed in the silicon substrate 10s. The thickness of the region portion 15a corresponds to the thickness of the pattern region portion 15, for example. The region portion 15a is replaced with the pattern region portion 15 by processing described later.

Next, as shown in FIG. 4B, the adhesive layer 20 is placed in the recess 13, and the reinforcing plate 30 is accommodated in the recess 13 with the adhesive layer 20 interposed therebetween. The material of the reinforcing plate 30 is the same as the material of the silicon substrate 10s.

Here, the thickness d2 of the peripheral portion 14 and the thickness d3 from the main surface 12 to the non-bonded surface (exposed surface) 30s of the reinforcing plate 30 are different. If there is a step, before forming the pattern region on the main surface 12, the main surface 11 or the non-bonded surface 30s is polished to align the main surface 11 and the non-bonded surface 30s. done.

For example, in the state of FIG. 4B, if d2>d3, as shown in FIG. The main surface 11 and the non-adhesive surface 30s are aligned so as to be aligned. At this time, if the material of the reinforcing plate 30 and the material of the silicon substrate 10s are the same, one of them is not preferentially polished. Furthermore, if the material of the reinforcing plate 30 and the material of the silicon substrate 10s are the same, the same polishing jig can be used, and the polishing material for the reinforcing plate 30 and the polishing material for the silicon substrate 10s are separately prepared. No need to.

Next, as shown in FIG. 4(d), the silicon substrate 10s with the reinforcing plate 30 attached thereto is placed on an adhesive substrate (dicing sheet) 40. Next, as shown in FIG. Main surface 11 and reinforcing plate 30 are in contact with base 40 .

Next, a dicing blade 50 is used to form the space grooves 15s shown in FIG. 3A on the main surface 12 side of the silicon substrate 10s. The depth of the space groove 15 s has at least the thickness of the pattern region portion 15 . Further, when the space groove 15s is formed, since the reinforcing plate 30 is accommodated in the recess 13, even if the dicing blade 50 comes into contact with the thin region 15a, the mechanical strength of the region 15a is ensured. be done. As a result, the space groove 15s is formed on the main surface 12 side of the silicon substrate 10s without cracking or chipping in the silicon substrate 10s. In addition, since the thickness of the peripheral portion 14 and the thickness from the main surface 12 to the non-bonded surface 30s of the reinforcing plate 30 are substantially the same, even if the dicing blade 50 is pressed against the main surface 12, the peripheral portion Unnecessary stress is not applied to the portion between the portion 14 and the region portion 15a, and the silicon substrate 10s is less likely to be cracked or chipped.

As a result, as shown in FIG. 5A, an opening 15h penetrating to the recess 13 is stably formed in the main surface 12 opposite to the recess 13. As shown in FIG. A plurality of space grooves 15s may be formed. For example, a plurality of space grooves 15s may be formed from left to right in FIG. 5(a), or may be formed from right to left. Alternatively, the center of the recess 13 may be formed first, and then the center may be formed as a starting point and formed symmetrically on both sides.

As a result, as shown in FIG. 5B, the dicing blade 50 forms the silicon substrate 10s on which the pattern region portion 15 is formed. After that, as shown in FIG. 5(c), the silicon base 10s is separated from the dicing blade 50, and the silicon base 10s is immersed in the chemical solution, thereby removing the reinforcing plate 30 and the adhesive layer 20 from the recess 13. A hard mask 10 is thus formed.

When forming the space grooves 15s, the space grooves 15s may be formed with a dicing blade 50 having the same line width and thickness as the space grooves 15s. In this case, one space groove 15s is formed each time the dicing blade 50 passes. Alternatively, as shown in FIG. 6, a dicing blade thinner than the line width of the space grooves 15s may be used, and the space grooves 15s may be formed by reciprocating the dicing blade multiple times for one space groove 15s. .

For example, as shown in FIG. 6, when forming one space groove 15s using a dicing blade having a width of about one-third of the line width of the space groove 15s, both sides of the space groove 15s have The corresponding groove portions 15-1 and 15-2 may be ground in advance, and finally the groove portion 15-3 corresponding to the central portion of the space groove 15s may be ground. According to such a technique, the load (stress) applied to the silicon substrate 10s by the dicing blade is relaxed, and the space grooves 15s without cracks and chips are formed. In this way, the space groove 15s having the desired line width can be finally formed.

[Method for manufacturing solar cell]

7(a) to 8(b) are schematic cross-sectional views illustrating the method for manufacturing the solar cell of this embodiment.

First, the hard mask 10 is prepared, and the hard mask 10 is made to face the major surface 111a of the silicon layer 111 as shown in FIG. 7(a). Here, the major surface 12 of the hard mask 10 opposite to the concave portion 13 is made to face the major surface 111a. A known texture forming technique may be employed for the surface 110 b of the crystalline silicon substrate 110 .

Next, using the hard mask 10, an n-type impurity element or a p-type impurity element is selectively implanted into the silicon layer 111 by an ion implantation method.

For example, as shown in FIG. 7B, n-type impurity ions 200n are selectively implanted into the main surface 111a of the silicon layer 111 exposed through the opening 15h. The n-type impurity ions 200n are, for example, phosphorus (P) ions. For example, a gas containing n-type impurities is introduced into vacuum chamber 1002 and a plasma is generated from this gas. Then, when main surface 111a of silicon layer 111 is irradiated with n-type impurity ions 200n through hard mask 10 by ion implantation, part of n-type impurity ions 200n pass through opening 15h of hard mask 10. FIG. N-type impurity ions 200n passing through opening 15h are selectively implanted into a predetermined region of silicon layer 111. As shown in FIG.

Next, as shown in FIG. 8A, the hard mask 10 is laterally moved to position the opening 15h at the position where the p-type region 111p is to be formed. Subsequently, the gas containing n-type impurities is switched to the gas containing p-type impurities to generate plasma in the vacuum chamber 1002 from the gas containing p-type impurities. Then, when the main surface 111a of the silicon layer 111 is irradiated with the p-type impurity ions 200p through the hard mask 10 by ion implantation, a portion of the p-type impurity ions 200p are selected in the silicon layer 111 exposed from the opening 15h. injected into the target. The p-type impurity ions 200p are, for example, boron (B) ions. The p-type region 111p is arranged in parallel with the n-type region 111n in a region of the silicon layer 111 where the n-type region 111n is not formed in the Y-axis direction. An ion implantation apparatus for implanting n-type impurities and an ion implantation apparatus for implanting p-type impurities may be prepared separately. In this case, the implantation of n-type impurities and the implantation of p-type impurities are performed by different ion implantation apparatuses.

The distance between n-type region 111n and p-type region 111p is set to 5 μm or more and 100 μm or less. As a result, since the distance between the n-type region 111n and the p-type region 111p can be set within the above range, the p-side electrode 130p or the n-side electrode 130n can be increased.

Next, as shown in FIG. 8B, a protective layer 112 and a protective layer 120 are formed on the crystalline silicon substrate 110 by CVD, sputtering, or the like. Thereafter, as shown in FIG. 1, an n-side electrode 130n connected to the n-type region 111n is formed in the n-type region 111n. A p-side electrode 130p connected to the p-type region 111p is formed in the p-type region 111p.

At least two hard masks 10 having different line widths of the openings 15h may be prepared. In this case, one hard mask 10 is used to selectively implant an n-type impurity element into the silicon layer 111 to form an n-type region 111n in the silicon layer 111 . Using the other hard mask 10, a p-type impurity element is selectively implanted into the silicon layer 111 where the n-type region 111n is not formed to form a p-type region 111p in the silicon layer 111. FIG. According to such a method, the n-type region 111n and the p-type region 111p having different widths in the Y-axis direction can be formed in the silicon layer 111 without repeating the photolithography process and the etching process multiple times.

According to such a manufacturing method, in order to form the back electrode structure, in order to form the n-type region 111n and the p-type region 111p, it is necessary to repeat each of the film formation process, the photolithography process, and the etching process multiple times. is eliminated, and the number of manufacturing processes for manufacturing solar cells is further reduced.

Moreover, the hard mask 10 is not formed by a process of repeating each of the photolithography process and the etching process multiple times, but is simply formed by mechanical processing using the dicing blade 50 . Thereby, the hard mask 10 is formed at low cost. Further, when the space groove 15s is formed by laser processing, a phenomenon may occur in which a part of the space groove 15s is locally melted. Since the present embodiment employs mechanical processing using the dicing blade 50, such a phenomenon does not occur.

Note that the solar cell is not limited to the TOPCon-IBC type, and the manufacturing method of the present embodiment is also applied to the TOPCon structure. In this case, in the TOPCon structure, a high-concentration p-layer or n-layer is selectively formed under the electrode on the light-receiving surface side. Applies to wafer processing on both sides. In this embodiment, the back surface 110a and the front surface 110b of the solar cell are collectively referred to as main surfaces.

When a mask made of graphite (Example 1) and a mask made of crystalline silicon (Example 2) are used as the hard mask 10, the processing accuracy of the line width of the opening 15h and the ion The injection results are shown below.

Table 1 shows the results when the hard mask is made of graphite, and Table 2 shows the results when the hard mask is made of crystalline silicon. In Tables 1 and 2, the openings 15h are both formed with a dicing blade. The ions implanted into the crystalline silicon substrate using these hard masks are phosphorus (P) (10 Kev, 1×10 ¹⁶ ions/cm ² ).

The target value of the line width of the openings of the graphite mask shown in Table 1 is 200 μm, the number of openings is 98, and the pitch is 1.6 mm. The target line width of the openings in the silicon mask shown in Table 2 is 260 μm, the number of openings is 161, and the pitch is 0.96 mm. Further, the variation value in Tables 1 and 2 is expressed by ((max value−min value)/(max value+min value))×100(%).

In the graphite mask shown in Table 1, the line width variation of the openings is 7.7%. Using a mask having this variation value, the variation value of the implanted region width of the region implanted with phosphorus is 9.7%. One possible cause of such variations is that the graphite mask is made of polycrystalline graphite and has a relatively large particle size.

On the other hand, in the crystalline silicon mask shown in Table 2, the variation value of the line width of the opening is 0.4%, which is greatly improved. Using this mask, the width of the implanted region in which phosphorus is implanted has a variation value of 0.5%. Since the crystalline silicon mask is composed of a single crystal of silicon, the variation in the line width of the opening is much smaller than that of a graphite mask. A solar cell with extremely small variation can be manufactured.

Although the embodiments of the present invention have been described above, it is needless to say that the present invention is not limited to the above-described embodiments and can be modified in various ways. For example, although the TOPCon-IBC structure has been described in this embodiment, the present invention can also be applied to a TOPCon structure in which an n-type region and a p-type region are formed under an electrode on the light receiving surface side. Each embodiment is not limited to an independent form, and can be combined as much as technically possible.

DESCRIPTION OF SYMBOLS 10... Hard mask 10s... Silicon substrate 10ea, 10eb... End part 11, 12... Main surface 13... Concave part 13La, 13Lb... Long side 13Sa, 13Sb... Short side 14... Peripheral part 15... Pattern region part 15a... Region part 15h... Opening 15t Groove 15s Space groove 15-1, 15-2, 15-3 Groove 20 Adhesive layer 30 Reinforcing plate 30s Non-adhesive surface 40 Base 50 Dicing blade 100 Solar cell 110 Crystalline silicon Substrate 110a back surface 110b front surface 111 silicon layer 111a, 111b main surface 111n n-type region 111p p-type region 112, 120 protective layer 130p p-side electrode 130n n-side electrode 200n n-type impurity ion 200p P-type impurity ion 1000 Ion implanter 1001, 1002 Vacuum chamber 1003 Insulating member 1004 Support base 1005 Gas supply source 1010 Plasma 1100 RF introduction coil 1101 Permanent magnet 1102 RF introduction window 1200, 1201 Electrodes 1300 DC power supply 1301 AC power supply S1 Substrate

Claims (11)

forming a recess in the first main surface of a plate-like substrate having a first main surface and a second main surface opposite to the first main surface;
A reinforcing plate is accommodated in the recess via an adhesive layer,
forming a pattern region portion having an opening penetrating to the recess on the second main surface opposite to the recess;
A method of manufacturing a hard mask, wherein the reinforcing plate and the adhesive layer are removed from the recess. A method for manufacturing a hard mask according to claim 1,
A method of manufacturing a hard mask, wherein a silicon substrate is used as the substrate. A method for manufacturing a hard mask according to claim 1 or 2,
A method of manufacturing a hard mask, wherein the auxiliary plate and the first main surface are aligned before forming the pattern region portion on the second main surface. A method for manufacturing a hard mask according to any one of claims 1 to 3,
A method of manufacturing a hard mask, wherein the pattern region portion is formed by a dicing blade. A method for manufacturing a hard mask according to any one of claims 2 to 4,
A method of manufacturing a hard mask, wherein a crystalline silicon substrate is used as the silicon substrate. It has a first principal surface and a second principal surface opposite to the first principal surface, the first principal surface is provided with a recess, and the second principal surface opposite to the recess is provided with a recess. preparing a hard mask provided with a pattern region portion having an opening penetrating to the recess;
A first conductivity type impurity element or a second conductivity type impurity element is selectively implanted into the silicon layer formed on the main surface of the crystalline silicon substrate by ion implantation using the hard mask on the main surface side of the crystalline silicon substrate. A method for manufacturing a solar cell. A method for manufacturing a solar cell according to claim 6,
The method of manufacturing a solar cell, wherein the hard mask is made of silicon. A method for manufacturing a solar cell according to claim 6 or 7,
preparing at least two hard masks;
selectively implanting a first conductivity type impurity element into the silicon layer using one of the hard masks to form a first conductivity type first region in the silicon layer;
Using the other hard mask, a second conductivity type impurity element is selectively implanted into the silicon layer where the first region is not formed, thereby forming a second conductivity type second region in the silicon layer. A method for manufacturing a solar cell. A method for manufacturing a solar cell according to any one of claims 6 to 8,
The method for manufacturing a solar cell, wherein the second region is arranged in parallel with the first region, and the distance between the first region and the second region is set to 5 μm or more and 100 μm or less. a support base capable of supporting the substrate;
It has a first main surface facing the support base and a second main surface opposite to the first main surface, and the first main surface is provided with a recess, the side opposite to the recess. a hard mask provided with a pattern region portion having an opening penetrating to the recess on the second main surface of the
an ion implantation source for implanting ions into the substrate through the hard mask. 11. The ion implanter of claim 10, comprising:
The ion implanter, wherein the hard mask is made of silicon.

Images