JP2022554371A - Memristor-based neural network parallel acceleration method, processor, and apparatus - Google Patents

Abstract

The present disclosure is a parallel acceleration method, processor, and apparatus for memristor-based neural networks. The neural network includes a plurality of sequentially arranged functional layers, the plurality of functional layers being positioned after a first functional layer including a plurality of parallel first memristor arrays and the first functional layer. and a second functional layer, wherein the plurality of first memristor arrays are used to perform the operation of the first functional layer and output the operation result to the second functional layer. The parallel acceleration method includes using a plurality of first memristor cell arrays to perform operations on a first functional layer in parallel and outputting operation results to a second functional layer.

Description

This application claims priority from a Chinese patent application filed on November 7, 2019, entitled "Parallel Acceleration Method and Processor, Apparatus for Neural Networks Based on Memristors" with Application No. 201911082236.3. , the content disclosed in the above Chinese patent application is hereby incorporated by reference in its entirety.

Embodiments of the present disclosure relate to parallel acceleration methods, processors, and apparatus for memristor-based neural networks.

Deep neural network algorithm brings intelligent information technology revolution. Based on various deep neural network algorithms, image recognition and segmentation, object detection, speech and text translation, generation and other processing can be realized. Using deep neural network algorithms to process different workloads is a data-centric computation, and the hardware platform that implements the algorithms should have high-performance, low-power processing capabilities. . However, the conventional hardware platform that implements the algorithm is a von Neumann architecture in which storage and computation are separated, and in such an architecture, it is necessary to move data back and forth between the storage device and the computation device at the time of computation. . Therefore, the efficiency of this architecture is low in the computation process of deep neural networks involving a large amount of parameters. For this reason, developing new computational hardware to implement deep neural network algorithms is now an urgent problem to be solved.

At least one embodiment of the present disclosure provides a parallel acceleration method for a memristor-based neural network, wherein the neural network includes a plurality of sequentially configured functional layers, the plurality of functional layers arranged in parallel a first functional layer including a plurality of first memristor arrays; and a second functional layer positioned after the first functional layer, the plurality of first memristor arrays operating the first functional layer. used to execute in parallel and output operation results to the second functional layer, wherein the parallel acceleration method uses the plurality of first memristor arrays to parallelize the operations of the first functional layer; executing and outputting the operation result to the second functional layer.

For example, in the parallel acceleration method according to some embodiments of the present disclosure, the plurality of first memristor arrays are used to perform the operations of the first functional layer in parallel, and the operation result is transmitted to the second function. The step of outputting to a layer includes dividing input data received by the first functional layer into a plurality of sub-input data corresponding to the plurality of first memristor cell arrays; performing in parallel the operations of the first functional layer on the plurality of sub-input data using to correspondingly generate a plurality of sub-operation results.

For example, a parallel acceleration method according to some embodiments of the present disclosure joins the plurality of sub-operation results and uses the second functional layer to perform the operation of the second functional layer on the joined result. Further including steps.

For example, in the parallel acceleration method according to some embodiments of the present disclosure, the sizes of the plurality of sub-input data are basically the same.

For example, in the parallel acceleration method according to some embodiments of the present disclosure, the plurality of first memristor arrays are used to perform the operations of the first functional layer in parallel, and the operation result is transmitted to the second function. The step of outputting to a layer includes providing a plurality of input data received by the first functional layer to the plurality of first memristor cell arrays, respectively; performing in parallel the operations of the first functional layer on the plurality of received input data to correspondingly generate a plurality of sub-operation results.

For example, the parallel acceleration method according to some embodiments of the present disclosure further includes performing operations of the second functional layer on each of the plurality of sub-operation results using the second functional layer.

For example, in parallel acceleration methods according to some embodiments of the present disclosure, the plurality of input data are different from each other.

For example, in parallel acceleration methods according to some embodiments of the present disclosure, the neural network is a convolutional neural network.

For example, in parallel acceleration methods according to some embodiments of the present disclosure, the first functional layer is an initial convolutional layer of the neural network.

For example, in parallel acceleration methods according to some embodiments of the present disclosure, the plurality of functional layers further includes a third functional layer, an output of the third functional layer being provided to the first functional layer.

For example, in the parallel acceleration method according to some embodiments of the present disclosure, the neural network weight parameters are obtained by off-chip training, and the neural network weight parameters are obtained from the first function The first functional layer weight parameters, including layer weight parameters, are written to the plurality of first memristor arrays to determine conductances of the plurality of first memristor arrays.

For example, in the parallel acceleration method according to some embodiments of the present disclosure, the weight parameters of the neural network further include weight parameters of functional layers other than the first functional layer, and weights of the other functional layers By writing the parameter into the memristor array corresponding to the other functional layer, the conductance of the memristor array corresponding to the other functional layer is determined.

At least one embodiment of the present disclosure further provides a memristor-based neural network parallel acceleration processor, wherein the neural network includes a plurality of sequentially arranged functional layers, the plurality of functional layers comprising a first a functional layer, wherein the parallel acceleration processor comprises a plurality of memristor array calculation units, the plurality of memristor array calculation units including a plurality of first memristor array calculation units, the weight of the first functional layer Parameters are written to the plurality of first memristor array computing units, and the plurality of first memristor array computing units are configured to perform operations corresponding to operations of the first functional layer in parallel. be.

At least one embodiment of the present disclosure further provides a memristor-based neural network parallel accelerator, comprising: a parallel acceleration processor according to any one embodiment of the present disclosure; and an input interface coupled to the parallel acceleration processor. and an output interface, wherein the input interface is configured to receive instructions to control operation of the parallel acceleration processor, and the output interface is configured to output an operation result of the parallel acceleration processor. be done.

In order to describe the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments are briefly introduced below. Apparently, the drawings in the following description do not limit the disclosure, but only relate to some embodiments of the disclosure.
FIG. 1 is a schematic diagram of a memristor unit circuit. FIG. 2 is a schematic diagram of a memristor array. FIG. 3 is a schematic diagram of a convolutional neural network. FIG. 4 is a schematic diagram of the operation process of the convolutional neural network. FIG. 5A is a schematic diagram of convolution computation of a convolutional neural network based on a memristor array. FIG. 5B is a schematic diagram of complete connectivity computation for a convolutional neural network based on a memristor array. FIG. 6 is a structural schematic block diagram of a neural network according to some embodiments of the present disclosure; FIG. 7A is a parallel processing scheme of the first functional layer in the neural network parallel acceleration method shown in FIG. FIG. 7B is another parallel processing scheme of the first functional layer in the neural network parallel acceleration method shown in FIG. FIG. 8 is a flowchart of a neural network off-chip training method according to some embodiments of the present disclosure. FIG. 9 is a schematic diagram of a memristor-based neural network parallel acceleration processor according to some embodiments of the present disclosure. FIG. 10 is a structural schematic diagram of a memristor array calculation unit in the parallel acceleration processor shown in FIG. FIG. 11 is a schematic block diagram of a memristor-based neural network parallel accelerator in accordance with some embodiments of the present disclosure.

In order to describe the objectives, technical solutions and advantages of the present disclosure more clearly, the following clearly and completely describes the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all embodiments of the present disclosure. Based on the described embodiments of the present disclosure, any other embodiments obtained by a person skilled in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, technical or scientific terms used in this disclosure have the common meanings that are understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not imply any order, quantity, or importance, but are merely to distinguish between different components. Similarly, similar terms such as "one," "one," or "the" are not intended to imply a numerical limitation, but rather indicate the presence of at least one. Similar words such as “include” and “include” mean that the element or thing appearing before the word includes the elements or things listed after the word and their equivalents, but not otherwise. is not intended to exclude any element or object from Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only to indicate relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationships may change accordingly. There is

A memristor (resistive memory, phase change memory, conductive bridge memory, etc.) is a non-volatile device whose conductance state can be adjusted by applying an external excitation. Based on Kirchhoff's current law and Ohm's law, arrays composed of such devices complete multiply-accumulate operations in parallel. and both storage and computation occur in each device of the array. Based on such computing architecture, in-memory computing that does not require transfer of large amounts of data can be realized. At the same time, multiply-accumulate operations are core computational tasks required for the operation of neural networks. Therefore, the conductance of the memristor-type devices in the array can be used to represent the weight values to realize highly efficient neural network operations based on such in-memory computing.

FIG. 1 is a schematic diagram of a memristor unit circuit. As shown in FIG. 1, the memristor unit circuit adopts a 1T1R structure, ie the memristor unit circuit includes one transistor M1 and one memristor R1.

It should be noted that the transistors employed in the embodiments of the present disclosure may all be thin film transistors or field effect transistors (eg, MOS field effect transistors) or switch devices with other characteristics that are the same. Since the source and drain of the transistor employed here may be structurally symmetrical, the source and drain may not be structurally distinguished. In the embodiments of the present disclosure, in order to distinguish the two electrodes other than the gate of the transistor, it is directly described that one of them is the first electrode and the other is the second electrode.

The embodiments of the present disclosure do not limit the type of transistors employed, for example, if the transistor M1 adopts an N-type transistor, its gate is connected to the word line end WL, and the word line end WL is at a high level, for example. At the input, transistor M1 turns on. The first electrode of the transistor M1 is the source and may be connected to the source line end SL, for example the transistor M1 can receive the reset voltage by the source line end SL. A second electrode of transistor M1 is a drain and may be connected to a second electrode (eg, negative electrode) of memristor R1. A first electrode (eg positive electrode) of the memristor R1 is connected to the bit line end BL, for example the memristor R1 can receive a set voltage by the bit line end BL. For example, if the transistor M1 employs a P-type transistor, its gate is connected to the word line end WL, and the transistor M1 is turned on, for example, when the word line end WL inputs a low level. The first electrode of the transistor M1 is the drain and may be connected to the source line end SL, eg the transistor M1 may receive the reset voltage by the source line end SL. a second electrode of the transistor M1 may be a source and connected to a second pole (e.g. negative electrode) of the memristor R1, a first electrode (e.g. positive electrode) of the memristor R1 being connected to the bit line end BL; For example, memristor R1 can receive a set voltage via bit line end BL. Note that the resistive memory structure may be implemented as other structures, such as a structure in which the second electrode of the memristor R1 is connected to the source line end SL, and the embodiments of the present disclosure are not limited to this. Each of the following embodiments will be described with an example in which the transistor M1 adopts an N-type transistor.

The function of word line end WL is to apply a corresponding voltage to the gate of transistor M1, thereby controlling the on or off of transistor M1. Any operation of the memristor R1, such as a set operation or a reset operation, must first turn on the transistor M1, that is, apply an on-voltage to the gate of the transistor M1 by the word line end WL. . After turning on the transistor M1, the resistance state of the memristor R1 can be changed by, for example, applying a voltage to the source line end SL and the bit line end BL of the storage R1. For example, the memristor R1 is in a low resistance state by applying a set voltage through the bit line end BL. Further, for example, by applying a reset voltage through the source line end SL, the memristor R1 is in a high resistance state.

It should be noted that in the embodiment of the present disclosure, the resistance value of the memristor R1 becomes smaller and smaller by simultaneously applying a voltage from the word line end WL and the bit line end BL, that is, the memristor R1 changes from a high resistance state to a low resistance state. The operation of changing the memristor R1 from the high resistance state to the low resistance state is called a set operation. By simultaneously applying voltages from the word line end WL and the source line end SL, the resistance value of the memristor R1 increases more and more, that is, the memristor R1 changes from the low resistance state to the high resistance state, and the memristor R1 changes to the low resistance state. to a high resistance state is called a reset operation. For example, when memristor R1 has a threshold voltage and the input voltage amplitude is less than the threshold voltage of memristor R1, the resistance value (or conductance value) of memristor R1 is not changed. In this case, by inputting a voltage lower than the threshold voltage, it can be calculated using the resistance value (or conductance value) of the memristor R1. By inputting a voltage higher than the threshold voltage, the resistance value (or conductance value) of the memristor R1 can be changed.

FIG. 2 shows a memristor array, which consists of a plurality of memristor unit circuits shown in FIG. For example, a plurality of memristor unit circuits form an array of m rows and n columns, where m is an integer greater than 1 and n is an integer greater than or equal to 1. In FIG. 2, BL<1>, BL<2>, . , are connected to the bit lines corresponding to the row. WL<1>, WL<2>, . . . , WL<n> in FIG. A gate of the transistor is connected to a word line corresponding to the column. SL<1>, SL<2>, . . . , SL<n> in FIG. The source of the transistor is connected to the source line corresponding to the column.

The m-by-n memristor array shown in FIG. 2 can represent a neural network weight matrix of size m-by-n. For example, the neuron layer of the first layer has m neuron nodes, and is connected to bit lines of m rows in the memristor cell array shown in FIG. The neuron layer of the second layer has n neuron nodes and is connected to the source lines of n columns of the memristor cell array shown in FIG. By inputting the voltage excitation in parallel to the neuron layer of the first layer, the neuron layer of the second layer is obtained by multiplying the voltage excitation vector by the conductance matrix of the memristor array (conductance is the reciprocal of the resistance). output current can be obtained.

ここで、ｊ＝１、…、ｎであり、ｋ＝１、…、ｍである。 Specifically, based on Kirchhoff's law, the output current of the memristor array can be obtained by Equation 1,

where j=1,...,n and k=1,...,m.

In the above equation, v _k represents the voltage excitation input from neuron node k in the first neuron layer, i _j represents the output current of neuron node j in the second neuron layer, and g _k,j represents the conductance matrix of the memristor array.

As can be seen from Kirchhoff's law, memristor arrays can complete multiply-accumulate operations in parallel.

Note that, for example, in some examples, each weight in the neural network weight matrix may be implemented using two memristors. In other words, two columns of memristors in the memristor cell array can realize output of one column of output current. In this case, representing a neural network weight matrix of size m rows and n columns requires a memristor array of m rows and 2n columns.

The current output from the memristor array is an analog current, and in some cases, the analog current is converted into a digital voltage by an analog-to-digital conversion circuit (ADC) and transmitted to the neuron layer of the second layer. so that the neuron layer of the second layer can convert a digital voltage to an analog voltage by a digital-to-analog conversion circuit (DAC) and connect to the neuron layer of another layer through another memristor array. can. In some other examples, a sample-and-hold circuit can convert the analog current to an analog voltage for transmission to the neuron layer of the second layer.

Convolute Neural Networks (CNNs) are primarily used to identify two-dimensional shapes and are highly invariant to image translation, scaling, tilting or other forms of deformation. CNN simplifies the complexity of neural network models and reduces the number of weights mainly through local receptive fields and weight value sharing. With the development of deep learning technology, the application range of CNN is not limited to the field of image recognition, but it can be applied to face recognition, character recognition, animal classification, image processing and other fields.

FIG. 3 shows a schematic diagram of a convolutional neural network. For example, the convolutional neural network can be used for image processing and uses images as input and output and uses convolution kernels instead of scalar weights. FIG. 3 only shows a convolutional neural network with three neuron layers, and the embodiments of the present disclosure are not so limited. As shown in FIG. 3, the convolutional neural network includes three layers of neurons, an input layer 101, a hidden layer 102 and an output layer 103, respectively. Input layer 101 has four inputs, hidden layer 102 has three outputs, and output layer 103 has two outputs.

For example, the four inputs of input layer 101 may be four images, or four feature maps of one image. The three outputs of hidden layer 102 may be feature maps of the image input from input layer 101 .

For example, as shown in FIG. 3, a convolutional layer has weights W ^k _ij and biases b ^k _i . The weights W ^k _ij represent the convolution kernel and the biases b ^k _i are scalar quantities superimposed on the output of the convolutional layer, where k is a tag representing the input layer 101 and i and j are: These are the tags for the units in the input layer 101 and the units in the hidden layer 102, respectively. For example, the first convolutional layer 201 includes a first set of convolution kernels (W ¹ _ij in FIG. 3) and a first set of biases (b ¹ _i in FIG. 3). The second convolutional layer 202 includes a second set of convolution kernels (W ² _ij in FIG. 3) and a second set of biases (b ² _i in FIG. 3). Generally, each convolutional layer contains tens or hundreds of convolution kernels, and if the convolutional neural network is a depth convolutional neural network, it can contain at least five convolutional layers.

For example, as shown in FIG. 3, the convolutional neural network further includes a first activation layer 203 and a second activation layer 204 . A first activation layer 203 follows the first convolutional layer 201 and a second activation layer 204 follows the second convolutional layer 202 . The activation layers (e.g., first activation layer 203 and second activation layer 204) include activation functions, which are used to introduce nonlinear factors into the convolutional neural network to generate convolutional Neural networks are better able to solve complex problems. The activation function may include a rectified linear unit (ReLU) function, an sigmoid function (sigmoid function) or a hyperbolic tangent function (tanh function), or the like. The ReLU function is a unsaturated nonlinear function, and the Sigmoid and tanh functions are saturated nonlinear functions. For example, an activation layer can be a single layer of a convolutional neural network alone, or an activation layer can be a convolutional layer (e.g., a first convolutional layer 201 may include a first activation layer 203 and a second activation layer 203). Convolutional layer 202 may be included in the second activation layer 204).

For example, in the first convolutional layer 201, first, for each input, some convolution kernels W ¹ _ij of the first set of convolution kernels and some biases b ¹ _i of the first set of biases are By application, the output of the first convolutional layer 201 is obtained, and then the output of the first convolutional layer 201 is processed by the first activation layer 203 to obtain the output of the first activation layer 203 . In the second convolutional layer 202, first, for the input output in the first activation layer 203, some convolution kernels W ² _ij of the second set of convolution kernels and some of the second set of biases Applying that bias b ² _i to obtain the output of the second convolutional layer 202 , and then processing the output of the second convolutional layer 202 by the second activation layer 204 , the second activation layer 204 output is obtained. For example, the output of the first convolutional layer 201 may be the result of applying a convolution kernel W ¹ _ij to its input followed by adding a bias b ¹ _i , and the output of the second convolutional layer 202 may be the result of applying the bias b 1 i to its input. It may be the result of applying the convolution kernel W ² _ij to the output of the activation layer 203 and then adding the bias b ² _i .

Before you can use a convolutional neural network to process images, you need to train the convolutional neural network. After being trained, the convolution kernels and biases of the convolutional neural network remain unchanged during image processing. In the training process, each convolution kernel and bias are adjusted by multiple sets of input/output example images and an optimization algorithm to obtain an optimized convolutional neural network model.

FIG. 4 shows a schematic diagram of the operation process of the convolutional neural network. For example, as shown in FIG. 4, after inputting the input image to the convolutional neural network, several processing steps (convolution calculation, down-sampling, vectorization, complete connection calculation, etc. in FIG. 4) are performed sequentially. to get the corresponding output after doing The main components of a convolutional neural network can include multiple convolutional layers, multiple down-sampling layers, flattening layers and fully connected layers. In the present disclosure, it should be understood that these layers, such as multiple convolutional layers, multiple downsampling layers, flattening layers and fully connected layers, respectively refer to corresponding processing/operations, i.e. convolutional processing/operations ( 4), downsampling operations/operations (as shown in downsampling in FIG. 4), flattening operations/operations (as shown in vectorization in FIG. 4), full connection processing/operations (as shown in the complete connection calculation in FIG. 4), etc., which will not be repeated later. It should be noted that in this disclosure, these layers are used to distinguish them from the neuron layers by generically referring to layers that refer to corresponding processing/operations as functional layers. Note that the functional layer may further include an up-sampling layer (up-sampling layer), a normalization layer, etc., and the embodiments of the present disclosure are not limited thereto.

A convolutional layer is the core layer of a convolutional neural network. In a convolutional layer of a convolutional neural network, one neuron is connected to some adjacent layer's neurons. A convolutional layer can apply several convolution kernels (also called filters) to an input image to extract multiple kinds of features of the input image. Each convolution kernel can extract one kind of features. The convolution kernel is generally initialized in the form of a random fraction matrix, and in the training process of the convolution neural network, the convolution kernel learns to obtain reasonable weight values. The results obtained after applying one convolution kernel to the input image are called feature maps, and the number of feature maps is equal to the number of convolution kernels. Each feature map is composed of several rectangular arrayed neurons, and neurons of the same feature map share a weight value, where the shared weight value is the convolution kernel. A feature map output from a first convolutional layer can be input to an adjacent next convolutional layer and reprocessed to obtain a new feature map. For example, as shown in FIG. 4, a first convolutional layer can output a first feature map, which is input to a second convolutional layer and processed again to produce a first feature map. 2 Get the feature map.

For example, as shown in FIG. 4, a convolution layer can convolve data in a local region of experience with an input image using different convolution kernels, and the convolution results are input to the activation layer. , and the activation layer is calculated based on the corresponding activation function to obtain the feature information of the input image.

のような方式で行うことができ、
ここで、ｖは、ｋ個の要素を含むベクトルであり、ｆは、ｉ行ｊ列を有する行列である。 For example, as shown in FIG. 4, a downsampling layer is placed between adjacent convolutional layers, where the downsampling layer is one form of downsampling. On the one hand, the downsampling layer is used to reduce the scale of the input image, simplify the computational complexity, and reduce the overtraining phenomenon to some extent. On the other hand, the downsampling layer can perform feature compression and extract the main features of the input image. A downsampling layer can reduce the size of feature maps, but does not change the number of feature maps. For example, if an input image with a size of 12×12 is sampled by a 6×6 convolution kernel, a 2×2 output image can be obtained, which is equivalent to 36 pixels on the input image. pixels are merged into one pixel in the output image. The output of the final downsampling layer can be input to a flattening layer to perform a flattening operation (Flatten). The flattening layer may transform the feature map (two-dimensional image) into a vector (one-dimensional). The flattening operation includes:

can be done in a manner like
where v is a vector containing k elements and f is a matrix with i rows and j columns.

The output of the planarization layer (ie, a one-dimensional vector) can then be input into one Fully Connected Layer (FCN). A fully connected layer may have a similar structure to the convolutional neural network shown in FIG. 3, except that the fully connected layer uses different scalar quantities instead of convolution kernels. A full connection layer is used to connect all extracted features. The output of a fully connected layer may be a one-dimensional vector.

Calculation processes such as convolution calculation and complete connection calculation in a convolutional neural network mainly include sum-of-products operations, so functional layers such as convolution layers and complete connection layers can be realized by memristor arrays. For example, both the convolutional and fully connected layer weights can be represented by the array conductance of the memristor array, while the convolutional and fully connected layer inputs can be represented by corresponding voltage excitations. Thereby, convolution calculation and complete connection calculation can be realized respectively based on Kirchhoff's law described above.

FIG. 5A is a schematic diagram of convolution computation of a convolutional neural network based on a memristor array, and FIG. 5B is a schematic diagram of complete connection computation of a convolutional neural network based on a memristor array.

As shown in FIG. 5A, one memristor array can be used to realize the convolution computation of one convolution layer, for example, the input image (shown as digital image “2” in FIG. 5A) is subjected to the convolution process. It can be carried out. For example, in some examples, the convolutional layer includes multiple convolution kernels, each row of the memristor cell array corresponds to one convolution kernel, and the multiple memristors in each row correspond to one convolution kernel. Used to represent the value of each element. For example, for a 3×3 convolution kernel, each row of the memristor array uses 9 memristors to represent the values of the 9 elements of the convolution kernel. It should be noted that the manner in which convolutional layers are characterized using memristor arrays is exemplary, and embodiments of the present disclosure include, but are not limited to, this.

What should be understood is that when a convolutional layer performs a convolution process on its input image, it should divide the input image into multiple image sub-blocks (whose size is the same as the size of the convolution kernel), and then A convolution operation is performed on each image sub-block using a convolution kernel. When a memristor array is used to implement the convolution operation of the convolutional layer, multiple convolution kernels can process each image sub-block in parallel, but still divide the data of each image sub-block into batches ( That is, each image sub-block must be serially input to the memristor array to implement the convolution process for the entire input image.

As shown in FIG. 5B, one memristor array can be used to realize the fully connected computation of one fully connected layer. For example, in some examples, each column of the memristor array is used to receive a fully connected layer input and each row is used to provide a fully connected layer output, as shown in FIG. 5B. A plurality of memristors in each row are used to indicate respective weights corresponding to the outputs in that row. It should be noted that the manner in which the memristor array is used to characterize a fully connected layer is exemplary, and embodiments of the present disclosure include, but are not limited to this.

It should be understood that the fully connected computation of the fully connected layer can be completed in one go. The convolutional computation of the convolutional layer requires batch-serial completion, and after processing all batches, the convolutional computation of the convolutional layer needs to be completed. Therefore, there is always a severe speed mismatch between convolutional computations and fully connected connections (the time taken by convolutional computations is much greater than the time taken by fully connected computations). Therefore, when implementing a convolutional neural network based on a memristor array, the performance of the convolutional neural network is always limited to the memory array with the lowest efficiency, such as the memristor array corresponding to the convolutional layer (efficiency bottleneck). Called).

At least one embodiment of the present disclosure provides a parallel acceleration method for a memristor-based neural network. The neural network includes a plurality of sequentially arranged functional layers, the plurality of functional layers being positioned after a first functional layer including a plurality of parallel first memristor arrays and the first functional layer. and a second functional layer, wherein the plurality of first memristor arrays are used to perform the operation of the first functional layer and output the operation result to the second functional layer. The parallel acceleration method includes using a plurality of first memristor cell arrays to perform operations on a first functional layer in parallel and outputting operation results to a second functional layer.

At least one embodiment of the present disclosure further provides a processor and apparatus corresponding to the above parallel acceleration method.

A parallel acceleration method, processor, and apparatus for a memristor-based neural network according to an embodiment of the present disclosure perform operations of a first functional layer in parallel by a plurality of first memristor arrays to generate a memristor-based neural network. Acceleration to the motion process can be realized. The memristor-based neural network architecture concept and parallel acceleration method are widely applied to various deep neural network models and different types of memristors, and help to solve the speed mismatch problem of deep neural network models.

Several embodiments of the present disclosure and examples thereof will now be described in detail with reference to the drawings.

At least one embodiment of the present disclosure provides a parallel acceleration method for a memristor-based neural network. FIG. 6 shows a structural schematic block diagram of a neural network according to some embodiments of the present disclosure, FIG. 7A shows the parallel processing scheme of the first functional layer in the parallel acceleration method of the neural network shown in FIG. 6; FIG. 7B shows another parallel processing scheme of the first functional layer in the neural network parallel acceleration method shown in FIG.

As shown in FIG. 6, the neural network includes a plurality of sequentially set functional layers. For example, as shown in FIG. 6, the plurality of functional layers includes a first functional layer and a second functional layer located after the first functional layer. For example, in some embodiments, the plurality of functional layers may further include functional layers other than the first functional layer and the second functional layer, and the present disclosure is not limited thereto.

For example, in some embodiments, as shown in FIGS. 7A and 7B, the first functional layer includes a plurality of parallel first memristor arrays, and a plurality of first memories corresponding to the first functional layer. The star array is used to execute the operations of the first functional layer in parallel and output the operation results to the second functional layer, thus realizing acceleration for the operation process of the neural network. For example, in some embodiments, if the first functional layer contains only one first memristor array, the first functional layer is an efficiency bottleneck that limits the performance of the neural network, e.g. The functional layer is a convolutional layer.

For example, in some embodiments, the neural network is a convolutional neural network that includes multiple convolutional layers. In general, the initial convolutional layer (i.e., the first convolutional layer) for performing convolutional processing on the input image of the neural network has the largest amount of computation and takes the longest time, which is the initial convolutional layer. The first functional layer can generally include the initial convolutional layer, since it is the efficiency bottleneck of neural networks. Note that this disclosure includes, but is not limited to, this. For example, in another embodiment, as shown in FIG. 6, the plurality of functional layers of the neural network may further include a third functional layer positioned before the first functional layer, the output of the third functional layer being The first functional layer may be another convolutional layer other than the initial convolutional layer of the neural network, such as an intermediate convolutional layer, as it is provided to the first functional layer as input for the first functional layer.

It should be appreciated that the neural network may include a plurality of first functional layers (eg, convolutional layers) such that a plurality of first memristor arrays corresponding to each first functional layer provide can be performed in parallel to improve the parallelism of the neural network, and further accelerate the operation process of the neural network. For example, the number of first memristor arrays corresponding to each first functional layer may be the same or different, and embodiments of the present disclosure do not limit this.

For example, the second functional layer may include one of a convolution layer, a downsampling layer, a flattening layer, a fully connected layer, and the like. For example, the third functional layer may include one of a convolutional layer, a downsampling layer, and the like. However, the embodiments of the present disclosure are not intended to limit this.

For example, FIGS. 7A and 7B both illustratively show the case where the first functional layer includes three first memristor arrays, which should not be considered a limitation on the present disclosure. That is, the number of first memristor arrays included in the first functional layer can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

For example, as shown in FIGS. 7A and 7B, the memristor-based neural network parallel acceleration method uses a plurality of first memristor arrays to perform the operations of the first functional layer in parallel, and the operation results are Outputting to a second functional layer (not shown in FIGS. 7A and 7B).

For example, in some embodiments, as shown in FIG. 7A, input data received by the first functional layer (shown in digital image "2" in FIG. 7A) is first serialized to a plurality of first memristor arrays. It can be divided into a corresponding plurality of sub-input data (shown in three parts divided from digital image "2" in FIG. 7A). Then, the operations of the first functional layer are performed in parallel on the plurality of sub-input data using the plurality of first memristor arrays to correspondingly generate a plurality of sub-operation results. Then, the plurality of sub-operation results can be further spliced and a second functional layer can be used to perform the operation of the second functional layer on the spliced result.

For example, in some examples, as shown in FIG. 7A, the first functional layer is a convolutional layer, and each first memristor array included in the first functional layer is a scheme as shown in FIG. 5A. can realize the convolution operation of the first functional layer.

For example, in some cases, in a plurality of sub-input images (i.e., sub-input data) obtained by dividing an input image (i.e., input data), adjacent sub-input images generally overlap each other. may and of course be non-overlapping, and embodiments of the present disclosure are not limited to this. For example, in some examples, the sizes of the plurality of sub-input data are basically the same, so that each sub-input data has the time it takes to perform convolution processing by the corresponding first memristor array. are basically the same, and overall, it can accelerate the processing speed of the first functional layer, that is, the processing speed of the neural network.

For example, in some examples, the plurality of sub-input data may be provided to the plurality of first memristor arrays respectively in any order, where each first memristor array of sub-input data can be processed. For example, in some other examples, the plurality of sub-input data should be provided in a predetermined order corresponding to the plurality of first memristor arrays. The storage array can process sub-input data corresponding thereto.

For example, if one first memory cell array is used to process an input image (see FIG. 5A), the time taken to operate the first functional layer is denoted as t. For example, when three sub-input images obtained by dividing an input image using three first memristor arrays are processed in parallel (see FIG. 7A), the time taken to operate the first functional layer is Decrease by t/3. Therefore, the parallel acceleration method shown in FIG. 7A can realize the acceleration of the operation process of the neural network processing single input data.

For example, in some examples, the second functional layer may be one of a convolutional layer, a downsampling layer, a flattening layer, and a fully connected layer, which embodiments of the present disclosure do not limit. .

For example, in another embodiment, as shown in FIG. 7B, first a plurality of input data received by the first functional layer (shown in digital images "2", "1", and "4" in FIG. 7B) are Each can be provided for a plurality of first memristor arrays. Next, using at least a part of the plurality of first memristor arrays, the operations of the first functional layer are performed in parallel on the plurality of received input data, and the plurality of sub-operation results are corresponded. to generate. Then, the operation of the second function layer can be performed on each of the plurality of sub-operation results using the second function layer.

For example, in some examples, as shown in FIG. 7B, the first functional layer is a convolutional layer, and each first memristor array included in the first functional layer is a scheme as shown in FIG. 5A. can realize the convolution operation of the first functional layer. For example, the plurality of input data may be assigned to the plurality of first memristor arrays in any order, in which case each first memristor array may process any input data. can. For example, the plurality of input data may be different from each other, and may of course be partially or entirely the same, and the embodiments of the present disclosure are not limited to this.

For example, if one first memristor array is used to process the input image (see FIG. 5A), the time taken for the operation of the first functional layer is denoted as t1, and the time taken for the subsequent functional layer operations is denoted by t1. Denote t2, and if t1>t2, then the time used to process three input images using the neural network is at least about 3*t1+t2 (e.g., the first functional layer is the current When processing the data of one input image, subsequent functional layers can process the associated data of previous input images). By comparison, for example, when processing three input images in parallel using three first memristor arrays (see FIG. 7B), to process the three input images using a neural network: The time used is about t1+3*t2. The time saved thereby is 2*(t1-t2). That is, the parallel acceleration method shown in FIG. 7B can realize acceleration to the operation process in which the neural network processes multiple input data.

It should be understood that the parallel acceleration method shown in FIG. 7A and the parallel acceleration method shown in FIG. 7B can be applied comprehensively to the same neural network (e.g., different first functional layers of the same neural network), Embodiments of the present disclosure do not limit this.

The neural network according to the embodiment of the present disclosure can adopt the above parallel acceleration method to operate, and in the operation process, the first functional layer is operated in parallel by a plurality of first memristor arrays. can be implemented to achieve acceleration for the neural network operation process. The neural network architecture concept and its parallel acceleration method are widely applied to various deep neural network models and different kinds of memristors, and help to solve the speed mismatch problem of deep neural network models.

At least one embodiment of the present disclosure further provides an off-chip training method for a memristor-based neural network. For example, the training method is used to obtain the parameters of the neural network according to the previous embodiment. For example, as shown in FIGS. 6, 7A and 7B, the neural network includes a plurality of sequentially configured functional layers, the plurality of functional layers being a first functional layer and a first functional layer followed by a first functional layer. a second functional layer located in the first functional layer, the first functional layer including a plurality of first memristor arrays arranged in parallel, the plurality of first memristor arrays performing operations of the first functional layer; is used to output to the second functional layer.

It should be understood that the neural network training method generally consists of using the neural network to process the training input data to obtain the training output data, and based on the training output data, by the loss function Calculating the loss value of the neural network, correcting the parameters of the neural network based on the loss value, determining whether the training of the neural network satisfies a predetermined condition, and if the predetermined condition is not satisfied , repeatedly performing the training process and, if a predetermined condition is met, stopping the training process and obtaining a trained neural network. Of course, when training a neural network, it is generally necessary to initialize the parameters of the neural network. For example, parameters of the neural network can generally be initialized to random numbers, such as random numbers conforming to a Gaussian distribution, and embodiments of the present disclosure are not limited thereto. It should be understood that the neural network training method according to the embodiments of the present disclosure can also refer to the above general training steps and processes.

After obtaining each weight parameter by off-chip training, the conductance of each device in the memristor array is programmed by set and reset operations to realize the corresponding weight. The specific programming method and memristor weight organization scheme are not limited.

FIG. 8 is a flowchart of a neural network off-chip training method according to some embodiments of the present disclosure. For example, as shown in FIG. 8, the off-chip training method can include the following steps S10-S30.

Step S10, building a mathematical model of the neural network.

For example, in some examples, software (eg, program code, etc.) may be used to construct mathematical models according to embodiments of the present disclosure.

Step S20, training the mathematical model to obtain a trained mathematical model.

For example, in some examples, the above mathematical models can be run and trained based on processors, memristors, and the like. For example, the training steps and processes of the mathematical model can refer to the general training steps and processes and will not be repeated here.

Step S30, write the weight parameters of the trained mathematical model into the memristor array corresponding to the neural network.

For example, in some examples, a first functional layer in the mathematical model includes a first weight parameter. In the process of training the mathematical model, the training input data of the first functional layer are processed according to the first weight parameter during forward propagation. When propagating in the backward direction, modify the first weight parameter to obtain the first weight parameter of the first trained function layer. In this case, the step of writing the weight parameter of the trained mathematical model to the memristor array corresponding to the neural network, i.e. step S30, is to write the first weight parameter of the first functional layer in the trained mathematical model to a plurality of Writing to each of the first memristor arrays. At this time, each first memristor array corresponding to the first functional layer includes the same conductance weight matrix.

For example, in some other examples, a first functional layer in the mathematical model includes multiple first weighting parameters. In the training process of the mathematical model, during forward propagation, the training input data received by the first functional layer in the mathematical model is divided into a plurality of training sub-input data corresponding to the plurality of first weight parameters one by one. , performing in parallel a first functional layer operation on the plurality of training sub-input data using the plurality of first weight parameters to generate a plurality of training sub-operation results; Update the parameter value of the first weight parameter according to the training sub-operation result corresponding to the parameter and the training intermediate data corresponding to the training sub-operation result. The same weight parameter may be written to each array, or different weight parameters may be written to each array, based on different specific methods of off-chip training.

In this case, the step of writing the weight parameters of the trained mathematical model into the memristor array corresponding to the neural network, i.e. step S30, respectively writes the plurality of first weight parameters of the first functional layer in the trained mathematical model to Writing to a plurality of first memristor arrays one by one. The resulting neural network can then be used to implement the parallel acceleration method shown in FIG. 7A.

For example, in some further examples, the first functional layer in the mathematical model includes a plurality of first weighting parameters. In the training process of the mathematical model, in forward propagation, a plurality of training input data received by the first functional layer in the mathematical model are respectively provided to the plurality of first weight parameters, and the plurality of first weight parameters performing in parallel a first functional layer operation on at least a portion of the plurality of training input data using the parameters to generate a plurality of training sub-operation results corresponding to each first weight parameter; Update the parameter value of the first weight parameter according to the training sub-operation result and the training intermediate data corresponding to the training sub-operation result.

In this case, the step of writing the weight parameters of the trained mathematical model into the memristor array corresponding to the neural network, i.e. step S30, respectively writes the plurality of first weight parameters of the first functional layer in the trained mathematical model to Writing to a plurality of first memristor arrays one by one. At this time, the obtained neural network may be used to implement the parallel acceleration method shown in FIG. 7B, or may be used to implement the parallel acceleration method shown in FIG. 7A.

Therefore, in the memristor-based parallel acceleration method for neural networks according to some other embodiments of the present disclosure, the neural network weight parameters are obtained by the above-described off-chip training method, and the neural network weight parameters are obtained from the first The first functional layer weight parameter including the functional layer weight parameter is written to the plurality of first memristor arrays to determine the conductance of the plurality of first memristor arrays. It should also be understood that the weight parameters of the neural network obtained by the off-chip training method further include weight parameters of other functional layers other than the first functional layer, and the weight parameters of the other functional layers are By writing to the memristor arrays corresponding to other functional layers, the conductances of the memristor arrays corresponding to other functional layers are determined.

At least one embodiment of the present disclosure further provides a memristor-based neural network parallel acceleration processor, which is used to perform the aforementioned parallel acceleration method. FIG. 9 is a schematic diagram of a memristor-based neural network parallel acceleration processor according to some embodiments of the present disclosure.

For example, as shown in FIG. 6, the neural network includes a plurality of sequentially set functional layers, and the plurality of functional layers includes a first functional layer. For example, as shown in FIG. 9, the parallel acceleration processor may include multiple computational cores, and the computational cores of each memristor may communicate with each other. At the same time, inside each computing core further includes a plurality of memristor array computing units.

For example, in some embodiments, the plurality of memristor array calculation units includes a plurality of first memristor array calculation units, and the weight parameters of the first functional layer are written to the plurality of first memristor array calculation units. and the plurality of first memristor array computation units are configured to perform operations corresponding to operations of the first functional layer in parallel. That is, by programming and writing the weights of a functional layer in the neural network to different computation cores or memristor array computation units, parallel acceleration computation for operations on the functional layer of multiple memristor arrays can be achieved. For example, the plurality of first memristor arrays can adopt the parallel acceleration method according to any one of the above embodiments to realize parallel acceleration calculation of the operation of the first functional layer.

FIG. 10 is a structural schematic diagram of a memristor array calculation unit in the parallel acceleration processor shown in FIG. Hereinafter, the principle of operation of the memristor array calculation unit will be described in detail with reference to the structure of the memristor array calculation unit shown in FIG.

For example, as shown in FIG. 10, the memristor array calculation unit includes a memristor array and peripheral circuits.

For example, in some examples, the memristor array includes 128×128 memristors, and embodiments of the present disclosure include, but are not limited to, as shown in FIG. For example, in some examples, the peripheral circuits include switch arrays, multiplexers, sample-and-hold modules (S&H modules), analog-to-digital conversion modules (ADCs) and shift & accumulators (Sh&A), etc., as shown in FIG.

ここで、ｓ＝０、…、Ｂ－１であり、Ｂは、入力データのビット数（例えば、図１０に示すように、Ｂ＝８）を表し、Ｖ_ｋは、第ｋ行の入力データに対応する電圧励起を表し、Ｖ_Ｒは、一定の基準電圧（例えば、図１０に示された読み出し電圧）を表し、ａ_ｋ，ｓは、［ｓ］番目の制御パルスのレベルを表す。例えば、一部の例において、ａ_ｋ，ｓは、８ビットの入力データａ_ｋのバイナリコード（ａ_ｋ，７、ａ_ｋ，６、…、ａ_ｋ，０）のうちの一つに対応することができる。ａ_ｋ，ｓ＝１の場合、［ｓ］番目の制御パルスがハイレベルであることを表し、それによりスイッチアレイにおける対応するスイッチをオンにすることができ、読み出し電圧Ｖ_Ｒをメモリスタアレイの第ｋ行に提供する。ａ_ｋ，ｓ＝０の場合、［ｓ］番目の制御パルスがローレベルであることを表し、それによりスイッチアレイにおける対応するスイッチをオフにすることができ、同時に、スイッチアレイにおける他のスイッチをオンにし、接地レベルをメモリセルアレイのｋ行目に提供し、すなわちこの時にメモリアレイの第ｋ行に信号を提供しない。 For example, in some examples, as shown in FIG. 10, the input of the memristor array computation unit includes a plurality of 8-bit input data. For example, each bit of each input data corresponds to one control pulse, and each control pulse is encoded according to the value of each bit. The specific encoding method is as follows.

where s= ₀ , . , V _R represents a constant reference voltage (eg, the read voltage shown in FIG. 10), and a _k,s represents the level of the [s] th control pulse. For example, in some examples, a _k,s corresponds to one of the binary codes (a _k,7 , a _k,6 , . . . , a _k,0 ) of the 8-bit input data a _k . be able to. If a _k,s =1, it means that the [s] th control pulse is high level, which can turn on the corresponding switch in the switch array, and apply the read voltage V _R to the memristor array. Provided in line k. If a _k,s =0, it means that the [s] th control pulse is at low level, which can turn off the corresponding switch in the switch array, and at the same time turn off the other switches in the switch array. It is turned on and the ground level is provided to the kth row of the memory cell array, ie no signal is provided to the kth row of the memory array at this time.

It should be understood that, as shown in FIG. 10, on the one hand, a plurality of input data are input in parallel to the memristor array. On the other hand, each input data is characterized corresponding to a plurality (eg, 8) of control pulses, which are serially input to the memristor cell array. As a matter of course, the same sequence of control pulses corresponding to different input data are input in parallel to the memristor cell array.

により得ることができ、
ここで、ｋ＝１、…、ｍであり、ｊ＝１、…、ｎであり、ｍは、メモリスタアレイの行数を示し、ｎは、メモリスタアレイの列数を示し、ｉ_ｊは、全ての入力データに対応するメモリスタアレイの第ｊ列の出力電流を示し、ｉ_ｊ，ｓは、全ての［ｓ］番目の制御パルスに対応するメモリスタアレイの第ｊ列のパルス出力電流を示し、ｇ_ｋ，ｊは、メモリスタアレイのコンダクタンス行列を示す。 Based on Kirchhoff's law, the output current of the memristor array is

can be obtained by
where k=1, . . . , m and _j =1, . , indicates the output current of the j-th column of the memristor array corresponding to all input data, and i _j,s is the pulse output current of the j-th column of the memristor array corresponding to all [s]th control pulses. and g _k,j denotes the conductance matrix of the memristor array.

As can be seen from the equation, when every [s]-th control pulse corresponding to all input data is applied to the switch array, the read voltage V _R is parallel to the memristor with the adjustment of the high-level control pulse. The array can be applied to cause the memristor array to correspondingly output a plurality of pulsed output currents i _j,s where i _j,s is Equation (5) below.

In the embodiment shown in FIG. 10, a weighting (the weighting value corresponding to the pulse output current i _j,s is 2s) is added to the pulse output current corresponding to each control pulse based on the above equation, and the j-th It does not obtain the column output current _ij . For example, as shown in FIG. 10, each pulsed output current is converted into a holdable voltage signal by a sample and hold (S&H) module and then quantized into digital information (e.g., binary digital information) by an analog-to-digital conversion module. Finally, the shift & accumulator shifts and accumulates the binary digital information corresponding to each pulse output current. For example, the binary digital information corresponding to pulsed output current i _j,1 is one bit for the binary digital information corresponding to pulsed output current i _j,0 (i.e., the least significant bit of the former is the penultimate bit of the latter). ), and the binary digital information corresponding to the pulse output current i _j,2 moves one bit forward with respect to the binary digital information corresponding to the pulse output current i _j,1 Go and by analogy with this.

For example, in some embodiments, as shown in FIG. 10, the output of each column of the memristor array is alternately converted by two sets of sample-and-hold modules, thereby increasing parallelism in hardware operation. be able to. At the same time, in order to save the power consumption and area of the processor chip, the analog-to-digital conversion (ADC) module can work in a time-division multiplexing manner, for example, four columns of output can be connected to one analog-to-digital conversion module. Share. When the memristor array calculation unit operates, the [s]th bit (that is, the [s]th control pulse) at the current time is taken as the input signal of the calculation unit, and the signal is switched to control the switch array to control the switch array. A set of sample-and-hold modules is gated to simultaneously convert the pulsed output current on the string to a corresponding voltage for output. At the same time, the analog-to-digital conversion module, assisted by a multiplexer, rapidly quantizes the pulse output current of the previous time (ie, the time corresponding to the [s−1]th control pulse). Subsequently, at the next time, the [s+1]th bit (i.e., the [s+1]th control pulse) is taken as the input signal of the calculation unit, and the signal is switched to control the switch array to control the switch array of the second set of sample-and-hold modules. and at the same time the analog-to-digital conversion module quantizes the voltage values held by the previous first set of sample-and-hold modules. For example, in the working process of the memristor array calculation unit, all switching operations can be realized by controlling multiplexers.

It should be noted that the parallel acceleration processor shown in FIG. 9 and the memristor array calculation unit shown in FIG. 10 are both exemplary, and the embodiments of the present disclosure do not limit their specific implementations and details. .

For the technical effects of the parallel acceleration processor according to the embodiments of the present disclosure, reference can be made to the description corresponding to the parallel acceleration method in the previous embodiments, and the description is omitted here.

At least one embodiment of the present disclosure further provides a memristor-based neural network parallel accelerator. FIG. 11 is a schematic block diagram of a memristor-based neural network parallel accelerator in accordance with some embodiments of the present disclosure. For example, as shown in FIG. 11, the parallel acceleration device includes the parallel acceleration processor according to the above embodiment, and an input interface and an output interface connected to the parallel acceleration processor. For example, the parallel acceleration device can perform the aforementioned parallel acceleration method by means of a parallel acceleration processor therein.

For example, in some examples, as shown in FIG. 11, the parallel accelerator further includes a system bus, and the parallel accelerator processor and the input and output interfaces can communicate with each other via the system bus. . For example, the input interface is configured to receive instructions from an external computing device, user, or the like to control the operation, or the like, of the parallel acceleration processor. For example, the parallel accelerator is configured to output an operation result of the parallel acceleration processor. For example, an external device that communicates with the parallel accelerator via input and output interfaces may be included in any type of environment that provides a user interface with which a user can interact. Types of user interfaces include, for example, graphical user interfaces and natural user interfaces. For example, a graphical user interface can receive input from a user employing input devices such as a keyboard, mouse, remote control, etc., and provide output to an output device such as a display. Also, the natural user interface allows the user to interact with the parallel accelerator in a manner that does not require the user to be strongly constrained to input devices such as keyboards, mice, remote controls, and the like. In contrast, natural user interfaces include voice recognition, touch and pointing pen identification, on- and near-screen gesture recognition, air gestures, head and eye tracking, voice and sound, vision, touch, gestures, and machine intelligence. can rely on.
Also, although the parallel accelerator is shown as a single system in FIG. 11, the parallel accelerator may be a distributed system and even located in a cloud facility (including a public network or private cloud). good. Thus, for example, multiple devices can communicate over a network connection and jointly perform tasks described as being performed by a parallel accelerator.

For example, the execution process of the parallel acceleration method can refer to the related descriptions in the embodiments of the parallel acceleration method above, and will not be described repeatedly.

It should be noted that the parallel accelerator according to the embodiments of the present disclosure is only an example and not a limitation. For example, to achieve the required functions of the parallel accelerator, those skilled in the art can set up other common parts or structures based on the specific application scene. , the embodiments of the present disclosure do not limit this.

For the technical effects of the parallel acceleration apparatus according to the embodiments of the present disclosure, reference can be made to the description corresponding to the parallel acceleration method and the parallel acceleration processor in the previous embodiments, and the description is omitted here.

For this disclosure, the following points need further explanation.
(1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the absence of conflict, features in the same and different embodiments of the disclosure may be combined with each other.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any change or replacement that can be easily imagined by a person skilled in the art within the technical scope disclosed in the present disclosure shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should follow the protection scope of the claims.

Claims (14)

A parallel acceleration method for a memristor-based neural network, comprising:
The neural network includes a plurality of sequentially arranged functional layers, the plurality of functional layers being a first functional layer including a plurality of first memristor arrays arranged in parallel and located after the first functional layer. and a second functional layer for performing, the plurality of first memristor arrays are used to perform operations of the first functional layer in parallel and output operation results to the second functional layer,
The parallel acceleration method includes:
A parallel acceleration method, comprising the step of performing operations of the first functional layer in parallel using the plurality of first memristor arrays and outputting the operation results to the second functional layer. The step of executing the operations of the first functional layer in parallel using the plurality of first memristor arrays and outputting the operation results to the second functional layer includes:
dividing the input data received by the first functional layer into a plurality of sub-input data corresponding to the plurality of first memristor arrays;
performing in parallel the operations of the first functional layer on the plurality of sub-input data using the plurality of first memristor cell arrays to correspondingly generate a plurality of sub-operation results. A parallel acceleration method according to claim 1. 3. The parallel acceleration method of claim 2, further comprising joining the plurality of sub-operation results and using the second functional layer to perform the operation of the second functional layer on the joined result. 4. The parallel acceleration method according to claim 2 or 3, wherein sizes of said plurality of sub-input data are basically the same. The step of executing the operations of the first functional layer in parallel using the plurality of first memristor arrays and outputting the operation results to the second functional layer includes:
respectively providing a plurality of input data received by the first functional layer to the plurality of first memristor arrays;
using at least a portion of the plurality of first memristor cell arrays to perform the operations of the first functional layer in parallel on the plurality of received input data to correspond to a plurality of sub-operation results; 2. The parallel acceleration method of claim 1, comprising the steps of: 6. The parallel acceleration method of claim 5, further comprising performing operations of the second functional layer on each of the plurality of sub-operation results using the second functional layer. 7. The parallel acceleration method according to claim 5, wherein said plurality of input data are different from each other. The parallel acceleration method according to any one of claims 1 to 7, wherein said neural network is a convolutional neural network. 9. The parallel acceleration method of claim 8, wherein said first functional layer is an initial convolutional layer of said neural network. A parallel acceleration method according to any one of claims 1 to 9, wherein said plurality of functional layers further comprises a third functional layer, the output of said third functional layer being provided to said first functional layer. The weight parameters of the neural network are obtained by off-chip training, the weight parameters of the neural network include the weight parameters of the first function layer, and the weight parameters of the first function layer are the plurality of first memristors. A parallel acceleration method according to any one of claims 1 to 10, wherein the conductance of said plurality of first memristor arrays is determined by writing to the array. The weight parameters of the neural network further include weight parameters of functional layers other than the first functional layer, and the weight parameters of the other functional layers are written in memristor arrays corresponding to the other functional layers. 12. The parallel acceleration method according to claim 11, wherein the conductance of the memristor array corresponding to said other functional layer is determined at . A memristor-based neural network parallel acceleration processor comprising:
The neural network includes a plurality of sequentially set functional layers, the plurality of functional layers including a first functional layer,
The parallel acceleration processor includes a plurality of memristor array calculation units, the plurality of memristor array calculation units includes a plurality of first memristor array calculation units, and the weight parameter of the first functional layer is the plurality of memristor array calculation units. wherein the plurality of first memristor array computation units are configured to perform in parallel operations corresponding to operations of the first functional layer . A parallel accelerator for a memristor-based neural network, comprising:
A parallel acceleration processor according to claim 13;
an input interface and an output interface connected to the parallel acceleration processor;
A parallel acceleration apparatus, wherein the input interface is configured to receive instructions to control operation of the parallel acceleration processor, and the output interface is configured to output an operation result of the parallel acceleration processor.

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