JP2022522590A - Packaging substrate and semiconductor device including it - Google Patents

Abstract

An embodiment relates to a packaging substrate and a semiconductor device, which includes an element portion including a semiconductor element; and a packaging substrate electrically connected to the element portion; and has a glass substrate as a core in the packaging substrate. By applying as, the semiconductor device and the motherboard are connected closer to each other so that the electric signal is transmitted in the shortest possible distance. Therefore, by greatly improving the electrical characteristics such as the signal transmission speed and substantially preventing the generation of parasitic elements, the insulating film processing process can be further simplified, and a packaging substrate applicable to high-speed circuits can be obtained. offer. [Selection diagram] FIG. 4

Description

An embodiment relates to a packaging substrate and a semiconductor device including the packaging substrate.

[Cross-reference with related applications]

This application is prioritized by US Provisional Application Patent Application No. 62 / 814,945 filed March 7, 2019 and US Provisional Application Patent Application No. 62 / 814,949 filed March 7, 2019. The contents of the basic application of the priority right, which has the benefit of the right, are all included as the contents of this application.

In manufacturing electronic components, embodying a circuit on a semiconductor wafer is called the pre-process (FE: Front-End), and assembling the wafer into a state that can be used in an actual product is called the post-process (BE: Back-End). ), And this post-process includes a packaging process.

The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as nano-scale line widths below the micro level, more than 10 million cells, high-speed operation, and a large amount of heat release, but it is a technology that relatively perfectly packages these. Is not supported. Therefore, the electrical performance of a semiconductor may be determined by the packaging technology and the electrical connection thereof, rather than the performance of the semiconductor technology itself.

As the material of the packaging substrate, ceramic or resin is applied. In the case of a ceramic substrate, it is not easy to mount a high-performance high-frequency semiconductor element because the resistance value is high or the dielectric constant is high. In the case of a resin substrate, a relatively high-performance high-frequency semiconductor element can be mounted, but there is a limit to the reduction of the wiring pitch.

In recent years, research is underway to apply silicon and glass to high-end packaging substrates. By forming a through hole in a silicon or glass substrate and applying a conductive substance to the through hole, the length of the wiring between the element and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

As a related precedent,

Korean Published Patent Gazette No. 10-2019-0008103,

Korean Published Patent Gazette No. 10-2016-0114710,

There is a Korean registered patent gazette No. 10-1468680 and the like.

An object of the embodiment is to provide a more integrated packaging substrate and a semiconductor device including the packaging substrate by applying a glass substrate.

In order to achieve the above object, the semiconductor device according to one embodiment is

A semiconductor device portion in which one or more semiconductor elements are located; a packaging substrate electrically connected to the semiconductor element; and electrically connected to the packaging substrate to transmit an external electrical signal to the semiconductor element. , A motherboard that connects the semiconductor devices to each other;

The packaging substrate includes a core layer and an upper layer located on the core layer.

The core layer includes a glass substrate and a core via.

The glass substrate has a first surface and a second surface facing each other.

The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.

The core layer includes a core distribution layer located on the surface of the glass substrate or core via.

At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.

The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.

The thickness of the thin electric conductive layer of the core distribution layer may be the same as the width of the thin electric conductive layer of the upper layer, but may be thicker than that.

In one embodiment, the thickness of the thin electric conductive layer of the core distribution layer may be 1 to 12 times thicker than the width of the thin electric conductive layer of the upper layer.

In one embodiment, the upper insulating layer and the upper distribution pattern are included.

The upper insulating layer is located on the first surface and is located on the first surface.

The upper distribution pattern is incorporated in the upper insulating layer as an electrically conductive layer in which at least a part thereof is electrically connected to the core distribution layer.

The upper distribution pattern contains at least a part thereof and a fine pattern.

The width and spacing of the fine patterns may each be less than 4 μm.

In one embodiment, the second surface distribution pattern is an electrically conductive layer located on the second surface.

The width of the thick second surface distribution pattern may be 1 to 20 times the width of the thin electrical conductive layer of the upper layer.

In order to achieve the above object, the packaging substrate according to another embodiment is

Including a core layer and an upper layer located on the core layer.

The core layer includes a glass substrate and a core via.

The glass substrate has a first surface and a second surface facing each other.

The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.

The core layer includes a core distribution layer located on the surface of the glass substrate or core via.

At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.

The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.

The thickness of the thin electric conductive layer of the core distribution layer may be the same as the width of the thin electric conductive layer of the upper layer, but may be thicker than that.

In order to achieve the above object, the semiconductor device according to another embodiment is

A semiconductor device portion in which one or more semiconductor elements are located; a packaging substrate electrically connected to the semiconductor element; and electrically connected to the packaging substrate to transmit an external electrical signal to the semiconductor element. , A motherboard that connects the semiconductor devices to each other;

The packaging substrate includes a core layer and an upper layer located on the core layer.

The core layer includes a glass substrate and a core via.

The glass substrate has a first surface and a second surface facing each other.

The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.

The core layer includes a core distribution layer located on the surface of the glass substrate or core via.

At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.

The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.

The thickness of the thin electric conductive layer of the core distribution layer may be the same as the thickness of the thin electric conductive layer of the upper layer, but may be thicker than that.

In one embodiment, the thickness of the thin electric conductive layer of the core distribution layer may be 0.7 to 12 times thicker than the thickness of the thin electric conductive layer of the upper layer. good.

In one embodiment, the upper insulating layer and the upper distribution pattern are included.

The upper insulating layer is located on the first surface and is located on the first surface.

The upper distribution pattern is incorporated in the upper insulating layer as an electrically conductive layer in which at least a part thereof is electrically connected to the core distribution layer.

The upper distribution pattern contains at least a part thereof and a fine pattern.

The width and spacing of the fine patterns may each be less than 4 μm.

In one embodiment, the second surface distribution pattern is an electrically conductive layer located on the second surface.

The width of the thick second surface distribution pattern may be 0.7 to 20 times the thickness of the thin electrical conductive layer of the upper layer.

In order to achieve the above object, the packaging substrate according to another embodiment is

Including a core layer and an upper layer located on the core layer.

The core layer includes a glass substrate and a core via.

The glass substrate has a first surface and a second surface facing each other.

The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.

The core layer includes a core distribution layer located on the surface of the glass substrate or core via.

At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.

The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.

The thickness of the thin electric conductive layer of the core distribution layer may be the same as the thickness of the thin electric conductive layer of the upper layer, but may be thicker than that.

The packaging substrate of the embodiment and the semiconductor device including it connect the semiconductor element and the motherboard closer to each other so that the electric signal is transmitted in the shortest possible distance, and the electric characteristics such as the signal transmission speed are obtained. Can be greatly improved.

Further, since the glass substrate applied as the core of the substrate itself is an insulator, there is almost no possibility that parasitic elements are generated as compared with the existing silicon core, and the insulating film treatment process can be further simplified. , Can also be applied to high-speed circuits.

At the same time, unlike the case where silicon is manufactured in the form of a round wafer, the glass substrate is manufactured in the form of a large panel, so that mass production becomes relatively easy and economic efficiency can be further improved.

It is a conceptual diagram explaining the cross section of the semiconductor device which concerns on one embodiment.

It is a conceptual diagram explaining the cross section of the packaging substrate which concerns on another embodiment.

(A) and (b) are conceptual diagrams illustrating a cross section of a core via applied in the embodiment, respectively.

It is a detailed conceptual diagram explaining a part of the cross section of the packaging substrate which concerns on embodiment. (The circle indicates the state observed on the upper surface or the bottom surface.) It is a detailed conceptual diagram explaining a part of the cross section of the packaging substrate which concerns on embodiment. (The circle indicates the state observed on the upper surface or the bottom surface.)

It is a flowchart explaining the manufacturing process of the packaging substrate which concerns on embodiment in the cross section. It is a flowchart explaining the manufacturing process of the packaging substrate which concerns on embodiment in the cross section. It is a flowchart explaining the manufacturing process of the packaging substrate which concerns on embodiment in the cross section.

Hereinafter, the examples will be described in detail with reference to the attached drawings so that a person having ordinary knowledge in the technical field to which the embodiment belongs can easily carry out the examples. However, the embodiment can be embodied in various different forms and is not limited to the examples described herein. The same drawing reference numerals are given to similar parts throughout the specification.

As used herein, the term "combinations thereof" as used in a Markush-style representation means one or more mixtures or combinations selected from the group consisting of each component described in the Markush-style representation. It is meant to include one or more selected from the group consisting of the above-mentioned components.

Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. Also, a singular expression includes multiple expressions unless they have a distinctly different meaning in context.

As used herein, the term "~ system" may mean a compound containing "a compound corresponding to ..." or "a derivative of ...".

In the present specification, the fact that B is located on A means that B is located on A in direct contact with A, or that B is located on A while another layer is located between them. It means that it is not construed as being limited to the position of B in contact with the surface of A.

In the present specification, the fact that B is concatenated on A means that A and B are directly concatenated, or A and B are concatenated via other components in between, which is special. Unless otherwise stated, it is not construed as being limited to the direct connection of A and B.

In the present specification, the expression of the singular is construed as meaning including the singular or the plural, which is interpreted in context, unless otherwise specified.

In the process of developing a semiconductor device that is more integrated and capable of exhibiting high performance with a thin thickness, the inventors recognized that not only the element itself but also the packaging part is an important factor in improving performance. In my research on this, unlike the case where two or more layers of cores were applied on the motherboard as a packaging substrate like the existing interposer and organic substrate, the glass core was applied in a single layer and penetrated. By applying a method of controlling the shape of the via and the width and thickness of the electrically conductive layer formed on the via, it was confirmed that the packaging substrate could be made thinner and the electrical characteristics of the semiconductor device could be improved. Completed the invention.

FIG. 1 is a conceptual diagram illustrating a cross section of a semiconductor device according to an embodiment of the embodiment, and FIG. 2 is a conceptual diagram illustrating a cross section of a packaging substrate according to another embodiment of the embodiment. 3 is a conceptual diagram for explaining a cross section of the core via applied in the embodiment, and FIGS. 4 and 5 are detailed conceptual diagrams for explaining a part of the cross section of the packaging substrate according to the embodiment, respectively. It shows the state observed on the bottom surface.). Hereinafter, the embodiment will be described in more detail with reference to FIGS. 1 to 5.

In order to achieve the above object, the semiconductor device 100 according to the embodiment is a semiconductor element portion 30 in which one or more semiconductor elements 32, 34, 36 are located; a packaging substrate 20 electrically connected to the semiconductor element; And a motherboard 10; which is electrically connected to the packaging substrate, transmits an external electrical signal to the semiconductor element, and connects the semiconductor elements to each other.

The packaging substrate 20 according to another embodiment includes a core layer 22; and an upper layer 26 ;.

The semiconductor element unit 30 means each element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by a connection electrode or the like. Specifically, the semiconductor element unit 30 includes, for example, an arithmetic element such as a CPU and a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element, 36), and the like. However, any semiconductor element mounted on a semiconductor device can be applied without limitation.

As the motherboard 10, a motherboard such as a printed circuit board or a printed wiring board can be applied.

The packaging substrate 20 includes a core layer 22; and an upper layer 26; which is located on one surface of the core layer.

The packaging substrate 20 may further include a lower layer 29 selectively located below the core layer.

The core layer 22 is located on the glass substrate 21; a large number of core vias 23 penetrating the glass substrate in the thickness direction; and on the surface of the glass substrate or the core via, at least a part thereof via the core via. It includes a core distribution layer 24; in which an electrically conductive layer that electrically connects one surface and the electrically conductive layer on the second surface is located.

The glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are generally parallel to each other and have a constant thickness throughout the glass substrate.

A core via 23 penetrating the first surface and the second surface is located on the glass substrate 21.

The packaging substrate of a semiconductor device has already been formed in a form in which a silicon substrate and an organic substrate are laminated. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a possibility that a parasitic element may occur when applied to a high-speed circuit, and there is a disadvantage that the power loss is relatively large. Further, in the case of an organic substrate, it is necessary to increase the area in order to form a more complicated distribution pattern, but this does not match the flow of manufacturing electronic devices to be ultra-miniaturized. In order to form a complicated distribution pattern within a specified size, it is practically necessary to miniaturize the pattern, but due to the characteristics of materials such as polymers applied to organic substrates, it is practically possible to miniaturize the pattern. There was a limit.

In the embodiment, the glass substrate 21 is applied as a support for the core layer 22 as a method for solving such a problem. Also, by applying the core via 23 formed through the glass substrate together with the glass substrate, the length of the electrical flow is shortened, the size is smaller, the reaction is faster, and the package has less loss characteristics. A glass substrate 20 is provided.

As the glass substrate 21, it is preferable to apply a glass substrate applied to a semiconductor, and for example, a borosilicate glass substrate, a non-alkali glass substrate, or the like can be applied, but the glass substrate 21 is not limited thereto.

The thickness of the glass substrate 21 may be 1,000 μm or less, 100 μm to 1,000 μm, or 100 μm to 700 μm. More specifically, the thickness of the glass substrate 21 may be 100 μm to 500 μm. Forming a thinner packaging substrate is advantageous in that the transmission of electrical signals can be made more efficient, but since it must also serve as a support, the glass substrate 21 having the above thickness is applied. It is preferable to do so. Here, the thickness of the glass substrate means the thickness of the glass substrate itself excluding the thickness of the electrically conductive layer located on the glass substrate.

The glass substrate 21 has a core via 23 together with the glass substrate 21. The core via 23 may be formed by a method of removing a predetermined region of the glass substrate 21, specifically, formed by etching plate-shaped glass by a physical and / or chemical method. You may.

Specifically, at the time of forming the core via 23, a method of forming a defect (groove) on the surface of the glass substrate by a method such as a laser and then chemically etching, a method of laser etching, or the like can be applied, but the present invention is limited to this. Not done.

The core via 23 is the first opening 233 in contact with the first surface; the second opening 234 in contact with the second surface; and the entire core via connecting the first opening and the second opening. Includes a minimum inner diameter portion 235; which is the narrowest inner diameter area.

The diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different or substantially the same.

The minimum inner diameter can be located at the first opening or the second opening, where the core vias may be cylindrical or (cut) triangular pyramidal core vias. In this case, the diameter (CV3) of the minimum inner diameter portion corresponds to the diameter of the smaller one of the first opening and the second opening.

The minimum inner diameter portion is located between the first opening portion and the second opening portion, and at this time, the core via may be a barrel type core via. In this case, the diameter of the minimum inner diameter portion (CV3) may be smaller than the diameter of the first opening and the diameter of the second opening, which are larger.

The core distribution layer 24 has a core distribution pattern 241 which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass substrate via a penetrating via, and a core insulation covering the core distribution pattern. Includes layer 223 and.

The core layer 22 has an electrically conductive layer formed therein through a core via, serves as an electrical passage across the glass substrate 21, and connects the upper part and the lower part of the glass substrate at a relatively short distance. It can have fast electrical signal transmission and low loss characteristics.

The core distribution pattern 241 is a pattern in which the first surface 213 and the second surface 214 of the glass substrate are electrically connected via the core via 23, and specifically, at least one of the first surface 213. The first surface distribution pattern 241a, which is an electrically conductive layer located on the portion, the second surface distribution pattern 241c, which is an electrically conductive layer located on at least a part of the second surface 214, and the first surface. The core via distribution pattern 241b, which is an electrically conductive layer that electrically connects the distribution pattern and the second surface distribution pattern to each other via the core via 23, is included. As each of the electrically conductive layers, for example, a copper-plated layer can be applied, but the present invention is not limited thereto.

The core via 23 is the first opening 233 in contact with the first surface; the second opening 234 in contact with the second surface; and the entire core via connecting the first opening and the second opening. Includes a minimum inner diameter portion 235; which is the narrowest inner diameter area.

Since the glass substrate 21 serves as an intermediate role and an intermediary role for connecting the semiconductor element portion 30 and the motherboard 10 to the upper part and the lower part, respectively, and the core via 23 serves as a passage for transmitting these electrical signals. Smooth signal transmission.

The thickness of the electrically conductive layer measured by the larger of the diameter of the first surface opening and the diameter of the second surface opening is the electric conductive layer formed on the portion of the core via having the minimum inner diameter. It may be as thick as or thicker than.

The core distribution layer 24 is an electrically conductive layer formed on a glass substrate, and can satisfy an adhesive force test (Cross Cut Attachment Test) value of 4B or more by ASTM D3359, specifically. 5B or more can be satisfied. Further, the electrically conductive layer, which is the core distribution layer 24, can have an adhesive force of 3 N / cm or more and a bonding force of 4.5 N / cm or more with respect to the glass substrate. When the degree of such a bonding force is satisfied, the bonding force between the substrate and the electrically conductive layer is sufficient to be applied as a packaging substrate.

The upper layer 26 is located on the first surface 213.

The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer, and the uppermost surface of the upper layer 26 is an opening to which the connection electrode of the semiconductor element portion can directly contact. Can be protected by the cover layer 60 on which it is formed.

The upper distribution layer 25 has a predetermined pattern with the upper insulation layer 253 located on the first surface, and the core distribution layer 24 and at least a part thereof are electrically connected to each other in electrical conductivity. As a layer, the upper distribution pattern 251 incorporated in the upper insulating layer is included.

As the upper insulating layer 253, any one that can be applied as an insulating layer to a semiconductor element or a packaging substrate can be applied, and for example, an epoxy resin containing a filler can be applied to this. Not limited.

The insulator layer may be formed by a method of forming a coating layer and curing, or is formed by a method of laminating an insulator film formed into a film in an uncured or semi-cured state on the core layer and curing the film. You may. At this time, if a pressure-sensitive lamination method or the like is applied, the insulator is embedded even in the space inside the core via, and efficient process progress is possible. Further, even when a plurality of insulator layers are laminated and applied, it may be difficult to substantially separate the insulator layers, and the plurality of insulator layers are collectively referred to as an upper insulating layer. Further, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253, and at this time, the boundaries thereof may not be substantially divided.

The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a preset form, and may be formed by, for example, a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary parts of the insulator layer, an electrically conductive layer is formed by a method such as copper plating, and the electrically conductive layer is selectively unnecessary. By repeating the method of forming the electric conductive layer on the electric conductive layer again after removing the unnecessary parts, removing the unnecessary parts again, and then forming the electric conductive layer by a method such as plating. It is possible to form the upper distribution pattern 251 in which the electrically conductive layer is formed vertically or horizontally in the intended pattern.

Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, the transmission of electrical signals to the semiconductor element portion 30 is smoothly promoted, and the intended complicated pattern is sufficiently accommodated. To obtain it, it is formed so as to contain a fine pattern at least in a part thereof. At this time, the width and spacing of the fine patterns may be less than about 4 μm, may be about 3.5 μm or less, may be about 3 μm or less, or may be about 2.5 μm or less, respectively. It may be about 1 μm to about 2.3 μm. The interval may be an interval between fine patterns adjacent to each other (hereinafter, the description for the fine patterns is the same).

In order to form the upper distribution pattern 251 so as to include a fine pattern, at least two or more methods are applied in the embodiment.

One method is to apply the glass substrate 21 as the glass substrate of the packaging substrate. The glass substrate 21 has a surface roughness (Ra) of 10 angstroms or less and can have a fairly flat surface characteristic, and as a result, the influence of the surface morphology of the support substrate on the formation of fine patterns is minimized. Can be transformed into.

Another method is based on the properties of the insulator. In the case of the insulator, a filler component is often applied together with the resin, but as the filler, inorganic particles such as silica particles can be applied. When the inorganic particles are applied to an insulator as a filler, the size of the inorganic particles can affect the presence or absence of the formation of fine patterns, but the insulator applied in the embodiment has an average diameter of about 150 nm or less. Includes a particle-type filler of, specifically, a particle-type filler having an average diameter of about 1 nm to about 100 nm. These features minimize the effect of the insulator itself on the formation of an electrically conductive layer with a width of several micrometers while maintaining the physical properties required for the insulator above a certain level, and by fine surface morphology. , Promotes the formation of fine patterns with excellent adhesion on its surface.

In the upper surface connecting layer 27, the upper surface connecting pattern 251 and at least a part thereof are electrically connected to each other, the upper surface connecting pattern 272 located in the upper insulating layer 253, the semiconductor element portion 30, and the upper surface connecting pattern 272. Includes a top connection electrode 271 that electrically connects the two. The upper surface connecting pattern 272 may be located on one surface of the upper insulating layer 253, or at least a part thereof may be embedded while being exposed on the upper insulating layer. For example, when the upper surface connecting pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating, and the upper surface connecting pattern is partially on the upper insulating layer. When it is embedded while being exposed to the surface, a copper plating layer or the like may be formed, and then a part of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

The upper surface connection pattern 272 can include a fine pattern at least as a part thereof, like the upper distribution pattern 251 described above. As described above, the upper surface connection pattern 272 including the fine pattern enables a larger number of elements to be electrically connected even in a narrow area, and makes the connection of electrical signals between the elements or with the outside smoother and more integrated. Packaged is possible.

The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 by a terminal or the like, or may be connected to the semiconductor element portion 30 via an element connecting portion 51 such as a solder ball.

The packaging board 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the second surface distribution pattern 241c, which is a core distribution layer located on at least a part of the second surface 214 of the core layer 22, via a terminal of the motherboard. The two-sided distribution pattern 241c may be electrically connected via a board connecting portion such as a solder ball. Further, the second surface distribution pattern 241c may be connected to the motherboard 10 via a lower layer 29 located below the core layer 22.

The lower layer 29 includes a lower distribution layer 291 and a lower surface connecting layer 292.

The lower distribution layer 291 is i) a lower insulating layer 291b in which the second surface 214 and at least a part thereof are in contact with each other; and ii) is embedded (embedded) in the lower insulating layer and has a predetermined pattern. Includes a lower distribution pattern 291a; in which the core distribution layer and at least a portion thereof are electrically connected.

The bottom surface connection layer 292 includes i) a bottom surface connection electrode 292a that is electrically connected to the bottom surface connection pattern, and ii) one surface of the bottom insulation layer that is electrically connected to the lower distribution pattern and at least a part thereof. Further can include a bottom connection pattern 292b on which at least a portion thereof is exposed.

The lower surface connection pattern 292b is a portion connected to the motherboard 10, and is formed by a non-fine pattern having a wider width than the fine pattern, unlike the upper surface connection pattern 272, for more efficient electric signal transmission. Can be done.

One of the features of the invention is that substantially no additional substrate other than the glass substrate 21 is applied to the packaging substrate 20 located between the semiconductor element portion 30 and the motherboard 10. ..

In the existing, the interposer and the organic substrate were laminated together and applied while connecting the element and the motherboard. It is understood that such a multi-stage form is applied for at least two reasons, one of which is that there is a scale problem in directly joining the fine pattern of the element to the motherboard. Another reason is that the problem of wiring damage due to the difference in the coefficient of thermal expansion may occur in the joining process or in the driving process of the semiconductor device. In the embodiment, a glass substrate having a coefficient of thermal expansion similar to that of a semiconductor device is applied, and a fine pattern having a fine scale sufficient for mounting the device is formed on the first surface of the glass substrate and the upper layer thereof. Solved such a problem.

In the embodiment, the thickness of the thin electric conductive layer of the core distribution layer 24 may be the same as or thicker than the width of the thin electric conductive layer of the upper layer 26. When the thickness of the thin electric conductive layer of the core distribution layer 24 is equal to or thicker than the width of the thin electric conductive layer of the upper layer 26, the element and the motherboard are electrically connected to each other. The signal can be transmitted more efficiently.

In the embodiment, the thickness of the thin electric conductive layer of the core distribution layer 24 may be the same as or thicker than the thickness (Tus) of the thin electric conductive layer of the upper layer 26. When the thickness of the thin electric conductive layer of the core distribution layer 24 is equal to or thicker than the thickness of the thin electric conductive layer of the upper layer 26, the element and the motherboard are electrically connected to each other. The signal can be transmitted more efficiently.

The thickness of the electrically conductive layer at the minimum inner diameter of the core via 23 may be the same as or thicker than the width of the thinner one of the electrically conductive layers of the upper layer 26. Thus, if the thickness of the electrical conductive layer at the minimum inner diameter of the core via is equal to or thicker than the width of the thinner electrical conductive layer of the upper layer, the electrical signal is transmitted between the element and the motherboard. It can be transmitted efficiently.

The thickness of the electrically conductive layer at the minimum inner diameter of the core via 23 may be the same as or thicker than the thickness of the thinner one of the electrically conductive layers of the upper layer 26. Thus, when the thickness of the electrically conductive layer at the minimum inner diameter of the core via is equal to or thicker than the thickness of the thinner one of the upper layers, the electrical signal is transmitted between the element and the motherboard. It can be transmitted efficiently.

In the embodiment, the average thickness of the core distribution pattern 241 may be about 1 to about 20 times thicker, about 1 to about 15 times, based on the width (Wus) of the thinner one of the upper surface connection patterns 272. It may be thick. Further, the average thickness of the core distribution pattern 241 may be about 1 to about 10 times thicker, or about 1 to about 8 times thicker, based on the width (Wus) of the thinner one of the upper surface connection patterns 272. May be good. When the core distribution pattern 241 having such a ratio is applied to the packaging substrate, the process of connecting an electric signal from a highly integrated element to the motherboard can be made more efficient.

In the embodiment, the average thickness of the core distribution pattern 241 is about 0.7 to about 12 times thicker (Tcv) with respect to the thickness (Tus) of the thinner one of the upper surface connection patterns 272. It may be about 1.0 to about 10 times thicker (Tcv). Further, the core distribution pattern 241 may have a thickness (Tcv) of about 1.1 times to about 8 times thicker (Tcv) based on the thickness (Tus) of the thinner one of the upper surface connection patterns 272, and is about 1 It may have a thickness of 1 to about 6 times thicker (Tcv) and may have a thickness of about 1.1 to about 3 times thicker (Tcv). Having a core distribution pattern 241 showing such a thickness ratio can make the process of connecting electrical signals from highly integrated elements to the motherboard more efficient.

In the embodiment, the average thickness of the core via distribution pattern 241b, which is the core distribution pattern located on the inner diameter surface of the core via, is about 1 to about 1 time to about 1 time based on the width (Wus) of the thin one of the upper surface connection patterns 272. It may be 12 times thicker, and may be about 1 to 10 times thicker. Further, the average thickness of the core via distribution pattern 241b may be about 1 to about 8 times thicker, or about 1 to about 6 times thicker, based on the width (Wus) of the thinner one of the upper surface connection patterns 272. You may. When the core via distribution pattern 241b having such an average thickness ratio is applied to the packaging substrate, the process of connecting an electric signal from a highly integrated element to the motherboard can be made more efficient. ..

As disclosed in the drawings, the core distribution pattern 241 has a form in which an electrically conductive layer is formed in the inner diameter of a core via with a certain thickness, and the remaining portion thereof is filled with an insulator layer. The space of the core via may be filled with an electrically conductive layer without extra space, if necessary. When the space of the core via is filled with the electrically conductive layer in this way, the width of the core via pattern is the distance from one side of the core via pattern near the inner diameter surface to the center of the electrically conductive layer (hereinafter, the same). Is).

In the embodiment, the thickness (Tcv) of the thin core distribution pattern 241 may be about 0.8 to 10 times thicker than the width (Wus) of the thin core distribution pattern 272. It may be about 0.8 times to about 7 times thicker. The thickness (Tcv) of the thin core distribution pattern 241 is about 0.9 to 6 times thicker (Tcv) with respect to the width (Wus) of the thinner core distribution pattern 272. It may be about 1 to 4 times thicker (Tcv). When the core distribution pattern 241 having such a thickness ratio is applied, the process of connecting the electrical signal from the highly integrated element to the motherboard can be made more efficient.

In the embodiment, the thicker one of the second surface distribution patterns 241c is about 0.7 to about 20 times thicker wiring thickness (Tsc) based on the thickness (Tus) of the thinner one of the upper surface connection patterns 272. It may have a wiring thickness (Tsc) that is about 0.7 times to about 15 times thicker. Further, the second surface distribution pattern 241c may have a wiring thickness (Tsc) that is about 1 to 12 times thicker than the thickness (Tus) of the thinner one of the upper surface connection patterns 272. It may have a wiring thickness (Tsc) 1.1 times to about 5 times thicker. When the second surface distribution pattern 241c has such a wiring thickness, the process of connecting an electric signal from a highly integrated element to the motherboard can be made more efficient.

In the embodiment, the width (Wsc) of the thick one of the second surface distribution pattern 241c may be about 1 to about 20 times thicker with respect to the width (Wus) of the thin one of the upper surface connection pattern 272. It may be 1 to 15 times thicker. Further, the width (Wsc) of the thick one of the second surface distribution pattern 241c may be about 2 to about 10 times thicker than the width (Wus) of the thin one of the upper surface connection pattern 272, or about 2 times. It may be about 8 times thicker. When the second surface distribution pattern 241c having such a ratio is applied, the process of connecting the electric signal from the highly integrated element to the motherboard can be made more efficient.

In the embodiment, the width (Wds) of the thick one of the lower surface connection pattern 292b may be about 1 to about 20 times thicker than the width (Wus) of the thin one of the upper surface connection pattern 272, and is about 1 It may be twice to about 15 times thicker. Further, the width (Wds) of the thick one of the lower surface connection pattern 292b may be about 2 to about 10 times thicker than the width (Wus) of the thin one of the upper surface connection pattern 272, and is about 2 times to more. It may be about 8 times thicker. When the bottom surface connection pattern 292b having such a width ratio is applied, the process of connecting an electrical signal from a highly integrated element to the motherboard can be made more efficient.

In the embodiment, the width of the thick one of the bottom surface connection electrodes 292a (not shown) may be about 0.7 to about 30 times thicker than the width of the thin one of the top surface connection patterns 272 (Wus). It may be about 0.8 times to about 20 times thicker. The width of the thick one of the bottom surface connection electrodes 292a (not shown) may be about 1 to about 15 times thicker than the width of the thin one of the top surface connection patterns 272 (Wus), and may be about 1 to 1 times. It may be about 10 times thicker. In the embodiment, the lower surface connection pattern 292b has a thickness (Tds) of about 0.7 to about 30 times based on the thickness (Tus) of the thinner one of the upper surface connection patterns 272 at least in part. It may have a thickness (Tds) that is about 1 to about 25 times wider, or may have a thickness (Tds) that is about 1.5 to about 20 times wider. When the bottom connection electrode 292a having such a width ratio is applied, the process of connecting the electrical signal from the highly integrated element to the motherboard can be made more efficient.

Since the semiconductor device 100 has a packaging substrate 20 having a considerably thin thickness, the overall thickness of the semiconductor device can be reduced, and by applying a fine pattern, a smaller area is intended. An electrical connection pattern can be placed. Specifically, the thickness of the packaging substrate may be about 2000 μm or less, about 1500 μm or less, or about 900 μm. Further, the thickness of the packaging substrate may be about 120 μm or more, or may be about 150 μm or more. Due to the features described above, the packaging substrate connects the element and the motherboard so as to be electrically and structurally stable even with a relatively thin thickness, and contributes to the miniaturization and thinning of the semiconductor device. Can be done.

The resistance value of the product cut into a size of about 100 μm × 100 μm with respect to the upper surface of the packaging substrate 20 may be about 2.6 × 10 ^-6 Ω or more, and may be about 3.6 × 10 ^-6 . It may be Ω or more, and may be about 20.6 × 10 ^-6 Ω or more. The resistance value of the packaging substrate may be about 27.5 × 10 ^-6 Ω or less, about 25.8 × 10 ^-6 Ω or less, and about 24.1 × 10 ^-6 Ω. It may be as follows. Illustratively, the resistance value is a measurement of the resistance between the electrically conductive layer of the upper layer and the electrically conductive layer of the lower layer after being cut to a certain size described above, and is a core. It is a resistance value measured by connecting the electric conductive layer of the upper layer and the electric conductive layer of the lower layer to each other by the via pattern. The resistance value can be measured by the method described in the following experimental example. The packaging substrate satisfying the resistance value can easily transmit an electric signal to the outside.

6 to 8 are flowcharts illustrating the manufacturing process of the packaging substrate according to the embodiment in a cross section. Hereinafter, a method for manufacturing a packaging substrate according to still another embodiment will be described with reference to FIGS. 6 to 8.

The method of manufacturing the packaging substrate of the embodiment is a preparatory step of forming defects at predetermined positions on the first and second surfaces of the glass substrate; an etching solution is added to the glass substrate on which the defects are formed. An etching step for providing a glass substrate on which a core via is formed; a core layer manufacturing step for forming a core distribution layer which is an electrically conductive layer by plating the surface of the glass substrate on which the core via is formed; And an upper layer manufacturing step of forming an upper distribution layer, which is an electrically conductive layer covered with an insulating layer, on one surface of the core layer; the packaging substrate described above is manufactured.

The core layer manufacturing step is a pretreatment process in which a presence / inorganic composite primer layer containing nanoparticles having an amine group is formed on the surface of the glass substrate on which the core via is formed, and the pretreated glass substrate is provided; The plating process of plating a metal layer on the pretreated glass substrate; can be included.

The core layer manufacturing step is a pretreatment step of forming a metal-containing primer layer on the surface of the glass substrate on which the core vias are formed by sputtering to provide a pretreated glass substrate; and a metal on the pretreated glass substrate. The plating process of plating the layer; can be included.

An insulating layer forming step may be further included between the core layer manufacturing step and the upper layer manufacturing step.

The insulating layer forming step may be a step of forming the core insulating layer by locating the insulating film on the core layer and then performing pressure-sensitive laminating.

Hereinafter, the method for manufacturing the packaging substrate will be described in more detail.

1) Preparation step (glass defect forming process): A glass substrate 21a having a flat first surface and a second surface is prepared, and defects (grooves, 21b) are formed on the glass surface at predetermined positions for forming core vias. To form. As the glass substrate, a glass substrate applied to a substrate of an electronic device or the like may be applied, and for example, a non-alkali glass substrate or the like may be applied, but the glass substrate is not limited thereto. As commercially available products, products manufactured by manufacturers such as Corning, Schott, and AGC can be applied. At the time of forming the defect (groove), a method such as mechanical etching or laser irradiation can be applied.

2) Etching step (core via forming step): The glass substrate 21a on which the defect (groove, 21b) is formed forms the core via 23 through a physical or chemical etching process. In the etching process, the surface of the glass substrate 21a can be etched at the same time as forming vias in the defective portion of the glass substrate. A masking film or the like can be applied to prevent such etching of the glass surface, but the defective glass substrate itself may be used in consideration of the complexity of the process of applying and removing the masking film. It can be etched, in which case the thickness of the glass substrate with the core vias may be slightly thinner than the thickness of the initial glass substrate.

3-1) Core layer manufacturing step: An electrically conductive layer 21d is formed on a glass substrate. As the electrically conductive layer, a metal layer containing a copper metal can be typically applied, but the electric conductive layer is not limited to this.

The surface of glass (including the surface of the glass substrate and the surface of the core via) and the surface of the copper metal have different properties, so that the adhesive strength is inferior. In the embodiment, the adhesive force between the glass surface and the metal was improved by two methods, a dry method and a wet method.

The dry method is a method of applying sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. At the time of forming the seed layer, dissimilar metals such as titanium, chromium and nickel may be sputtered together with copper and the like. Is expected to improve.

The wet method is a method of performing primer treatment, and is a method of forming a primer layer 21c by pretreatment with a compound having a functional group such as an amine. Depending on the degree of adhesion intended, it can be pretreated with a silane coupling agent and then primed with a compound or particles having an amine functional group. As mentioned above, the supporting substrate of the embodiment needs to have high performance enough to form a fine pattern, which must be maintained even after the primer treatment. Therefore, when such a primer contains nanoparticles, nanoparticles having an average diameter of 150 nm or less are preferably applied, and for example, nanoparticles are applied as particles having an amine group. Is preferable. The primer layer can be formed by applying a bonding force improving agent exemplified by MEC's CZ series or the like.

In the seed layer / primer layer 21c, the electrically conductive layer can selectively form a metal layer in a state where a portion unnecessary for forming the electrically conductive layer is removed or not removed. Further, in the seed layer / primer layer 21c, the portion requiring or not requiring the formation of the electrically conductive layer is selectively treated in a state of being activated or inactivated by metal plating, and thereafter. The process can be advanced. For example, as the activation or deactivation treatment, a light irradiation treatment such as a laser having a certain wavelength, a chemical treatment, or the like can be applied. At the time of forming the metal layer, a copper plating method or the like applied to the manufacture of a semiconductor device may be applied, but the present invention is not limited thereto.

During the metal plating, many variables such as the concentration of the plating solution, the plating time, and the type of the additive to be applied can be adjusted to adjust the thickness of the electrically conductive layer formed.

If a part of the core distribution layer is unnecessary, it may be removed, and by proceeding with metal plating after the seed layer is partially removed or inactivated, electricity is obtained in a predetermined pattern. The conductive layer may be formed, and the etching layer 21e of the core distribution layer may be formed.

3-2) Insulation layer forming step: The core via can go through an insulating layer forming step of filling an empty space with an insulating layer after forming the core distribution layer which is the electric conductive layer. At this time, as the insulating layer, one manufactured in the form of a film may be applied, and for example, an insulating layer in the form of a film by a pressure-sensitive lamination method or the like may be applied. By advancing the pressure-sensitive laminating in this way, the insulating layer is sufficiently embedded even in the empty space inside the core via, and the core insulating layer without the formation of voids can be formed.

4) Upper layer manufacturing step: A step of forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or by laminating an insulating film, and is preferably formed by a method of laminating an insulating film. Lamination of the insulating film can proceed in the process of laminating and curing the insulating film. At this time, if the pressure-sensitive lamination method is applied, the insulating film is also insulated from the layer in which the electrically conductive layer is not formed inside the core via. The resin can be fully embedded. Also in the case of the upper insulating layer, one having sufficient adhesive force as a result of direct contact with the glass substrate at least a part thereof is applied. Specifically, it is preferable that the glass substrate and the upper insulating layer have a characteristic that the adhesion test value by ASTM D3359 is 4B or more.

The upper distribution pattern is a process of forming the insulating layer 23a, forming the electrically conductive layer 23c with a predetermined pattern, etching unnecessary portions, and then forming the etching layer 23d of the electrically conductive layer. It may be formed by repeating the process, and in the case of an electrically conductive layer formed so as to be adjacent to each other across the insulating layer, it may be formed by a method in which the blind via 23b is formed on the insulating layer and then the plating process is advanced. good. At the time of forming the blind via, a dry etching method such as laser etching or plasma etching, a wet etching method using a masking layer and an etching solution, or the like can be applied.

5) Top connection layer and cover layer formation step: The top connection pattern and top connection electrodes can also be formed in a process similar to the formation of the top distribution layer. Specifically, in the upper surface connection pattern and the upper surface connection electrode, the etching layer 23f of the insulating layer is formed on the insulating layer 23e, the electric conductive layer 23g is formed again on the etching layer 23f, and then the etching layer 23h of the electric conductive layer is formed. It may be formed by a method of forming or the like, but it may be formed by a method of selectively forming only the electrically conductive layer without applying the etching method. The cover layer can be formed so that the upper surface connecting electrode is exposed by forming an opening (not shown) at a position corresponding to the upper surface connecting electrode and can be directly connected to the element connecting portion or the terminal of the element.

6) Bottom connection layer and cover layer forming step: The lower distribution layer and / or the bottom connection layer is formed by a method similar to the upper surface connection layer and cover layer forming step described above, and the cover layer (not shown) is selectively formed. ) Can be formed.

Hereinafter, the present invention will be described in more detail through specific examples. The following examples are merely examples for facilitating the understanding of the present invention, and the scope of the present invention is not limited thereto.

<Manufacturing example 1-Manufacturing of packaging substrate>

1) Preparation step (glass defect forming process): A glass substrate 21a having a flat first surface and a second surface is prepared, and defects (grooves, 21b) are formed on the glass surface at predetermined positions for forming core vias. Was formed. As the glass, borosilicate glass (Corning Inc.) was applied. At the time of forming the defect (groove), a mechanical etching and laser irradiation method was applied.

2) Etching step (core via forming step): The glass substrate 21a on which the defect (groove, 21b) was formed formed the core via 23 through a physical or chemical etching process.

3-1) Core layer manufacturing step: An electrically conductive layer 21d was formed on a glass substrate. As the electrically conductive layer, a metal layer containing a copper metal was applied. The adhesive force between the surface of the glass substrate and the metal layer was improved by two methods, a dry method and a wet method. The dry method is a method of applying sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. During the formation of the seed layer, one or more dissimilar metals of titanium, chromium, and nickel were sputtered together with copper and the like. The wet method is a method of performing primer treatment, and is a method of forming a primer layer 21c by pretreatment with a compound having a functional group such as an amine. After pretreatment with a silane coupling agent, a primer treatment was performed with a compound or particles having an amine functional group. As such a primer, nanoparticles having an average diameter of 150 nm or less were applied, and as particles having an amine group, nanoparticles were applied. The primer layer was formed by applying a bonding force improving agent manufactured by MEC's CZ series.

In the seed layer / primer layer 21c, the portion requiring or not requiring the formation of the electrically conductive layer was selectively treated in a state of being activated or inactivated by metal plating. As the activation or deactivation treatment, a light irradiation treatment such as a laser having a certain wavelength, a chemical treatment, or the like was applied. At the time of forming the metal layer, the copper plating method applied to the manufacture of semiconductor devices was applied.

By proceeding with metal plating after the seed layer was partially removed or inactivated, an electrically conductive layer was formed in a predetermined pattern, and an etching layer 21e of the core distribution layer was formed.

3-2) Insulation layer formation step: After the formation of the core distribution layer, which is the electrical conduction layer, the insulation layer formation step of filling the empty space with the insulation layer was advanced. At this time, as the insulating layer, one manufactured in the form of a film was applied, and the insulating layer in the form of a film by a pressure-sensitive lamination method or the like was applied.

4) Upper layer manufacturing step: The step of forming the upper insulating layer and the upper distribution layer including the upper distribution pattern on the core layer was advanced. The upper insulating layer was formed by laminating an insulating film, and was formed in the process of laminating and curing the insulating film. Also in the case of the upper insulating layer, one having sufficient adhesive force was applied as a result of direct contact with the glass substrate at least a part thereof. Specifically, as the glass substrate and the upper insulating layer, those having a characteristic that the adhesion test value by ASTM D3359 is 4B or more was applied.

The upper distribution pattern is a process of forming the insulating layer 23a, forming the electrically conductive layer 23c with a predetermined pattern, etching an unnecessary portion, and then forming the etching layer 23d of the electrically conductive layer. Formed by repeating. In the case of the electrically conductive layer formed so as to be adjacent to each other with the insulating layer interposed therebetween, the blind via 23b was formed on the insulating layer and then the plating process was advanced. At the time of forming the blind via, a dry etching method such as laser etching or plasma etching, a wet etching method using a masking layer and an etching solution, or the like was applied.

5) Top connection layer and cover layer forming step: A method in which the etching layer 23f of the insulating layer is formed on the insulating layer 23e, the electrically conductive layer 23g is formed again, and then the etching layer 23h of the electrically conductive layer is formed. I proceeded with. The cover layer is formed so that the upper surface connecting electrode is exposed by forming an opening (not shown) at a position corresponding to the upper surface connecting electrode and can be directly connected to the element connecting portion or the terminal of the element.

At this time, the thickness (Tcv) of the thin electrical conductive layer in the core via formed in the 3-1) step, and the upper distribution pattern and the upper surface connecting layer formed in the 4) and 5) steps. The ratio of the pattern of the electrically conductive layer to the width (Wus) of the thin one is 1: 1 so that the thickness (Tcv) is combined with the upper distribution pattern and the upper surface formed in the steps 4) and 5). The ratio of the pattern of the electrically conductive layer of the connecting layer to the thickness (Tus) of the thin one was set to 1: 0.7.

6) Bottom connection layer and cover layer forming step; The lower distribution layer and / or the bottom connection layer is formed by a method similar to the upper surface connection layer and cover layer forming step described above, and the cover layer (not shown) is selectively formed. ) Was formed to manufacture a packaging substrate.

The packaging substrate 20 manufactured by the above method is

A glass substrate 21 having first and second surfaces facing each other, a large number of core vias 23 penetrating the glass substrate in the thickness direction, and at least a part thereof located on the surface of the glass substrate or the core via. A core layer including a core distribution layer 24 in which an electrically conductive layer that electrically connects the first surface and the electrically conductive layer on the second surface is located via a core via; and

The upper layer 26, which is located on the first surface and includes an electrically conductive layer that electrically connects the core distribution layer and the external semiconductor element portion, is included.

The upper layer includes an upper distribution layer 25 and an upper surface connecting layer 27 located on the upper distribution layer.

The upper distribution layer has an upper insulation layer 253 located on the first surface; and a predetermined pattern, and is an electrically conductive layer in which at least a part thereof is electrically connected to the core distribution layer 24. Includes the upper distribution pattern 251; built into the upper insulating layer.

The core via has an inner diameter thereof in the first opening 233 in contact with the first surface; the second opening 234 in contact with the second surface; and the entire core via connecting the first opening and the second opening. Includes the smallest inner diameter 235; which is the narrowest area

The ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the width (Wus) of the thin electric conductive layer of the upper layer is 1: 1.

The ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the thickness (Tus) of the thin electric conductive layer of the upper layer is 0.7: 1.

<Manufacturing example 2-Manufacturing of packaging substrate>

In the packaging substrate of Production Example 1, the ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the width (Wus) of the thin electric conductive layer of the upper layer is 12 :. Make it 1

Except that the ratio of the thickness (Tcv) of the thin electrical conductive layer of the core distribution layer to the thickness (Tus) of the thin electrical conductive layer of the upper layer is 12: 1. The semiconductor device was manufactured in the same manner as in Production Example 1.

<Manufacturing example 3-Manufacturing of packaging substrate>

In the packaging substrate of Production Example 1, the ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the thickness (Tus) of the thin electric conductive layer of the upper layer is 0. The semiconductor device was manufactured in the same manner as in Production Example 1 except that the ratio was set to 5.5: 1.

<Manufacturing example 4-Manufacturing of packaging substrate>

In the packaging substrate of Production Example 1, the ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the width (Wus) of the thin electric conductive layer of the upper layer is 12 :. Make it 1

Except that the ratio of the thickness (Tcv) of the thin electrical conductive layer of the core distribution layer to the thickness (Tus) of the thin electrical conductive layer of the upper layer is 13: 1. The semiconductor device was manufactured in the same manner as in Production Example 1.

<Experimental example-Measurement of electrical characteristics>

The packaging substrate of Production Examples 1 to 4 is cut into a size of 100 μm × 100 μm with reference to the upper surface of the packaging substrate, and the resistance value among the electrical characteristics thereof is measured through a resistivity measuring machine to obtain the thickness (Tcv). , Tus) and width (Wus) conditions are the same, and the results are shown in Table 1.

Tcv: Thickness of the thin electrical conductive layer of the core distribution layer, Wus: Width of the thin electrical conductive layer of the upper layer

Tus: Thickness of the thin electrical conductive layer in the upper layer

Referring to Table 1 above, in the packaging substrate, the ratio of the thickness (Tcv) of the thin electric conductive layer of the core distribution layer to the width (Wus) of the thin electric conductive layer of the upper layer is A production example in which the ratio of the thickness (Tcv) to the thickness (Tus) of the thin one of the electrically conductive layers in the upper layer is 0.7: 1 to 12: 1 in the ratio of 1: 1 to 12: 1. 1 and Production Example 2 showed good resistance values of 3.6 × 10 ^-6 Ω to 20.6 × 10 ^-6 Ω. It is determined that the packaging substrate having such characteristics can sufficiently and smoothly transmit an electric signal to the elements arranged on the upper side or the lower side thereof.

The packaging substrate of the embodiment has excellent properties such as being able to serve as a substrate support that is thin and has sufficient strength without forming the parasitic element of the glass substrate, and has an appropriate width and width in the glass substrate. It forms an electrically conductive layer with a thickness and utilizes excellent properties such as inducing efficient signal transmission.

If the diameter of the core via formed on the glass substrate is excessively small, it may be difficult to sufficiently form an electrically conductive layer inside the core via, and the electrical signals on the upper and lower parts of the packaging substrate are sufficiently smooth. May not be transmitted to.

If the diameter of the core via is excessively large, it is not necessary to fill the entire interior with an electrically conductive layer, or voids may be easily formed. Further, when the core vias having an excessively large diameter are formed at a high density, it may be difficult to maintain the mechanical properties of the glass substrate itself above a certain level.

Considering each of these characteristics, in order to efficiently transmit electrical signals, the thickness (Tcv) of the thin electrical conductive layer of the core distribution layer and the electrical conductive layer of the upper layer The ratio of the thin one to the width (Wus) is 1: 1 to 12: 1, and the ratio of the thickness (Tcv) to the thickness of the thin one (Tus) of the upper electric conductive layer is 0. It is considered preferable that the ratio is 7: 1 to 12: 1.

In the above, although the preferred embodiment of the embodiment has been described in detail, the scope of rights of the embodiment is not limited to this, but the basic concept of the embodiment defined in the following claims. Many modifications and improvements of those skilled in the art using the above also belong to the scope of the embodiment.

100: Semiconductor device 10: Semiconductor device 30: Semiconductor element 32: First semiconductor element 34: Second semiconductor element 36: Third semiconductor element 20: Packaging substrate 22: Core layer 223: Core insulating layer 21, 21a: Glass substrate 213: First surface 214: Second surface 23: Core via 233: First opening 234: Second opening 235: Minimum inner diameter 24: Core distribution layer 241: Core distribution pattern 241a: First surface distribution pattern 241b: Core via Distribution pattern 241c: Second surface distribution pattern 26: Upper layer 25: Upper distribution layer 251: Upper distribution pattern 252: Blind via 253: Upper insulating layer 27: Top connection layer 271: Top connection electrode 272: Top connection pattern 29: Lower Layer 291: Lower distribution layer 291a: Lower distribution pattern 291b: Lower insulating layer 292: Bottom connection layer 292a: Bottom connection electrode 292b: Bottom connection pattern 50: Connection 51: Element connection 52: Board connection 60: Cover layer 21b : Glass defect 21c: Seed layer, Primer layer 21d: Core distribution layer 21e: Core distribution layer etching layer 23a: Insulation layer 23b: Insulation layer etching layer 23c: Electrically conductive layer 23d: Electrically conductive layer etching layer 23e : Insulation layer 23f: Insulation layer etching layer 23g: Electrically conductive layer 23h: Electrically conductive layer etching layer

Claims (10)

A semiconductor device portion in which one or more semiconductor elements are located; a packaging substrate electrically connected to the semiconductor element; and electrically connected to the packaging substrate to transmit an external electrical signal to the semiconductor element. , A motherboard that connects the semiconductor devices to each other;
The packaging substrate includes a core layer and an upper layer located on the core layer.
The core layer includes a glass substrate and a core via.
The glass substrate has a first surface and a second surface facing each other.
The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.
The core layer includes a core distribution layer located on the surface of the glass substrate or core via.
At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.
The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.
A semiconductor device in which the thickness of the thin electric conductive layer of the core distribution layer is the same as the width of the thin electric conductive layer of the upper layer, but is thicker than that. The semiconductor according to claim 1, wherein the thickness of the thin electric conductive layer of the core distribution layer is about 1 to 12 times thicker than the width of the thin electric conductive layer of the upper layer. Device. Includes top insulation layer and top distribution pattern
The upper insulating layer is an insulating layer located on the first surface.
The upper distribution pattern is an electrically conductive layer in which at least a part thereof is electrically connected to the core distribution layer.
The upper distribution pattern is built in the upper insulating layer.
The upper distribution pattern contains at least a part thereof and a fine pattern.
The semiconductor device according to claim 1, wherein the fine pattern includes a device having a width of less than about 4 μm and a distance between adjacent fine patterns of less than about 4 μm. The second surface distribution pattern is an electrically conductive layer located on the second surface.
The semiconductor device according to claim 1, wherein the width of the thick second surface distribution pattern is about 1 to about 20 times the width of the thin electric conductive layer of the upper layer. Including a core layer and an upper layer located on the core layer.
The core layer includes a glass substrate and a core via.
The glass substrate has a first surface and a second surface facing each other.
The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.
The core layer includes a core distribution layer located on the surface of the glass substrate or core via.
At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.
The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.
A packaging substrate in which the thickness of the thin electrical conductive layer of the core distribution layer is equal to or thicker than the width of the thin electrical conductive layer of the upper layer. A semiconductor device portion in which one or more semiconductor elements are located; a packaging substrate electrically connected to the semiconductor element; and electrically connected to the packaging substrate to transmit an external electrical signal to the semiconductor element. , A motherboard that connects the semiconductor devices to each other;
The packaging substrate includes a core layer and an upper layer located on the core layer.
The core layer includes a glass substrate and a core via.
The glass substrate has a first surface and a second surface facing each other.
The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.
The core layer includes a core distribution layer located on the surface of the glass substrate or core via.
At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.
The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.
A semiconductor device in which the thickness of the thin electric conductive layer of the core distribution layer is the same as or thicker than the thickness of the thin electric conductive layer of the upper layer. The thickness of the thin electric conductive layer of the core distribution layer is about 0.7 to 12 times thicker than the thickness of the thin electric conductive layer of the upper layer, according to claim 6. The semiconductor device described. Includes top insulation layer and top distribution pattern
The upper insulating layer is an insulating layer located on the first surface.
The upper distribution pattern is an electrically conductive layer in which at least a part thereof is electrically connected to the core distribution layer.
The upper distribution pattern is built in the upper insulating layer.
The upper distribution pattern contains at least a part thereof and a fine pattern.
The semiconductor device according to claim 6, wherein the fine pattern includes a device having a width of less than about 4 μm and a distance between adjacent fine patterns of less than about 4 μm. The second surface distribution pattern is an electrically conductive layer located on the second surface.
The semiconductor device according to claim 6, wherein the width of the thick second surface distribution pattern is about 0.7 to about 20 times the thickness of the thin electric conductive layer of the upper layer. Including a core layer and an upper layer located on the core layer.
The core layer includes a glass substrate and a core via.
The glass substrate has a first surface and a second surface facing each other.
The core vias penetrate the glass substrate in the thickness direction, and a large number of the core vias are arranged.
The core layer includes a core distribution layer located on the surface of the glass substrate or core via.
At least a part of the core distribution layer electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface via the core via.
The upper layer includes an electrically conductive layer located on the first surface and electrically connecting the core distribution layer and an external semiconductor element portion.
A packaging substrate in which the thickness of the thin electrical conductive layer of the core distribution layer is equal to or thicker than the thickness of the thin electrical conductive layer of the upper layer.

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