JP2022181307A - Imaging device and imaging apparatus - Google Patents

Abstract

To materialize high quality of an image generated from a signal output from a pixel.SOLUTION: An imaging device comprises: a plurality of pixel blocks each of which has a plurality of pixels including photoelectric conversion units performing photo-electric conversion of light thereby generating electric charges and arranged in a first direction and a second direction intersecting with the first direction; and a plurality of control lines which are electrically connected to one pixel of the plurality of pixel blocks, being a part of the plurality of pixel blocks, and supply a control signal to the plurality of pixels. The plurality of pixels to which one control line of the plurality of control lines is connected, include pixels each of which has a first spectral responsivity and a second spectral responsivity different from the first spectral responsivity.SELECTED DRAWING: Figure 2

Description

The present invention relates to an imaging device and an imaging device.

2. Description of the Related Art An imaging device is known in which one control line for transfer control is provided in common for a plurality of pixels that generate signals of the same color (for example, Japanese Unexamined Patent Application Publication No. 2002-100003). 2. Description of the Related Art Conventionally, it has been desired to improve the quality of images generated from output signals.

JP 2013-143730 A

According to the first aspect, the imaging device includes a photoelectric conversion unit that photoelectrically converts light to generate electric charges, and includes a plurality of pixels provided in a first direction and in a second direction that intersects with the first direction. and a plurality of pixel blocks, which are part of the plurality of pixel blocks and electrically connected to each one of the pixels in the plurality of pixel blocks, to supply a control signal to the plurality of pixels. and a plurality of control lines, wherein the plurality of pixels to which one of the plurality of control lines is connected has a first spectral sensitivity, and the first spectral sensitivity is and pixels having different second spectral sensitivities.

It is a sectional view showing composition of an imaging device typically. FIG. 2 is an overall plan view of the imaging device viewed from the imaging surface side; 3 is an enlarged view of a part of the imaging element shown in FIG. 2; FIG. 2 is a circuit diagram of pixels and a readout circuit of an imaging device; FIG. It is a sectional view of an image sensor. FIG. 10 is a circuit diagram of pixels and a readout circuit of an image sensor in Modification 1; FIG. 10 is a circuit diagram of pixels and a readout circuit of an image sensor in Modification 2;

An imaging device according to an embodiment and an imaging device included in the imaging device will be described with reference to the drawings.
FIG. 1 is a block diagram schematically showing the configuration of an imaging device according to an embodiment. FIG. 1 shows a configuration example of an electronic camera 1 (hereinafter referred to as camera 1), which is an example of an imaging device according to an embodiment. For convenience of explanation, an orthogonal coordinate system consisting of x-axis, y-axis and z-axis is provided as shown in the figure. In FIG. 1, the z-axis is provided along the direction of the optical axis O of the imaging optical system 2, and the y-axis is perpendicular to the z-axis and provided along the vertical direction of the paper surface of FIG. The x-axis is provided along a direction orthogonal to the y-axis and z-axis.
The camera 1 includes an imaging optical system (imaging optical system) 2 , an imaging element 3 , a control section 4 , a memory 5 and an operating section 7 . The imaging optical system 2 has a plurality of lenses including a focusing lens (focus lens) and a diaphragm, and forms a subject image on the imaging device 3 . Note that the imaging optical system 2 may be detachable from the camera 1 .

The imaging device 3 is, for example, a CMOS image sensor. The imaging element 3 receives the light flux that has passed through the imaging optical system 2 and captures an image of the subject. In the imaging element 3, as will be described in detail later, a plurality of pixels each having a microlens and a photoelectric conversion unit are arranged two-dimensionally (row direction and column direction intersecting therewith). The photoelectric conversion unit is composed of, for example, a photodiode (PD). The imaging device 3 has imaging pixels and AF pixels (focus detection pixels). The imaging pixels photoelectrically convert incident light and output signals (image signals) used for image generation. The AF pixel photoelectrically converts incident light and outputs a signal (focus detection signal) used for focus detection. A signal (image signal, focus detection signal) generated by the imaging element 3 is output to the control section 4 .

The memory 5 is, for example, a recording medium such as a memory card. Image data and the like are recorded in the memory 5 . Writing data to the memory 5 and reading data from the memory 5 are performed by the control unit 4 . The operation unit 7 includes various setting switches such as a release button and a power switch, and outputs operation signals to the control unit 4 according to the respective operations.

The control unit 4 includes a CPU, ROM, RAM, etc., and controls each unit of the camera 1 based on a control program. The control unit 4 has an image data generation unit 4a as a function. The image data generator 4a performs various image processing on the imaging signal output from the imaging element 3 to generate image data. Image processing includes, for example, known image processing such as tone conversion processing, color interpolation processing, edge enhancement processing, and the like.

The imaging device 3 included in the camera 1 of this embodiment will be described in detail.
FIG. 2 is a diagram schematically showing the overall configuration when the imaging device 3 is viewed from the imaging plane side, that is, from the +z side in FIG. The imaging device 3 has a plurality of pixels 30 arranged in the x direction and the y direction in FIG. Although some of the pixels 30 are omitted in FIG. 2, the pixels 30 may be arranged in large numbers, for example, 1000 or more in the x direction and the y direction.
A horizontal control unit HC is provided at the left end in the drawing, and a vertical control unit VC is provided at the upper end in the drawing, of the region (imaging region) in which a plurality of pixels 30 are arranged.

The imaging device 3 has a plurality of pixel blocks BC. In FIG. 2, one pixel block BC has a plurality of pixels 30 arranged in the x-direction and the y-direction surrounded by a boundary line BB indicated by a dashed line. A plurality of pixels 30 in each of the pixel blocks BC have their respective output sections connected to one output line and to one readout section, as will be described later. A plurality of pixels 30 in each pixel block BC may be connected to a plurality of output lines and may be connected to a plurality of readout units.

In FIG. 2, a portion corresponding to one pixel block BC is hatched for ease of explanation. However, each area surrounded by each boundary line BB indicated by a broken line is a pixel block BC.
In the example shown in FIG. 2, a total of 16 pixels 30 arranged four in the x direction and four in the y direction form one pixel block BC.
The number of pixels arranged in the x direction and the y direction in one pixel block BC is not limited to four, and may be another number such as six or eight. The number of arrays may differ between the x direction and the y direction.
Also, the contour shape of the pixel block BC is not limited to the rectangular shape shown in FIG. In this case, the shape of the boundary line BB is not a simple straight line, but a shape in which a plurality of straight lines are bent and connected.

FIG. 3 is an enlarged view of some pixel blocks BC (that is, two pixel blocks BC1 and BC2 adjacent in the x direction) of the pixels 30 shown in FIG. As shown in FIG. 3, each of the plurality of pixels 30 is provided with one of three color filters (color filters) having different spectral characteristics, for example, R (red), G (green), and B (blue). The R color filter mainly transmits light in the red wavelength range, the G color filter mainly transmits light in the green wavelength range, and the B color filter mainly transmits light in the blue wavelength range. . Pixels have different spectral characteristics depending on the color filters arranged. The pixel 30 includes a pixel sensitive to red (R) light (hereinafter referred to as R pixel 30R) and a pixel sensitive to green (G) light (hereinafter referred to as G pixel 30Gr or G pixel 30Gb). ) and pixels sensitive to blue (B) light (hereinafter referred to as B pixels 30B). These pixels 30 are arranged in a so-called Bayer arrangement. The G pixel 30Gb is a G pixel arranged in the same x direction as the B pixel 30B, and the G pixel 30Gr is a G pixel arranged in the same x direction as the R pixel 30R.

The pixel block BC1 has four G pixels 30Gb1, G pixels 30Gr1, R pixels 30R1, and B pixels 30B1 arranged in a Bayer array. The pixel block BC2 has four G pixels 30Gb2, four G pixels 30Gr2, four R pixels 30R2, and four B pixels 30B2 arranged in a Bayer array. These pixels 30 are all imaging pixels Gb, Gr, R, and B used for imaging an optical image formed on the imaging surface of the imaging device 3 .

From the vertical control unit VC shown in FIG. 2, vertical selection lines VS1 to VS8 (generally referred to as vertical selection lines VS) connected to vertical selection transistors TV (see FIG. 4), which will be described later, of each pixel 30 extends in the y-direction. From the horizontal control unit HC, horizontal control lines HS1 to HS4 (generally referred to as horizontal control lines HS) are connected to transfer transistors TX (see FIG. 4) functioning as transfer units (described later) of the pixels 30 for each row. ) and a horizontal select line HD connected to a later-described horizontal select transistor TH (see FIG. 4) of the pixel 30 extends in the x direction.

As shown in FIG. 3, each of the vertical selection lines VS1 to VS8 is shared by multiple pixels 30 aligned in the y direction, and the horizontal selection line HD is shared by multiple pixels 30 aligned in the x direction.
In the present embodiment, the plurality of pixels 30 to which one horizontal control line out of the plurality of horizontal control lines HS1 to HS4 is connected are the pixels 30 having the first spectral sensitivity and the pixels 30 having the first spectral sensitivity. includes pixels 30 having different second spectral sensitivities. Specifically, the spectral sensitivity of the pixels 30 connected to the horizontal control line HS1 in the pixel block BC1 is different from the spectral sensitivity of the pixels 30 connected to the horizontal control line HS1 in the pixel block BC2.

FIG. 4 is a diagram showing an outline of an electric circuit of pixels 30 forming pixel blocks BC1 and BC2 shown in FIG. 4 representatively shows the electric circuit of the pixels 30 in the n-th row and the (n+1)-th row shown in FIG.
As shown in FIG. 4, the horizontal control line HS1 is connected to the R pixel 30R1a of the pixel block BC1 and the G pixel 30Gr2a of the pixel block BC2. Similarly, the horizontal control line HS2 is connected to the G pixel 30Gr1a of the pixel block BC1 and to the R pixel 30R2a of the pixel block BC2. The horizontal control line HS3 is connected to the R pixel 30R1b of the pixel block BC1 and to the G pixel 30Gr2b of the pixel block BC2. The horizontal control line HS4 is connected to the G pixel 30Gr1a of the pixel block BC1 and to the R pixel 30R2b of the pixel block BC2.

In each pixel 30 (Gr, R), the photodiode PD, which is a photoelectric conversion unit, photoelectrically converts incident light to generate charges, and temporarily accumulates the generated charges. The transfer transistor TX is a transfer unit that transfers charges accumulated in the photodiode PD to a floating diffusion (FD) region FD based on a control signal sent to its gate from the horizontal control line HS. The FD region FD is an accumulation portion in which a capacitor CC is formed and charges generated by the photodiode are accumulated. A voltage generated in the FD region FD by the transferred charges is applied to the gate of the amplification transistor TA, thereby outputting a signal corresponding to the charges generated in the photodiode PD.

A power supply voltage VDD is applied to the input side (drain) of the amplification transistor TA. The reset transistor TR is a reset unit that resets the voltage of the FD area FD to the power supply voltage VDD by discharging the charge of the FD area FD to the power supply voltage VDD side. The output side (source side) of the amplification transistor TA of each pixel 30 is connected to the input side of the vertical selection transistor TV. A gate of the vertical selection transistor TV is connected to a vertical selection line VS, and the vertical selection transistor TV is rendered conductive or non-conductive by a control signal from the vertical selection section VC shown in FIG.

The output side of the vertical selection transistor TV is connected to the input side of the horizontal selection transistor TH. A gate of the horizontal selection transistor TH is connected to a horizontal selection line HD, and the horizontal selection transistor TH is rendered conductive or non-conductive by a control signal sent from the horizontal control section HC shown in FIG. The output side of the horizontal selection transistor TH is connected to the output line RW, and serves as an output section for outputting a signal based on charges generated by photoelectric conversion to the output line RW, which is a signal line. The output line RW is connected to a readout section 100 that reads out signals of the pixels 30 . The readout unit 100 has, for example, an AD conversion unit that converts an analog signal output from the pixel 30 into a digital signal, and is provided for each pixel block BC.

The imaging operation including the reset operation of the pixels 30 of the imaging device 3 of this embodiment is substantially the same as that of the conventional CMOS type imaging device. That is, prior to an exposure operation for imaging or focus detection, reset transistor TR and transfer transistor TX are brought into conduction with power supply voltage VDD, and FD region FD and photodiode PD are reset to power supply voltage VDD. After that, the transfer transistor TX is made non-conductive, and the photodiode PD is exposed for imaging or focus detection.

Next, readout of signals from the pixels 30 of the image sensor 3 will be described.
The vertical control unit VC is connected to a vertical selection line VS1 connected to the n-th row R pixel 30R1a of the pixel block BC1 shown in FIGS. 3 and 4, and to the n-th row G pixel 30Gr2a of the pixel block BC2. A signal is sent to the vertical selection line VS6, thereby conducting the vertical selection transistor TV of the R pixel 30R1a and the vertical selection transistor TV of the G pixel 30Gr2a. Then, the horizontal control unit HC sends a control signal to the horizontal control line HS1 to make the transfer transistor TX of the R pixel 30R1a and the transfer transistor TX of the G pixel 30Gr2a conductive. Then, the horizontal control unit HC sends a signal to the horizontal selection line HD to turn on the horizontal selection transistors TH of the R pixel 30R1a and the G pixel 30Gr2a.
By the above control, the signal (R signal) of the R pixel 30R1a of the pixel block BC1 is output to RW1, and the signal (G signal) of the G pixel 30Gr2a of the pixel block BC2 is output to RW6. As a result, the reading unit 100 connected to the pixel block BC1 can read the signal (R signal) of the R pixel 30R1a, and the reading unit 100 connected to the pixel block BC2 can read the signal (G signal) of the G pixel 30Gr2a. ) can be read.
After that, the vertical control unit VC sends a signal to the vertical selection line VS1 and the vertical selection line VS6 to make the vertical selection transistor TV non-conductive. The horizontal control unit HC sends a signal to the horizontal control line HS1 to make the transfer transistor TX non-conductive.

The vertical control unit VC sends a signal to the vertical selection line VS2 connected to the G pixel 30Gr1a of the pixel block BC1 and the vertical selection line VS5 connected to the R pixel 30R2a of the pixel block BC2 to select the G pixel 30Gr1a vertically. The transistor TV and the vertical selection transistor TV of the R pixel 30R2a are made conductive. The horizontal control unit HC sends a control signal to the horizontal control line HS2 to make the transfer transistor TX of the G pixel 30Gr1a of the pixel block BC1 and the transfer transistor TX of the R pixel 30R2a of the pixel block BC2 conductive. Then, the horizontal control unit HC sends a signal to the horizontal selection line HD to turn on the horizontal selection transistors TH of the G pixel 30Gr1a and the R pixel 30R2a.
By the above control, the signal (G signal) of the G pixel 30Gr1a of the pixel block BC1 is output to RW2, and the signal (R signal) of the R pixel 30R2a of the pixel block BC2 is output to RW5. As a result, the reading section 100 can read the G signal and the R signal.
After that, the vertical control unit VC sends a signal to the vertical selection line VS2 and the vertical selection line VS5 to make the vertical selection transistor TV non-conductive. The horizontal control section HC sends a signal to the horizontal control line HS2 to make the transfer transistor TX non-conductive.

The vertical control unit VC sends a signal to the vertical selection line VS3 connected to the R pixel 30R1b of the pixel block BC1 and the vertical selection line VS4 connected to the G pixel 30Gr2b of the pixel block BC2 to select the R pixel 30R1b vertically. The transistor TV and the vertical selection transistor TV of the G pixel 30Gr2b are made conductive. The horizontal control unit HC sends a control signal to the horizontal control line HS3 to make the transfer transistor TX of the R pixel 30R1b of the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2b of the pixel block BC2 conductive. Then, the horizontal control unit HC sends a signal to the horizontal selection line HD to turn on the horizontal selection transistors TH of the R pixel 30R1b and the G pixel 30Gr2b.
By the above control, the signal of the R pixel 30R1b of the pixel block BC1 is output to RW3, and the signal of the G pixel 30Gr2b of the pixel block BC2 is output to RW8. As a result, the reading unit 100 connected to the pixel block BC1 can read the signal (R signal) of the R pixel 30R1b, and the reading unit 100 connected to the pixel block BC2 can read the signal (G signal) of the G pixel 30Gr2b. ) can be read.
After that, the vertical control unit VC sends a signal to the vertical selection line VS3 and the vertical selection line VS8 to make the vertical selection transistor TV non-conductive. The horizontal control unit HC sends a signal to the horizontal control line HS3 to make the transfer transistor TX non-conductive.

The vertical control unit VC sends a signal to the vertical selection line VS4 connected to the G pixel 30Gr1b of the pixel block BC1 and to the vertical selection line VS7 connected to the R pixel 30R2b of the pixel block BC2 to select the G pixel 30Gr1b vertically. The transistor TV and the vertical selection transistor TV of the R pixel 30R2b are made conductive. The horizontal control unit HC sends a control signal to the horizontal control line HS4 to make the transfer transistor TX of the G pixel 30Gr1b of the pixel block BC1 and the transfer transistor TX of the R pixel 30R2b of the pixel block BC2 conductive. Then, the horizontal control unit HC sends a signal to the horizontal selection line HD to turn on the horizontal selection transistors TH of the G pixel 30Gr1b and the R pixel 30R2b.
By the above control, the signal of the G pixel 30Gr1b of the pixel block BC1 is output to RW4, and the signal of the R pixel 30R2b of the pixel block BC2 is output to RW7. As a result, the reading unit 100 connected to the pixel block BC1 can read the signal (G signal) of the G pixel 30Gr1b, and the reading unit 100 connected to the pixel block BC2 can read the signal (R signal) of the R pixel 30R2b. ) can be read.
After that, the vertical control unit VC sends a signal to the vertical selection line VS4 and the vertical selection line VS7 to make the vertical selection transistor TV non-conductive. The horizontal control unit HC sends a signal to the horizontal control line HS4 to make the transfer transistor TX non-conductive.

For the (n+1)th and subsequent rows, the same processing as the above-described nth row is performed. As a result, the signal (B signal) of the B pixel 30B and the signal (G signal) of the G pixel 30Gb can be read from the (n+1)th row.
The reading of the signals of the pixels 30 in the pixel blocks BC1 and BC2 has been described above, but the same applies to the other pixel blocks BC. A signal of each pixel 30 in each pixel block BC is output to an output line RW provided in each pixel block BC and read by the readout section 100 . Note that the vertical selection line VS may be shared by a plurality of pixel blocks BC. For example, the vertical selection lines VS1 to VS8 may be connected to each pixel 30 in another pixel block BC aligned in the y direction with respect to the pixel block BC.
A signal read by the readout unit 100 of each pixel block BC is output from the image sensor 3 via an output circuit (not shown).

The image data generation unit 4 a rearranges the signals output from the image pickup device 3 in order according to the arrangement of the pixels 30 . In this case, the horizontal control line HS1, the horizontal control line HS2, the horizontal control line HS3, and the horizontal control line HS4 are turned on in this order, so that the image data generation unit 4a generates a Gr signal from the G pixel 30Gr2a and a Gr signal from the R pixel 30R2a. , the Gr signal from the G pixel 30Gr2b, and the R signal from the R pixel 30R2b are rearranged in the order in which the pixels 30 in the n-th row are arranged in the x direction. That is, the image data generator 4a converts the signals output in the above order into the R signal from the R pixel 30R2a, the Gr signal from the G pixel 30Gr2a, the R signal from the R pixel 30R2b, and the Gr signal from the G pixel 30Gr2b. Sort in the order of The image data generation unit 4a rearranges the signals from the pixels 30 on the n+1th row and after in the same order according to the arrangement of the pixels 30 . After the above processing, the image data generator 4a performs various image processing on the signal output from the image sensor 3 to generate image data.

FIG. 5 is a diagram showing a cross section of the pixel 30 portion of the image sensor 3 of this embodiment. Note that FIG. 5 shows only a partial cross section of the entire imaging element 3 . The x-direction and z-direction shown in FIG. 5 are the same as the directions shown in FIG. The imaging device 3 is a so-called back-illuminated imaging device. The imaging element 3 photoelectrically converts light incident from the upper direction of the paper surface. The imaging device 3 includes a first semiconductor substrate 7 and a second semiconductor substrate 8 .

As described above, the imaging device 3 has multiple pixels 30 . One pixel 30 includes a pixel upper portion 30 x provided on the first semiconductor substrate 7 and a pixel lower portion 30 y provided on the second semiconductor substrate 8 . One pixel upper portion 30x includes one microlens 74, one color filter 73, one light receiving portion 31 of the photodiode PD, and the like.

The first semiconductor substrate 7 includes a light receiving layer 71 including the light receiving portion 31 of the photodiode PD included in the pixel upper portion 30x, and a wiring layer 72 in which transistors such as the transfer transistor TX and the amplification transistor TA are formed. The light receiving layer 71 is arranged on the opposite side (rear surface side) of the first semiconductor substrate 7 to the wiring layer 72 . A plurality of light receiving portions 31 are arranged two-dimensionally in the light receiving layer 71 .

Vertical selection transistors TV, horizontal selection transistors TH, vertical selection lines VS, horizontal control lines HS, a reading section 100, a current source CS, and the like, which are included in the pixel lower portion 30y, are arranged on the second semiconductor substrate 8 .
A plurality of bumps 75 are arranged on the surface of the wiring layer 72 . A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72 . The plurality of bumps 75 and the plurality of bumps 76 are bonded together. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the plurality of bumps 75 and the plurality of bumps 76 .

The configuration of the circuit elements respectively arranged on the first semiconductor substrate 7 and the second semiconductor substrate 8 described above is an example, and some of the components are the first semiconductor substrate 7 and the second semiconductor substrate 8. can be placed in either For example, the light receiving layer 71 including the light receiving portion 31 of the photodiode PD, the transfer transistor TX, the amplification transistor TA, and the vertical selection transistor TV are formed on the first semiconductor substrate 7, and the horizontal selection transistor TH and the horizontal control line HS are formed. , the readout section 100 and the current source CS may be arranged on the second semiconductor substrate 8 .

A light-receiving layer 71 including a light-receiving portion 31 of a photodiode PD, a transfer transistor TX, an amplification transistor TA, a vertical selection transistor TV, a horizontal selection transistor TH, and a horizontal control line HS are formed on a first semiconductor substrate 7, and a reading portion 100 is formed. and the current source CS may be arranged on the second semiconductor substrate 8 .
The vertical controller VC and the horizontal controller HC may be arranged on either the first semiconductor substrate 7 or the second semiconductor substrate 8 .
Further, the pixel 30 is not limited to the laminated structure having the first semiconductor substrate 7 and the second semiconductor substrate 8, and each of the above structures may be arranged on one semiconductor substrate.

However, if many circuit elements are arranged on the first semiconductor substrate 7, the area or volume for arranging the light receiving section 31 on the first semiconductor substrate 7 cannot be sufficiently secured. It is preferably arranged on the semiconductor substrate 8 .
The color filter 73 of each pixel 30 is arranged with a color filter that matches the spectral sensitivity characteristic of each pixel.

In the embodiments of the imaging device described above, the arrangement of the pixels 30 is not necessarily limited to the Bayer arrangement. Further, the horizontal control lines HS may extend in the short side direction (y direction) instead of the long side direction (x direction) of the imaging device 3, and the vertical selection lines VS may extend in the short side direction (y direction) of the imaging device 3. direction), but may extend in the long side direction (x direction). Further, the horizontal control line HS and the vertical selection line VS for controlling the signal output of each pixel 30 do not have to extend in the horizontal direction (x direction) and vertical direction (y direction).

According to the embodiment described above, the following effects are obtained.
(1) The imaging device 3 includes a plurality of pixel blocks BC and a plurality of horizontal control lines HS. Each of the plurality of pixel blocks BC includes a photodiode PD, which is a photoelectric conversion unit that photoelectrically converts light to generate electric charges, and includes a first direction (x direction) and a second direction (y direction) intersecting the first direction. ), respectively. The plurality of horizontal control lines HS are part of the plurality of pixel blocks BC, are electrically connected to each one pixel 30 in the plurality of pixel blocks BC, and supply control signals to the plurality of pixels 30. do. A plurality of 30 pixels to which one horizontal control line out of the plurality of horizontal control lines HS is connected has a pixel 30 having a first spectral sensitivity and a second spectral sensitivity different from the first spectral sensitivity. and pixels 30 .
When one control line for transfer control is provided in common for a plurality of pixels that generate signals of the same color as in the prior art, if there is an abnormality in the wiring, the lines are arranged in the same row. It becomes impossible to output a signal of a predetermined color from the pixel.
On the other hand, in the present embodiment, by having the above-described configuration, when any one of the plurality of horizontal control lines HS has an abnormality, the same-color horizontal control lines HS arranged in the same row It is possible to prevent the characteristic color from becoming a defect in the generated image because the signal from the pixel 30 provided with the color filter cannot be obtained. Further, even if there is an abnormality in any horizontal control line HS among the plurality of horizontal control lines HS and a signal of a certain color cannot be obtained, other color filters of the same color arranged in the same row are Complementary processing can be performed using signals from the provided pixels 30 .

(2) The pixel 30 of the imaging element 3 includes a transfer transistor TX that transfers charges generated by the photodiode PD, which is a photoelectric conversion unit, and at least one horizontal control line among the plurality of horizontal control lines HS is It is connected to the transfer transistor TX. As a result, the circuit configuration of the image sensor 3 of the embodiment can be realized only by changing the connection destination of the horizontal control line HS in the circuit configuration of the conventional image sensor.

The following modifications are also within the scope of the present invention, and it is also possible to combine one or more of the modifications with the above-described embodiments.
(Modification 1)
The electric circuit of each pixel 30 is not limited to the example shown in FIG.
FIG. 6 is a diagram showing an outline of an electric circuit of the pixels 30 forming the pixel blocks BC1 and BC2 in Modification 1. As shown in FIG. Note that FIG. 6 also shows the circuit configuration of the pixels 30 in the n-th row and the (n+1)-th row as representatives.
In Modified Example 1, the imaging device 3 has a configuration in which the FD area FD, which is an accumulation section, is shared by a plurality of pixels 30 included in the pixel block BC. That is, each pixel 30 of pixel blocks BC1 and BC2 has a photodiode PD and a transfer transistor TX, and each pixel 30 of each pixel block BC1 and BC2 shares reset transistor TR, amplification transistor TA and horizontal selection transistor TH. .

Also in Modification 1, as in the embodiment, the plurality of pixels 30 to which one of the plurality of horizontal control lines HS1 to HS4 is connected is the pixel 30 having the first spectral sensitivity. and a pixel 30 having a second spectral sensitivity different from the first spectral sensitivity. That is, the horizontal control line HS1 is connected to the transfer transistor TX of the R pixel 30R1a of the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2a of the pixel block BC2. The horizontal control line HS2 is connected to the transfer transistor TX of the G pixel 30Gr1a of the pixel block BC1 and the transfer transistor TX of the R pixel 30R2a of the pixel block BC2. The horizontal control line HS3 is connected to the transfer transistor TX of the R pixel 30R1b of the pixel block BC1 and the transfer transistor TX of the G pixel 30Gr2b of the pixel block BC2. The horizontal control line HS4 is connected to the transfer transistor TX of the G pixel 30Gr1a of the pixel block BC1 and the transfer transistor TX of the R pixel 30R2b of the pixel block BC2.
Even with the configuration of the electric circuit of the imaging device 3 of Modification 1, the same effects as the effects (1) and (2) obtained by the above-described embodiment can be obtained.

(Modification 2)
Instead of rearranging the signals output from the pixels 30 in the image data generator 4 a in the order according to the arrangement of the pixels 30 , the image pickup device 3 rearranges the signals from the pixels 30 in the order according to the arrangement of the pixels 30 . can be output. FIG. 7 shows an outline of an electric circuit of the pixels 30 forming the pixel blocks BC1 and BC2 of Modification 2. As shown in FIG. FIG. 7 also representatively shows the circuit configuration of the pixels 30 arranged in the n-th row and the (n+1)-th row. The imaging device 3 has a memory (storage unit) 101 for each pixel block BC. Other configurations are the same as those of the charge circuit of the pixel 30 shown in FIG.

As described in the embodiment, in the pixel block BC2, the Gr signal from the G pixel 30Gr2a, the R signal from the R pixel 30R2a, the Gr signal from the G pixel 30Gr2b, and the R signal from the R pixel 30R2b are applied in this order. A signal is output. The signals output in the above order are converted into digital signals by the reading unit 100, and are temporarily stored in the memory 101 provided in the pixel block BC2 sequentially. Each signal is output from the memory 101 in the order of the R signal from the R pixel 30R2a, the Gr signal from the G pixel 30Gr2a, the R signal from the R pixel 30R2b, and the Gr signal from the G pixel 30Gr2b. Input to the data generator 4a. That is, even when the horizontal control line HS is connected to each pixel 30 as in the embodiment, signals can be output from the imaging device 3 in an order according to the arrangement of the pixels 30 .

(Modification 3)
At least one of the horizontal control lines HS may be connected to a reset transistor TR, which is a reset section. At least one of the horizontal control lines HS may be connected to the vertical selection transistor TV which is the output section. At least one of the horizontal control lines HS may be connected to the transfer transistor TX, at least one may be connected to the reset transistor TR, and at least one may be connected to the vertical selection transistor TV. Even when the horizontal control line HS is connected as described above, the same effect as the effect (1) obtained by the above-described embodiment can be obtained.

Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

1: imaging device,
3: image sensor,
4a: image data generator,
7: first semiconductor substrate,
8: second semiconductor substrate,
30: pixel,
100: reading unit,
101: memory,
BC, BC1, BC2: pixel blocks,
HS, HS1, HS2, HS3, HS4: horizontal control line PD: photodiode,
TX: transfer transistor;
TR: reset transistor,
TA: amplification transistor

Claims (10)

a plurality of pixel blocks each having a plurality of pixels provided in a first direction and in a second direction intersecting the first direction;
a plurality of control lines that are part of the plurality of pixel blocks and are electrically connected to each one of the pixels in the plurality of pixel blocks to supply control signals to the plurality of pixels; prepared,
The plurality of pixels to which one of the plurality of control lines is connected includes pixels having a first spectral sensitivity and pixels having a second spectral sensitivity different from the first spectral sensitivity. An image sensor, including In the imaging device according to claim 1,
A transfer unit that transfers the charge generated by the photoelectric conversion unit,
The imaging device, wherein at least one control line among the plurality of control lines is connected to the transfer section. In the imaging device according to claim 1 or claim 2,
an accumulation unit for accumulating charges generated by the photoelectric conversion unit;
a reset unit that resets the charge accumulated in the accumulation unit;
The imaging device, wherein at least one control line among the plurality of control lines is connected to the reset section. In the imaging device according to claim 3,
The imaging device, wherein the storage section is shared by a plurality of pixels included in the pixel block. In the imaging device according to any one of claims 1 to 4,
a signal line for outputting a signal based on the charge generated by the photoelectric conversion unit;
an output unit that outputs a signal based on the charge generated by the photoelectric conversion unit to the signal line,
The imaging device, wherein at least one control line among the plurality of control lines is connected to the output section. In the imaging device according to any one of claims 1 to 5,
An imaging device, comprising a storage unit that stores signals output from the plurality of pixels. In the imaging device according to claim 6,
The storage unit is an imaging element provided for each pixel block. In the imaging device according to claim 6 or claim 7,
The pixels are provided on a first substrate,
The imaging device, wherein the storage unit is provided on a second substrate laminated on the first substrate. In the imaging device according to any one of claims 1 to 8,
The imaging device, wherein the arrangement of the plurality of pixels included in the plurality of pixel blocks is a Bayer arrangement. An imaging device according to any one of claims 1 to 9;
and a generation unit that generates image data based on the signal output from the imaging device.

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