JP2022179239A - Three-dimensional logic lsi using stacked logic circuit - Google Patents

Abstract

To solve a problem in which there is currently no means for achieving both low cost and high speed in a large-scale logic LSI using a conventional planar transistor formed on a planar pattern.SOLUTION: Instead of a planar transistor used in a conventional 3D logic LSI, a logic LSI is realized by using a NAND circuit formed by connecting in series stacked SGTs that use a multi-layered vertical transistor structure used in a large-capacity stacked NAND memory. As a result, when a large-scale logic LSI is divided into three dimensions, the chip area can be reduced compared to the conventional type, such that cost reduction, which has not been possible with the conventional type, can be realized. Furthermore, the reduction of the chip area also makes it possible to achieve a higher speed than the conventional type.SELECTED DRAWING: Figure 1

Description

The present invention relates to a three-dimensional logic LSI using stacked logic circuits.

In the past, according to Moore's Law, LSIs have progressed in miniaturization of planar transistors, and have steadily advanced in capacity increase, cost reduction, speed increase, and power consumption reduction. As a result, MPUs (Micro Processor Units), which are representative of logic LSIs, have realized GHz operation using more than 1 billion planar transistors, and have used planar transistors with the highest capacity among memory LSIs. The capacity of NAND flash memory is being increased up to 64 Gbit (Reference 1).

In LSI, according to Moore's Law, the number of planar transistors has steadily doubled every 18 months (one generation), and billions of planar transistors are currently integrated. If the area of the planar transistor is large, the LSI becomes very large, and a realistic LSI cannot be realized in terms of operating performance and manufacturing cost.

To solve this problem, a scaling law has been used in the past that shrinks planar transistor dimensions by a factor of 0.7 in length in one generation. According to the scaling law, if a planar transistor is shrunk at the same rate (0.7 times) in the vertical, horizontal, and height directions, it not only becomes smaller, but it also has the characteristics of achieving higher speed and lower power consumption. . In other words, in the past half century, Moore's law and scaling law have been used as guiding principles in LSIs to realize high integration (increasing the number of planar transistors in a small LSI area of about 1 square millimeter), high speed, and low power consumption. I've been

However, the miniaturization of planar transistors is approaching its limit in recent years due to the short channel effect and the like.
In order to solve this problem, a three-dimensional transistor that is resistant to the short channel effect has been developed. A typical example is an SGT (Surrounding Gate Transistor) (Reference 2).

Although the short channel effect can be reduced by introducing an SGT or the like, there is a problem that it only contributes to the reduction of the delay time of the transistors required for increasing the speed of the logic LSI. In order to reduce the delay time of wiring, which is more important than the delay time of transistors, logic LSIs created using planar transistors are stacked vertically (hereinafter abbreviated as the planar stacking method. The patent name is planar. The official name is a three-dimensional logic LSI that uses a logic circuit based on type transistors (Fig. 4, Reference 3).

A logic LSI consisting of planar transistors with a large chip area is divided vertically and horizontally, and these are stacked vertically, and necessary wirings are connected vertically using TSVs. As a result, the long wiring of the logic LSI in the case of one layer can be divided into short pieces in the horizontal direction, and can be connected by the TSV in the vertical direction. Therefore, the wiring delay time can be greatly reduced. As a result, not only the delay time of the transistor but also the delay time of the wiring can be reduced, so that it becomes possible to increase the speed of a logic LSI with a large chip size.

However, although this planar lamination method can achieve high speed, it cannot achieve cost reduction. This is because a logic LSI with a large chip area is divided in the vertical and horizontal directions and then laminated, so there is no reason for cost reduction. Conversely, there is even a problem that the cost increases due to the division of large chips, the stacking in the vertical direction, and the connection of wiring in the vertical direction by TSV.

In other words, in logic LSIs, no method has been proposed so far that not only speeds up but also lowers the cost. Until now, there is no means that can continue to achieve both low cost and high speed logic LSIs even after the limit of Moore's Law.

[Reference 1] M. Sako et al, "A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology", ISSCC Dig. Tech. Papers, 2015.
[Reference 2] H.I. Takato et al. , "Impact of SGT for ultra-high density LSIs", IEEE Trans. Electron Devices, vol. 38, pp. 573-578, 1991.
[Reference 3] Shigeka Watanabe, "System LSI Design Technology Using Three-Dimensional Stacked Logic Circuits", Vol. 102, No. 1, pp. 74-78, 2019.

At present, there is no means for continuously achieving both low cost and high speed logic LSIs even after the limit of Moore's Law.

Instead of the planar transistor used in the planar stacked logic LSI, the manufacturing technology (Documents 4, 5, Patent Document 1) used for the large-capacity stacked NAND memory is used for the stacked SGT. are connected in series.

[Reference 4] H.I. Tanaka et al. ,: "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", Symp. on VLSI Technology, 2007.
[Reference 5] R.I. Katsumata et al. , "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices", Symp. on VLSI Technology, pp. 136-137, 2009.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2009-4517, Keian Tanaka, Hideaki Aochi, Ryuta Katsumata, Suguru Kito, Yoshiaki Fukuzumi, Dai Kito, Mitsuru Sato, and Yasuyuki Matsuoka “Non-volatile semiconductor memory device and manufacturing method thereof”

According to the present invention, instead of the planar transistor, by using the manufacturing technology used for the large-capacity stacked NAND memory and connecting the stacked SGTs in series, not only the speed of the conventional example can be increased. It will be possible for the first time to achieve both low cost and low cost.

As will be described later, as a result of the reduction in chip area according to the present invention, there is an effect that the manufacturing cost can be reduced to half that of the conventional example while ensuring high-speed performance as compared with the conventional example.
[Best mode for carrying out the invention]

Hereinafter, a first embodiment of a logic LSI using a stacked logic circuit according to the present invention will be described with reference to the drawings.
[First embodiment]
(Configuration of the first embodiment)

One embodiment of the present invention will be described below. FIG. 1 shows the configuration of a three-dimensional logic LSI (100) based on a newly proposed stacked logic circuit.
Instead of the planar transistor used in the planar stacked logic LSI, a method in which stacked SGTs are connected in series using the manufacturing technology used for large-capacity stacked NAND memory (stacked SGT series-connected logic LSI (reference 6)).

[Reference 6]
S. Watanabe, "Design Guideline for Logic LSI Using 3D Stacked SGT Logic Circuit Overcoming Miniaturization Limit of Planar Transistor," The Institute of Electronics, Information and Communication Engineers Transaction C, Vol. J103-C, No. 11, pp. 483-484, 2020, Early publication date September 1, 2020.

FIG. 1 shows the configuration of a logic LSI (100) based on a newly proposed stacked logic circuit. 100 is a system in which the serially connected logic LSIs (101, 102, 103, 104) of the stacked SGTs stacked in four layers (any number of layers are acceptable as long as there are multiple layers) are vertically connected by TSVs (105). formed.

FIG. 2 shows the details of the logic LSI (201, 202, 203, 204) of the series connection system of the stacked SGTs. The serially connected logic LSIs (101, 102, 103, 104) of the stacked SGTs are composed of K stages of NAND circuits (211, 221). Signals 201, 202 and 203 are input to the gates of the K-stage circuits.
A dynamic circuit is used for the load portion of the NAND circuit, which is characterized by being able to reduce the pattern area. A precharge signal 208 is input to the gate of the load transistor.

The pattern area of the driver portion (209) of the K-stage NAND circuit is the standardization of the SGT (204) for both the driver portion and the load portion (208 composed of a transistor to which the gate is input) of the K-stage NAND circuit. If the pattern area obtained is B, then ^BF2 is obtained. The reason why the SGT is used in this proposal is that it has a current driving capability and an S factor comparable to those of a planar transistor and can be easily laminated. We assume B=4 in this paper.

As a result, the pattern area of one NAND circuit can be reduced to 2BF ² /(KAF ² )=2/K as compared with the conventional planar type by introducing the first embodiment. As a result, the chip area of the first embodiment can be reduced to (2/K) ^0.5 (2/K) ^0.5 =2/K. In FIG. 2, the horizontal length of the logic LSI is indicated by 222, and the vertical length is indicated by 223. As shown in FIG. Therefore, according to the first embodiment, the cost can be reduced as compared with the conventional example using the planar transistor.

Since K=4 is often used in logic LSIs using ordinary planar transistors, in that case, the pattern area of the serially connected logic LSIs (101, 102, 103, 104) of the stacked SGTs is that of the planar stacked type. The pattern area of the logic LSI (401, 402, 403, 404) of the method can be reduced to 2/K=2/4=half. Since the manufacturing cost of a logic LSI is usually proportional to the chip area, the manufacturing cost of the first embodiment can be reduced to half that of a conventional planar stacked logic LSI.

As shown in [0025], by introducing the first embodiment, the operating speed of the logic LSI can be made faster than that of the conventional flat-type stacked logic LSI.

The delay time of the K-stage NAND circuit (211) is expressed by C(K), assuming that the SGT and the plane type have the same current driving capability. The delay time of a logic circuit is usually represented by the sum of the gate delay and the wiring delay. Assume that the ratio of both is 1:L in the planar type. Since the wiring length is proportional to the square root of the chip area, the wiring length of the proposed method can be reduced to (2/K) ^0.5 of the planar type. Since both the parasitic capacitance and the parasitic resistance of the wiring are proportional to the wiring length, the wiring delay in the first embodiment is (2/K) ^0.5 (2/K) ^0.5 = 2/K of the planar type. can be reduced. As a result, the total delay time of the K-stage NAND circuit is C(K)(1+L) in the planar type, whereas it is C(K)(1+L(2/K)) in the proposed type. can be reduced.

(Configuration of Second Embodiment)
FIG. 3 shows the configuration of a logic LSI (320) based on the stacked logic circuit of the second embodiment. The logic LSI is constructed by vertically stacking N NAND circuits (301, 302, 303) of K stages. The load portion of the NAND circuit uses a dynamic circuit which is characterized by being able to reduce the pattern area as in the first embodiment. A precharge signal 208 is input to the gate of the load transistor.

By introducing the proposed method, the pattern area of one NAND circuit can be reduced to 2BF ² /(KANF ² )=2/K compared to the conventional planar type. As a result, the chip area of the second embodiment can be reduced to (2/KN) ^0.5 (2/KN) ^0.5 =2/(NK). The effect of reducing the chip area is N times that of the first embodiment. In FIG. 2, the horizontal length of the logic LSI is indicated by 322, and the vertical length is indicated by 323. As shown in FIG. In other words, when N=2, the second embodiment can further reduce the manufacturing cost to half that of the first embodiment.
[Effect of Embodiment]

According to the first embodiment, the manufacturing cost can be reduced by half compared with the conventional example using a logic LSI using planar transistors. Furthermore, according to the second embodiment, the manufacturing cost can be reduced to 1/4 of the conventional example using a logic LSI using planar transistors.

In the first embodiment, not only can the cost be reduced as compared with the conventional planar stacked logic LSI, but also the speed can be increased by reducing the wiring delay time. For example, if a conventional planar stacked logic LSI is used and the length of one side is 1 cm and the thickness of the silicon substrate is 4 microns, the delay time of the logic LSI is divided equally into 14 sides (short side and long side). It becomes minimum when 14*14=196 layers are stacked.

On the other hand, in the first embodiment, the chip area can be reduced to half that of the conventional planar stacked logic LSI. The value is characterized by speeding up by several percent as compared with the conventional flat-type stacked logic LSI.
[Other embodiments]

The present invention is applicable not only to logic LSIs but also to all LSIs that operate on digital logic such as memory LSIs that are currently on the market.

1 is a diagram realizing a first embodiment of a three-dimensional logic LSI using a stacked logic circuit according to the present invention; FIG. Detailed view of 101, 102, 103, 104 parts of the first embodiment FIG. 10 is a diagram realizing a second embodiment of a three-dimensional logic LSI using a stacked logic circuit according to the present invention; 1 is a diagram of a three-dimensional logic LSI using conventional planar transistors; FIG.

100 .
201... First input signal to NAND, 202... Second input signal to NAND, 203... Kth input signal to NAND, 204... SGT, 205... Ground , 206 . Driver section 211... K-stage NAND circuit structure 221... K-stage NAND circuit structure 220... Logic LSI by K-stage NAND circuit of the first embodiment 222... The horizontal length of the logic LSI by the K-stage NAND circuit of the first embodiment, 223 ... the vertical length of the logic LSI by the K-stage NAND circuit of the first embodiment,
301 K-stage NAND circuit 1, 302 K-stage NAND circuit 2, 303 K-stage NAND circuit N, 304 SGT, 305 ground, 306 second 307 . NAND circuits in stages, 311 . Logic LSI by K-stage NAND circuits connected in series in N stages of the example, 322 . - The vertical length of the logic LSI by the N stages of series-connected K stage NAND circuits of the second embodiment,
400 ... three-dimensional logic LSI by logic circuits using planar transistors, 401 to 404 ... logic LSIs by logic circuits using planar transistors, 405 ... 401 to 404 are vertically connected. TSV,
420 . . . Planar logic LSI with planar transistors before division, 421 . 423 . to form a three-dimensional logic LSI

Claims (4)

A logic circuit stack connection structure realized by serially connecting transistors for inputting digital information, a NAND circuit for digital operation is configured by the logic circuit stack connection structure, and a plurality of the NAND circuits are integrated on the same plane. A three-dimensional logic LSI characterized by vertically stacking a plurality of such logic LSIs. 2. In the three-dimensional logic LSI according to claim 1, the logic circuit stack connection structure realized by connecting the transistors in series transmits an output signal in the vertical direction with respect to the semiconductor substrate. A three-dimensional logic LSI characterized by forming a gate electrode and an interlayer insulating film by stacking them a number of times to connect them in series, and then isolating adjacent transistors and forming the transistors by a collective etching technique reaching the semiconductor substrate. 3. A three-dimensional logic LSI according to claim 1, wherein a plurality of NAND circuits with three or more inputs are integrated in said three-dimensional logic LSI. 3. The three-dimensional logic LSI according to any one of claims 1, 2, and 3, wherein a plurality of NAND circuits having a wiring delay time longer than its own gate delay time are integrated in the three-dimensional logic LSI. 3D type logic LSI.

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