JP2022177671A - Information processing device and storage control method - Google Patents

Abstract

To increase processor performance by reducing the amount of data exchanged between a memory and an integrated circuit that has the processor and a cache memory.SOLUTION: An information processing device includes an integrated circuit and a memory. The integrated circuit includes: a processor; a cache memory that stores data used by the processor; a compressor and a decompressor; and a storage control device. The memory is connected to the integrated circuit. The storage control device compresses target data using the compressor when storing the target data in the memory; transmits the compressed target data to the memory; decompresses the compressed target data using the decompressor when receiving the compressed target data from the memory; and writes the decompressed target data in the cache memory.SELECTED DRAWING: Figure 1

Description

The present invention relates to an information processing device and a storage control method.

Conventionally, a method of compressing data blocks in a cache and virtually increasing the capacity of the cache itself has been proposed. In this method, a data compressor/decompressor is interposed between a cache data block read/written from a processor and the processor to increase the size of the cache that can be virtually stored (for example, see Non-Patent Document 1).

There is also a method of adding a compression mechanism to file systems such as ZFS, BTFS, and NFS. In this method, compression is performed on storage block data, and data indicating whether or not compression has been performed is stored in a "block table" in the file system separately from the data body (for example, Non-Patent Document 4 reference).

Shingo Otani, Airi Ogawa, Kenji Kichise, Skewed DRAM cache using data compression in FPGA system, Proc. www.arch.cs.titech.ac.jp/a/thesis/Bthesis-2016-02-ohya.pdf V. Young, P. J. Nair and M. K. Qureshi, "DICE: Compressing DRAM caches for bandwidth and capacity," 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), Toronto, ON, Canada, 2017, pp. 627－638 , doi: 10.1145/3079856.3080243. S. Sardashti, A. Seznec and D. A. Wood, "Skewed Compressed Caches," 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, Cambridge, UK, 2014, pp. 331－342, doi: 10.1109/MICRO.2014.41. Hyun S., Ahn S., Lee S., Bahn H., Koh K. (2007) Memory-Efficient Compressed Filesystem Architecture for NAND Flash-Based Embedded Systems. In: Gervasi O., Gavrilova M.L. (eds) Computational Science and Its Applications - ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74472-6_20 Xiang Gao, Mingkai Dong, Xie Miao, Wei Du, Chao Yu, Haibo Chen, EROFS: A Compression-friendly Readonly File System for Resource-scarce Devices, 2019 {USENIX} Annual Technical Conference, https://www.usenix.org /conference/atc19/presentation/gao

In a system that includes an integrated circuit (LSI) with a processor and a cache memory, and a memory connected to the integrated circuit, the time to write data to the memory and the time to cache the data stored in the memory are used to improve the performance of the processor. Shortening the time to write to memory is desired. Therefore, it is conceivable to compress the data to be written to the memory, write the compressed data to the memory, decompress the data read from the memory, and write it to the cache memory.

However, the prior art does not disclose or suggest the aspect of compressing data to be written to memory and decompressing data read from memory and storing it in cache memory. Also, the size of compressed data does not necessarily decrease due to compression processing, and conversely, the size may increase. There is no disclosure or suggestion of problems that arise when the size of data after such compression becomes larger than the size of the original data.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus capable of improving processor performance by reducing the amount of data exchanged between a memory and an integrated circuit having a processor and cache memory.

One aspect of the present invention is an information processing device. The information processing apparatus includes a processor, a cache memory for storing data used by the processor, a compressor and decompressor, an integrated circuit including a storage controller, and a memory connected to the integrated circuit. When the target data is stored in the memory, the storage controller compresses the target data using a compressor, transmits the target data in the compressed state to the memory, and when the target data in the compressed state is received from the memory Then, the target data in the compressed state is decompressed using a decompressor, and the decompressed target data is written in the cache memory.

One aspect of the present invention is a storage control method. In this storage control method, a processor, a cache memory for storing data used by the processor, and a storage controller included in an integrated circuit together with a compressor and a decompressor store target data in a memory connected to the integrated circuit. compressing the target data using the compressor, transmitting the target data in the compressed state to the memory, and compressing the target data in the compressed state using the decompressor when the target data in the compressed state is received from the memory It includes decompressing the data and writing the decompressed target data to the cache memory.

The following configuration may be employed in the storage control method. That is, the storage area of the memory is divided into blocks having a predetermined size, and the storage control device determines that the size of the target data in an uncompressed state does not exceed the block size, but the size of the target data in a compressed state does not exceed the block size. exceeds the block size, the uncompressed target data is transferred to the memory.

Also, in the storage control method, the following configuration may be adopted. That is, the storage control device transmits target data in a compressed state or an uncompressed state together with information indicating whether the target data is in a compressed state or an uncompressed state, receives the target data and information from the memory, and sends the target data and information to the memory. When indicating the compression state of the data, the target data is decompressed using the decompressor.

According to the present invention, the performance of the processor can be improved by reducing the amount of data exchanged between the memory and the integrated circuit having the processor and cache memory.

It is a figure which shows the structural example of the information processing apparatus which concerns on embodiment. FIG. 2A is an explanatory diagram for storing target data in a memory, and FIG. 2B shows an example data structure of a management table managed by a storage control device. 3A and 3B are diagrams for explaining the problem in the reference example. 4A and 4B are diagrams for explaining the storage control method in the embodiment. FIG. 5 is a diagram illustrating a first configuration example of a memory according to the embodiment; FIG. 6 is a flow chart showing an operation example of the storage control device when writing to the memory. FIG. 7 is a flow chart showing an operation example of the storage control device when writing to the cache memory. FIG. 8 is a diagram showing a second configuration example of the memory. FIG. 9 is a flow chart showing an operation example of the storage control device when the second configuration example is applied. FIG. 10 is a flow chart showing an operation example of the storage control device when the second configuration example is applied.

An information processing apparatus according to an embodiment includes an integrated circuit including a processor, a cache memory for storing data used by the processor, a compressor and decompressor, and a storage controller, and a memory connected to the integrated circuit. include. When the target data is stored in the memory, the storage controller compresses the target data using a compressor, transmits the target data in the compressed state to the memory, and when the target data in the compressed state is received from the memory Then, the target data in the compressed state is decompressed using a decompressor, and the decompressed target data is written in the cache memory.

According to the information processing apparatus, when target data is stored in the memory, the target data in a compressed state is transmitted from the integrated circuit to the memory. Also, when storing data in the cache memory, compressed target data is received. When the communication speed between the integrated circuit and the memory is constant, the compression of the target data reduces the size of the target data, thereby shortening the time required for data transmission between the two. Therefore, it is possible to shorten the time required for writing data to the memory as seen from the processor. In addition, target data in a compressed state whose size is smaller than that in an uncompressed state is received by the integrated circuit, decompressed, and stored in the cache memory, thereby shortening the read time from the memory as seen from the processor. can do. In this way, the performance of the processor can be improved by shortening the write time and read time for the memory.

The information processing apparatus can employ the following configuration. That is, when the storage area of the memory is partitioned into blocks of a predetermined size capable of storing target data, the storage control device determines that the size of the uncompressed target data does not exceed the block size, but the When the target data size exceeds the block size, the uncompressed target data is sent to the memory. The size of target data is not necessarily reduced by compression, and the size after compression may become larger than the original size. In such a case, the amount of data to be transmitted to the memory is suppressed by transmitting not the compressed target data, which is the target data after compression, but the uncompressed target data, which is the original target data.

Further, the information processing apparatus can employ the following configuration. That is, the storage control device transmits the compressed or uncompressed target data to the memory along with information indicating whether the target data is compressed or uncompressed. A memory stores information and target data in one of blocks. When target data and information are received from the memory and the information indicates the compression state of the target data, the storage controller decompresses the target data using the decompressor. In this way, information indicating whether the target data to be transmitted to the memory is in a compressed state or a non-compressed state is stored in the memory together with the target data, and the target data and information are passed to the storage control device when reading from the memory. Thus, the storage controller can determine whether or not decompression is necessary. If decompression is not required, writing to the cache memory without decompression can shorten the time required to complete writing to the cache memory.

When information indicating whether the target data is in a compressed state or a non-compressed state is stored in the memory, the memory uses an error correction code memory (ECC memory), and the information is stored in the error correction code storage area of the error correction code memory. Preferably, a stored configuration is employed. As a result, the target data and the information can be stored in the memory while being associated with each other.

Further, the information processing apparatus can employ the following configuration. That is, it is stipulated that data is stored in the storage area of the memory in compressed block units having a size larger than the block size. Compressed subject data sent to memory is stored in each compressed block. By adopting such a configuration, even if the size of the target data in the compressed state becomes larger than the size of the target data before compression, and the size exceeds the size of the block, the target data in the compressed state is preferably stored. can do.

Embodiments of an information processing apparatus and a storage control method will be described below with reference to the drawings. The configuration of the embodiment is an example, and the present invention is not limited to the configuration of the embodiment.

FIG. 1 shows a configuration example of an information processing apparatus 1 according to an embodiment. In FIG. 1, an information processing apparatus 1 includes a microprocessor LSI 10 (hereinafter, integrated circuit 10) which is an example of an integrated circuit, a memory (main storage device) 15 connected to the integrated circuit 10 via a bus 2, and an integrated circuit. and a storage (auxiliary storage device) 21 connected to the circuit 10 via the bus 2 .

The integrated circuit 10 includes a processor 11, a cache memory 12, a memory controller (Memory
Management Unit (MMU) 13, and compressor 14A and decompressor 14B used by MMU 13.

The processor 11 is a microprocessor (MPU), a CPU (Central Processing Unit), or the like. Cache memory 12 is implemented within integrated circuit 10 . memory 1
5 and storage 21 are connected to integrated circuit 10 via bus 2 . That is, the memory 15 and storage 21 are arranged outside the integrated circuit 10 .

Cache memory 12 , memory 15 , and storage 21 store data used by processor 11 . The cache memory 12 is a high-speed and small-capacity storage medium (a clock frequency on the order of GHz and a capacity of several megabytes) located closer to the memory 15 and the storage 21, and is composed of an SRAM or the like. The memory 15 is a recording medium that is slower than the cache memory 12 but has a large capacity (a clock frequency of about 100 MHz and a capacity of several GB), and is configured using a DRAM or the like. The storage 21 is a storage medium that is slower than the memory 15 but has a large capacity (several tens of MHz clock frequency and several TB capacity), such as a hard disk or SSD (Solid State Drive).

Normally, when the processor 11 performs processing, data to be processed is read from the storage 11 and stored in the memory 15 . If the data is not stored in the cache memory 12 in the process of passing the data stored in the memory 15 to the processor 11 , the data is stored in the cache memory 12 . When the processor 11 requests to read data stored in the memory 15, it is determined whether the requested data is stored in the cache memory 12, and if the data is stored, the read from the memory 15 is performed. is not performed, and the data stored in the cache memory 12 is passed to the processor 11 .

Since the SRAM used for the cache memory 12 is expensive, currently there are CPUs having first to fourth level caches, but it is difficult to increase the capacity of the cache memory. Therefore, shortening the time required for writing to and reading from the memory 15 is an important factor in improving the performance of the processor 11 .

In order to speed up the input/output speed between the processor 11 and the memory 15, the following can be considered.
(1) Speeding up the interface of the memory 15 (2) Increasing the number of bits of the interface of the memory 15

However, the method (1) for speeding up the interface of the memory 15 has the problem that it is difficult to mount it on a printed circuit board, or the switching of transistors increases, power consumption increases, and heat generation occurs. On the other hand, in the method (2) of increasing the number of bits of the interface of the memory 15, the number of pins of the integrated circuit 10 is increased, resulting in an increase in cost. In addition, as in (1), there are problems such as high difficulty in mounting on a printed circuit board and heat generation due to increased switching of transistors. Therefore, in the present embodiment, by compressing the data to be written to the memory 15 (target data), the amount of data transmitted to the memory 15 for writing and the amount of data transmitted from the memory 15 to the integrated circuit 10 for reading are reduced. By reducing the amount of data transmitted to the , the required time for writing and reading can be shortened, and the performance of the processor 11 can be improved.

Cache control such as management of data stored in the cache memory 12 is performed by the MMU 13, for example. However, a configuration may be adopted in which an entity (cache controller) that performs cache control is provided in addition to the MMU, and the cache control is performed by the cache controller. That is, the "storage control device" according to the present invention may have a configuration in which the MMU controls the cache, or may have a configuration including the MMU and the cache controller. In this embodiment, the MMU 13 has the functions of the compressor 14A and decompressor 14B, or employs a configuration that controls the operations of the compressor 14A and decompressor 14B, enabling compression and decompression of target data. The compression and decompression methods applied to compressor 14A and decompressor 14B are not limited as long as reversible compression and decompression of data are possible.

In this embodiment, data management in the memory 15 is performed in units of physical blocks (referred to as blocks 15a) in which storage areas of a plurality of consecutive addresses starting from an address referred to as a base address are collected. A storage area of the memory 15 is partitioned into blocks 15a having a predetermined size. Data is read from and written to the memory 15 by sequentially accessing a predetermined number of continuous addresses forming one block 15a starting from a base address (called a burst mode). Data is written to the cache memory 12 in units of blocks 15a. The size of the block 15a can be determined appropriately.

In order to obtain the benefit of burst mode access to the memory 15, the cache memory 12 has a configuration that manages cache data in units of blocks (storage areas) of several tens to several kilobytes that match the size of the blocks 15a. Data is exchanged with the memory 15 in units of this block.

As shown in FIG. 2A, the MMU 13 has a management table 16 that manages the relationship between the storage areas of the cache memory 12 and the storage areas of the memory 15. FIG. As shown in FIG. 2B, the management table 16 includes cache tags (identifiers of blocks in the cache memory 12) indicating the locations (addresses) of the blocks 12a in the cache memory 12 that store the data stored in the blocks 15a of the memory 15. , and the base address, which is the starting point address of the block 15a in which the data stored in the block 12a is stored on the memory 15, is stored.

The processor 11 can access all addresses of the memory 15 , and data write and read instructions are performed by designating the base address of the memory 15 . When data stored in the block 15a of the memory 15 is stored in the block 12a of the cache memory 12, a cache tag identifying the block 12a of the cache memory 12 is stored in the management table 16 in association with the base address of the memory 15. be done.

The MMU 13 refers to the management table 16 when receiving from the processor 11 an instruction to read data specifying a certain base address in the memory 15 . At this time, if a cache tag related to the specified base address is stored in the management table 16, the MMU 13 reads data from the block 12a of the cache memory 12 specified by the cache tag and supplies it to the processor 11 ( cache hit).

In referring to the management table 16, if the management table 16 does not store the cache tag associated with the designated base address, the MMU 13 determines that the data to be read is not stored in the cache memory 12 (cache mistake). At this time, the MMU 13 accesses (reads data) one block of consecutive addresses starting from the base address of the memory 15 specified by the read command, and reads data from the block 15a of the memory 15 specified by the base address. . The MMU 13 stores the data read from the memory 15 in an empty (including overwriteable) block 12a of the cache memory 12, and stores the cache tag of this block 12a in the management table 16 in association with the base address.

When the processor 11 updates the data stored in the cache memory 12 and issues a write command to the memory 15, the MMU 13 refers to the management table 16 and caches data associated with the base address specified in the write command. A tag is specified, and the updated data is written to the block 12a of the cache memory 12 specified by this cache tag.

For example, the MMU 13 monitors access to each block 12a of the cache memory 12 storing data, and when a block 12a is not accessed continuously for a predetermined time, the data stored in the block 12a is read. . Alternatively, when there is no block 12a in the cache memory 12 that can store the data read from the memory 15 according to the data read command of the processor 11, the MMU 13 selects one of the blocks 12a according to a predetermined rule, and selects the selected block. Read the data stored in 12a.

As a predetermined rule for selecting the blocks 12a, for example, the block 12a corresponding to the current position of the pointer pointing cyclically (round robin) to one of the blocks 12a is selected as the read target. There are various ways to advance the pointer. For example, the pointer is advanced by one each time a block 12a is read. Alternatively, each block 12a may be set with a time stamp for recording the last read time, and the block 12a with the oldest time stamp may be selected as a read target. Predetermined rules are not limited to these examples.

The MMU 13 refers to the management table 16, specifies the block 15a on the memory 15 starting from the base address associated with the cache tag of the block 12a, and uses the burst mode to read data from the block 12a. Store in the specified block 15a. At this time, the MMU 13 deletes the pair of the corresponding cache tag and base address from the management table 16, thereby setting the block 12a of the cache memory 12 specified by the cache tag to an empty state.

In addition, when the processor 11 generates data that is not stored in the cache memory 13 and the memory 15 by processing or calculation according to the program, the processor 11 writes the data that specifies the base address of the write destination of the memory 15 according to the program. Issue a write command. As the base address, the base address of the block 15a on the memory 15 in the free state (including the overwritable state) is specified. Since such a base address is not found in the management table 16, the MMU 13 writes the data to be written into the block 15a specified by the base address specified by the write command.

As described above, the information processing apparatus 1 of the present embodiment is configured such that the memory 15 cannot be accessed at a granularity finer than the base address. That is, the memory 15 is partitioned for each base address.

In the information processing apparatus 1 according to the present embodiment, when writing (storing) data in the memory 15, the MMU 13 compresses data to be written using the compressor 14A. However, the size of data to be written is not necessarily reduced by compression, and conversely, the size may be increased. Such an increase in size occurs when the randomness of data is high.

FIG. 3A shows a case where the size of data to be written is reduced by compression by the compressor 14A. When the size of the data is reduced by compression, the data (indicated by hatching) fits within the write destination block 15a. At this time, the amount of data to be transferred to the memory 15 is reduced.

FIG. 3B shows a case where the size of data to be written increases due to compression by the compressor 14A. When the size of the data increases due to compression, the data (shown by hatching) does not fit in the write destination block 15a, and the data is written to the block 15a (adjacent block) adjacent to the write destination block 15a. There was a risk of being In this case, there is a risk that the data in the adjacent block will be damaged by overwriting the data in the adjacent block. In addition, an increase in the amount of data due to compression increases the overhead time for writing, which may be a factor in degrading the performance of the processor 11 .

Therefore, in this embodiment, as shown in FIG. 4, when the MMU 13 detects that the size of the data to be written by the compressor 14A is equal to or larger than the size of the block 15a after compression, Compressor 14A is deactivated and the original (uncompressed) data is transferred to memory 15 for writing. Since the size of the original data is a size that fits in block 15a, the amount of data transmitted to memory 15 is not reduced, but the problem of overwriting adjacent blocks can be avoided.

FIG. 5 shows a configuration example (first configuration example) of the memory 15 according to the embodiment. As shown in FIG. 5, in the memory 15, storage areas corresponding to four addresses form one block 15a. An area (field) 15b is provided in which information indicating whether or not the status is set.

In this embodiment, when the data is compressed, a bit (compression bit) indicating the compression state of the data is set. However, a bit (uncompressed bit) indicating the uncompressed state of data may be set. When the address is set in units of access to the memory 15 (for example, in word units), the compression bit is added to each word and indicates whether the word is in a compressed state or a non-compressed state. When reading data from the block 15a of the memory 15, the MMU 13 refers to the compression bit in word units to identify whether the data is in a compressed state or an uncompressed state, and to what extent the data is compressed.

Compressed bits are implemented by adding pins to integrated circuit 10 to transmit the compressed bits. Also, an area 15b for storing compressed bits is added to the memory 15. FIG. For example, if one address has a word length of 32 bits and the compression bit is 1 bit, the data width of the memory 15 is increased so that a data width of 33 bits can be stored. An ECC memory can be applied as memory 15, and a field for storing error correction codes can be used as area 15b to store compressed bits.

FIG. 6 is a flow chart showing an operation example of the MMU 13 when writing data to the memory 15. As shown in FIG. In step S<b>11 , the MMU 13 acquires (receives) a data write command (write request) to the memory 15 issued by the processor 11 .

In step S<b>12 , the MMU 13 acquires data to be written to the memory 15 (target data). The target data is updated data stored in the block 12a of the cache memory 12 or new data received from the processor 11 (data not stored in the cache memory 12 and memory 15).

In step S13, the MMU 13 turns on the operation of the compressor 14A to compress the target data. Compression is done on a word-by-word basis. In step S14, the MMU 14 determines whether or not the size of the compressed data (compressed data) exceeds the size of the block 15a of the memory 15 or not. If it is determined that the size of the compressed data is smaller than the size of the block 15a (NO in S14), the process proceeds to step S15; YES), the process proceeds to step S17.

In step S15, the MMU 13 determines whether or not the compression of all the target data has been completed. At this time, if it is determined that the compression has been completed, the process proceeds to step S16, and if not determined, the process returns to step S13 to compress the data of the next word.

In step S16, the MMU 13 writes the compressed target data to the block 15a starting from the base address of the write destination block 15a. At this time, the MMU 13 transfers the compressed data and compressed bits to the memory 15 in word units (address units) forming the block 15a in burst mode. The compressed data and compressed bits are written to the appropriate storage areas in block 15a.

At step S17, the MMU 13 stops the operation of the compressor 14A. In step S18, the MMU 13 writes the uncompressed target data to the block 15a starting from the base address of the write destination block 15a. At this time, the MMU 13 transfers uncompressed data (uncompressed data) to the memory 15 in units of words (units of address) forming the block 15a in burst mode. The uncompressed data is written to the corresponding storage area in block 15a.

It should be noted that the transfer of the compressed data in units of words and the compressed bits may be performed by real-time processing or by batch processing. When real-time processing is transferred, the transfer of compressed data and compressed bits is stopped by stopping data compression when a determination of YES is made in step S14, and the transfer of non-compressed target data is started. be done.

FIG. 7 is a flow chart showing an operation example of the MMU 13 when reading data from the memory 15 . In step S<b>21 , the MMU 13 acquires (receives) a data read command (read request) from the memory 15 issued by the processor 11 .

In step S22, the MMU 13 refers to the management table 16 and searches the management table 16 for the record of the base address specified by the read command. If a cache tag associated with the specified base address is found from the management table 16, the MMU 13 determines that there is a cache hit, and advances the process to step S27. On the other hand, if the record of the specified base address is not found from the management table 16, the MMU 13 determines that there is a cache miss, and advances the process to step S23.

In step S23, the MMU 13 acquires data stored in the block 15a of the memory 15 starting from the designated base address. In step S24, the MMU 13 determines whether the data is compressed data (compressed or uncompressed) by determining whether the compression bit has been read from the block 15a. At this time, if the data is determined to be compressed data, the process proceeds to step S25; otherwise, the process proceeds to step S26.

In step S25, the MMU 13 decompresses the data read from the memory 15 using the decompressor 14B (controlling the operation of the decompressor 14B). In step S<b>26 , the MMU 13 writes data to the empty block 12 a of the cache memory 12 . At this time, the MMU 13 registers in the management table 16 a pair of the base address and the cache tag of the block 12a into which the data is written.

At step S26, the MMU 13 supplies the data stored in the block 12a of the cache memory 12 to the processor 11. FIG. Data corresponding to the read command is thereby supplied to the processor 11 .

FIG. 8 shows another configuration example (second configuration example) of the memory 15, which is different from the configuration of the memory 15 shown in FIG. In FIG. 8, the memory 15 defines, as an example, a block 15c (referred to as a compressed block) having twice the size of the block 15a. The data compressed by the compressor 14A is stored in units of compressed blocks 15c regardless of the increase or decrease in size due to compression.

FIG. 9 is a flowchart showing an operation example of the MMU 13 when writing data to the memory 15 according to the second configuration example. The processing of steps S11 to S13 in the flow chart shown in FIG. 9 is the same processing as steps S11 to S13 in FIG. On the other hand, in the flowchart shown in FIG. 9, step S16A is provided instead of steps S14 to S18 shown in FIG. At step S16A, the MMU 13 writes the compressed data to the compressed block 15c of the memory 15 starting from the base address. In the second configuration example, the base address is the starting point of the compression block 15c.

FIG. 10 is a flowchart showing an operation example of the MMU 13 when reading data from the memory 15 in the second configuration example. When the second configuration example is applied, the data read from the memory 15 is compressed data. Therefore, in the flowchart shown in FIG. 10, the processing of step S24 in the flowchart of FIG. 7, that is, the determination of whether the data is in a compressed state or a non-compressed state is not performed, and the process proceeds from step S23 to step S25 to decompress the data. be. Except for this point, the processing of the flowchart of FIG. 10 is the same as the processing of the flowchart of FIG.

The information processing apparatus 1 according to the embodiment is an integrated circuit 10 that includes a processor 11, a cache memory 12 that stores data used by the processor 11, a compressor 14A and a decompressor 14B, and a memory control unit (MMU) 13. and a memory 15 connected to the integrated circuit 10 . When storing the target data in the memory 15 , the MMU 13 compresses the target data using the compressor 14 A and transmits the target data in the compressed state to the memory 15 . When compressed target data is received from the memory 15 , the MMU 13 decompresses the compressed target data using the decompressor 14 B and writes the decompressed target data to the cache memory 12 .

As a result, the amount of data transmitted between the integrated circuit 10 and the memory 15 can be reduced, and the transmission bandwidth (throughput) between the integrated circuit 10 and the memory 15 can be increased. Due to this increase in throughput, the time required for reading and writing to the memory 15 can be shortened, and the performance of the processor 11 can be improved.

In the information processing apparatus 1, the storage area of the memory 15 is divided into blocks for storing target data. The MMU 13 transmits the uncompressed target data to the memory 15 when the size of the target data in the uncompressed state does not exceed the size of the block 15a but the size of the target data in the compressed state exceeds the size of the block 15a. . Thereby, the amount of data transmitted to the memory 15 can be reduced.

The MMU 13 also transmits the target data in the compressed state to the memory 15 together with information (compression bit) indicating the compression state of the target data. The memory 15 stores the compressed bits and the compressed target data in one of the blocks 15a. When the target data and compressed bits are received from memory 15, MMU 13 decompresses the target data with a decompressor. In this manner, whether or not data read from the memory 15 needs to be decompressed can be determined using the compression bit. As a configuration of the memory 15 suitable for this configuration, an ECC memory is applied to the memory 15, and compressed bits are stored in an error correction code storage area (field) 15b of the ECC memory.

Further, in the embodiment, as a second configuration example of the memory 15, it is possible to specify that data is stored in the storage area of the memory 15 in units of compressed blocks 15c having a size larger than the size of the block 15a. Then, the compressed target data transmitted to the memory 15 is stored in the compression block 15c. By using the compressed block 15c in this way, even if the data size increases due to compression, the compressed data can be stored in the compressed block 15c, and overwriting of adjacent blocks can be avoided. The configurations of the embodiments described above can be appropriately combined without departing from the object of the invention.

1 Information processing device 2 Bus 10 Integrated circuit (microprocessor LSI)
11 Processor 12 Cache memory 13 Memory control unit (MMU)
14A Compressor 14B Decompressor 15 Memory 15a Block 15b Compressed bit storage area (field)
15c Compression block 16 Management table

Claims (8)

an integrated circuit including a processor, a cache memory for storing data used by the processor, a compressor and decompressor, and a storage controller;
a memory connected to the integrated circuit;
When storing target data in the memory, the storage control device compresses the target data using the compressor, transmits the target data in a compressed state to the memory, and stores the target data in a compressed state. is received from the memory, decompressing the target data in a compressed state using the decompressor, and writing the decompressed target data to the cache memory;
Information processing equipment. When the storage area of the memory is partitioned into blocks of a predetermined size capable of storing the target data, the storage control device determines that the size of the target data in an uncompressed state does not exceed the size of the block, 2. The information processing apparatus according to claim 1, wherein when the size of the target data in a compressed state exceeds the size of the block, the target data in a non-compressed state is transmitted to the memory. The storage control device transmits information indicating whether the target data is in a compressed state or an uncompressed state and the target data in a compressed state or an uncompressed state to the memory,
the memory stores the information and the target data in any of the blocks;
3. The method according to claim 2, wherein when the target data and the information are received from the memory and the information indicates the compression state of the target data, the storage control device causes the decompressor to decompress the target data. Information processing equipment. 4. The information processing apparatus according to claim 3, wherein said memory is an error correction code memory, and said information is stored in an error correction code storage area of said error correction code memory. The storage area of the memory is defined to store data in units of compressed blocks having a size larger than the size of the block,
3. The information processing apparatus according to claim 2, wherein the compressed target data transmitted to the memory is stored in the compressed block. a processor, a cache memory for storing data used by the processor, and a storage controller included on an integrated circuit with a compressor and a decompressor,
when storing target data in a memory connected to the integrated circuit, compressing the target data using the compressor;
transmitting the target data in a compressed state to the memory;
when the target data in a compressed state is received from the memory, decompressing the target data in a compressed state using the decompressor;
A storage control method comprising writing the decompressed target data into the cache memory. a storage area of the memory is partitioned into blocks having a predetermined size;
When the size of the target data in an uncompressed state does not exceed the size of the block, but the size of the target data in a compressed state exceeds the size of the block, the storage control device controls the size of the target data in an uncompressed state. 7. The storage control method according to claim 6, wherein the data is transferred to said memory. The storage control device transmits the target data in a compressed state or an uncompressed state together with information indicating whether the target data is in a compressed state or an uncompressed state, and receives the target data and the information from the memory. 7. The storage control method according to claim 6, wherein said target data is decompressed using said decompressor when said information indicates the compression state of said target data.

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