JP2022176355A - Error detection device and error detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to estimate FEC symbol errors and FEC code word errors.

SOLUTION: FEC symbol error detection sections 15A, 15B compare most significant bit string data with a reference pattern in the same phase and least significant bit string data with a reference pattern in the same phase in units of FEC symbols to detect FEC symbol errors. Error analysis sections 16A, 16B analyze, for each of the most significant bit string data and the least significant bit string data, an FEC symbol error occurrence state on the basis of an FEC symbol error detection result and an FEC code word error occurrence state on the basis of whether or not the number of FEC symbol errors in one FEC code word exceeds a threshold for the number of FEC symbol errors in one FEC code word.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to an error detection apparatus and an error detection method for detecting an error contained in a test signal by comparing a test signal of a known pattern that is input to a device under test and returned with a reference signal that serves as a reference.

For example, as disclosed in Patent Document 1 below, an error rate measurement device outputs a test signal of a known pattern including fixed data in a state where a device under test (DUT: Device Under Test) is transitioned to a signal pattern loopback state. Conventionally, as a device for measuring a bit error rate by comparing a signal under test transmitted to a device under test and received back from the device under test in accordance with the transmission of the test signal with a reference signal as a reference on a bit-by-bit basis. Are known.

JP 2007-274474 A

By the way, in Ethernet (registered trademark), which is the mainstream of wired network technology, for example, in 400G Ethernet (registered trademark), a stressed input test is specified for the C2M (chip 2 module) interface. For the Stressed Input test, a scrambled idle pattern with RS-FEC (Reed-Solomon Forward Error Correction) encoding is defined in addition to a pseudo-random pattern such as PRBS13Q.

Since the scrambled idle pattern with RS-FEC encoding is subjected to error correction by FEC, the error correction effect by FEC can be evaluated by checking the number of FEC symbol errors.

Error correction by FEC can correct multiple-bit errors in one FEC symbol. Even if there are multiple FEC symbol errors in one FEC codeword, errors in one codeword can be corrected if the number of FEC symbol errors does not exceed the threshold. For this reason, it is difficult to correctly evaluate the error correction effect of FEC only by confirming bit errors.

Since error correction by FEC is a prerequisite for 200G and 400G Ethernet (registered trademark), it is important to evaluate the effect of FEC with a scrambled idle pattern with RS-FEC encoding.

However, to generate a scrambled idle pattern with RS-FEC encoding, eg a 400G transmit PCS layer must be implemented. In addition, it is also necessary to implement eg a 400G receive PCS layer to detect FEC symbol errors. There is a problem that it is difficult to build a test system after mounting these 400G transmission PCS layer and 400G reception PCS layer, and the cost also increases.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an error detection apparatus and an error detection method capable of estimating FEC symbol errors and FEC codeword errors.

In order to achieve the above object, the error detection device according to claim 1 of the present invention generates an error measurement pattern by a known PAM4 signal in the pattern generator 3 and returns it when input to the device under test W. An error detection device 1B that detects an error in an input pattern that is input by an error detector 4,
A setting unit 2a for setting the sizes of FEC symbols and FEC codewords and the threshold value of the number of FEC symbol errors in one FEC codeword,
The error detector is
a PAM4 decoder 4C for decoding the input pattern of the PAM signal returned from the device under test into the most significant bit string data and the least significant bit string data;
an MSB error detector 4A for detecting errors in the most significant bit string data;
and an LSB error detector 4B that detects an error in the least significant bit string data,
The MSB error detector is
a first reference pattern generator 11A for generating a reference pattern having the same pattern as the most significant bit string data of the error measurement pattern so as to be in phase with the most significant bit string data;
generating a timing signal for dividing the most significant bit string data and the bit string of the reference pattern generated by the first reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; 1 timing generator 12A;
a first input pattern boundary generation unit 13A that divides the bit string of the most significant bit string data into units of the FEC symbol and the FEC codeword based on the timing signal generated by the first timing generation unit;
a first reference that divides the bit string of the reference pattern generated by the first reference pattern generation unit into units of the FEC symbol and the FEC codeword according to the timing signal generated by the first timing generation unit; a pattern boundary generator 14A;
A first FEC for detecting an FEC symbol error by comparing the most significant bit string data from the first input pattern boundary generator and the reference pattern from the first reference pattern boundary generator in units of the FEC symbols. a symbol error detector 15A;
Based on the detection result of the first FEC symbol error detection unit, whether the occurrence status of the FEC symbol error and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword a first error analysis unit 16A that analyzes the occurrence status of FEC codeword errors depending on whether
The LSB error detector is
a second reference pattern generator 11B for generating a reference pattern having the same pattern as the least significant bit string data of the error measurement pattern so as to have the same phase as the least significant bit string data;
generating a timing signal for dividing the least significant bit string data and the bit string of the reference pattern generated by the second reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; 2 timing generator 12B;
a second input pattern boundary generation unit 13B that divides the bit string of the least significant bit string data into units of the FEC symbol and the FEC code word by the timing signal generated by the second timing generation unit;
a second reference that divides the bit string of the reference pattern generated by the second reference pattern generation unit into units of the FEC symbol and the FEC codeword according to the timing signal generated by the second timing generation unit; a pattern boundary generator 14B;
second FEC for detecting an FEC symbol error by comparing the least significant bit string data from the second input pattern boundary generator and the reference pattern from the second reference pattern boundary generator in units of the FEC symbol; a symbol error detector 15B;
Whether the FEC symbol error occurrence status and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword based on the detection result of the second FEC symbol error detection unit and a second error analysis unit 16B for analyzing the occurrence status of FEC codeword errors depending on whether or not.

In the error detection method according to claim 2 of the present invention, an error measurement pattern generated by a known PAM4 signal is generated by the pattern generator 3 and input to the device under test W. An error detection method for detection by the detector 4,
a step of setting the size of FEC symbols and FEC codewords and the threshold value of the number of FEC symbol errors in one FEC codeword in the setting unit 2a;
a step of decoding the input pattern of the PAM signal returned from the device under test into the most significant bit string data and the least significant bit string data by the PAM4 decoder 4C;
a step of generating a reference pattern having the same pattern as the most significant bit string data of the error measurement pattern in the first reference pattern generator 11A so as to have the same phase as the most significant bit string data;
a timing signal for dividing the most significant bit string data and the bit string of the reference pattern generated by the first reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; a step of generating by the timing generation unit 12A;
a step of dividing the bit string of the most significant bit string data into units of the FEC symbol and the FEC codeword by the first input pattern boundary generating unit 13A according to the timing signal generated by the first timing generating unit; ,
The bit string of the reference pattern generated by the first reference pattern generator is converted to the FEC symbol by the first reference pattern boundary generator 14A according to the timing signal generated by the first timing generator. partitioning into units of FEC codewords;
The most significant bit string data from the first input pattern boundary generation unit and the reference pattern from the first reference pattern boundary generation unit are compared by the first FEC symbol error detection unit 15A in units of the FEC symbols. detecting FEC symbol errors with
Based on the detection result of the first FEC symbol error detection unit, whether the occurrence status of the FEC symbol error and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword a step of analyzing the occurrence status of the FEC codeword error by the first error analysis unit 16A depending on whether
a step of generating a reference pattern having the same pattern as the least significant bit string data of the error measurement pattern in the second reference pattern generation unit 11B so as to have the same phase as the least significant bit string data;
a second timing signal for dividing the least significant bit string data and the bit string of the reference pattern generated by the second reference pattern generator into units of FEC symbols and FEC codewords set by the setting unit; a step of generating by the timing generation unit 12B;
a step of dividing the bit string of the least significant bit string data into the units of the FEC symbol and the FEC codeword by the second input pattern boundary generating unit 13B according to the timing signal generated by the second timing generating unit; ,
The bit string of the reference pattern generated by the second reference pattern generation unit is converted to the FEC symbol by the second reference pattern boundary generation unit 14B according to the timing signal generated by the second timing generation unit. partitioning into units of FEC codewords;
The least significant bit string data from the second input pattern boundary generation unit and the reference pattern from the second reference pattern boundary generation unit are compared by the second FEC symbol error detection unit 15B in units of the FEC symbols. detecting FEC symbol errors with
Whether the FEC symbol error occurrence status and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword based on the detection result of the second FEC symbol error detection unit A second error analysis unit 16B analyzes the FEC codeword error occurrence status depending on whether or not the error occurs.

According to the present invention, the occurrence of FEC symbol errors and FEC codeword errors is grasped by using known patterns such as PRBS patterns that are commonly used for error measurement without using FEC encoded patterns. becomes possible.

1 is a block diagram showing a first embodiment of an error detection device according to the present invention; FIG. FIG. 4 is a block diagram showing a second embodiment of an error detection device according to the present invention; FIG. 5 is a diagram showing an example of outputs separated in FEC symbol units and FEC codeword units in an input pattern boundary generation unit and a reference pattern boundary generation unit of the error detection device according to the present invention; FIG. 5 is a diagram showing an example of the output of the pattern comparison result for each FEC symbol in the FEC symbol error detection section of the error detection device according to the present invention; FIG. 4 is a diagram showing an example of inputs and outputs of an FEC symbol error detection section of the error detection device according to the present invention; 2 is a flowchart of error detection operation by the error detection device of FIG. 1;

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated in detail, referring attached drawings.

[Overview of the present invention]
For example, 400G Ethernet (registered trademark) is transmission based on error correction by FEC. Therefore, in this system, the quality of the system cannot be correctly evaluated only by measuring bit errors, and it is necessary to accurately grasp the error rate after error correction.

On the other hand, in order to generate FEC-encoded patterns, it is necessary to implement the PCS layer of 400G Ethernet (registered trademark), which increases the difficulty and cost of constructing a test system.

Therefore, the present invention has a function of estimating FEC symbol errors and FEC codeword errors by pseudo-determining boundaries (delimiters) of FEC symbols and FEC codewords for arbitrary known patterns that are not FEC-encoded. Then, without using a scrambled idle pattern with RS-FEC encoding, using a pattern commonly used in error measurement (pseudo random pattern such as PRBS pattern), FEC symbol error and FEC code word error occurrence status To provide an error detection device and an error detection method capable of grasping.

[First embodiment]
As shown in FIG. 1, the error detection device 1A of the first embodiment realizes a function of estimating FEC symbol errors and FEC codeword errors using an NRZ signal that is an arbitrary known pattern that is not FEC-encoded. Therefore, it is roughly configured with an operation unit 2 , a pattern generator 3 , and an error detector 4 .

The operation unit 2 performs various settings (for example, FEC symbol and FEC codeword size settings, threshold settings for the number of FEC symbol errors in one FEC codeword, pattern selection settings, etc.) and various instructions (known It is composed of a graphical user interface (GUI) including a setting section 2a for instructing generation of NRZ signals of patterns, instruction for generating reference patterns, etc., and a display section 2b for displaying measurement results.

Although FIG. 1 shows the operation unit 2 including the setting unit 2a and the display unit 2b, the setting unit 2a and the display unit 2b may be provided separately.

The pattern generator 3 includes a pattern generator 3a and generates an NRZ signal of known pattern as an error measurement pattern to be input to the object W to be measured. The pattern generator 3a follows an instruction from the operation unit 2 to generate a known pseudo-random pattern such as PRBS generally used for error measurement, NRZ-encode it, and output it.

A known pattern NRZ signal generated by the pattern generator 3 is input to the device under test W to be measured for FEC symbol errors, and the input known pattern NRZ signal is returned to the error detector 4 and output.

The error detector 4 detects an error in the known pattern of the NRZ signal (error measurement pattern) that is input from the pattern generator 3 to the device under test W and is returned. An input pattern boundary generator 13 , a reference pattern boundary generator 14 , an FEC symbol error detector 15 and an error analyzer 16 are provided.

The reference pattern generator 11 generates the same pattern as the NRZ signal generated by the pattern generator 3 as a reference pattern for error measurement according to instructions from the operation unit 2 . The reference pattern generator 11 generates a reference pattern based on the input pattern so that it can be compared with the input pattern of the NRZ signal returned from the device under test W, and the top of the generated reference pattern has the same phase as the top of the input pattern. Output the reference pattern so that

The timing generation unit 12 divides the bit strings of the input pattern of the NRZ signal and the reference pattern into units of FEC symbols and FEC codewords set by the setting unit 2a so as to have the size instructed by the operation unit 2. to generate a timing signal for

The timing generator 12 is built in the input pattern boundary generator 13 or the reference pattern boundary generator 14 so that the input pattern boundary generator 13 and the reference pattern boundary generator 14 share the timing signal. may be

The input pattern boundary generator 13 divides the bit string of the input pattern of the NRZ signal input from the device under test W into units of FEC symbols. For example, if one FEC symbol is set to 10 bits, it is divided into 10-bit units as shown in FIGS. FIG. 3 shows an example in which the serial bit string of the input pattern is separated from the head by "1110011000" (398: hexadecimal notation) corresponding to 1 FEC symbol=10 bits. Timing for separating the serial bit string of the input pattern is determined by a timing signal generated by the timing generator 12 .

The reference pattern boundary generation unit 14 divides the bit string of the reference pattern based on the NRZ signal input from the reference pattern generation unit 11 into FEC symbol units. For example, if one FEC symbol is set to 10 bits, it is divided into 10-bit units as shown in FIGS. FIG. 3 shows an example in which the serial bit string of the reference pattern is separated from the head by "1111111000" (3F8: hexadecimal notation) corresponding to 1 FEC symbol=10 bits. Timing for dividing the serial bit string of the reference pattern is determined by a timing signal generated by the timing generator 12 .

Here, since the input pattern from the device under test W and the pattern from the reference pattern generator 11 are in phase, the positions of the bit string delimiters in the input pattern boundary generator 13 and the reference pattern boundary generator 14 are be in the same position. The input pattern boundary generation unit 13 and the reference pattern boundary generation unit 14 generate FEC symbol units (for example, 10 bits)×N (N: FEC code word) as shown in FIG. ) is output for each FEC codeword and input to the FEC symbol error detection unit 15 .

In the above description, the inputs to the input pattern boundary generation unit 13 and the reference pattern boundary generation unit 14 are serial bit strings, and the outputs are parallel bit strings. Both outputs may be serial bit strings and both may be parallel bit strings. In this case, the timing signal generated by the timing generation unit 12 is also input to the FEC symbol error detection unit 15, and the input pattern (input pattern, reference pattern) is divided into FEC symbol units. A bit string is output from the input pattern boundary generation unit 13 and the reference pattern boundary generation unit 14, and the serial bit string or parallel bit string of the pattern separated by the FEC symbol unit is input to the FEC symbol error detection unit 15 and compared by the FEC symbol unit, The timing signal generated by the timing generation unit 12 is used to separate the FEC codewords.

The FEC symbol error detection unit 15 compares the input pattern from the input pattern boundary generation unit 13 and the reference pattern from the reference pattern boundary generation unit 14 for each FEC symbol to detect an FEC symbol error, and determines whether there is an FEC symbol error. is output as the detection result.

To explain further, as shown in FIG. 4, as an input pattern separated by FEC symbols (10 bits) in one FEC codeword (=544 FEC symbols), 390→011→250→042→...→ in hexadecimal notation. A 2FF bit string is input from the input pattern boundary generation unit 13, and 3F0→012→250→042→ . → Assume that a 3FF bit string is input from the reference pattern boundary generation unit 14 . In this case, the FEC symbol error detection unit 15 compares the first bit strings “390” and “3F0” of the input pattern separated by FEC symbols (10 bits) and the reference pattern. Symbol error present: Detected as "1". Below, comparison between the second bit strings "011" and "012" of the input pattern and the reference pattern separated by FEC symbol units, comparison between the third bit strings "250" and "250", comparison of the fourth bit string " 042" and "042", .

The error analysis unit 16 analyzes errors based on the detection result of the FEC symbol error detection unit 15, and includes an FEC symbol error analysis unit 16a and an FEC codeword error analysis unit 16b. Based on the detection result of the FEC symbol error detection unit 15, the FEC symbol error analysis unit 16a counts FEC symbol errors, measures the distribution of FEC symbol errors in one FEC codeword, and determines the occurrence status of FEC symbol errors. is analyzed, and the analysis result is displayed on the display unit 2b of the operation unit 2. FIG.

Based on the detection result of the FEC symbol error detection unit 15, the FEC codeword error analysis unit 16b performs, for example, counting FEC codeword errors, capturing FEC codeword errors, and the like, and determines the number of FEC symbol errors in one FEC codeword. , the occurrence of FEC codeword errors is analyzed depending on whether or not the number of FEC symbol errors in one FEC codeword specified by the operation unit 2 exceeds the threshold value, and the analysis result is displayed on the display unit 2b of the operation unit 2. .

[Second embodiment]
As shown in FIG. 2, the error detection device 1B of the second embodiment uses a PAM4 signal as an arbitrary known pattern that is not FEC-encoded to realize a function of estimating FEC symbol errors and FEC codeword errors. , an operation unit 2 , a pattern generator 3 and an error detector 4 . The same reference numerals are assigned to components that function in the same or equivalent manner as in the error detection apparatus 1A of the first embodiment.

The operation unit 2 performs various settings (for example, FEC symbol and FEC codeword size settings, threshold settings for the number of FEC symbol errors in one FEC codeword, pattern selection settings, etc.) and various instructions (known It is composed of a graphical user interface (GUI) including a setting unit 2a for instructing generation of PAM4 signals of patterns, instruction for generating reference patterns, etc., and a display unit 2b for displaying measurement results.

Although FIG. 2 shows the operation unit 2 including the setting unit 2a and the display unit 2b, the setting unit 2a and the display unit 2b may be provided separately.

The pattern generator 3 includes a pattern generator 3a and a PAM4 encoder 3b, and generates a PAM4 signal of a known pattern as an error measurement pattern to be input to the object W to be measured. The pattern generator 3a generates the most significant bit string data (hereinafter referred to as MSB data) and the least significant bit string data according to a known pseudo-random pattern such as PRBS, which is generally used for error measurement, according to instructions from the operation unit 2. (hereinafter referred to as LSB data) is generated, PAM4-encoded by the PAM4 encoder 3b, and output.

The DUT W to be measured for the FEC symbol error receives the known pattern PAM4 signal generated by the pattern generator 3 and outputs the input known pattern PAM4 signal to the error detector 4 after folding back.

The error detector 4 detects an error in the PAM4 signal (error measurement pattern) of a known pattern input from the pattern generator 3 to the device under test W and returned. , a PAM4 decoder 4C.

The PAM4 decoder 4C decodes the known pattern PAM4 signal input from the pattern generator 3 to the device under test W and returns to generate MSB data and LSB data, and inputs the generated MSB data to the MSB error detector 4A. and inputs the LSB data to the LSB error detector 4B.

The MSB error detector 4A includes a first reference pattern generator 11A, a first timing generator 12A, a first input pattern boundary generator 13A, a first reference pattern boundary generator 14A, and a first FEC symbol error detector. A detection unit 15A and a first error analysis unit 16A are provided.

Although FIG. 2 shows the internal configuration of the MSB error detector 4A, the LSB error detector 4B corresponds to the internal configuration of the MSB error detector 4A (11A, 12A, 13A, 14A, 15A, 16A (16Aa, 16Ab)). ) equivalent internal configuration (second reference pattern generation unit 11B, second timing generation unit 12B, second input pattern boundary generation unit 13B, second reference pattern boundary generation unit 14B, second FEC symbol error It includes a detection unit 15B and a second error analysis unit 16B (FEC symbol error analysis unit 16Ba, FEC codeword error analysis unit 16Bb). The internal configuration of the MSB error detector 4A will be described below. The LSB error detector 4B operates by replacing the MSB data of the MSB error detector 4A with LSB data.

The first reference pattern generating section 11A generates the same pattern as the MSB data generated by the pattern generator 3 as a reference pattern in error measurement according to an instruction from the operation section 2. FIG. The first reference pattern generator 11A generates a reference pattern based on the input pattern so that it can be compared with the input pattern of the MSB data decoded by the PAM4 decoder 4C. Output the reference pattern so that it is in phase with the beginning.

The first timing generator 12A converts the bit strings of the input pattern of the MSB data and the reference pattern into the units of the FEC symbol and FEC codeword set by the setting unit 2a so as to have the size instructed by the operation unit 2. Generates a timing signal for dividing into

Note that the first timing generator 12A is designed to share the timing signal between the first input pattern boundary generator 13A and the first reference pattern boundary generator 14A. 13A or the first reference pattern boundary generator 14A.

The first input pattern boundary generator 13A divides the bit string of the MSB data (input pattern) input from the PAM4 decoder 4C into FEC symbol units. For example, if one FEC symbol is set to 10 bits, it is divided into 10-bit units as shown in FIGS. FIG. 3 shows an example in which the serial bit string of the input pattern is separated from the head by "1110011000" (398: hexadecimal notation) corresponding to 1 FEC symbol=10 bits. The timing for dividing the serial bit string of the input pattern is determined by the timing signal generated by the first timing generator 12A.

The first reference pattern boundary generator 14A divides the bit string of the MSB data (reference pattern) input from the first reference pattern generator 11A into FEC symbol units. For example, if one FEC symbol is set to 10 bits, it is divided into 10-bit units as shown in FIGS. FIG. 3 shows an example in which the serial bit string of the reference pattern is separated from the head by "1111111000" (3F8: hexadecimal notation) corresponding to 1 FEC symbol=10 bits. The timing for separating the serial bit string of the reference pattern is determined by the timing signal generated by the first timing generator 12A.

Here, since the input pattern from the PAM4 decoder 4C and the reference pattern from the first reference pattern generator 11A are in phase, the first input pattern boundary generator 13A and the first reference pattern boundary generator The position of the break of the bit string is the same in the part 14A. The first input pattern boundary generation unit 13A and the first reference pattern boundary generation unit 14A generate FEC symbol units (for example, 10-bit )×N (N: FEC codeword size “544”) parallel bit strings are output for each FEC codeword and input to the first FEC symbol error detector 15A.

As described above with reference to FIG. 4, the first FEC symbol error detector 15A detects the input pattern from the first input pattern boundary generator 13A and the reference pattern from the first reference pattern boundary generator 14A. An FEC symbol error is detected by comparing FEC symbol units, and the presence or absence of an FEC symbol error is output as a detection result.

The first error analysis section 16A analyzes errors based on the detection result of the first FEC symbol error detection section 15A, and includes an FEC symbol error analysis section 16Aa and an FEC codeword error analysis section 16Ab. Based on the detection result of the first FEC symbol error detection unit 15A, the FEC symbol error analysis unit 16Aa counts FEC symbol errors, measures the distribution of FEC symbol errors in one FEC codeword, and detects the FEC symbol errors. is analyzed, and the analysis result is displayed on the display section 2b of the operation section 2. FIG.

The FEC codeword error analysis unit 16Ab performs, for example, counting FEC codeword errors and capturing FEC codeword errors based on the detection result of the first FEC symbol error detection unit 15A, and analyzes FEC symbols in one FEC codeword. The occurrence of FEC codeword errors is analyzed depending on whether the number of errors exceeds the threshold for the number of FEC symbol errors in one FEC codeword specified by the operation unit 2, and the analysis result is displayed on the display unit 2b of the operation unit 2. Display output.

Next, the operation of the error detection device 1A configured as described above will be described with reference to the flow chart of FIG.

First, the setting section 2a of the operation section 2 performs size setting of FEC symbols and FEC codewords, threshold setting of the number of FEC symbol errors in one FEC codeword, and selection setting of NRZ signal patterns (ST1).

The pattern generator 3 generates an NRZ signal error measurement pattern according to the instruction from the operation unit 2, and inputs the generated NRZ signal of the error measurement pattern to the device under test W for FEC symbol error measurement (ST2).

When the NRZ signal of the error measurement pattern is inputted from the pattern generator 3 to the object W to be measured, the NRZ signal of the error measurement pattern is returned by the object W to be measured and inputted to the error detector 4 (ST3 ).

The reference pattern generator 11 of the error detector 4 generates a reference pattern having the same pattern as the NRZ signal of the error measurement pattern returned from the device under test W, and the top of the generated reference pattern is the top of the NRZ signal of the error measurement pattern. A reference pattern is output so as to have the same phase as that of (ST4).

Next, the input pattern boundary generation unit 13 divides the bit string of the NRZ signal of the error measurement pattern returned from the device under test W by the timing signal generated by the timing generation unit 12 for each FEC symbol and each FEC codeword. is output to the FEC symbol error detection unit 15 (ST5).

In addition, the reference pattern boundary generation unit 14 divides the bit string of the NRZ signal of the reference pattern generated by the reference pattern generation unit 11 by the timing signal generated by the timing generation unit 12 into FEC symbol units, and generates FEC codewords. is output to the FEC symbol error detection unit 15 (ST6).

Then, the FEC symbol error detection unit 15 compares the bit string of the NRZ signal of the error measurement pattern from the input pattern boundary generation unit 13 and the bit string of the NRZ signal of the reference pattern from the reference pattern boundary generation unit 14 for each FEC symbol, The presence or absence of FEC symbol errors is detected (ST7).

Next, the FEC symbol error analysis unit 16a analyzes the occurrence of FEC symbol errors based on the detection result of the FEC symbol error detection unit 15, and displays the analysis result on the display unit 2b (ST8).

Further, the FEC codeword error analysis unit 16b analyzes the FEC codeword error occurrence status based on the detection result of the FEC symbol error detection unit 15, and displays and outputs the analysis result on the display unit 2b (ST9).

By the way, the flowchart of FIG. 6 explains the operation of the error detection apparatus 1A when the NRZ signal of the error measurement pattern is input to the device under test W. The PAM4 signal of the error measurement pattern is input to the device under test W. In this case, the error detection device 1B of FIG. 2 is used. In this case, the PAM4 encoder 3b PAM4-encodes the MSB data and LSB data generated by the pattern generator 3a in accordance with the setting of the operation unit 2, and inputs the PAM4 signal of the error measurement pattern to the device under test W. FIG. The PAM4 signal input as the error measurement pattern is returned by the device under test W and input to the PAM4 decoder 4C of the error detector 4 . The PAM4 decoder 4C decodes the PAM4 signal into MSB data and LSB data, inputs the MSB data to the MSB error detector 4A, and inputs the LSB data to the LSB error detector 4B. Then, in the MSB error detector 4A, the same processing as the bit string of the NRZ signal by the error detector 4 is performed on the bit string of the MSB data, and in the LSB error detector 4B, the NRZ signal by the error detector 4 is processed. The same processing as for the bit string is performed for the LSB data bit string.

In this way, the error detection devices 1A and 1B divide the input pattern and the reference pattern into arbitrary units and positions, compare the patterns in those units, and calculate the presence/absence of errors in each unit. Since this is the same process as the determination of the presence or absence of errors in FEC symbol units, the same results (number of FEC symbol errors and FEC code calculation of the number of word errors) can be performed in any pattern. Moreover, since the arbitrary pattern used for error measurement is a random pattern, there is little pattern-dependent difference.

Then, according to the present embodiment described above, by using a known pattern such as a PRBS pattern that is generally used for error measurement, it is possible to grasp the occurrence status of FEC symbol errors and FEC codeword errors. It becomes possible. As a result, the error rate after error correction can be estimated without using FEC-encoded patterns, and the difficulty and cost of constructing a test system can be reduced.

Although the best mode of the error detection device and error detection method according to the present invention has been described above, the present invention is not limited by the description and drawings according to this mode. In other words, it goes without saying that other forms, embodiments, operation techniques, etc. made by persons skilled in the art based on this form are all included in the scope of the present invention.

1A, 1B error detection device 2 operation unit 2a setting unit 2b display unit 3 pattern generator 3a pattern generation unit 3b PAM4 encoder 4 error detector 4A MSB error detector 4B LSB error detector 4C PAM4 decoder 11 reference pattern generation unit 11A 1 reference pattern generator 11B second reference pattern generator 12 timing generator 12A first timing generator 12B second timing generator 13 input pattern boundary generator 13A first input pattern boundary generator 13B second input pattern boundary generator 14 reference pattern boundary generator 14A first reference pattern boundary generator 14B second reference pattern boundary generator 15 FEC symbol error detector 15A first FEC symbol error detector 15B second FEC Symbol error detection section 16 Error analysis section 16A First error analysis section 16B Second error analysis section 16Aa, 16Ba FEC symbol error analysis section 16Ab, 16Bb FEC codeword error analysis section W DUT

Claims (2)

Error detection in which an error detector (4) detects an input pattern error that is returned when an error measurement pattern generated by a known PAM4 signal is generated by a pattern generator (3) and input to the device under test (W). A device (1B),
A setting unit (2a) for setting the sizes of FEC symbols and FEC codewords and the threshold value of the number of FEC symbol errors in one FEC codeword,
The error detector is
a PAM4 decoder (4C) for decoding the input pattern of the PAM signal returned from the device under test into most significant bit string data and least significant bit string data;
an MSB error detector (4A) for detecting errors in the most significant bit string data;
an LSB error detector (4B) for detecting an error in the least significant bit string data;
The MSB error detector is
a first reference pattern generator (11A) for generating a reference pattern having the same pattern as the most significant bit string data of the error measurement pattern so as to have the same phase as the most significant bit string data;
generating a timing signal for dividing the most significant bit string data and the bit string of the reference pattern generated by the first reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; 1 timing generator (12A);
a first input pattern boundary generation unit (13A) that divides the bit string of the most significant bit string data into units of the FEC symbol and the FEC code word by the timing signal generated by the first timing generation unit;
a first reference that divides the bit string of the reference pattern generated by the first reference pattern generation unit into units of the FEC symbol and the FEC codeword according to the timing signal generated by the first timing generation unit; a pattern boundary generator (14A);
A first FEC for detecting an FEC symbol error by comparing the most significant bit string data from the first input pattern boundary generator and the reference pattern from the first reference pattern boundary generator in units of the FEC symbols. a symbol error detector (15A);
Based on the detection result of the first FEC symbol error detection unit, whether the occurrence status of the FEC symbol error and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword a first error analysis unit (16A) that analyzes the occurrence status of FEC codeword errors depending on whether
The LSB error detector is
a second reference pattern generator (11B) for generating a reference pattern having the same pattern as the least significant bit string data of the error measurement pattern so as to have the same phase as the least significant bit string data;
generating a timing signal for dividing the least significant bit string data and the bit string of the reference pattern generated by the second reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; 2 timing generator (12B);
a second input pattern boundary generation unit (13B) that divides the bit string of the least significant bit string data into units of the FEC symbol and the FEC code word by the timing signal generated by the second timing generation unit;
a second reference that divides the bit string of the reference pattern generated by the second reference pattern generation unit into units of the FEC symbol and the FEC codeword according to the timing signal generated by the second timing generation unit; a pattern boundary generator (14B);
second FEC for detecting an FEC symbol error by comparing the least significant bit string data from the second input pattern boundary generator and the reference pattern from the second reference pattern boundary generator in units of the FEC symbol; a symbol error detector (15B);
Whether the FEC symbol error occurrence status and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword based on the detection result of the second FEC symbol error detection unit and a second error analysis unit (16B) for analyzing the occurrence status of FEC codeword errors depending on whether or not the error detection device is characterized. Error detection in which an error detector (4) detects an input pattern error that is returned when an error measurement pattern generated by a known PAM4 signal is generated by a pattern generator (3) and input to the device under test (W). a method,
a step of setting the size of FEC symbols and FEC codewords and the threshold value of the number of FEC symbol errors in one FEC codeword in a setting unit (2a);
a step of decoding the input pattern of the PAM signal returned from the device under test into the most significant bit string data and the least significant bit string data with a PAM4 decoder (4C);
generating a reference pattern having the same pattern as the most significant bit string data of the error measurement pattern in a first reference pattern generator (11A) so as to be in phase with the most significant bit string data;
a timing signal for dividing the most significant bit string data and the bit string of the reference pattern generated by the first reference pattern generation unit into units of FEC symbols and FEC codewords set by the setting unit; a step of generating by the timing generation unit (12A);
A first input pattern boundary generation unit (13A) divides the bit string of the most significant bit string data into units of the FEC symbol and the FEC codeword according to the timing signal generated by the first timing generation unit. a step;
The bit string of the reference pattern generated by the first reference pattern generation unit is converted to the FEC symbol by the first reference pattern boundary generation unit (14A) using the timing signal generated by the first timing generation unit. , partitioning into units of the FEC codeword;
The most significant bit string data from the first input pattern boundary generation unit and the reference pattern from the first reference pattern boundary generation unit are processed by the first FEC symbol error detection unit (15A) in units of the FEC symbols. comparing to detect FEC symbol errors;
Based on the detection result of the first FEC symbol error detection unit, whether the occurrence status of the FEC symbol error and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword a step of analyzing the occurrence status of the FEC codeword error by the first error analysis unit (16A) depending on whether or not;
a step of generating a reference pattern having the same pattern as the least significant bit string data of the error measurement pattern in a second reference pattern generator (11B) so as to have the same phase as the least significant bit string data;
a second timing signal for dividing the least significant bit string data and the bit string of the reference pattern generated by the second reference pattern generator into units of FEC symbols and FEC codewords set by the setting unit; a step of generating by a timing generation unit (12B);
A second input pattern boundary generation unit (13B) divides the bit string of the least significant bit string data into units of the FEC symbol and the FEC codeword according to the timing signal generated by the second timing generation unit. a step;
The bit string of the reference pattern generated by the second reference pattern generator is generated by the second reference pattern boundary generator (14B) according to the timing signal generated by the second timing generator (14B). , partitioning into units of the FEC codeword;
The least significant bit string data from the second input pattern boundary generation section and the reference pattern from the second reference pattern boundary generation section are processed by the second FEC symbol error detection section (15B) in units of the FEC symbols. comparing to detect FEC symbol errors;
Whether the FEC symbol error occurrence status and the number of FEC symbol errors in one FEC codeword exceed the threshold of the number of FEC symbol errors in the one FEC codeword based on the detection result of the second FEC symbol error detection unit A second error analysis unit (16B) analyzes the occurrence status of FEC codeword errors depending on whether or not an error is detected.

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