JP2022158717A - Semiconductor element, semiconductor integrated circuit, and manufacturing method for semiconductor element - Google Patents

Abstract

To provide a smaller semiconductor element that can be manufactured easily at low cost and can obtain large on current, a semiconductor integrated circuit, and a manufacturing method for the semiconductor element.SOLUTION: A semiconductor element 10 includes an element structure of a tunnel field effect transistor. A channel part 13 formed of an indirect transition type semiconductor is configured as a plate-shaped part having one end connected to a source part 14 and the other end connected to a drain part 15. At least a pair of opposing surfaces among two pairs of first opposing surfaces and second opposing surfaces which form the channel part 13 and oppose each other in directions orthogonal to a direction where current flows from the source part 14 to the drain part 15 is formed so that electron confinement surfaces that a direct transition type semiconductor band structure can provide in a pseudo manner to the indirect transition type semiconductor by the restriction of electron movement are disposed with a space of 15 nm therebetween at maximum.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device having a device structure of a tunnel field effect transistor, a semiconductor integrated circuit, and a method of manufacturing the semiconductor device.

In recent years, many attempts have been made to reduce the power consumption of LSIs. Reducing the operating voltage is one such attempt, but with the MOS transistors used in conventional circuits, it is difficult to significantly lower the voltage due to physical limitations. Therefore, in order to reduce the power consumption of LSI, development of a low voltage switching device based on a different operating principle is desired.

A tunnel field effect transistor that utilizes the band-to-band tunneling phenomenon of a semiconductor is one of them, and utilizes the tunneling phenomenon as an operation principle different from that of the MOS transistor. The band-to-band tunneling phenomenon is a phenomenon in which even electrons with an energy that does not cross a potential barrier pass through the barrier with a certain probability. A barrier due to this potential is called a tunnel barrier.

The tunnel field effect transistor can control the speed at which electrons pass through the tunnel barrier, that is, the magnitude of the tunnel current, by the gate voltage, and can operate at a voltage lower than that of the MOS transistor. A prototype has been reported (see, for example, Non-Patent Document 1).
However, in the prototype, the tunnel resistance that defines the current amount of the tunnel current is large, so there is a problem that the current in the ON state (ON current) is small.
Regarding this problem, it is conceivable to simply increase the area of the tunnel junction portion forming the tunnel barrier, that is, the area where the band-to-band tunneling phenomenon occurs, thereby increasing the current per element even at a low current density. Such a configuration increases the size of the device, making it an impractical device unsuitable for forming an integrated circuit. In order to obtain a highly integrated practical integrated circuit, miniaturization of elements is required.

By the way, there are two types of semiconductor materials for manufacturing the tunnel field effect transistor: direct transition semiconductors and indirect transition semiconductors. The former mainly corresponds to compound semiconductors, and the latter mainly corresponds to Group IV semiconductors.
Since the probability of occurrence of the band-to-band tunneling phenomenon is generally higher in the direct transition semiconductor than in the indirect transition semiconductor, the use of the compound semiconductor is considered effective for increasing the on-current. (See Non-Patent Document 2).
However, in the method using the compound semiconductor, most of the existing semiconductor device manufacturing equipment cannot be used for manufacturing the tunnel field effect transistor, so there is a problem that new equipment investment is required and the manufacturing cost increases. .

On the other hand, representative materials of the group IV semiconductor are silicon and germanium, and although the tunnel field effect transistor can be manufactured using existing semiconductor device manufacturing equipment, the probability of occurrence of the band-to-band tunneling phenomenon is high. is low, and there still remains the problem of increasing the on-current.
In response to this problem, the present inventors have reported a tunnel field effect transistor in which an on-current is increased by introducing an isoelectronic trap-forming impurity into the indirect transition semiconductor (see Patent Document 1). .
The technique of introducing this isoelectronic trap-forming impurity is also one of the techniques for solving the problem.

As another method, it has been reported that the on-current is increased by introducing a silicon nanowire structure obtained by processing silicon into a wire shape having a diameter of about 3 nm (see Non-Patent Document 3). In this report, it is also reported that silicon, which is originally an indirect transition type semiconductor, is converted into a pseudo direct transition type by adopting the silicon nanowire structure.
However, the silicon nanowires with a diameter of 3 nm are difficult to process, leading to increased manufacturing costs. In particular, the cross section of the silicon nanowires is perfectly circular, and the gate electrode is arranged to uniformly cover the entire periphery of the silicon nanowires, which increases the difficulty of the processing process and increases the manufacturing cost. is significant.

Japanese Patent No. 6253034

W. Y. Choi et al., IEEE Electron Device Letters vol.28, p743(2007), “Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60mV/dec” G. Dewey et al., 2011 International Electron Devices Meeting Technical Digest, 33.6, "Fabrication, characterization, and physics of III-V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing" Mathieu Luisier et al., Journal of Applied Physics vol.107, p.084507 (2010), "Simulation of nanowire tunneling transistors: From the Wentzel-Kramers-Brillouin approximation to full-band phonon-assisted tunneling"

An object of the present invention is to solve the above-mentioned conventional problems and to achieve the following objects. That is, an object of the present invention is to provide a semiconductor element, a semiconductor integrated circuit, and a method of manufacturing the semiconductor element which are small, can be manufactured easily and at low cost, and can provide a large on-current.

Means for solving the above problems are as follows. Namely
<1> In a semiconductor element having an element structure of a tunnel field effect transistor, a channel portion formed of an indirect transition semiconductor has a plate-shaped portion having one end connected to a source portion and the other end connected to a drain portion. and two of the first opposing surfaces and the second opposing surfaces, which constitute the plate-shaped portion, facing each other in a direction orthogonal to the direction in which the current flows from the source portion to the drain portion. At least one pair of the opposing surfaces among the pairs of opposing surfaces has an elongated electron confinement surface in which a pseudo direct transition semiconductor band structure can be imparted to the indirect transition semiconductor by regulation of electron motion. A semiconductor device characterized in that both are arranged at a facing distance of 15 nm.
<2> The semiconductor device according to <1> above, wherein all of the four surfaces constituting the first opposing surfaces and the second opposing surfaces are electron confining surfaces.
<3> The gate portion constituting the device structure of the tunnel field effect transistor covers all or part of at most three of the four surfaces constituting the first opposing surfaces and the second opposing surfaces. The semiconductor device according to any one of <1> to <2> above.
<4> The semiconductor device according to any one of <1> to <3>, wherein the indirect transition semiconductor is silicon and the electron confinement plane is a {100} plane.
<5> The semiconductor device according to any one of <1> to <3>, wherein the indirect transition semiconductor is germanium and the electron confinement plane is a {111} plane.
<6> The indirect transition semiconductor is a mixed crystal of silicon and germanium, the electron confinement plane is a {100} plane when the germanium content is less than 85 atomic percent, and the germanium content is 85 atoms. % or more, the electron confinement plane is a {111} plane.
<7> The semiconductor device according to any one of <1> to <6>, wherein the tunnel junction formed in the tunnel field effect transistor is composed of a semiconductor junction.
<8> The semiconductor device according to any one of <1> to <6>, wherein the tunnel junction formed in the tunnel field effect transistor is a Schottky junction.
<9> A semiconductor integrated circuit comprising the semiconductor element according to any one of <1> to <8>.
<10> The method for manufacturing a semiconductor device according to any one of <1> to <8>,
A channel portion having a plate-shaped portion, one end of which is connected to a source portion and the other end of which is connected to a drain portion, is formed by an indirect transition type semiconductor, and the plate-shaped portion is formed from the source portion to the drain portion. At least one of the two sets of opposing surfaces, that is, the first opposing surfaces and the second opposing surfaces facing each other in the direction orthogonal to the direction in which the current flows toward the A semiconductor characterized by comprising a channel portion forming step of forming electron confining surfaces capable of imparting a pseudo-direct band structure to an indirect band semiconductor at an opposing interval of at most 15 nm. A method for manufacturing an element.

According to the present invention, a semiconductor element, a semiconductor integrated circuit, and a method for manufacturing the semiconductor element that can solve the above-mentioned problems in the prior art, can be manufactured in a small size, can be manufactured easily and at low cost, and can obtain a large on-current. can be provided.

FIG. 4 is a diagram showing energy bands of an indirect bandgap semiconductor in the bulk state; FIG. 10 is a diagram showing an energy band of an indirect bandgap semiconductor which is pseudo direct bandgap semiconductor; FIG. 4 is an explanatory diagram for explaining how an indirect transition semiconductor is pseudo-direct transition semiconductor; FIG. 4 is a diagram schematically showing how a tunnel current increases, taking an N-type tunnel field effect transistor as an example; 1 is an exploded perspective view of a semiconductor device according to a first embodiment; FIG. 5 is a cross-sectional view in a direction (X direction in FIG. 4) orthogonal to the direction of current flow; FIG. FIG. 5B is a cross-sectional view taken along line AA in a direction (Y direction in FIG. 4) parallel to the direction of current flow in FIG. 5A; FIG. 3 is a diagram showing isoenergetic surfaces near the bottom of the conduction band of silicon in a bulk state; It is a figure which shows the isoenergetic surface near the bottom of the conduction band of germanium in a bulk state. FIG. 8 is an exploded perspective view of a semiconductor device according to a second embodiment; FIG. 8 is a cross-sectional view in a direction (X direction in FIG. 7) orthogonal to the direction of current flow; 8A is a cross-sectional view taken along line AA in a direction (Y direction in FIG. 7) parallel to the direction of current flow in FIG. 8A. FIG. It is a figure (1) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. FIG. 9A is a diagram (1) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. 9A. It is a figure (2) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. FIG. 10B is a diagram (2) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. 10A. It is a figure (3) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. 11(a) is a cross-sectional view taken along the line AA of FIG. 11(a). FIG. It is a figure (4) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. 12A is a cross-sectional view taken along the line AA of FIG. 12A, showing the manufacturing process of the semiconductor device 10 according to the first embodiment; FIG. It is a figure (5) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. FIG. 5 is a diagram (5) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. 13(a). It is a figure (6) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. FIG. 6 is a diagram (6) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. 14(a). It is a figure (7) which shows the manufacturing process of the semiconductor element 10 which concerns on 1st Embodiment. FIG. 7 is a diagram (7) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. 15(a). FIG. 4 is a diagram showing an overview of a method of forming a channel portion using an SOI substrate having a (100) plane as a principal surface; FIG. 10 is a diagram showing an overview of a method of forming a channel portion using a GOI substrate having a (110) plane as a principal surface; FIG. 11 is a diagram (1) showing a manufacturing process of the semiconductor device of the present invention related to the semiconductor device 20 according to the second embodiment; FIG. 17(a) is a diagram (1) showing a manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment, and is a cross section taken along the line AA of FIG. 17(a). It is a figure (2) which shows the manufacturing process of the said semiconductor element of this invention related to the semiconductor element 20 which concerns on 2nd Embodiment. FIG. 18B is a diagram (2) showing the manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment, and is a cross section taken along the line AA of FIG. 18(a). FIG. 13 is a diagram (3) showing a manufacturing process of the semiconductor device of the present invention related to the semiconductor device 20 according to the second embodiment; FIG. 19(3) is a diagram (3) showing a manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment, and is a cross section taken along the line AA of FIG. 19(a). It is a figure which shows the energy band structure of bulk silicon. FIG. 4 is a diagram showing the energy band structure of plate-like silicon with a thickness of about 1.1 nm. It is a figure which shows the correlation between the energy band structure of silicon, and a silicon film thickness. FIG. 3 is an explanatory diagram for explaining the configuration of a thinned TFET that is the target of a simulation test; FIG. 4 is a diagram showing simulation test results of band-to-band tunneling current; FIG. 10 is a diagram showing a scanning electron microscope image of a semiconductor device according to Example 4 taken from above; FIG. 10 is a diagram showing switching characteristics of a semiconductor device according to Example 4; FIG. 4 is a diagram showing the relationship between tunnel current and Fin width; FIG. 4 is a diagram showing the relationship between tunnel current density and Fin width;

(Semiconductor element and its manufacturing method)
The semiconductor element of the present invention has an element structure of a tunnel field effect transistor, and a channel portion formed of an indirect transition semiconductor is a plate-shaped portion having one end connected to a source portion and the other end connected to a drain portion. and constituting the plate-shaped portion, first opposing surfaces and second opposing surfaces facing each other in a direction orthogonal to a direction in which current flows from the source portion to the drain portion At least one of the two pairs of opposing surfaces of (1) is formed with the electron confining surfaces arranged at an interval of 15 nm at the longest.

A method of manufacturing a semiconductor element of the present invention is a method of manufacturing the semiconductor element of the present invention, wherein the indirect transition semiconductor has one end connected to the source portion and the other end connected to the drain portion. The first opposing surfaces forming the channel portion having the plate-shaped portion and constituting the plate-shaped portion are opposed to each other in a direction perpendicular to a direction in which current flows from the source portion to the drain portion. and a channel portion forming step of forming at least one pair of the opposing surfaces of the two pairs of the second opposing surfaces with the electron confining surfaces arranged at an opposing interval of at most 15 nm. characterized by

With these characteristics, the behavior of electrons confined in the electron confinement surface is controlled in the plate-shaped portion formed of the indirect transition semiconductor in the same manner as in the direct transition semiconductor, and the semiconductor element tunnels. Increase current. In addition, the semiconductor device can be made small by forming the channel portion through which the tunnel current flows so as to have the plate-shaped portion that can be manufactured in a small size, easily, and at low cost while using existing manufacturing equipment. To enable simple and low-cost manufacturing.

A mechanism for increasing the tunnel current will be described in detail.
A characteristic feature of the indirect bandgap semiconductor is that the momentum at the top end of the valence band does not match the momentum at the bottom end of the conduction band.
That is, as shown in FIG. 1A, the momentum of electrons at the top end of the valence band is zero, whereas the momentum of electrons at the bottom end of the conduction band is not zero. In other words, there is a momentum difference between electrons at the top end of the valence band and electrons at the bottom end of the conduction band. FIG. 1(a) is a diagram showing energy bands of the indirect bandgap semiconductor in a bulk state.
The state transition of electrons from the valence band to the conduction band accompanying interband tunneling must satisfy the law of conservation of momentum. In the tunnel field effect transistor used, it is difficult to obtain a large tunnel current.

However, by converting the indirect transition semiconductor into a pseudo direct transition semiconductor, the tunnel current can be increased even in the tunnel field effect transistor using the indirect transition semiconductor, and A configuration required for this purpose is a configuration in which the plate-shaped portion is provided to the channel portion.
In the plate-shaped portion, (1) two sets of opposing surfaces, ie, first opposing surfaces and second opposing surfaces facing each other in a direction perpendicular to the direction in which current flows from the source portion to the drain portion, and (2) the electron confinement surfaces are arranged at an extremely short interval of 15 nm at the longest. , the indirect transition type semiconductor is pseudo-direct transition type semiconductor.
That is, as shown in FIG. 1(b), the plate-shaped portion that satisfies the above two conditions loses the above-mentioned characteristic features of the indirect bandgap semiconductor, and the valence band uppermost end and the conduction band lowermost end are lost. The momentum of the electrons at becomes zero. In addition, FIG.1(b) is a figure which shows the energy band of the said indirect transition semiconductor made into a pseudo direct transition semiconductor.

This state will be described with reference to FIG.
As shown in the example of FIG. 2, when the distance between the electron confinement surfaces facing each other is shortened, that is, when the thickness of the plate-like indirect transition semiconductor 1 in the _kx direction is decreased, the electron narrow region When this thickness becomes 15 nm or less, the momentum of electrons in the _kx direction is lost. Therefore, a state occurs in which the momentum of electrons at the highest end of the valence band and the lowest end of the conduction band is zero (transition state of the direct bandgap semiconductor). At this time, the indirect transition semiconductor 1 is arranged in a direction in which the direction in which the current flows from the source portion to the drain portion is parallel to the _{ky direction} (or _{kz direction} ). If the opposing surfaces facing each other in the _kx direction orthogonal to and are composed of the electron confinement surfaces, the restriction due to the law of conservation of momentum is relaxed, and the tunneling probability of electrons directly transitioning from the valence band to the conduction band is increased. and a large tunnel current is obtained. Hereinafter, the effect of obtaining a large tunnel current based on the control of electron motion is referred to as a "convolution effect", following the manner in which electrons are convoluted into local positions according to the thickness.
FIG. 2 is an explanatory diagram for explaining how the indirect transition semiconductor is pseudo-direct transition semiconductor.

As a physical phenomenon suggesting that the indirect bandgap semiconductor becomes a pseudo direct bandgap semiconductor by thinning the indirect bandgap semiconductor, there is a light emission phenomenon from the indirect bandgap semiconductor. Originally, it is not possible to obtain large light emission from the indirect bandgap semiconductor, but it is known that the light emission intensity increases exponentially by making the layer thinner (see Reference Document 1 below).
This is because the indirect transition semiconductor becomes a pseudo-direct transition semiconductor, and electron-hole pairs are easily recombined at the point of zero momentum.
Reference 1: Japanese Patent Laid-Open No. 2007-294628

Although the luminescence phenomenon and the band-to-band tunneling phenomenon are different phenomena, in the present invention, a tunnel electric field utilizing the band-to-band tunneling phenomenon is used to create a pseudo direct bandgap semiconductor by thinning the indirect bandgap semiconductor. Applies to effect transistors. By satisfying the two conditions described above for the plate-shaped portion, an effect of increasing the tunnel current in the tunnel field effect transistor can be obtained.
FIG. 3 is a diagram schematically showing how the tunnel current increases, taking an N-type tunnel field effect transistor as an example.
As shown in the example of FIG. 3, when passing through the tunnel barrier of the tunnel junction 2 formed between the p ⁺ source region and the n-type channel region in the plate-shaped indirect transition semiconductor 1′, the plate-shaped In the indirect bandgap semiconductor 1', due to the convolution effect, a state in which the momentum of electrons at the top of the valence band and the bottom of the conduction band is both zero occurs, the restriction by the law of conservation of momentum is relaxed, and the tunnel probability increases. do.
Next, each configuration in the semiconductor device of the present invention will be described in detail.

<Device Structure of Tunnel Field Effect Transistor>
The device structure of the tunnel field effect transistor includes the source portion, the channel portion adjacent to the source portion and having a boundary thereof as the tunnel junction where the tunnel barrier is formed, and the channel portion. The drain portion is arranged adjacent to the drain portion, and the gate portion is arranged so as to cover the whole or part of the exposed portion of the channel portion.
The semiconductor element of the present invention has the above-described characteristics in the more specific structure of the channel portion in the element structure.

<Source part and drain part>
The source portion and the drain portion are formed in the same manner as known source and drain regions formed by introducing impurities into a semiconductor, or known source and drain electrodes made of a metal material.

When the source region and the drain region are formed as the source region and the drain region, the source region is formed of a first conductivity type that is either a P-type or an N-type conductivity type, and the drain region is is formed of a second conductivity type which is the conductivity type different from the first conductivity type. Further, the source region forms a semiconductor junction constituted by a junction between semiconductors with the channel portion formed of the indirect transition semiconductor, and the tunnel junction is constituted by the semiconductor junction.
A method for forming the tunnel junction in the semiconductor junction is not particularly limited, and a known method such as providing a steep concentration profile of an impurity substance between the source region and the channel portion can be used.
The semiconductor forming the source region and the drain region is not particularly limited as long as it is a material capable of forming a tunnel junction with the channel portion, and known semiconductor materials can be applied. It is preferable that the channel portion is made of the same semiconductor material as the indirect transition semiconductor that constitutes the channel portion. That is, in this case, a typical manufacturing method can be applied in which the impurity is doped into one semiconductor substrate by ion implantation or the like to form the source region and the drain region.
Further, the impurities are not particularly limited, and known impurities such as boron, phosphorus, arsenic, etc. can be used.
When the semiconductor element is operated as a P-type tunnel field effect transistor, the source region is configured as an N-type (N ⁺ ) semiconductor region, and the drain region is configured as a P-type (P ⁺ ) semiconductor region. Conversely, when the semiconductor element is operated as an N-type tunnel field effect transistor, the source region is configured as a P-type (P ⁺ ) semiconductor region and the drain region is configured as an N-type (N ⁺ ) semiconductor region. .

When the source and drain portions are formed as the source and drain electrodes, a tunnel junction is formed by joining the source electrode and the channel portion with a Schottky junction.
The source electrode and the drain electrode are not particularly limited, and may be a known metal material. For example, when the channel portion is made of silicon, metal silicide such as NiSi ₂ may be used. When the channel portion is made of germanium, a metal germanide such as NiGe can be used, and when the channel portion is made of a mixed crystal of silicon and germanium, an alloy of NiSi and NiGe, etc. Ni, Si, and alloys containing Ge can be mentioned.
Also, the method for forming the source electrode and the drain electrode is not particularly limited, and known forming methods such as a sputtering method and a CVD method using the metal material can be mentioned.

<Channel part>
As described above, the channel portion is formed of the indirect transition semiconductor and has the plate-shaped portion having one end connected to the source portion and the other end connected to the drain portion. .
Based on the two conditions described above, the plate-shaped portion has the first opposing surfaces facing each other in a direction orthogonal to the direction in which the current flows from the source portion to the drain portion. And at least one set of the two pairs of opposing surfaces of the second opposing surfaces is formed with the electron confining surfaces arranged at an interval of 15 nm at the longest.

The plate-shaped portion may be a portion existing in the channel portion. may constitute a part. Since the band-to-band tunneling phenomenon occurs when electrons pass through the tunnel junction formed between the source region and the channel portion, the entire channel portion including the portion not involved in the tunnel junction is thinned. It doesn't have to be.
Further, as the plate-shaped portion, the channel portion may be formed by one plate-shaped portion, or the channel portion may be formed by a plurality of plate-shaped portions.

When all the four planes forming the first opposing planes and the second opposing planes are composed of the electron confining planes, the restriction by the law of conservation of momentum is further relaxed, and the tunneling probability is further increased. can be increased.
In addition, both the first opposing surfaces and the second opposing surfaces formed by the electron confinement surfaces are formed by arranging the electron confinement surfaces at an opposing interval of 15 nm at the longest. , the restriction by the law of conservation of momentum is further relaxed, and the tunnel probability can be further increased.

The electron confinement plane is a plane that allows the band structure of the direct bandgap semiconductor to be artificially given to the indirect bandgap semiconductor by regulation of electron motion, and differs depending on the type of the indirect bandgap semiconductor. The electron confinement plane can be described by the crystal plane for each type of the indirect transition semiconductor.
Specifically, from the band structure peculiar to the bulk material illustrated in FIG. 1A, it is determined for each type of the indirect transition semiconductor. , and germanium, the {111} plane corresponds to the electron confinement plane. In the case of the mixed crystal of silicon and germanium, the {100} plane corresponds to the electron confinement plane if the germanium content is less than 85 atomic %, and the germanium content is 85 atomic % or more. , the {111} plane corresponds to the electron confinement plane.

The spacing between the facing surfaces (the electron confinement surfaces) for obtaining the convolution effect is not particularly limited as long as it is 15 nm or less. The following is preferable, 8 nm or less is more preferable, 6 nm or less is more preferable, and 4 nm or less is particularly preferable. The lower limit is about 1 nm from the viewpoint of reducing the amount of current due to the surface roughness of the channel portion.

The method of forming the channel portion is not particularly limited, and can be appropriately selected from among the forming methods in existing semiconductor facilities. mentioned.
Further, the channel portion may be formed of the indirect transition semiconductor, and it is preferable to use a single crystal structure of the material for forming the channel portion, an intrinsic semiconductor, or a material doped with the impurity at a low concentration. can.

<Gate part>
The gate portion is a portion configured such that a gate electrode covers all or part of the exposed portion of the channel portion with a gate insulating film interposed therebetween.
The material for forming the gate insulating film is not particularly limited and can be appropriately selected according to the purpose. Examples thereof include HfO ₂ , Al ₂ O ₃ and ZrO ₂ .
A method for forming the gate insulating film is not particularly limited and can be appropriately selected according to the purpose.
The material for forming the gate electrode is not particularly limited and can be appropriately selected depending on the purpose. Examples thereof include TiN, TaN, NiSi and the like.
A method for forming the gate electrode is not particularly limited and can be appropriately selected according to the purpose. Examples thereof include ALD, sputtering, and CVD using the forming material.

A specific configuration of the gate portion is not particularly limited and can be appropriately selected according to the purpose. Although it is possible to configure an all-around structure that covers all of the four constituent surfaces forming each other, it is not necessary to cover all of the constituent surfaces, and from the viewpoint of small, simple, and low-cost manufacturing, the first opposing It is preferable to be arranged so as to cover all or part of at most three of the four constituting surfaces constituting the surface and the second opposing surface.

[First embodiment]
A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.
FIG. 4 is an exploded perspective view of the semiconductor device according to the first embodiment. 5A is a cross-sectional view in a direction perpendicular to the direction of current flow (the X direction in FIG. 4), and FIG. FIG. 5 is a cross-sectional view taken along the line AA in the direction (Y direction in FIG. 4);

As shown in FIG. 4, the semiconductor element 10 includes a source portion 14, a channel portion 13 which is arranged adjacent to the source portion 14 and whose boundary is the tunnel junction where the tunnel barrier is formed, and the channel portion 13. and a gate portion G arranged so as to cover all or part of the exposed portion of the channel portion 13, and has the element structure of the tunnel field effect transistor.
As shown in FIGS. 5A and 5B, the semiconductor element 10 is formed on an arbitrary substrate such as an SOI (Silicon-on-insulator) substrate having a surface insulating layer 12 formed on a semiconductor layer 11. However, semiconductor layer 11 and surface insulating layer 12 are optional structures that do not participate in the operation of semiconductor device 10 .

The channel portion 13 is formed of an intrinsic semiconductor or silicon doped with the impurity at a low concentration (for example, about 1×10 ¹³ cm ⁻³ to 1×10 ¹⁶ cm ⁻³ ), and one end thereof is connected to the source portion 14 . It is composed of the plate-shaped portion itself that is connected and the other end is connected to the drain portion 15 .
Two sets of the first opposing surfaces and the second opposing surfaces that constitute the plate-shaped portion of the channel portion 13 and are opposed in a direction orthogonal to the direction in which current flows from the source portion 14 to the drain portion 15 A pair of the opposing surfaces (the opposing surfaces facing each other in the X direction in FIG. 4) among the opposing surfaces are formed of {100} planes of silicon, and constitute the electron confining surfaces. The thickness D ₁ (see FIG. 5A) of the channel part 13 in the X direction in FIG. is configured to obtain

The source region 14 and the drain region 15 are formed by doping silicon with the impurity at a high concentration (for example, about 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ⁻³ ). , and the tunnel junction is composed of the semiconductor junction between the channel portion 13 and the source portion 14 .

The gate portion G is configured such that the gate electrode 17 covers all or part of the exposed portion of the channel portion 13 with the gate insulating film 16 interposed therebetween. is arranged so as to cover three of the four constituent surfaces constituting the . The element structure of the transistor in which the three sides of the plate-shaped channel portion 13 are covered with the gate portion G is known as Fin-FET, and can be suitably manufactured using existing semiconductor equipment.

In this example, the thickness D1 of the channel portion ₁₃ is uniform. Since it occurs in a form passing through, the portion near the tunnel junction extending from one end in contact with the source portion 14 in the channel portion 13 to the other end side in the direction toward the drain portion 15 (the Y direction in FIG. 4) from this one end. The interval between the electron confinement surfaces (thickness D ₁ of the channel portion 13) of the electron confinement surfaces (the portion extending from one end to the other end by about 15 nm at the shortest) is a short interval of 15 nm at the longest, and the neighboring portion In the channel portion 13 closer to the drain portion 15, the facing distance between the electron confining surfaces (the thickness D ₁ of the channel portion 13) may exceed 15 nm.
In this example, the portion of the source portion 14 forming the tunnel junction with the channel portion 13 has the same shape as the plate-shaped portion of the channel portion 13 . That is, the source portion 14 is formed so as to be tapered toward the channel portion 13 side, and the end portion joined to the channel portion 13 is one end, and the portion on the one end side is formed as a plate-shaped portion. Two sets of opposing surfaces, ie, the first opposing surfaces and the second opposing surfaces, which constitute the plate-shaped portion and face each other in a direction orthogonal to the direction in which the current flows from the source portion 14 to the drain portion 15. One pair of the opposing surfaces (the opposing surfaces facing each other in the X direction in FIG. 4) is formed of the {100} plane of silicon, similarly to the plate-shaped portion in the channel portion 13, and the electron constitute the confinement surface. Further, the thickness of the plate-shaped portion in the source portion 14 in the X direction in FIG. The vicinity of the formed tunnel junction (at least, the portion extending about 10 nm from the one end toward the other end in the direction away from the drain portion 15, which is the direction opposite to the direction in which the current flows) has the convolution effect. configured to obtain
When the channel portion 13 and the source portion 14 forming the tunnel junction are configured to obtain the convolution effect in this way, the tunnel probability in the tunnel junction increases, and a larger tunnel current can be obtained. can be done.

In this example, the channel portion 13 is made of silicon. However, when the channel portion 13 is made of germanium, the opposing surfaces (the opposing surfaces facing each other in the X direction in FIG. 4) are each replaced by {111 } plane to constitute the electron confinement plane. When the channel portion 13 is formed of a mixed crystal of silicon and germanium and the germanium content is less than 85 atomic %, the opposing surfaces (the opposing surfaces facing each other in the X direction in FIG. 4) are respectively formed of {100} planes in a mixed crystal of silicon and germanium to form the electron confinement planes. are formed of {111} planes in a mixed crystal of silicon and germanium, respectively, to constitute the electron confining planes.

The reason for this is as follows.
First, FIG. 6A shows an isoenergetic surface near the bottom of the conduction band of bulk silicon. In the case of silicon, the position of the conduction band bottom is not on the zero-momentum point, but on the 6-fold symmetrical <100> axis. Therefore, it is most effective to obtain the convolution effect by thinning in the direction perpendicular to the <100> direction. That is, it is most effective to form the electron confining plane by forming the opposing planes (opposing planes opposing each other in the X direction in FIG. 4) with {100} planes of silicon.
Next, FIG. 6B shows an isoenergy surface near the bottom of the conduction band of germanium in the bulk state. In the case of germanium, the position of the bottom of the conduction band is not on the zero-momentum point, but on the <111> direction axis with 8-fold symmetry. Therefore, it is most effective to obtain the convolution effect by thinning in the direction perpendicular to the <111> direction. That is, it is most effective to form the electron confining plane by forming the opposing planes (opposing planes facing each other in the X direction in FIG. 4) with {111} planes of germanium.
Next, in the case of a mixed crystal of silicon and germanium having a germanium content of less than 85%, the component contributing to silicon is strong when no external stress is applied. It exists on a rotationally symmetrical <100> direction axis. Therefore, as with silicon, the electron confining planes can be formed by forming the opposing planes (opposing planes opposing each other in the X direction in FIG. 4) with {100} planes in a mixed crystal of silicon and germanium. Most effective.
Next, in the case of a mixed crystal of silicon and germanium with a germanium content of 85% or more, since the component contributing to germanium is strong in the state where no external stress is applied, the position of the bottom of the conduction band is similar to germanium. is on the <111> direction axis with 8-fold symmetry. Therefore, as in the case of germanium, the electron confining surfaces can be formed by forming the opposing surfaces (the opposing surfaces facing each other in the X direction in FIG. 4) with {111} planes in a mixed crystal of silicon and germanium. Most effective.
Thus, the electron confinement plane can be defined by determining the crystal orientation that regulates electron motion from the material-specific energy state of the indirect bandgap semiconductor in the bulk state.

As described above, in the semiconductor device 10, at and near the tunnel junction where the band-to-band tunneling phenomenon occurs, the tunneling probability of electrons passing through the tunnel junction is improved by the convolution effect to the same level as that of the direct transition semiconductor, and tunneling occurs. Current can be increased. In addition, by utilizing the existing manufacturing equipment for the indirect transition semiconductor, it is possible to manufacture the device in a small size, simply, and at low cost.

As a modification of the first embodiment, when the source electrode and the drain electrode are arranged and the source electrode and the channel portion are joined by the Schottky junction to form the tunnel junction, the source in the semiconductor element 10 The portion 14 and the drain portion 15 may be composed of the source electrode and the drain electrode, and the source electrode and the channel portion 13 may be joined by the Schottky junction to form the tunnel junction.

[Second embodiment]
A semiconductor device according to a second embodiment of the present invention will be described below with reference to the drawings.
FIG. 7 is an exploded perspective view of a semiconductor device according to the second embodiment. 8A is a cross-sectional view in a direction orthogonal to the direction of current flow (X direction in FIG. 7), and FIG. 8B is a cross-sectional view in parallel with the direction of current flow in FIG. 8 is a cross-sectional view taken along the line AA in the direction (Y direction in FIG. 7); FIG.

As shown in FIG. 7, the semiconductor element 20 includes a source portion 24, channel portions 23a to 23c arranged adjacent to the source portion 24 and whose boundaries are the tunnel junctions where the tunnel barriers are formed, and channel portions 23a to 23c. The drain portion 25 arranged adjacent to the portions 23a to 23c, and the gate portion G arranged so as to cover all or part of the exposed portions of the channel portions 23a to 23c, and the It has an element structure.
As shown in FIGS. 8A and 8B, the semiconductor element 20 can be formed on any substrate such as an SOI substrate in which a surface insulating layer 22 is formed on a semiconductor layer 21. , the semiconductor layer 21 and the surface insulating layer 22 are optional structures that do not participate in the operation of the semiconductor device 20 .

The semiconductor element 20 according to the second embodiment differs structurally from the semiconductor element 10 according to the first embodiment in that the channel portion 13 is composed of channel portions 23a to 23c. Differences will be described below.

Each of the channel portions 23a to 23c is formed of the indirect transition semiconductor, and is composed of the plate-shaped portion itself having one end connected to the source portion 24 and the other end connected to the drain portion 25. As shown in FIG.
Two sets of the first opposing surfaces and the second opposing surfaces that constitute the plate-shaped portion of the channel portion 23a and are opposed in a direction perpendicular to the direction in which current flows from the source portion 24 to the drain portion 25. At least one set of the opposing surfaces (the opposing surfaces facing each other in the Z direction in FIG. 7) constitutes the electron confinement surface. The thickness D ₂ (see FIG. 8A) of the channel portion 23a in the Z direction in FIG. 7, which determines the facing distance between these electron confinement surfaces, is 15 nm at the longest. is configured to obtain
The channel portions 23b and 23c each have the same structure as the channel portion 23a and are arranged side by side with the channel portion 23a.
That is, in the semiconductor device 20, a plurality of the plate-shaped portions that provide the convolution effect are arranged to obtain a larger tunnel current than a single plate-shaped portion.
The thinning of the channel portions 23a to 23c for obtaining the convolution effect provides room for forming a plurality of the plate-shaped portions in the same formation region as in the case of forming the channel portions in bulk.
From this point of view, the channel portions 23b and 23c are arranged such that the distance between the opposing surfaces in the channel portion 23a is 15 nm at the longest, and the direction in which the opposing surfaces formed by the electron confinement surfaces are opposed to each other (see FIG. 7). Z direction), it is preferably the plate-shaped portion itself (or the channel portion having the plate-shaped portion) arranged side by side with the channel portion 23a.

The channel portions 23a to 23c configured in this manner are covered with the gate insulating films 26a to 26c in the entire exposed portions except for the connection surfaces with the source portion 24 and the drain portion 25, respectively, and the gate insulating films 26a to 26c. is covered with the gate electrode 27 via the .
In this example, both the channels 23b and 23c arranged side by side with the channel part 23a are configured to obtain the convolution effect, but only one of them is configured to obtain the convolution effect. may be
In addition, the matters described for the semiconductor device 10 according to the first embodiment can be applied to matters other than this.

Next, an example of the method for manufacturing the semiconductor element of the present invention will be described with reference to the drawings.
9 to 15 are diagrams (1) to (7) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and (b) of each diagram is a cross-sectional view taken along the line AA in (a). be.

First, on a Si semiconductor layer 11 for a handle, a SiO ₂ surface insulating layer (BOX layer) 12 having a thickness of 145 nm and an SOI layer 13' having a thickness of 50 nm made of Si are formed in this order on an SOI substrate. Prepare (see FIGS. 9(a) and (b)). The SOI layer 13' is doped with a p-type impurity of about 1.times.10.sup.15 ^{cm.sup. -3} .
Next, after forming an etching mask 101 with a thickness of 65 nm at a predetermined position on the SOI layer 13' by electron beam lithography, reactive ion etching (RIE) is performed using the etching mask 101 as a mask to shape the SOI layer 13'. are processed into the shapes of the channel portion 13, the source portion 14 and the drain portion 15 (see FIGS. 10A and 10B). Plasma in the reactive ion etching (RIE) includes plasma of hydrogen bromide (HBr), mixed plasma of hydrogen bromide (HBr) and chlorine (Cl ₂ ), and hydrogen bromide (HBr) and argon (Ar). A mixed plasma or the like with is used.
Next, after removing the etching mask 101, a SiO ₂ protective oxide film 102 having a thickness of 4 nm is formed on the surface of the SOI layer 13' for subsequent ion implantation (see FIGS. 11A and 11B).

Next, a resist layer 103 having a thickness of 100 nm is formed on the protective oxide film 102 by ^electron beam ^lithography . ₂ to form a drain portion 15 as the drain region in the SOI layer 13' (see FIGS. 12A and 12B).
Next, the resist layer 103 is removed by oxygen ashing, and the surface is cleaned with SPM (Sulfuric Acid Peroxide Mixture). In the SPM cleaning, a mixture of H ₂ SO ₄ and H ₂ O ₂ at a ratio of 3:1 is used as a cleaning liquid.
Next, a resist layer 104 having a thickness of 100 nm is formed on the SPM-cleaned protective oxide film 102. Using this resist layer 104 as a mask, As is doped at an acceleration energy of 5 keV and a dose of 2×10 ¹⁵ cm ⁻² . A source portion 14 as the source region is formed in the SOI layer 13' by ion implantation using a silicon oxide (see FIGS. 13A and 13B).
A remaining portion of the SOI layer 13 ′ where the source portion 14 and the drain portion 15 are formed constitutes the channel portion 13 .
Next, the resist layer 104 is removed by oxygen ashing, and the surface is SPM-cleaned. In the SPM cleaning, a mixture of H ₂ SO ₄ and H ₂ O ₂ at a ratio of 3:1 is used as a cleaning liquid.
Next, an activation annealing process is performed at a temperature of 1,000° C. for 1 second under the atmospheric pressure of N ₂ gas atmosphere to activate each impurity material in the source section 14 and the drain section 15 .
Next, the protective oxide film 102 is removed using dilute hydrofluoric acid (DHF) with a concentration of 1%.

Next, the substrate is immersed in an SC2 cleaning solution (mixed solution of HCl, H ₂ O ₂ and H ₂ O at a ratio of 1:1:6) at a temperature of 70° C. for 5 minutes for cleaning.
Next, by ALD, HfO ₂ is deposited at a temperature of 250° C. to form a gate insulating film forming film 16 ′ having a thickness of 2.4 nm around the channel portion 13 , and a gate insulating film is formed by sputtering. A 30 nm thick TaN gate electrode forming layer 17' is formed on the film forming film 16' (see FIGS. 14A and 14B).
Next, the gate insulating film forming film 16' and the gate electrode forming layer 17' are shaped by reactive ion etching with Cl ₂ plasma using a mask to form the gate insulating film 16 and the gate electrode 17 ( See FIGS. 15(a) and (b)).
As described above, the semiconductor device 10 is manufactured.
This manufacturing method is an example of the manufacturing method of the semiconductor device 10, and the user can appropriately select suitable manufacturing equipment and manufacture by a known method.

An important matter in manufacturing the semiconductor device 10 is to secure the electron confinement surface in the channel portion 13 .
This point can be easily implemented by selecting the crystal plane orientation (crystal axis direction perpendicular to the substrate) of the SOI substrate, which is the start substrate, and the extending direction of the channel portion 13 .
For example, as shown in FIG. 16A, the structure for obtaining the convolution effect in the <100> direction in silicon uses the SOI substrate whose main surface is the (100) plane, and the [ 110] direction notch (orientation flat or notch; indicated by a horizontal line at the bottom of the circle in the figure) by aligning the extending direction of the channel part 13 in a 45 degree (or equivalent) direction. be able to.
Further, for example, as shown in FIG. 16B, the structure for obtaining the convolution effect in the <111> direction in germanium is a GOI (Germanium-on-insulator) substrate having the (110) plane as the main surface. , the channel portion is oriented 55 degrees (or equivalent) with respect to the [1-10] direction notch portion (orientation flat or notch; indicated by a horizontal line at the bottom of the circle in the figure) in the GOI substrate It can be obtained by aligning the extending directions of 13.
FIG. 16A is a diagram showing an outline of a method of forming a channel portion using an SOI substrate having the (100) plane as the main surface, and FIG. It is a figure which shows the outline|summary of the formation method of the channel part using the GOI board|substrate which makes it.

Next, an example of the method for manufacturing the semiconductor device according to the present invention related to the semiconductor device 20 according to the second embodiment will be described with reference to the drawings.
17 to 19 are diagrams (1) to (3) showing the manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment, and (b) of each diagram corresponds to (a). ) is a cross-sectional view taken along line AA.

First, the Si substrate 31 for the handle is prepared. For this substrate 31, the crystal plane orientation similar to that of the SOI substrate is selected based on the matter described with reference to FIG. be able to.
A silicon-germanium sacrificial layer 201a', a Si semiconductor layer 33a, a silicon-germanium sacrificial layer 201b', a Si semiconductor layer 33b, a silicon-germanium sacrificial layer 201c', and a Si semiconductor layer 33c are formed on the substrate 31 in this order. It is formed by an epitaxial growth method (see FIGS. 17A and 17B). The thickness of each layer of the Si semiconductor layers 33a to 33c is 15 nm at the thickest according to the thickness D ₂ (see FIG. 8A) of the channel portion 23a in the semiconductor device 20 according to the second embodiment. It can be controlled by adjusting the epitaxial growth time.
Next, the shapes of the silicon-germanium sacrificial layers 201a' to 201c' and the Si semiconductor layers 33a to 33c are processed by lithography using a mask 202 (see FIGS. 18A and 18B).
Next, the central portion is selectively etched by hydrogen peroxide solution (H ₂ O ₂ ) so as to divide the silicon-germanium sacrificial layer 201a′ into two silicon-germanium sacrificial layers 201a. At the same time, the silicon-germanium sacrificial layers 201b' and 201c' are similarly etched. At this time, the etching rate of the Si semiconductor layers 33a to 33c of the hydrogen peroxide solution (H ₂ O ₂ ) is sufficiently slower than the etching rate of the silicon-germanium sacrificial layers 201a′ to 201c′. Only the layers 33a to 33c are in a crosslinked state without being divided, so that the channel portion can be formed (see FIGS. 19(a) and 19(b)).

Matters other than this are based on the matters explained in the semiconductor element 10 according to the first embodiment and/or the semiconductor device according to the element configuration of the semiconductor element 20 according to the second embodiment based on the known method of manufacturing the semiconductor element. can be manufactured.

(semiconductor integrated circuit)
A semiconductor integrated circuit of the present invention includes the semiconductor element of the present invention.
The method for integrating the semiconductor elements is not particularly limited and can be appropriately selected according to the purpose, and known methods can be appropriately adopted.

(simulation)
A simulation was carried out as follows regarding changes in the energy band structure and changes in inter-band tunneling current caused by making silicon, which is the indirect transition type semiconductor, into a two-dimensional plate shape.

<Change in energy band structure>
Simulation of changes in energy band structure for two types of silicon: bulk silicon with an infinite thickness and plate-like silicon with a thickness of about 1.1 nm. did the test.
Specifically, a simulation test was conducted as follows.
First, the energy band structure of silicon was obtained by first-principles calculation based on density functional theory.
The calculation software VASP (Vienna Ab Initio Simulation Package) version 5.4 was used for the calculation.
Generalized Gradient Approximation (GGA) and Perdue-Burke-Ernzerhof (PBE) formalism were used for the exchange-correlation functional describing electron interaction.
The wave function of valence electrons is represented by the superposition of plane waves and considered up to wavenumbers corresponding to kinetic energies of up to 500 eV. The interaction of core electrons with valence electrons was expressed using the pseudopotential of the PAW (Projector Augmented Wave) method.
Here, the plate-shaped silicon with a thickness of about 1.1 nm has a structure in which eight layers of two atoms per layer are stacked as a basic unit, and a system that repeats infinitely periodically in the in-plane direction. prepared on the assumption that At this time, it was assumed that both the upper and lower surfaces in the thickness direction of the silicon were terminated with hydrogen, and that a vacuum layer having a thickness of 2 nm or more existed on the outside thereof.
On the other hand, bulk silicon has a structure in which four layers of two atoms per layer are stacked as a basic unit, and this basic unit is a system in which this basic unit is repeated infinitely periodically in the in-plane and perpendicular directions. I assumed and prepared.

FIG. 20(a) shows the energy band structure of bulk silicon obtained by the simulation test. Also, FIG. 20(b) shows the energy band structure of plate-like silicon with a thickness of about 1.1 nm.
As shown in FIG. 20( a ), in bulk silicon, the top of the valence band is located at the Γ point, which means zero momentum, whereas the bottom of the conduction band is located at a point different from the Γ point. positioned. In other words, the direct characteristics of the indirect transition semiconductor are shown.
On the other hand, as shown in FIG. 20(b), in the silicon plate having a thickness of about 1.1 nm, both the valence band uppermost end and the conduction band lowermost end are located at the Γ point. In other words, it can be seen that silicon, which is originally an indirect transition semiconductor, is transformed into a pseudo direct transition semiconductor by forming it into a thin plate-like shape.

Next, FIG. 21 shows the correlation between the energy band structure of silicon and the silicon film thickness obtained by using the same method as the first-principles calculation. However, here, it is assumed that the maximum kinetic energy of the wave number of the plane wave representing the wave function is 550 eV, and the thickness of the vacuum layer outside the silicon thin film is assumed to be 1.1 nm. The vertical axis in FIG. 21 represents the bandgap (energy difference between the top end of the valence band and the bottom end of the conduction band, Eg _thin ) when changing the thickness of the plate-like silicon in the simulation test, and the bulk silicon. The difference between the bandgap (energy difference between the top end of the valence band and the bottom end of the conduction band, Eg _bulk ) is expressed as a ratio to the bandgap of bulk silicon (={Eg _thin −Eg _bulk }. / _Egbulk ). Also, the horizontal axis indicates the thickness of the silicon plate.
Since the change in the bandgap of silicon is caused by the mixing of the electron orbits of the component related to the indirect transition and the component related to the direct transition, the change in the bandgap due to thinning results in supporting the enhancement of the component related to the direct transition. .
As shown in FIG. 21, when the thickness of the plate-shaped silicon becomes 15 nm or less, the band structure of silicon begins to change, and it is confirmed that the component related to the direct transition is enhanced.

<Band-to-band tunnel current>
Next, we conducted a simulation test on the change in band-to-band tunneling current.
Two targets of this simulation test are assumed to be the following thinned TFET and bulk TFET.

First, as shown in FIG. 22, the thinned TFET is a silicon plate 40 whose thickness direction is the <100> direction, whose thickness is uniform at 1.1 nm, and whose front and back surfaces are {100} planes. is used as a base material, and a channel region 43 is formed between a source region 44 formed on one longitudinal end side and a drain region 45 formed on the other longitudinal end side. At this time, it was assumed that both the upper and lower surfaces in the thickness direction were terminated with hydrogen, and that a vacuum layer having an infinitely large thickness existed outside.
Here, the source region 44 is made of P-type silicon, and the impurity concentration is set to about 5×10 ¹⁹ cm ⁻³ so that the Fermi level and the upper end of the valence band have the same energy.
The drain region 45 is made of N-type silicon, has an impurity concentration of about 5×10 ¹⁹ cm ⁻³ , and is set so that the energy between the Fermi level and the bottom of the conduction band coincides.
The channel region 43 is made of silicon and is set to have no impurity added thereto.
Also, the tunnel junction 42 is set as a semiconductor junction constituted by a junction between semiconductors of the source region 44 and the channel region 43 .
The source region 44 is connected to a metal electrode (source electrode) not shown, and the junction between the metal electrode and the source region 44 is set as an ideal ohmic junction.
The drain region 45 is similarly connected to a metal electrode (drain electrode) not shown, and the junction between the metal electrode and the drain region 45 is set as an ideal ohmic junction.
FIG. 22 is an explanatory diagram for explaining the configuration of the thinned TFET, which is the object of the simulation test.

The thinned TFET is set to operate by inputting an electric field applied to the channel region 43 by an arbitrary gate insulating film and gate electrode instead of inputting the gate voltage.
The electric field was set to be applied to a portion of the channel region 43 from the position of the tunnel junction 42 to a position 10 nm away in the extending direction of the channel region 43 toward the drain region 45 . It is assumed that no electric field is applied to the source region 43 because the impurity concentration is high. Based on this setting, the electric field (E) applied to the tunnel junction 42 is set by the following formula: electric field (E)=voltage drop (ΔV)/distance (=10 nm).
In the portion of the channel region 43 which is separated from the position of the tunnel junction 42 by a distance longer than 10 nm in the extending direction, no electric field is applied, and the energies of the Fermi level and the bottom of the conduction band are the same, so that the drain region 45 and the barrier It was set as being connected without being connected.

Next, the bulk TFET was set in the same manner as the thinned TFET except that the thickness of the silicon plate 40 was changed from 1.1 nm to infinite in the thinned TFET.

In the simulation test, these two TFETs are targeted, and the band-to-band tunneling currents in these two TFETs are confirmed by comparing the band-to-band tunneling currents with the input value of the electric field as a variable.
In this simulation test, the same calculation software as used for calculating the interband tunnel current for bulk silicon and compound semiconductors containing intermediate impurity levels in Reference 2 below was used to calculate the interband tunnel current. Calculated.
Here, the current intensity was determined by calculating the non-equilibrium Green's function transmission coefficient. The sp3s* orbitals of silicon atoms based on the tight-binding approximation were adopted as the basis for expressing the electron wavefunction and density. The orbital energy and interatomic jump energy of electrons used in the tight-binding approximation are based on the band structure of bulk silicon (see FIG. 20(a)) and the known bandgap energy of silicon (1.1 eV) obtained by experiments. decided to reproduce the Using this tight-binding approximation, the energy band structure of a thin film with a thickness of 1.1 nm was obtained, and the tunnel current was calculated using it. The interaction of electrons tunneling through the pn junction interface was described by the Green's function of electrons in the electrode, between the electrode and the semiconductor, and in the semiconductor itself.
Reference 2: Xianghun Cho, Takashi Nakayama, "Increase in tunnel current due to resonant impurity level in p/n junction: Comparison of direct and indirect bandgap systems" Proceedings of the 26th Electronic Device Interface Technology Study Group pp.109- 113, January 2021.

FIG. 23 shows the simulation test results of band-to-band tunneling current. In FIG. 23, the tunnel current begins to flow when a current of 1×10 ⁻¹⁵ A/μm flows. The horizontal axis shows the electric field.
As shown in FIG. 23, it is confirmed that the band-to-band tunneling current is significantly increased in the thinned TFET as compared to the bulk TFET.
As described above, in the semiconductor element of the present invention, the channel portion formed of the indirect transition semiconductor can be pseudo-direct transition semiconductor to increase the tunnel current.

In order to confirm the simulation result and the effectiveness of the effects brought about by the present invention, the semiconductor device was manufactured and its performance was evaluated. A specific description will be given below.

(Example 1)
A semiconductor device according to Example 1 was manufactured according to the configuration of the semiconductor device 10 according to the first embodiment shown in FIGS.
The semiconductor device according to Example 1 relates to a trial production for confirming effectiveness. a) and (b)) as the gate electrode. Although it is assumed that the semiconductor device according to Example 1 having the back gate structure provides a smaller on-current than the semiconductor device 10 according to the first embodiment having the gate insulating film 16 and the gate electrode 17, switching The characteristics and various conditions for obtaining a large tunnel current and tunnel current density are common to the semiconductor device 10 according to the first embodiment. The results of confirming the effectiveness of the semiconductor device according to Example 1 strongly support the effectiveness of the semiconductor device of the present invention, including the semiconductor device 10 according to the first embodiment.

The semiconductor device according to Example 1 was manufactured as follows by a manufacturing method similar to the method described with reference to FIGS. 9 to 13B. The reference numerals in the description are the same as the reference numerals in FIGS. 9 to 13(b).
First, on a Si semiconductor layer 11 for a handle, a SiO ₂ surface insulating layer (BOX layer) 12 having a thickness of 145 nm and an SOI layer 13' having a thickness of 50 nm made of Si are formed in this order on an SOI substrate. prepared (see FIGS. 9A and 9B). The SOI layer 13' is doped with a p-type impurity of about 1.times.10.sup.15 ^{cm.sup. -3} .
Here, as the SOI substrate, one having a (100) plane as a main surface is used, and in subsequent manufacturing steps, the channel portion is oriented 45 degrees with respect to the notch portion in the [110] direction of the SOI substrate. By aligning the extending directions of 13, the formed channel portion 13 is provided with the electron confining surface (see FIG. 16(a)).

Next, after forming an etching mask 101 with a thickness of 65 nm at a predetermined position on the SOI layer 13' by electron beam lithography, reactive ion etching (RIE) is performed using the etching mask 101 as a mask to shape the SOI layer 13'. were processed into the shapes of the channel portion 13, the source portion 14 and the drain portion 15 (see FIGS. 10A and 10B). Mixed plasma of hydrogen bromide (HBr) and argon (Ar) was used as the plasma in the reactive ion etching (RIE).
Here, the shape processing of the SOI layer ₁₃ ' is performed by the reactive ion etching ( RIE) settings were adjusted. That is, considering the thickness of 4 nm of the SiO ₂ protective oxide film 102 to be formed in the next step, the setting of the reactive ion etching (RIE) is adjusted so that the thickness of the SOI layer 13' becomes 18 nm. rice field.
Next, after removing the etching mask 101, a SiO ₂ protective oxide film 102 having a thickness of 4 nm was formed on the surface of the SOI layer 13' for subsequent ion implantation (see FIGS. 11A and 11B).

Next, by electron beam ^lithography , a resist layer 103 having a thickness of 100 nm is formed on the protective oxide film ^102. Using this resist layer 103 as a mask, As was performed to form a source portion 14 as the source region in the SOI layer 13'.
Next, the resist layer 103 was removed by oxygen ashing, and the surface was washed with SPM (Sulfuric Acid Peroxide Mixture). A 3:1 mixture of H ₂ SO ₄ and H ₂ O ₂ was used for SPM cleaning.
Next, a 100 nm-thick resist layer 104 is formed on the SPM-cleaned protective oxide film 102. Using this resist layer 104 as a mask, BF ₂ is irradiated with an acceleration energy of 5 keV and a dose of 2×10 ¹⁵ cm ⁻² . was performed to form the drain portion 15 as the drain region in the SOI layer 13' (see FIGS. 12 and 13 for examples of forming the source portion 14 and the drain portion 15).
A remaining portion of the SOI layer 13 ′ where the source portion 14 and the drain portion 15 are formed constitutes the channel portion 13 .
Next, the resist layer 104 was removed by oxygen ashing, and the surface was SPM-cleaned. In the SPM cleaning, a mixture of H ₂ SO ₄ and H ₂ O ₂ at a ratio of 3:1 was used as a cleaning liquid.
Next, activation annealing was performed at a temperature of 1,000° C. for 1 second under the atmospheric pressure of N ₂ gas atmosphere to activate each impurity material in the source portion 14 and the drain portion 15 .
Next, the protective oxide film 102 was removed using dilute hydrofluoric acid (DHF) with a concentration of 1%.

As described above, a semiconductor device according to Example 1 was manufactured.
In the semiconductor device according to Example ₁ , the Fin width of the channel portion 13 (corresponding to the thickness D1 in FIG. 5A) is 14 nm, and the opposing surfaces of the channel portion 13 that regulate the Fin width are the above-mentioned An electron confining surface.

(Example 2)
Example 2 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 12 nm. A semiconductor device was manufactured.

(Example 3)
Example 3 was performed in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 10 nm. A semiconductor device was manufactured.

(Example 4)
Example 4 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 8 nm. A semiconductor device was manufactured.

(Example 5)
Example 5 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 4 nm. A semiconductor device was manufactured.

(Comparative example 1)
Comparative Example 1 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 16 nm. A semiconductor device was manufactured.

(Comparative example 2)
Comparative Example 2 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 28 nm. A semiconductor device was manufactured.

(Comparative Example 3)
Comparative Example 3 was fabricated in the same manner as in Example 1, except that the setting of the reactive ion etching (RIE) was changed to shape the SOI layer 13' so that the Fin width was 38 nm. A semiconductor device was manufactured.

<Performance evaluation>
In evaluating the performance of each semiconductor device of Examples 1 to 5 and Comparative Examples 1 to 3, each semiconductor device was photographed with an electron microscope to confirm in advance that each setting including the Fin width was correctly realized. did.
As an example, FIG. 24 shows a scanning electron microscope image of the semiconductor device according to Example 4 taken from above.

(switching characteristics)
Next, the switching characteristics of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 were measured.
The switching characteristics were measured as follows.
That is, each measurement needle of a manual prober (manufactured by Micronics Japan, 708fT) connected to a semiconductor device parameter analyzer (manufactured by Agilent Technologies, Inc., B1500) was used to measure the source portion 14, the drain portion 15, and the Si semiconductor layer as a gate electrode. 11 is terminal-connected via a metal plate (an alloy of aluminum (approximately 98% by mass) mixed with trace amounts of silicon and copper), and the drain current (tunnel current) is measured by sweeping the gate voltage at a predetermined drain voltage. Measurements were carried out to measure the switching characteristics. In addition, the measurement was implemented in a room temperature environment.

As a result of measuring the switching characteristics of each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3, the switching characteristics of the drain current (tunnel current) between the ON state and the OFF state according to the gate voltage were confirmed. rice field. That is, each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 operates as the tunnel field effect transistor.
As an example, FIG. 25 shows the switching characteristics of the semiconductor device according to Example 4. In FIG. In FIG. 25 , the plot indicated by black circles indicates the drain current on the logarithmic scale of the right axis, and the plot indicated by white rhombuses indicates the drain current on the linear scale of the left axis. Also, the gate voltage when the drain current is 1×10 ⁻¹² A is shifted to 0 V as V _off .
As shown in FIG. 25, in the semiconductor device according to the fourth embodiment, when the value of the gate voltage is increased in the negative direction from the gate voltage V _off in the off state, the semiconductor device enters the on state and the drain current flows. At this time, as can be understood from the transition of the drain current on the logarithmic scale on the right axis, the semiconductor device according to Example 4 has a steep drop in the low voltage region, which is one of the features of the tunnel field effect transistor. It shows the switching characteristics. These features are features commonly seen in the semiconductor devices of Examples 2-5 and Comparative Examples 1-3.

(Tunnel current and tunnel current density)
FIGS. 26 and 27 show drain currents and drain current densities of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 when the gate voltage is −11.5 V in the measurement of the switching characteristics described above. FIG. 26 is a diagram showing the relationship between tunnel current and Fin width, and FIG. 27 is a diagram showing the relationship between tunnel current density and Fin width.

As shown in FIG. 26, when the Fin width is 16 nm, the drain current becomes minimum, and when the Fin width decreases to about 15 nm or less, the drain current tends to increase.
This phenomenon indicates that when the Fin width reaches 15 nm, the tunnel current increases due to the confinement effect based on the pseudo direct transition type semiconductor conversion of the indirect transition type semiconductor, and the simulation It clearly supports the validity of the results and the effects provided by the present invention.
Moreover, the effect of increasing the drain current is extremely large, as understood from the tunnel current density shown in FIG.
In each of the semiconductor devices of Examples 1 to 5, the tunnel current is increased due to the confinement effect based on the pseudo direct transition semiconductor of the indirect transition semiconductor, and the semiconductor devices of Comparative Examples 1 to 3 are It is clear that a large tunnel current can be obtained from the tunnel current estimated from the decreasing tendency of the tunnel current as the Fin width is decreased, at the same Fin width. Therefore, the semiconductor device according to the present invention can be evaluated as having a large on-current.
In addition, in each of the semiconductor devices of Examples 1 to 5, as the Fin width decreases, the tunnel current tends to increase. The demand for miniaturization can be satisfied at the same time.
In addition, since each of the semiconductor devices of Examples 1 to 5 can be manufactured using existing manufacturing equipment without problems in processing, the semiconductor device according to the present invention can be manufactured using existing manufacturing equipment. It also has the merit of being able to be manufactured easily and at low cost.

Reference Signs List 1, 1' indirect transition semiconductor 2, 42 tunnel junction 10, 20 semiconductor element 11, 21 semiconductor layer 12, 22 surface insulating layer 13, 23a, 23b, 23c channel portion 13' SOI layer 14, 24 source portion 15, 25 drain Part 16, 26a, 26b, 26c gate insulating film 16' gate insulating film forming film 17, 27 gate electrode 17' gate electrode forming layer 31 substrate 33a, 33b, 33c Si semiconductor layer 40 silicon plate 43 channel region 44 source region 45 drain Region 102 Protective oxide film 103, 104 Resist layer 201a, 201a', 201b, 201b', 201c, 201c' Silicon-germanium sacrificial layer

Claims (10)

In a semiconductor device having an element structure of a tunnel field effect transistor,
A channel portion formed of an indirect transition semiconductor is configured to have a plate-shaped portion having one end connected to the source portion and the other end connected to the drain portion,
Of the two sets of opposing surfaces, ie, the first opposing surfaces and the second opposing surfaces, which constitute the plate-shaped portion and are opposed in a direction perpendicular to the direction in which the current flows from the source portion to the drain portion At least one pair of the opposing surfaces is arranged at an interval of 15 nm at the longest between the opposing surfaces, such that the electron confining surfaces are capable of imparting a pseudo direct transition semiconductor band structure to the indirect transition semiconductor by regulation of electron motion. A semiconductor device characterized by being formed by: 2. The semiconductor device according to claim 1, wherein all of the four surfaces forming the first opposing surfaces and the second opposing surfaces are electron confining surfaces. The gate portion constituting the device structure of the tunnel field effect transistor is arranged so as to cover all or part of at most three of the four constituting surfaces constituting the first opposing surfaces and the second opposing surfaces. 3. The semiconductor device according to any one of claims 1 and 2. 4. The semiconductor device according to any one of claims 1 to 3, wherein the indirect transition semiconductor is silicon and the electron confining plane is a {100} plane. 4. The semiconductor device according to any one of claims 1 to 3, wherein the indirect transition semiconductor is germanium and the electron confinement plane is a {111} plane. The indirect transition semiconductor is a mixed crystal of silicon and germanium, the electron confinement plane is a {100} plane when the germanium content is less than 85 atomic %, and the germanium content is 85 atomic % or more. 4. A semiconductor device according to any one of claims 1 to 3, wherein sometimes said electron confinement plane is a {111} plane. 7. The semiconductor device according to claim 1, wherein the tunnel junction formed in the tunnel field effect transistor is composed of a semiconductor junction. 7. The semiconductor device according to any one of claims 1 to 6, wherein the tunnel junction formed in the tunnel field effect transistor is composed of a Schottky junction. A semiconductor integrated circuit comprising the semiconductor element according to claim 1 . A method for manufacturing a semiconductor device according to any one of claims 1 to 8,
A channel portion having a plate-shaped portion, one end of which is connected to a source portion and the other end of which is connected to a drain portion, is formed by an indirect transition type semiconductor, and the plate-shaped portion is formed from the source portion to the drain portion. At least one of the two sets of opposing surfaces, that is, the first opposing surfaces and the second opposing surfaces facing each other in the direction orthogonal to the direction in which the current flows toward the A semiconductor characterized by comprising a channel portion forming step of forming electron confining surfaces capable of imparting a pseudo-direct band structure to an indirect band semiconductor at an opposing interval of at most 15 nm. A method of manufacturing an element.

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