JP2022141181A - Gate drive device - Google Patents

Abstract

To provide a gate drive device capable of detecting on-off timings of semiconductor switching elements with accuracy to shorten a setting margin of dead time.SOLUTION: A gate drive device comprises: a control circuit 20 that transmits drive signals for semiconductor switching elements of upper and lower arms; drive circuits 40a and 40b that drive gates of the semiconductor switching elements; a gate fluctuation detection circuit 60 that detects timings when gate voltages and reference voltages coincide with each other; and reference voltage adjustment circuits 50a and 50b that adjust the reference voltages of the gate fluctuation detection circuit depending on current values of the semiconductor switching elements. The control circuit has a timing adjustment function of calculating dead time from gate voltage fluctuation of the semiconductor switching elements detected by the gate fluctuation detection circuit and adjusting a drive timing at the side to be driven next.SELECTED DRAWING: Figure 1

Description

The present invention relates to gate drives.

Examples of gate-driven semiconductor switching elements include an inverter configured by arranging MOS transistors in upper and lower arms, and supplying power to a load by alternately driving the MOS transistors, and a converter that converts the voltage of a DC power supply. be. In these configurations, in order to prevent the MOS transistors of the upper and lower arms from being turned on at the same time, a dead time is provided during which the two MOS transistors are both turned off.

However, lengthening the dead time increases the loss caused by the current flowing through the body diode during that period, so it is desired to set it as short as possible. In order to shorten the dead time, it is necessary to detect the dead time accurately.

As a dead time detection method, when the dead time is detected by looking at the variation of the gate-source voltage Vgs of the upper and lower arm MOS transistors, conventionally, the on/off timing is detected using the threshold voltage Vth as a reference value. The Vgs fluctuation timing difference of the arm MOS transistors is detected as the dead time.

However, the on/off switching timing of the MOS transistor to be controlled actually deviates from the timing at which the gate-source voltage Vgs coincides with the threshold voltage Vth, and accurate dead time cannot be detected. For this reason, a dead time with a margin for the detection error must be set in advance for the deviation of the detection timing, and the dead time corresponding to the detection error cannot be shortened.

JP 2020-127145 A

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and its object is to shorten the margin for setting dead time by accurately detecting the on/off timing of a gate-driven semiconductor switching element. To provide a gate drive device which is

According to a first aspect of the present invention, there is provided a gate drive device for driving a gate drive type semiconductor switching element having a rectifying element disposed in each of an upper arm and a lower arm. A control circuit (20) for transmitting drive signals for alternately driving the semiconductor switching elements, and a drive circuit (40a) for driving the gates of the respective semiconductor switching elements of the upper and lower arms according to the drive signals from the control circuit. , 40b), a gate fluctuation detection circuit (60) for detecting the timing at which the gate voltage of each of the semiconductor switching elements of the upper and lower arms matches the reference voltage, and the gate fluctuation detection circuit (60) according to the current value of the semiconductor switching element. a reference voltage adjustment circuit (50a, 50b) for adjusting the reference voltage of the circuit, wherein the control circuit detects timing of gate voltage fluctuation of the semiconductor switching elements of the upper and lower arms detected by the gate fluctuation detection circuit; It has a timing adjustment function that calculates the dead time and adjusts the driving timing of the next driving side.

By adopting the above configuration, the reference voltage adjustment circuit adjusts the reference voltage according to the current value of the semiconductor switching element and sets it in the gate variation detection circuit. The actual ON or OFF timing can be detected by detecting the timing at which V coincides with the reference voltage.

As a result, the control circuit can accurately detect the time corresponding to the actual dead time from the timing of the gate voltage fluctuations of the semiconductor switching elements of the upper and lower arms detected by the gate fluctuation detection circuit. It is no longer necessary to set a margin including dependent fluctuations, and the time during which current flows through the rectifier connected in parallel to the semiconductor switching element can be reduced as much as possible.

Electrical configuration diagram showing the first embodiment FIG. 4 is an operation explanatory diagram of gate voltage detection timing showing the first embodiment; Timing chart showing the first embodiment Electrical configuration diagram showing the second embodiment Electrical configuration diagram showing the third embodiment Effect explanatory drawing which shows 3rd Embodiment

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG.
In FIG. 1 showing the electrical configuration, N-channel MOS transistors 1 and 2, which are two semiconductor switching elements forming upper and lower arms, are connected in series between power supply terminals. A common connection point of the MOS transistors 1 and 2 is an output terminal to a load. MOS transistor 1 has a body diode 1a, and MOS transistor 2 has a body diode 2a.

The two MOS transistors 1 and 2 are controlled to be turned on and off by a gate driver 10 . Also, the two MOS transistors 1 and 2 have current sensing functions for monitoring drain currents Id1 and Id2, which are load currents, respectively. In this case, a configuration in which a current sensing element is provided separately may be employed, or a configuration in which a current detection unit is separately provided in the conducting path for detection may be employed.

The gate drive device 10 includes a control circuit 20, dead time setting circuits 30a and 30b, drive circuits 40a and 40b, reference voltage adjustment circuits 50a and 50b, and a gate variation detection circuit 60. FIG. In the configuration of gate drive device 10, dead time setting circuits 30a and 30b, drive circuits 40a and 40b, and reference voltage adjustment circuits 50a and 50b with subscripts a and b correspond to MOS transistors 1 and 2, respectively. They are individually provided and each has the same internal configuration. In the description of the configuration below, the circuits with the suffix a corresponding to the MOS transistor 1 will be described, and the description of the circuits with the suffix b will be omitted.

The control circuit 20 generates a drive signal for the MOS transistors 1 and 2 of the upper and lower arms in response to an externally applied ON/OFF instruction signal to perform ON/OFF drive control. In this case, control circuit 20 supplies a drive signal to drive circuit 40a for MOS transistor 1 through dead time setting circuit 30a, and drives MOS transistor 2 to drive circuit 40b through dead time setting circuit 30b. give a signal.

The dead time setting circuit 30a sets the dead time by adding a predetermined margin in consideration of errors occurring in the circuit configuration to the instruction signal based on the detected dead time signal. The dead time setting circuit 30a includes a delay circuit 31a, a phase comparator 32a, an F/B gain circuit 33a and a sample and hold circuit 34a.

The reference voltage adjustment circuit 50 a sets a reference voltage Vgsm 1 for determining the on/off timing of the MOS transistor 1 and outputs it to the inverting input terminal of the comparator 61 a forming the gate change detection circuit 60 . The reference voltage Vgsm1 indicates a mirror voltage when the gate voltage Vgs enters the mirror period while the MOS transistor 1 is on or off.

Therefore, the reference voltage adjustment circuit 50a is configured to calculate the reference voltage Vgsm1 from the drain current Id1 and the threshold voltage Vth based on the following equation (1).

In equation (1), the drain current Id indicates the saturation current during the mirror period. The width is W, the electron mobility is .mu.n, and the gate oxide film capacitance per unit area is Cox, which are constant values determined by the device. Also, the threshold voltage Vth is a constant value determined by the element.

As a result, the mirror voltage Vgsm is obtained by adding a value proportional to the square root of the drain current Id to the threshold voltage Vth. Therefore, the reference voltage Vgsm changes according to the level at which the drain current Id as the load current flows.

The reference voltage adjustment circuit 50a has a current monitor section 51a, a current direction determination section 52a, a square root calculation section 53a, a proportional coefficient multiplication section 54a, a threshold value setting section 55a, and an addition section 56a. The current monitor unit 51a takes in the detection signal of the drain current Id1 of the MOS transistor 1, and the current direction determination unit 52a detects that the drain current Id1 is positive when the current flows from the drain side to the source side. Id1 is output as it is, and when the drain current is negative, it is output as zero to the square root calculator 53a.

Subsequently, the square root of the value of the drain current Id1 is calculated by the square root calculator 53a, and is multiplied by the proportional coefficient A1 by the proportional coefficient calculator 54a. The adder 56a outputs the reference voltage Vgsm1 obtained by adding the output from the proportional coefficient calculator 54a and the threshold value Vth from the threshold value setter 55a to the gate variation detection circuit 60. FIG.

The gate variation detection circuit 60 includes comparators 61a and 61b corresponding to the MOS transistors 1 and 2, respectively, inverters 62a and 62b and insulating communication units 63a and 63b for inverting and transmitting the respective determination results to opposing arms. .

Comparator 61a compares gate voltage Vgs1 of MOS transistor 1 with reference voltage Vgsm1 set by reference voltage adjustment circuit 50a, and outputs a high-level detection signal when gate voltage Vgs1 exceeds reference voltage Vgsm1. This detection signal is output to the phase comparator 32a of the dead time setting circuit 30a, and the inverted signal is output to the phase comparator 32b of the dead time setting circuit 30b through the inverter 62a and the insulating communication section 63a.

Similarly, the comparator 61b compares the gate voltage Vgs2 of the MOS transistor 2 with the reference voltage Vgsm2 set by the reference voltage adjustment circuit 50b, and outputs a high-level detection signal when the gate voltage Vgs2 exceeds the reference voltage Vgsm2. Output. This detection signal is output to the phase comparator 32b of the dead time setting circuit 30b, and an inverted signal is output to the phase comparator 32a of the dead time setting circuit 30a through the inverter 62b and the insulating communication section 63b.

Next, the operation of the above configuration will be described with reference to FIGS. 2 and 3 as well. As for the basic operation of the gate drive device 10, when signals for alternately turning on and off the MOS transistors 1 and 2 are output from the control circuit 20 to the dead time setting circuits 30a and 30b respectively, the delay circuits 31a and 31b A driving signal is generated at a timing according to the dead time DT set to , and is output to the driving circuits 40a and 40b. The drive circuits 40a and 40b apply gate drive signals to the gates of the MOS transistors 1 and 2 to turn them on and off.

Drain currents Id1 and Id2, which are load currents flowing through the MOS transistors 1 and 2, are measured and input to the reference voltage adjustment circuits 50a and 50b. In the reference voltage adjustment circuits 50a and 50b, the reference voltages Vgsm1 and Vgsm2 are calculated by executing the arithmetic processing corresponding to the above equation (1) and set in the comparators 61a and 61b, respectively.

In this case, when the drain currents Id1 and Id2 are positive, the current direction determination units 52a and 52b generate a signal corresponding to the magnitude thereof, and when negative, the current value is generated as zero. As a result, the reference voltages Vgsm1 and Vgsm2 are set to values based on the drain current Id during normal driving, and threshold values Vth1 and Vth2 are set during synchronous rectification, respectively.

As described above, the magnitudes of the gate voltages Vgs1 and Vgs2 when the MOS transistors 1 and 2 are switched on and off are determined by the mirror voltages that hold intermediate voltages during the on/off transition of the elements. Therefore, the mirror voltage is represented by the drain current Id and the threshold voltage Vth, as shown in the above equation (1).

Therefore, by obtaining constants corresponding to the characteristics of the MOS transistors 1 and 2 in advance and setting them in the proportional coefficient multiplier 54a and the threshold value setting section 55a of the reference voltage adjustment circuits 50a and 50b, respectively, A mirror voltage corresponding to the drain current Id can be obtained. Then, the comparators 61a and 61b compare with the mirror voltage set corresponding to the drain current Id, so that the ON/OFF timing can be determined accurately.

Further, when the drain current Id is negative, that is, when it is on the synchronous rectification side, the gate voltage Vgs, which is the ON/OFF switching timing, becomes the threshold voltage Vth regardless of the drain current Id. Therefore, in the reference voltage adjustment circuits 50a and 50b, when the drain current Id becomes negative, the current direction determination units 52a and 52b set the drain current Id to zero so as to cope with this case. This makes the reference voltage equal to the threshold voltage Vth.

FIG. 2 shows the case where the on/off timings of the MOS transistors 1 and 2 are detected by the comparators 61a and 61b of the gate change detection circuit 60, and the mirror voltage of the gate voltage Vgs varies depending on whether the load current, that is, the drain current Id is large or small. This indicates that the determination timing is different.

For example, when the drain current Id is at a high level IdH, the mirror voltage is VgsmH indicated by the solid line, and when the drain current Id is at a low level IdL, the mirror voltage is VgsmL indicated by the broken line. For the comparators 61a and 61b, reference voltages Vgsm1 and Vgsm2 are set to VgsmH and VgsmL according to the current value, depending on whether the drain current Id is large or small. These reference voltages Vgsm are calculated and set by the reference voltage adjusting circuits 50a and 50b based on the equation (1).

When the MOS transistors 1 and 2 are on and the gate voltage Vgs starts to fall from the level of the predetermined voltage VGS at time t0, it reaches a constant level at the intermediate mirror voltages VgsmH and VgsmL, and then starts to fall again at time t1H. At t1L, the comparators 61a and 61b determine that the voltage has dropped below the reference voltage, and change the output signal from high level to low level. MOS transistors 1 and 2 are turned off at times t1H and t1L, respectively.

Therefore, assuming that the timing determined by the reference voltage Vth equivalent to the conventional one is time t1, the output signal changes at a timing t1L (indicated by a white circle in the figure) that is slightly earlier than time t1 when the current is small, and the output signal changes at time t1L when the current is large. The output changes at timing t1H (indicated by a black circle in the figure) earlier than t1L.

On the other hand, if the MOS transistors 1 and 2 are off and the gate voltage Vgs starts to rise from the zero level at time t2, it reaches a constant level at the intermediate mirror voltages VgsmL and VgsmH, and then starts to rise again at time t3H. At t3L, the comparators 61a and 61b determine that the reference voltage has been reached, and change the output signal from low level to high level. MOS transistors 1 and 2 are turned on at times t3L and t3H, respectively.

Therefore, assuming that the timing determined by the reference voltage Vth equivalent to the conventional one is time t3, the output signal changes at a timing t3L (indicated by a white circle in the figure) that is slightly later than time t3 when the current is small, and when the current is large, the time t3L changes. The output changes at timing t3H (indicated by a black circle in the figure), which is later than t3L.

As a result, it can be seen that the ON/OFF timing shifts according to the magnitude of the drain current Id, and the larger the drain current Id, the longer the time difference from the detection timing at the threshold voltage Vth.

FIG. 3 shows that one of the MOS transistors 1 and 2 on the upper and lower arms is on the drive side (upper stage) based on the operation of detecting the on/off timing of the MOS transistors 1 and 2 by the comparators 61a and 61b of the gate change detection circuit 60 described above. ), and the other is on the synchronous rectification side (shown at the bottom).

As described above, when the current is small, the reference voltage Vgsm is at a low level VgsmL, which is slightly higher than the threshold voltage Vth. Moreover, it is VgsmH, which is a high level when the current is large.

First, when the drain current Id is a small current, when the drive side of the MOS transistors 1 and 2 is turned off at time t0, the gate voltage Vgs drops from the applied VGS. At time t1L, it reaches the reference voltage VgsmL and shifts to the off state. After that, the voltage reaches the threshold voltage Vth at time t1.

Here, the start time of the dead time DT is the time t1L when the switch is turned off, and the start times of the actual dead time and the detected dead time DT are substantially the same. On the other hand, in the comparative example of the conventional method for determination based on the threshold voltage Vth, the off timing is detected with a slight delay.

After that, when dead time DT elapses and MOS transistors 1 and 2 on the synchronous rectification side are turned on at time T0a, gate voltage Vgs rises and reaches threshold voltage Vth at time Ta. is turned on, and this time Ta is detected.

As a result, the actual dead time at this time is from time t1L to time Ta, which is substantially the same as the detected dead time DT. On the other hand, in the comparative example, the off-time of the driving side is detected at time t1, which is later than t1L, so that the detected dead time is slightly short, resulting in a difference from the actual dead time.

Next, when the drain current Id is a large current, when one of the MOS transistors 1 and 2 on the drive side is turned off at time t0, the gate voltage Vgs begins to fall from VGS to which Vgs was applied, and at time t1H. It reaches the reference voltage VgsmH and shifts to the off state. After that, the voltage reaches the threshold voltage Vth at time t1.

The start time of the dead time DT here is the time t1H when the switch is turned off, and the start times of the actual dead time and the detected dead time DT are substantially the same. On the other hand, in the comparative example of the conventional method in which determination is made using the threshold voltage Vth, the off timing is detected with a delay.

After that, when dead time DT elapses and MOS transistors 1 and 2 on the synchronous rectification side are turned on at time T0a, gate voltage Vgs rises and reaches threshold voltage Vth at time Ta. is turned on, and this time Ta is detected.

As a result, the actual dead time at this time is from time t1H to time Ta, which is substantially the same as the detected dead time DT. On the other hand, in the comparative example, the off-time of the driving side is detected at time t1, which is later than t1H, so that the detected dead time is a little short, resulting in a large difference from the actual dead time. .

The above detection error increases as the drain current Id increases. For this reason, conventionally, the dead time is set by adding a margin considering such a detection error. Therefore, even when the drain current Id is small, the dead time is set to be longer than necessary.

In this embodiment, the reference voltage adjustment circuits 50a and 50b set the on/off timings of the MOS transistors 1 and 2 as the reference voltages Vgsm1 and Vgsm2 according to the magnitudes of the drain currents Id1 and Id2 which are the load currents. I made it As a result, even if the drain currents Id1 and Id2 fluctuate, the actual on/off timing of the MOS transistors 1 and 2 can be matched with the timing of detecting the fluctuation of the gate voltage Vgs. can match the length of

As a result, it becomes possible to perform detection in a state in which variations in the detection dead time DT that fluctuate due to the magnitude of the drain currents Id1 and Id2 are included. is no longer required, and the dead time to be set can be shortened accordingly.

(Second embodiment)
FIG. 4 shows a second embodiment, and portions different from the first embodiment will be described below. In this embodiment, the gate drive device 100 is configured to perform the functions of the dead time setting circuits 30a and 30b in the control circuit 120, and the gate change detection circuit 160 is configured to include comparators 61a and 61b. there is

Further, in this embodiment, instead of using the current detection function of the MOS transistors 1 and 2, current detection sensors 3a and 3b are provided so as to detect the drain currents Id1 and Id2 in the respective conducting paths. . Current monitor units 51a and 51b of reference voltage adjustment circuits 50a and 50b are configured to receive current detection signals from respective current detection sensors 3a and 3b.

The control circuit 120 calculates the actual dead time from the detection signal of the fluctuation of the gate voltage of the MOS transistors 1 and 2 output from the gate fluctuation detection circuit 160, and adds a margin to set the dead time. It is configured to apply drive signals to the circuits 40a and 40b.
Therefore, even in such a third embodiment, it is possible to obtain the same effect as in the first embodiment.

(Third embodiment)
5 and 6 show a third embodiment, and the differences from the first embodiment will be explained below. In this embodiment, the gate drive device 110 is configured to have a function of monitoring the temperatures of the MOS transistors 1 and 2 as the reference voltage adjustment circuits 150a and 150b. As a configuration of the temperature monitor, for example, a configuration is provided in which a diode is arranged at the detection portion and a constant current is passed through it. The temperature can be calculated by detecting the forward voltage when a constant current flows through the diode.

The reference voltage adjustment circuits 150a and 150b have the same configuration, and the reference voltage adjustment circuit 150a will be described below. When temperature monitor unit 57a receives a signal corresponding to temperature from MOS transistor 1, temperature monitor unit 57a outputs a temperature signal to threshold value setting unit 55a. Threshold setting unit 55a outputs the value of threshold Vth corresponding to temperature T to adder 56a.

In the first embodiment, the value of the threshold voltage Vth shown in the above equation (1) was treated as a unique value for each of the MOS transistors 1 and 2. When the element temperature changes due to the flow of the current Id, the threshold voltage Vth changes accordingly.

As shown in FIG. 6, the temperature characteristic of the threshold voltage Vth is such that, as the temperature T rises, the threshold voltage Vth linearly decreases as shown. As shown in FIG. 6, when the temperature T increases from Ta to Tb, the threshold voltage Vth decreases from Vtha to Vthb.

Temperature monitor units 57a and 57b receive detection signals of temperatures T of MOS transistors 1 and 2 and output signals corresponding to the detected temperatures to threshold setting units 55a and 55b. Threshold value setting unit 55a stores data corresponding to temperature characteristics of MOS transistor 1 in advance, and when temperature signal T is input, threshold value setting unit 55a reads and outputs a corresponding threshold value Vth(T). . It should be noted that the relationship between the temperature and the threshold voltage shown in FIG. 6 may be stored as a formula, calculated, and output.

Thus, the reference voltage adjustment circuit 150a can set the reference voltage Vgsm1 to the comparator 61a according to the magnitude of the drain current Id1 of the MOS transistor 1 and the temperature T.

As a result, the on/off timing of the MOS transistors 1 and 2 can be detected more accurately, and the margin setting can be set by a slight amount due to the error in the circuit, and the dead time can be detected with high accuracy. It can be carried out. In particular, during synchronous rectification, the threshold voltage Vth is set as a reference voltage corresponding to the temperature, so that the on/off timing can be detected accurately.

According to this embodiment, the reference voltage Vgsm1 for detecting the on/off timings corresponds not only to the magnitudes of the drain currents Id1 and Id2 of the MOS transistors 1 and 2, but also to the element temperatures T1 and T2. , Vgsm2 can be set.

It should be noted that, depending on the usage environment and mode of use of the apparatus, if there is little temperature change and the threshold voltage Vth fluctuates little, there is no problem in using the configuration of the first embodiment in which a constant value is set. As handled in this embodiment, when the change in the threshold voltage Vth due to the fluctuation of the element temperature becomes large, the dead time can be detected with high accuracy by applying this embodiment.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions can be made.

As semiconductor switching elements, MOS transistors can be made of silicon carbide (SiC) in addition to general silicon (Si), and gate-driven transistors such as IGBTs (Insulated Gate Bipolar Transistors). can be applied to the switching element of

Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 and 2 are MOS transistors (gate-driven semiconductor switching elements), 3a and 3b are current detection elements, 10, 100 and 110 are gate drivers, 20 is a control circuit, and 30a and 30b are dead time setting circuits. , 40a and 40b are drive circuits, 50a and 50b are reference voltage adjustment circuits, 60 is a gate change detection circuit, and 61a and 61b are comparators.

Claims (5)

A gate drive device for driving a gate drive type semiconductor switching element provided with a rectifying element and arranged on each of an upper arm and a lower arm,
a control circuit (20) for transmitting drive signals for alternately driving the respective semiconductor switching elements of the upper and lower arms;
drive circuits (40a, 40b) for driving the gates of the semiconductor switching elements of the upper and lower arms according to drive signals from the control circuit;
a gate variation detection circuit (60) for detecting the timing at which the gate voltage of each of the semiconductor switching elements of the upper and lower arms matches the reference voltage;
a reference voltage adjustment circuit (50a, 50b) for adjusting the reference voltage of the gate variation detection circuit according to the current value of the semiconductor switching element;
The control circuit has a timing adjustment function of calculating a dead time from the timing of gate voltage variation of the semiconductor switching elements of the upper and lower arms detected by the gate variation detection circuit, and adjusting the driving timing of the side to be driven next. gate drive. 2. The gate drive device according to claim 1, wherein said reference voltage adjustment circuit sets said reference voltage by varying it in proportion to the square root of the current value of said corresponding semiconductor switching element. The reference voltage is set to a voltage value obtained by adding a constant term corresponding to the threshold voltage of the semiconductor switching element and a variable term that is set by varying in proportion to the square root of the current value of the semiconductor switching element. 3. The gate drive device according to claim 2. 4. The gate drive device according to claim 3, wherein the reference voltage sets the fluctuation term to zero when the semiconductor switching element corresponds to synchronous rectification and the current value is negative. 5. The gate driving device according to claim 3, wherein a constant term corresponding to a threshold voltage of said semiconductor switching element is also changed in said reference voltage according to the element temperature of said semiconductor switching element.

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