JP2022137550A - Measuring circuit and electro-optical device - Google Patents

Abstract

To measure the voltage change amount of a signal to be measured by using a comparator even if the voltage of the signal to be measured is higher than the withstanding voltage of the comparator.SOLUTION: A measuring circuit 10 comprises a comparator Cmp that compares the voltage of a node C and the voltage of a signal Vref_B with each other. In a first period, the voltage of a signal to be measured is a voltage before change and a first voltage is applied to the node C. In a second period after the first period, the voltage of the first signal to be measured becomes a voltage after change and the first voltage of the node C changes to a second voltage. The second voltage is a voltage obtained by adding, to the first voltage, a compressed amount of the voltage change amount in the first signal to be measured.SELECTED DRAWING: Figure 1

Description

The present invention relates, for example, to measuring circuits and electro-optical devices.

As a technique for measuring or comparing voltages using elements such as transistors formed on a semiconductor substrate, for example, the technique described in Japanese Unexamined Patent Application Publication No. 2002-200316 can be cited. Specifically, in Patent Document 1, in an AD converter provided on a semiconductor substrate, a voltage generated in a capacitive element that constitutes the AD converter and a voltage generated in a capacitive element for inspection are formed on the same semiconductor substrate. Comparison is performed by a comparison circuit composed of transistors.

JP 2015-128203 A

However, in the technique described in Patent Document 1, the voltage of the signal under measurement is directly applied to the comparison circuit, so the breakdown voltage of the transistor that constitutes the comparison circuit is required to be equal to or higher than the voltage of the signal under measurement. . A transistor with a high withstand voltage is larger in size than a transistor with a low withstand voltage, and the area of the semiconductor substrate is enlarged accordingly. In addition, a high-voltage transistor has problems such as a smaller current/voltage amplification factor and a slower operation than a low-voltage transistor.

A measurement circuit according to one aspect of the present disclosure is a measurement circuit that measures a voltage change amount of a first signal under measurement supplied to a first input node, and compares the voltage of a comparison node with a predetermined reference voltage. a comparing circuit, wherein during a first period the voltage of the first signal under measurement is the voltage before the change, the first voltage is applied to the comparison node, and during the second period after the first period, the The voltage of the first signal under measurement is a changed voltage, the comparison node changes from the first voltage to a second voltage, the second voltage is the first voltage, and the first signal under measurement is The first voltage, the second voltage, and the reference voltage are lower than the voltage of the first signal under measurement, and the voltage of the transistor included in the comparison circuit A breakdown voltage is a voltage that is equal to or higher than the first voltage, the second voltage, and the reference voltage and is lower than the voltage of the first signal under measurement, and the transistors included in the comparison circuit are included in the same semiconductor substrate. .

3 is a circuit diagram showing the configuration of a measurement circuit in the integrated circuit according to the first embodiment; FIG. FIG. 4 is a diagram showing the operation of the measurement circuit; FIG. 7 is a circuit diagram showing the configuration of a measurement circuit in the integrated circuit according to the second embodiment; FIG. 11 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a third embodiment; FIG. 11 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a fourth embodiment; FIG. 14 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a fifth embodiment; FIG. 14 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a sixth embodiment; FIG. 11 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a seventh embodiment; FIG. 20 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to an eighth embodiment; FIG. 21 is a circuit diagram showing the configuration of a measurement circuit in an integrated circuit according to a ninth embodiment; FIG. 20 is a circuit diagram showing the configuration of a measurement circuit in the integrated circuit according to the tenth embodiment; FIG. 20 is a circuit diagram showing the configuration of a measurement circuit in the integrated circuit according to the eleventh embodiment; It is a figure which shows the electrical structure of a display apparatus. 1 is a perspective view showing a display device to which an integrated circuit is applied; FIG. 1 is a diagram showing a configuration of a pixel circuit in a display device; FIG. 1 is a diagram showing the configuration of an integrated circuit in a display device; FIG. 3 is a diagram showing the configuration of a driver circuit in an integrated circuit; FIG. FIG. 10 is a diagram showing an electrical configuration of another display device;

Preferred embodiments of the present invention will be described below with reference to the drawings. It should be noted that the embodiments described below do not unduly limit the scope of the invention described in the claims. Moreover, not all the configurations described below are essential constituent elements of the present invention.

[First embodiment]
FIG. 1 is a circuit diagram of a measurement circuit 10 according to the first embodiment. It should be noted that the elements forming the measuring circuit 10 are part of an integrated circuit cut out from the same semiconductor substrate.
As shown in FIG. 1, the measurement circuit 10 includes capacitive elements CL_1 and CL_2, a switch Swrb, a comparison circuit Cmp and a control circuit 120. FIG. A voltage of the signal Vin to be measured is applied to one end of the capacitive element CL_1. In this embodiment, the amount of voltage change, etc. of the signal Vin is measured.

A voltage of the signal Vref_C is applied to one end of the switch Swrb, and one end of the capacitive element CL_2 is grounded to the potential Gnd, which is a zero voltage reference. Note that one end of the capacitive element CL_2 is not limited to the potential Gnd, and may be kept at the same potential that is substantially constant over time.

The other end of the capacitive element CL_1, the other end of the switch Swrb, and the other end of the capacitive element CL_2 are commonly connected to the positive input terminal (+) of the comparison circuit Cmp. The voltage of the signal Vref_B is applied to the negative input terminal (-) of the comparison circuit Cmp.
When the capacitance size of the capacitive element CL_1 is denoted as C1 and the capacitance size of the capacitive element CL_2 is denoted as C2, the capacitance ratio C1:C2 is 9:1 in this embodiment. For convenience of explanation, the node C is the other end of the capacitive element CL_1, the other end of the switch Swrb, the other end of the capacitive element CL_2, and the positive input terminal (+) of the comparison circuit Cmp.

Switch Swrb is controlled to be on or off according to control circuit 120 . When the switch is turned on, it means that one end and the other end are closed and conducting, or that the switch is in a low impedance state. or in a high impedance state. The switch Swrb is composed of, for example, a MOS transistor that turns on or off between the source and drain nodes according to the voltage of the gate node.
The control circuit 120 may set the voltages of the signals Vref_B and Vref_C in addition to turning on or off the switch Swrb. You may

The comparison circuit Cmp compares the voltage applied to the positive input terminal (+) with the voltage of the signal Vref_B applied to the negative input terminal (-), and outputs a signal Cout indicating the comparison result. Specifically, if the voltage of the positive input terminal (+) is equal to or higher than the voltage of the signal Vref_B, the comparison circuit Cmp outputs the signal Cout at H level, and the voltage of the positive input terminal (+) is less than the voltage of the signal Vref_B. If so, the signal Cout is output at L level.

The power supply voltage of the comparison circuit Cmp is, for example, 1.8 V (volt), although not shown. When the power supply voltage of the comparison circuit Cmp is 1.8V, the H level is 1.8V and the L level is 0 volt among the logic levels of the signal Out indicating the comparison result.
Although the equivalent circuit of the comparison circuit Cmp is not particularly illustrated, the withstand voltage of the transistors forming the comparison circuit Cmp is designed to be equal to or higher than the voltage applied to the node C and equal to or higher than the voltage of the signal Vref_B. .

The signal Vin is an example of the first signal under measurement, one end of the capacitive element CL_1 is an example of a first input node, and one end of the capacitive element CL_2 is an example of a fixed potential node. The positive input terminal (+) of the comparison circuit Cmp, ie node C, is an example of a comparison node. The voltage of signal Vref_B is an example of a predetermined reference voltage. Capacitive element CL_1 is an example of a first capacitive element, and capacitive element CL_2 is an example of a second capacitive element.

Next, operation of the measurement circuit 10 according to the first embodiment will be described.
The basic operation of the measurement circuit 10 is divided into a first period operation and a second period operation. First, assume that the voltage of signal Vin is 5.000 V in the first period. 1, the control circuit 120 turns on the switch Swrb to set the voltage of the signal Vref_B to 0.910V and the voltage of the signal Vref_C to 0.900V in the first period.
In the first period, the voltage of the negative input terminal (-) of the comparison circuit Cmp is 0.910 V, while the voltage of the positive input terminal (+), that is, the node C is 0.900 V, so the signal Cout is low. be the level.

In the next second period, control circuit 120 turns off switch Swrb, as shown in FIG. Also assume that the voltage of signal Vin changes to 5.020V.
When the signal Vin rises by the voltage ΔVin, the voltage Vc at the node C rises by ΔVc corresponding to the capacitance ratio of the capacitive elements CL_1 and CL_2 with respect to the voltage ΔVc. .
Vc = 0.900 + ΔVc
=0.900+{ΔVin×C1/(C1+C2)} (1)
In equation (1), ΔVin is 0.020V and the term C1/(C1+C2) is 9/10, so the voltage Vc in the second period is 0.918V.
Therefore, in the second period, the voltage of the negative input terminal (-) is 0.910 V, while the voltage of the node C is 0.918 V. Therefore, the logic level of the signal Cout changes from the L level in the first period to Inverts to H level.

Note that the voltage of 0.900 V applied to the positive input terminal (+) in the first period is an example of the first voltage. A voltage of 0.918 V applied to the positive input terminal (+) in the second period, more specifically, a voltage of 0.020 V, which is the voltage change of the signal Vin, multiplied by 9/10 of the capacitance ratio and compressed to 0 An example of the second voltage is 0.918V obtained by adding 0.018V to 0.900V before the change. Also, the switch Swrb is an example of an initial switch, and one end of the switch Swrb is an example of a reference node.

If the voltage rise of the signal Vref_C is not 0.020 V but is less than 0.011 V, the voltage of the node C is less than 0.910 V, so the logic level of the signal Cout is maintained at L level without being inverted. be.
In other words, when the amount of voltage increase of the signal Vin is unknown, the control circuit 120 may obtain the amount of voltage increase of the signal Vin by changing the voltage of the signal Vref_B. Specifically, the control circuit 120 gradually changes the voltage of the signal Vref_B, and when the voltage of the signal Vref_B is b (V) and the logic level of the signal Cout is inverted to H level, ΔVin, which is the amount of voltage increase of signal Vin, can be obtained by the following equation (2).
ΔVin=(b−0.900)×10/9 (1)
In the above example, when the voltage b of the signal Vref_B is 0.918 V in the second period and the logic level of the signal Cout is inverted, the voltage increase ΔVin of the signal Vin is 0.020 V. can ask.

In this embodiment, the voltage change in signal Vin is compressed at node C according to the capacitance ratio of capacitive elements CL_1 and CL_2.
Therefore, even if the voltage before and after the change in the signal Vin is higher than the withstand voltage of the transistor forming the comparison circuit Cmp, the voltage at the positive input terminal (+) of the comparison circuit Cmp, that is, at the node C is the power source of the comparison circuit Cmp. lower than the voltage. It should be noted that the voltage of the signal Vref_B at the negative input terminal (-) of the comparison circuit Cmp is set lower than the withstand voltage of the transistor that constitutes the comparison circuit Cmp, as described above.
As described above, according to the present embodiment, even if the voltage before and after the change in the signal Vin is higher than the withstand voltage of the transistor forming the comparison circuit Cmp, the amount of voltage change in the signal Vin can be obtained using the comparison circuit Cmp. can. In other words, the breakdown voltage of the transistor that constitutes the comparison circuit Cmp can be made smaller than the voltage before and after the change in the signal Vin.

In order to directly input the voltage of the signal Vin to the comparison circuit Cmp without compressing it, it is conceivable to simply configure the comparison circuit Cmp with a high withstand voltage transistor. However, a high-voltage transistor has a low current/voltage amplification factor and does not operate at a high speed as compared to a low-voltage transistor, and thus has a small gain-bandwidth product (GB product). Therefore, high accuracy and high sensitivity cannot be expected from a comparison circuit composed of high-voltage transistors.
On the other hand, in the present embodiment, the comparison circuit Cmp can be configured with a transistor having a withstand voltage lower than the voltage of the signal to be measured, so that the comparison circuit Cmp can be made highly accurate and highly sensitive. Become.
Note that the withstand voltage of a transistor is determined by the thickness of a gate oxide film forming the transistor.

The voltages of the signals Vref_B and Vref_C can be appropriately changed within the withstand voltage of the transistors forming the comparison circuit Cmp.
Further, in this embodiment, it goes without saying that not only the voltage rise of the signal Vin but also the voltage drop is obtained. That is, the term "addition" used in this description is used in a broad sense, and includes not only addition but also subtraction of adding a negative value.
In addition, in this embodiment, it is possible to obtain not only the amount of voltage change ΔV but also the capacitance ratio of the capacitive elements CL_1 and CL_2. Specifically, if the voltage change amount ΔV is known, the capacitance ratio can be obtained from the known ΔV by modifying equation (1).

[Second embodiment]
In the first embodiment, the voltage change amount of only the signal Vin is obtained, but the voltage change amount of two or more different signals may be obtained as in the following second embodiment.

FIG. 3 is a circuit diagram of the measurement circuit 10 according to the second embodiment. In the second embodiment, switches Swra1 and Swra2 are provided as compared to the first embodiment shown in FIG. Specifically, the signal Vin1 is supplied to one end of the switch Swra1, and the signal Vin2 is supplied to one end of the switch Swra2. The other end of the switch Swra1 and the other end of the switch Swra2 are connected to one end of the capacitive element CL_1.

In the second embodiment, when obtaining the voltage change amount of the signal Vin1, the control circuit 120 turns on only the switch Swra1 among the switches Swra1 and Swra2. Further, when obtaining the voltage change amount of the signal Vin2, the control circuit 120 turns on only the switch Swra2 among the switches Swra1 and Swra2.
Therefore, according to the second embodiment, it is possible to selectively obtain the voltage change amounts of the signals Vin1 and Vin2. In FIG. 3, the voltage change amounts of the signals Vin1 and Vin2 are obtained, but a switch may be added to obtain the voltage change amounts of three or more signals.

The switch Swra1 is an example of a first input switch, and the switch Swra2 is an example of a second input switch. The end of the switch Swra2 to which the signal Vin2 is supplied is an example of the second input node, and the signal Vin2 is an example of the second signal under measurement.

[Third embodiment]
In the first embodiment, ΔVc indicating the voltage change of the node C is a constant value obtained by multiplying ΔVin of the voltage change of the signal Vin by a coefficient according to the capacitance ratio of the capacitive elements CL_1 and CL_2. Therefore, when ΔVin is small, ΔVc is also small, and the measurement sensitivity may be lowered. Therefore, a third embodiment capable of improving the measurement sensitivity will be described next.

FIG. 4 is a circuit diagram of the measurement circuit 10 according to the third embodiment. In the third embodiment, compared with the first embodiment shown in FIG. 1, a switch Swrc and a capacitive element CL_3 are provided. Specifically, one end of the capacitive element CL_3 is connected to one end of the capacitive element CL_1, the other end of the capacitive element CL_3 is connected to one end of the switch Swrc, and the other end of the switch Swrc is connected to the node C.

In the third embodiment, if the switch Swrc is off, the operation is the same as in the first embodiment.
On the other hand, if the switch Swrc is on, the capacitive elements CL_1 and CL_3 are connected in parallel. When the capacitance size of the capacitive element CL_3 is denoted as C3, the term C1/(C1+C2) in equation (1) is replaced with the term (C1+C3)/(C1+C2+C3).
Therefore, in the third embodiment, even if the voltage change amount ΔVin is the same as in the first embodiment, the voltage change amount ΔVc at the node C is increased, so that the measurement sensitivity can be improved. can be done.

Note that the capacitive element CL_3 is an example of a third capacitive element, and the switch Swrc is an example of a selection switch. Also, since the capacitive element CL_3 and the switch Swrc may be provided between one end of the capacitive element CL_1 and the node C, the connections are exchanged so that one end of the switch Swrc is connected to one end of the capacitive element CL_1, and the capacitive element CL_3 is connected to one end of the capacitive element CL_3. may be connected to node C.

[Fourth embodiment]
In the third embodiment, the configuration is such that the measurement sensitivity is improved, but conversely, a configuration is also possible in which the measurement sensitivity is reduced. Therefore, a fourth embodiment capable of reducing the measurement sensitivity will be described next.

FIG. 5 is a circuit diagram of the measurement circuit 10 according to the fourth embodiment. In comparison with the first embodiment shown in FIG. 1, the fourth embodiment is provided with a switch Swrc and a capacitive element CL_3 as in the third embodiment. However, the fourth embodiment differs from the third embodiment in that the switch Swrc and the capacitive element CL_3 are provided. Specifically, one end of the switch Swrc is connected to the node C, the other end of the switch Swrc is connected to one end of the capacitive element CL_3, connected to one end of the capacitive element CL_3, and the other end of the capacitive element CL_3 is grounded to the potential Gnd. be done.

In the fourth embodiment, if the switch Swrc is off, the operation is the same as in the first embodiment.
On the other hand, if the switch Swrc is on, the capacitive elements CL_2 and CL_3 are connected in parallel. When the capacitance size of the capacitive element CL_3 is denoted by C3, the term C1/(C1+C2) in equation (1) is replaced with the term C1/(C1+C2+C3).
Therefore, in the fourth embodiment, compared to the first embodiment, even if the voltage change amount ΔVin is the same, the voltage change amount ΔVc at the node C is smaller, so that the measurement sensitivity is reduced. can be done.

Also in the fourth embodiment, the capacitive element CL_3 and the switch Swrc may be provided between one end of the capacitive element CL_2 and the node C, so the series connection shown in FIG. 5 may be exchanged.

[Fifth embodiment]
Although the sensitivity is improved in the third embodiment and the sensitivity is lowered in the fourth embodiment, it is also possible to combine them. Therefore, next, a fifth embodiment, which is a combination of the third embodiment and the fourth embodiment, will be described.

FIG. 6 is a circuit diagram of the measurement circuit 10 according to the fifth embodiment. In the sixth embodiment, switches Swrc1, Swrc2 and a capacitive element CL_3 are provided as compared with the first embodiment shown in FIG.
In the fifth embodiment, one end of the switch Swrc1 is connected to one end of the capacitive element CL_1, and the other end of the switch Swrc1 is connected to one end of the capacitive element CL_3. A signal Vref_D is supplied to one end of the switch Swrc2, and the other end of the switch Swrc2 is connected to one end of the capacitive element CL_3. The other end of switch Swrc3 is connected to node C.
Note that the voltage of the signal Vref_D is arbitrary as long as it is substantially constant over time, and may be the potential Gnd, for example.

The fifth embodiment operates in the same manner as the first embodiment if the switches Swrc1 and Swrc2 are off.
Further, the measurement circuit 10 according to the fifth embodiment operates in the same manner as in the third embodiment when the switch Swrc1 is on and the switch Swrc2 is off. If there is, it operates in the same manner as in the fourth embodiment.
That is, in the fifth embodiment, the switches Swrc1 and Swrc2 should be exclusively turned on.

On the other hand, instead of supplying the signal Vref_D to one end of the switch Swrc2, one end of the switch Swrc2 may be used as a terminal for outputting to the outside of the integrated circuit. In this configuration, when the switches Swrc1 and Swrc2 are on, the signal Vin is output to the corresponding terminal. Therefore, if a measuring device or the like other than the integrated circuit is connected to the terminal, the measuring device or the like can measure the voltage of the signal Vin.
That is, in the fifth embodiment, switches Swrc1 and Swrc2 may be turned on at the same time.

The switch Swrc1 is an example of a first selection switch, and the switch Swrc2 is an example of a second selection switch.

[Sixth Embodiment]
In an actual integrated circuit, each part has a parasitic capacitance. In particular, in the measurement circuit 10, the voltage of the node C is affected when the capacitance parasitic on the supply path of the signal Vin is large. Therefore, a sixth embodiment in which the influence of parasitic capacitance is reduced will be described next.

FIG. 7 is a circuit diagram of the measurement circuit 10 according to the sixth embodiment. In the sixth embodiment, compared to the second embodiment shown in FIG. 3, it includes impedance transformers Imc1 and Imc2. The impedance converter Imc1 is a non-inverting amplifier circuit. Specifically, the impedance converter Imc1 has a positive input terminal (+) supplied with the signal Vin1, and an output terminal connected to one terminal of the switch Swra1 and a negative input terminal (-). Impedance converter Imc2, like impedance converter Imc1, is a non-inverting amplifier circuit. Specifically, the impedance converter Imc2 has a positive input terminal (+) supplied with the signal Vin2, and an output terminal connected to one terminal of the switch Swra2 and a negative input terminal (-).

In the sixth embodiment, the switch Swra1 is turned on by the control circuit when measuring the amount of voltage change of the signal Vin1, for example. The supply path of the signal Vin1 is converted to low impedance by the impedance converter Imc1, and the signal Vin1 is supplied to one end of the capacitive element CL_1. Therefore, one end of the capacitive element CL_1 is disconnected from the supply path of the signal Vin1. Therefore, according to the sixth embodiment, the capacitive element CL_1 is less susceptible to the parasitic capacitance in the supply path of the signal Vin1.
If the capacitance size C1 of the capacitive element CL_1 is relatively small, the parasitic capacitance in the supply path of the signal Vin1 adversely affects the voltage at the node C, degrading the measurement accuracy. On the other hand, according to the sixth embodiment, one end of the capacitive element CL_1 is separated from the supply path of the signal Vin1, so that the effect of the parasitic capacitance on the supply path of the signal Vin1 is reduced, resulting in a decrease in measurement accuracy. can be suppressed.
Here, for example, the case of measuring the amount of voltage change of the signal Vin1 has been described, but the same applies to the case of measuring the amount of voltage change of the signal Vin2. Also, the impedance converter Imc1 is an example of a first impedance converter, and the impedance converter Imc2 is an example of a second impedance converter.

[Seventh embodiment]
FIG. 8 is a circuit diagram of the measurement circuit 10 according to the seventh embodiment. In the seventh embodiment, compared to the second embodiment shown in FIG. 3, it includes an impedance converter Imc. The impedance converter Imc is, for example, a non-inverting amplifier circuit like the impedance converters Imc1 and Imc2 in the sixth embodiment.
In the seventh embodiment, the signal Vin1 is supplied to the input terminal of the impedance converter Imc through the switch Swra1_1, and the signal Vin2 is supplied to the input terminal of the impedance converter Imc through the switch Swra1_2. An output end of the impedance converter Imc is connected to one end of the capacitive element CL_1.

In the seventh embodiment, for example, when measuring the voltage change amount of the signal Vin1, the control circuit 120 turns on the switch Swra1_1 and turns off the switch Swra1_2. When measuring the voltage change amount of the signal Vin2, the control circuit 120 turns off the switch Swra1_1 and turns on the switch Swra1_2.
In the seventh embodiment, since the supply path of the signal Vin1 and the supply path of the signal Vin2 are impedance-converted by the common impedance converter Imc, they are individually impedance-converted by the impedance converters Imc1 and Imc2 as in the sixth embodiment. Compared to the configuration, it is less susceptible to characteristic differences in the impedance converter.
Therefore, according to the seventh embodiment, it is possible to improve the accuracy when switching the signals Vin1 and Vin2 for measurement.

[Eighth embodiment]
FIG. 9 is a circuit diagram of the measurement circuit 10 according to the eighth embodiment.
In the measurement circuit 10 according to the eighth embodiment, the signal Vin1 in the sixth embodiment shown in FIG. 7 is divided into two signals Vin1_1 and Vin1_2. In the eighth embodiment, the signal Vin1_1 is supplied to the input terminal of the impedance converter Imc1 through the switch Swra1_1, and the signal Vin1_2 is supplied to the input terminal of the impedance converter Imc1 through the switch Swra1_2.
According to the eighth embodiment, the signals Vin1_1 or Vin1_2 and the signals Vin2 can be switched by the switches Swra1 and Swra2, and either the signals Vin1_1 or Vin1_2 can be switched by the switches Swra1_1 and Swra1_2.
Also, the supply path of the signal Vin1_1 or the supply path of the signal Vin1_2 is converted to low impedance by the impedance converter Imc1, and the supply path of the signal Vin2 is converted to low impedance by the impedance converter Imc2.
Therefore, according to the eighth embodiment, the effect of the parasitic capacitance in the supply paths of the signals Vin1_1, Vin1_2, and Vin2 is less likely to be exerted, thereby suppressing deterioration in measurement accuracy.

The switch Srwa1 is an example of a first changeover switch, the switch Srwa2 is an example of a second changeover switch, and the supply path of the signal Vin1_2 is an example of a third input node.

[Ninth Embodiment]
FIG. 10 is a circuit diagram of the measurement circuit 10 according to the ninth embodiment.
In the ninth embodiment, compared to the first embodiment shown in FIG. 1, an impedance converter Imc and terminals Ext_N are provided. The impedance converter Imc is, for example, the non-inverting amplifier circuit described above, and converts one end of the capacitive element CL_1 to low impedance. The terminal Ext_N is connected to the output end of the impedance converter Imc.

According to the ninth embodiment, the signal Vin supplied to one end of the capacitive element CL_1 is amplified by the impedance converter Imc and output to the terminal Ext_N. Therefore, if the terminal Ext_N is connected to a measuring instrument or the like other than the integrated circuit, the signal Vin can be monitored by the measuring instrument or the like.

[Tenth embodiment]
FIG. 11 is a circuit diagram of the measurement circuit 10 according to the tenth embodiment.
In the tenth embodiment, a switch Swo is provided as compared to the ninth embodiment shown in FIG. Specifically, the switch Swo is provided between one end of the capacitive element CL_1 and the terminal Ext_N, and is controlled to be on or off by the control circuit 120 .

When the switch Swo is off, one end of the capacitive element CL_1, ie, the supply path of the signal Vin, is converted to low impedance and output to the terminal Ext_N, as in the ninth embodiment. Therefore, if the terminal Ext_N is connected to a measuring instrument or the like other than the integrated circuit, the signal Vin can be monitored by the measuring instrument or the like.
On the other hand, if the switch Swo is on, it becomes possible to apply a predetermined voltage to one end of the capacitive element CL_1 through the terminal Ext_N by a measuring instrument or the like other than the integrated circuit. Therefore, it is possible to inspect the circuits connected after the comparison circuit Cmp in the integrated circuit by the signal output from the measuring instrument or the like.
Note that the switch Swo is an example of an external supply switch.

[Eleventh embodiment]
FIG. 12 is a circuit diagram of the measurement circuit 10 according to the eleventh embodiment.
In the twelfth embodiment, a terminal Ext_N is provided as compared to the seventh embodiment shown in FIG. The terminal Ext_N is connected to one end of the capacitive element CL_1, that is, the output end of the impedance converter Imc.

In the eleventh embodiment, when the switch Swra1_1 is on and the switch Swra1_2 is off, the impedance converter Imc converts the supply path of the signal Vin1 to a low impedance, and the output signal of the impedance converter Imc is transferred to the capacitive element CL_1. and terminal Ext_N. If a measuring instrument or the like separate from the integrated circuit is connected to the terminal Ext_N, the signal Vin1 can be monitored by the measuring instrument or the like. becomes possible.
In the eleventh embodiment, when the switch Swra1_1 is off and the switch Swra1_2 is on, the impedance converter Imc converts the supply path of the signal Vin2 to a low impedance, and the output signal of the impedance converter Imc is transferred to the capacitive element CL_1. and terminal Ext_N. If a measuring instrument or the like other than the integrated circuit is connected to the terminal Ext_N, the signal Vin2 can be monitored by the measuring instrument or the like. becomes possible.

In addition, in the measurement circuit 10 according to the above-described first to eleventh embodiments, it is also possible to understand it as a measurement method.

[Example of application to display device]
Next, a display device to which an integrated circuit including the measurement circuit 10 is applied will be described.
13 is a block diagram showing the electrical configuration of the display device DM, FIG. 14 is a perspective view showing the configuration of the display device DM excluding the printed circuit board 40, and FIG. 15 is a display device. 3 is a diagram showing a pixel circuit 210 of the liquid crystal panel 20 that constitutes DM. FIG.

As shown in FIG. 13, the display device DM includes a liquid crystal panel 20, an FPC board 30 and a printed circuit board 40. FIG. Note that FPC is an abbreviation for Flexible Printed Circuits.
The liquid crystal panel 20 is of a transmissive type used, for example, as a light valve of a liquid crystal projector. A Y driver 230 is provided on the periphery of the display area 200 in the liquid crystal panel 20 . In the display area 200, pixel circuits 210 corresponding to pixels of an image to be displayed are arranged in a matrix. More specifically, in the display area 200, a plurality of scanning lines 212 are provided extending in the X direction in the figure, and a plurality of data lines 214 are provided extending in the Y direction, and the scanning lines 212 and 214 are provided. They are provided while maintaining electrical insulation from each other. Pixel circuits 210 are provided at intersections of the plurality of scanning lines 212 and the plurality of data lines 214 .

When the number of scanning lines 212 is m and the number of data lines 214 is n, the pixel circuits 210 are arranged in a matrix of m rows (vertical) and n columns (horizontal). Both m and n are integers of 2 or more. In order to distinguish the rows of the matrix in the scanning lines 212 and the pixel circuits 210, the rows are sometimes referred to as 1, 2, 3, . Similarly, in the data line 24 and the pixel circuit 210, in order to distinguish the columns of the matrix, they may be referred to as columns 1, 2, 3, .
The Y driver 230 selects the scanning lines 212 one by one in the order of, for example, the 1st, 2nd, 3rd, . is set to H level. Note that the Y driver 230 sets the scanning signal to the scanning lines 212 other than the selected scanning line 212 to L level.

For convenience of explanation, the configuration of the pixel circuit 210 will be explained.
As shown in FIG. 15, pixel circuit 210 includes transistor 216 and liquid crystal element 220 . The transistor 216 is, for example, an n-channel transistor. In pixel circuit 210 , the gate node of transistor 216 is connected to scan line 212 . The source node of transistor 216 is connected to data line 214 . A drain node of the transistor 216 is connected to a pixel electrode 218 patterned in a substantially square shape in plan view.

A common electrode 208 is commonly provided for all pixels so as to face the pixel electrode 218 . A voltage LCcom is applied to the common electrode 208 . A liquid crystal 205 is sandwiched between the pixel electrode 218 and the common electrode 208 . Therefore, for each pixel circuit 210 , the pixel electrode 218 , common electrode 208 and liquid crystal 205 form a liquid crystal element 220 .

As will be described later, in a horizontal scanning period in which a scanning signal to one scanning line 212 is at H level, pixels to be represented by the pixel circuit 210 are directed to the pixel circuit 210 located on the scanning line 212. A data signal having a voltage corresponding to the gradation is supplied to the data line 214 corresponding to the pixel circuit 210 concerned.

In the scanning line 212 for which the scanning signal has become H level, the transistor 216 of the pixel circuit 210 provided corresponding to the scanning line 212 is turned on. Since the data line 214 and the pixel electrode 218 are electrically connected by turning on the transistor 216, the data signal supplied to the data line 24 reaches the pixel electrode 218 via the turned-on transistor 216. . When the scanning line 212 becomes L level, the transistor 216 is turned off, but the voltage of the data signal that has reached the pixel electrode 218 is held by the capacitive properties of the liquid crystal element 220 and a storage capacitor (not shown).

As is well known, in the liquid crystal element 220 , the alignment state of the liquid crystal 205 changes according to the electric field generated by the pixel electrode 218 and the common electrode 208 . Specifically, the liquid crystal element 220 has a transmittance (optical state) corresponding to the effective value of the applied voltage. Therefore, in the liquid crystal panel 20 , the transmittance changes for each liquid crystal element 220 of the pixel circuit 210 .
Such a voltage holding operation to the liquid crystal elements 220 is performed in the order of the 1st, 2nd, 3rd, . A voltage corresponding to the data signal is held. By maintaining such a voltage, each of the liquid crystal elements 220 has a target transmittance, and an image composed of pixels arranged in m rows and n columns is generated.

As shown in FIG. 14, the integrated circuit 1 is a substantially rectangular parallelepiped semiconductor chip, and is mounted on the FPC board 30 by face-down bonding. The liquid crystal panel 20 is housed in a frame-shaped case 22 that opens in the display area.
One end of the FPC board 30 is connected to the liquid crystal panel 20 . The other end of the FPC board 30 is connected to the printed board 40 .

Returning to FIG. 13 again, the printed circuit board 40 includes a control circuit 400 . The control circuit 400 receives grayscale data and a synchronization signal from a higher-level circuit (not shown). The gradation data digitally specifies the gradation level of each pixel in an image to be displayed on the liquid crystal panel 20, for example, in 8 bits.
The control circuit 400 supplies a control signal generated based on the synchronization signal to the Y driver 230 via the FPC board 30 .
The control circuit 400 also supplies the integrated circuit 1 with a control signal generated according to the gradation data and the synchronization signal.

In addition to the measurement circuit 10 according to any one of the first to eleventh embodiments described above, the integrated circuit 1 generates an analog data signal based on the gradation data for one row and supplies it to each of the data lines 214. Contains driver circuits that

FIG. 16 is a block diagram showing the configuration of the integrated circuit 1. As shown in FIG. The integrated circuit 1 includes a measurement circuit 10, a plurality of driver circuits Drv, a data input circuit 12 and a data controller .
The driver circuits Drv are provided in one-to-one correspondence with the data lines 214 . When the number of data lines 214 is n, the number of driver circuits Drv is also n.
The data input circuit 12 is an interface for inputting gradation data and synchronization signals supplied from the control circuit 400 via the FPC board 30 . The data controller 14 distributes the gradation data supplied via the data input circuit 12 to the n driver circuits Drv according to the synchronization signal supplied via the data input circuit 12 .

The n driver circuits Drv are arranged along the long side of the integrated circuit 1 . As shown in FIGS. 13 and 14, the integrated circuit 1 is mounted on the FPC board 30 so that the long side of the integrated circuit 1 extends along the X direction, which is the direction in which the scanning lines 212 extend. The driver circuits Drv are also provided along the extending direction of the scanning lines 212 .

The measurement circuit 10 is provided in the integrated circuit 1 next to a region in which n driver circuits Drv are arranged along the extending direction of the scanning line 212 . The measurement circuit 10 measures the amount of voltage change in the signal output from each part of the n driver circuits Drv, and adjusts the parameters in each of the n driver circuits Drv based on the measurement results. Examples of parameters will be described later.

One driver circuit Drv latches grayscale data supplied corresponding to the column of the driver circuit Drv and converts the grayscale data into an analog data signal. Note that each of the n driver circuits Drv simultaneously outputs the converted data signal in accordance with the selection of the scanning line 212 by the Y driver 230 .

FIG. 17 is a diagram showing a schematic configuration of the driver circuit Drv provided corresponding to the data line 214 of the j-th column. The driver circuit Drv includes an arithmetic circuit Air_j, a latch circuit Lat_j, a DA converter circuit Dac_j, and an amplifier circuit Amp_j.
Arithmetic circuit Air_j performs computations and the like on the gradation data supplied corresponding to the j-th column. Examples of this calculation include four arithmetic calculations and conversions for suppressing variations in the liquid crystal panel 20 .
The latch circuit Lat_j latches the gradation data that has been subjected to computation until the scanning line 212 is selected by the Y driver 230 .
The DA conversion circuit Dac_j converts the latched grayscale data into an analog signal. As the DA conversion circuit Dac_j, for example, the driver described in Japanese Patent Application Laid-Open No. 2016-80805 or the driver described in Japanese Patent Application Laid-Open No. 2016-90882 has a configuration that changes to an analog signal using a capacitive element. can be adopted. The measurement circuit 10 measures the amount of voltage change and the capacitance ratio of the signal converted to analog by the DA conversion circuit Dac_j having such a configuration.
The amplifier circuit Amp_j appropriately amplifies the analog-converted signal and outputs it as a data signal to the j-th data line 214 .

In FIG. 17, the elements of the arithmetic circuit Air_j, the latch circuit Lat_j, the DA conversion circuit Dac_j, and the amplifier circuit Amp_j are not connected to each other because another element may be interposed between these elements. to show.

Among the signals generated inside the driver circuit Drv, the signal to be measured by the measurement circuit 10 is arbitrary. A data signal that is amplified and output to data line 214 is considered.
When a signal or data signal converted to analog by the DA conversion circuit Dac_j is to be measured, the measurement circuit 10 changes the gradation data regardless of the gradation data supplied from the host device during the non-display period. Then, the amount of voltage change in the signal accompanying the change in the gradation data can be measured.
In the liquid crystal panel 20, the darker the gradation, the greater the amount of voltage change in the data signal. Therefore, when the output signal of the DA conversion circuit Dac_j or the output signal of the amplification circuit Amp_j is to be measured, it is preferable to change the gradation data of the low gradation.
Since the measurement circuit 10 selects the signal to be measured in a time division manner, any one of the second, sixth, seventh, eighth and eleventh embodiments is applied in practice. That is, in the second embodiment, the measurement circuit 10 selects a signal to be measured by the switches Swra1 to Swrn in a time division manner, and measures the voltage change amount of the selected signal.
The switches Swra1 to Swrn mean switches provided corresponding to each of the 1st to n-th driver circuits Drv. Moreover, as described above, not only the amount of voltage change but also the capacitance ratio may be measured.
When measuring the capacitance ratio, the configuration is such that the capacitive elements CL_1 and CL_2 to be measured in the driver circuit Drv are sequentially selected by a switch (not shown).
Then, the control circuit 120 in the measurement circuit 10 adjusts the parameters of the driver circuit Drv of the column whose voltage variation and capacitance ratio are measured.

Specifically, the control circuit 120 selects the output signal of the j-th DA conversion circuit Dac_j or the output signal of the amplification circuit Amp_j as the object to be measured, and determines the amount of voltage change of the signal and the capacitance of the DA conversion circuit Dac_j. When a ratio (expressed as a voltage change amount, etc.) is measured, the calculation contents of the arithmetic circuit Air_j included in the j-th driver circuit Drv, the gain of the amplifier circuit Amp_j, Adjust the parameters that specify the reference current, reference voltage, etc. in these elements.

The period during which the control circuit 120 measures the amount of voltage change and the like includes a period that does not affect the display, specifically, a horizontal scanning blanking period and a vertical scanning blanking period. The horizontal scanning blanking period is a period from the end of selection of one scanning line 212 to the start of selection of the next one scanning line 212 . The vertical scanning blanking period is a period from the end of selection of the last scanning line 212 in a certain frame to the start of selection of the first scanning line 212 in the next frame.
Generally, the vertical scanning blanking period is longer than the horizontal scanning blanking period, so that it is possible to continuously measure more voltage changes and the like in the vertical scanning blanking period than in the horizontal scanning blanking period.

In the display device DM shown in FIG. 15, the driver circuits Drv corresponding to the data lines 214 on a one-to-one basis supply data signals to the data lines 214, but the configuration is not limited to this. For example, one driver circuit Drv may correspond to the k data lines 214, and the data signals may be supplied to the k data lines 214 in a time division manner in one horizontal scanning period. Note that k is an arbitrary integer of 2 or more.

In the display device DM shown in FIG. 13, the integrated circuit 1 is mounted on the FPC board 30, and the liquid crystal panel 20 and the integrated circuit 1 are separate bodies, but the configuration is not limited to this. For example, as shown in FIG. 18, the function of the integrated circuit 1 may be transferred to the liquid crystal panel 20. FIG. Specifically, the element substrate in the liquid crystal panel 20 may be a semiconductor substrate, and the semiconductor substrate may have the function of the integrated circuit 1 .
The display device DM is applicable not only to the liquid crystal panel 20 but also to an organic EL panel using OLED. In the organic EL panel, it is preferable that the semiconductor substrate constituting the organic EL panel has the function of the integrated circuit 1 .

REFERENCE SIGNS LIST 1 integrated circuit 10 measurement circuit 20 liquid crystal panel 30 FPC board 40 printed circuit board 120 control circuit Vin signal CL_1, CL_2, CL_3 capacitive element Cmp comparator circuit Ext_N terminal.

Claims (15)

A measurement circuit for measuring a voltage change amount of a first signal under measurement supplied to a first input node,
comprising a comparison circuit that compares the voltage of the comparison node with a predetermined reference voltage;
in the first period,
the voltage of the first signal under measurement is a voltage before change;
a first voltage is applied to the comparison node;
During the second period after the first period,
the voltage of the first signal under measurement is a voltage after the change;
the comparison node changes from the first voltage to a second voltage;
the second voltage is a voltage obtained by adding a compressed voltage change amount in the first signal under measurement to the first voltage;
the first voltage, the second voltage and the reference voltage are lower than the voltage of the first signal under measurement;
a transistor included in the comparator circuit has a withstand voltage equal to or greater than the first voltage, the second voltage, and the reference voltage, and less than the voltage of the first signal under measurement;
A measurement circuit in which the transistors included in the comparison circuit are included in the same semiconductor substrate.
a first capacitive element provided between the first input node and the comparison node;
a second capacitive element provided between a fixed potential node and the comparison node;
a reference node to which the first voltage is applied;
an initial switch provided between the reference node and the comparison node;
including
during the first period, the initial switch is turned on;
During the second period, the initial switch is turned off,
2. Based on the comparison result of the comparison circuit in the first period and the comparison result of the comparison circuit in the second period, it is determined whether the voltage change amount of the first signal under measurement is appropriate. Measurement circuit as described.
a first input switch provided between the first input node and the first capacitive element;
a second input switch provided between a second input node supplied with a second signal under measurement and the first capacitive element;
including,
3. A measurement circuit as claimed in claim 2.
including a third capacitive element and a selection switch;
3. The measurement circuit according to claim 2, wherein a series connection of said third capacitive element and said selection switch is provided between said first input node and said comparison node.
including a third capacitive element and a selection switch;
3. The measurement circuit according to claim 2, wherein the series connection of the third capacitive element and the selection switch is provided between a fixed potential node and the comparison node.
including a third capacitive element, a first selection switch and a second selection switch;
the first selection switch is provided between the first input node and the third capacitive element;
the second selection switch is provided between a fixed potential node and the third capacitive element;
the third capacitive element is provided between the first selection switch and the second selection switch and the comparison node;
3. The measurement circuit according to claim 2, wherein said first selection switch and said second selection switch are exclusively turned on or turned on simultaneously.
a first impedance converter provided between the first input node and the first input switch for converting the impedance of the first input node and outputting the result toward the first input switch;
a second impedance converter provided between the second input node and the second input switch for converting the impedance of the second input node and outputting the result toward the second input switch. Item 4. The measurement circuit according to item 3.
is provided between the first input switch and the second input switch and the first capacitive element, converts the impedance of the first input node or the second input node, and directs the impedance toward the first capacitive element 4. The measurement circuit of claim 3, comprising an impedance transformer that outputs a .
including a first changeover switch, a second changeover switch and a third input node;
the first selector switch is provided between the first input node and the first impedance converter;
The second selector switch is provided between the third input node and the first impedance converter,
8. A measurement circuit as claimed in claim 7.
3. The measurement circuit according to claim 2, further comprising an impedance converter that converts the impedance of the first input node and outputs the result to a terminal for external output.
11. The measurement circuit of claim 10, including an externally supplied switch also received between said first input node and said terminal.
8. The measurement circuit according to claim 7, further comprising a terminal for outputting the output signal of said impedance converter to the outside.
a data signal obtained by converting gradation data by a DA conversion circuit is supplied to the first input node as the first signal under measurement;
13. A measurement circuit as claimed in any preceding claim.
14. The measurement circuit according to claim 13, wherein the DA conversion circuit converts the grayscale data into the data signal using a capacitive element.
a measurement circuit according to claim 14;
a data line to which the data signal is supplied;
a pixel circuit connected to the data line;
electro-optical device including

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