JP2022135540A - Transmission device and reception device - Google Patents

Abstract

To provide a transmission device and a reception device capable of appropriately executing convolutional interleave processing even when a modulation multilevel number is adaptively changed.SOLUTION: A transmission device includes an intermediate parallel conversion unit for converting a serial bit string forming a fixed-length error correction block into two or more parallel bit strings, an interleaving unit for applying different delay times to each of the two or more parallel bit strings output from the intermediate parallel conversion unit, a puncturing unit for thinning out predetermined bits of at least a part of two or more parallel bit strings output from the interleaving unit and outputting the two or more parallel bit strings from which the predetermined bits are thinned, an intermediate serial conversion unit for converting the two or more parallel bit strings output from the puncturing unit into serial bit strings, and a parallel conversion unit for converting the serial bit string output from the intermediate serial conversion unit into two or more parallel bit strings whose number is equal to the number of sub carriers.SELECTED DRAWING: Figure 2

Description

The present invention relates to a transmitting device and a receiving device.

A digital wireless transmission system is known that wirelessly transmits a digital signal from a transmitting device (eg, FPU; Field Pickup Unit) to a receiving device (eg, broadcasting station). In the digital radio transmission system, the TDD-SVD-MIMO (Time Division Duplex-Singular Value Decomposition-Multiple-Input Multiple-Output) scheme is under study. In the TDD-SVD-MIMO system, transmission from the transmitter to the receiver is performed by adaptive control that feeds back transmission parameters (for example, the coding rate of the error correction code and the number of modulation levels) from the receiver to the transmitter. large-capacity and stable execution.

On the other hand, generally in a digital wireless transmission system, a process called interleaving is performed to change the order in order to improve the correction capability of the error correction code. Among digital radio transmission systems, especially in systems using OFDM, a technique called convolutional interleaving is often used for bits transmitted in each subcarrier. Convolutional interleaving has the advantage of less delay time required for interleaving than other interleaving methods, and is widely used in FPU systems and digital broadcasting systems. In convolutional interleaving processing, different delay times are applied to OFDM symbols for each subcarrier (for example, Non-Patent Document 1).

"Portable Microwave Band OFDM Digital Wireless Transmission System for Ultra High Definition Television Broadcast Program Material Transmission" Standard ARIB STD-B75 Version 1.0

As a result of intensive studies, the inventors have focused on the necessity of adaptively changing the modulation multilevel number according to the state of the transmission path between the transmitting device and the receiving device. Furthermore, the inventors have found that adaptively changing the modulation multilevel number adaptively changes the number of bits represented by one OFDM symbol, so that the convolutional interleaving process described above can be performed appropriately. I found that I can't.

Therefore, the present invention has been made to solve the above-described problems. The object is to provide a device and a receiving device.

A transmission device according to an aspect of the disclosure includes: an intermediate parallel conversion unit that converts a serial bit string forming a fixed-length error correction block into two or more parallel bit strings; an interleaving unit applying different delay times to each of two or more bit strings; and thinning out predetermined bits of at least part of the two or more parallel bit strings output from the interleaving unit, and parallel thinning out the predetermined bits. a puncturing section that outputs two or more bit strings, an intermediate serial conversion section that converts two or more parallel bit strings output from the puncturing section into serial bit strings, and a serial bit string that is output from the intermediate serial conversion section. into two or more parallel bit strings equal to the number of subcarriers.

A receiver according to an aspect of the disclosure includes a demodulator that demodulates two or more parallel bit strings equal to the number of subcarriers; a conversion unit, an intermediate parallel conversion unit for converting a serial bit string output from the serial conversion unit into two or more parallel bit strings, and predetermined bits for the two or more parallel bit strings output from the intermediate parallel conversion unit and a depuncturing unit that outputs two or more parallel bit strings in which the predetermined bits are interpolated, and a deinterleaving unit that applies different delay times to each of the two or more parallel bit strings output from the depuncturing unit. an intermediate serial converter for converting two or more parallel bit strings output from the deinterleaving unit into serial bit strings; and decoding an error correction block based on the serial bit strings output from the intermediate serial converter. and a decoding unit for decoding.

Advantageous Effects of Invention According to the present invention, it is possible to provide a transmitting device and a receiving device that can appropriately perform convolutional interleaving even when the modulation multilevel number is adaptively changed.

FIG. 1 is a diagram showing a digital wireless transmission system 10 according to an embodiment. FIG. 2 is a block diagram showing the transmitting device 100 according to the embodiment. FIG. 3 is a block diagram showing the receiving device 200 according to the embodiment. FIG. 4 is a diagram for explaining a problem with the conventional technology. FIG. 5 is a diagram for explaining a problem with the conventional technology. FIG. 6 is a diagram for explaining interleaving processing according to the embodiment. FIG. 7 is a diagram for explaining puncturing processing according to the embodiment. FIG. 8 is a diagram for explaining depuncture processing according to the embodiment. FIG. 9 is a diagram for explaining deinterleaving processing according to the embodiment. FIG. 10 is a diagram for explaining the experiment.

Next, embodiments of the present invention will be described. In addition, in the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the ratio of each dimension is different from the actual one.

Therefore, specific dimensions should be determined with reference to the following description. In addition, it goes without saying that there are portions with different dimensional relationships and ratios between the drawings.

[Summary of Disclosure]
A transmission device according to the outline of the disclosure includes an intermediate parallel conversion unit that converts a serial bit string that constitutes a fixed-length error correction block into two or more parallel bit strings, and parallel two bit strings that are output from the intermediate parallel conversion unit. an interleaving unit applying different delay times to each of the above bit strings; and thinning out predetermined bits of at least a part of the two or more parallel bit strings output from the interleaving unit, and parallel processing in which the predetermined bits are thinned out. A puncturing section that outputs two or more bit strings, an intermediate serial conversion section that converts two or more parallel bit strings output from the puncturing section into serial bit strings, and a serial bit string that is output from the intermediate serial conversion section. a parallel conversion unit that converts into two or more parallel bit strings equal to the number of subcarriers.

In the overview of the disclosure, a transmitting device converts a serial bit string that constitutes an error correction block into two or more parallel bit strings before converting a serial bit string into two or more parallel bit strings equal to the number of subcarriers. After that, interleaving processing (hereinafter referred to as convolutional interleaving processing) that applies different delay times to each of the two or more parallel bit strings is performed to return the two or more parallel bit strings to serial bit strings. According to such a configuration, the convolutional interleaving process can be executed without depending on the modulation level, and the convolutional interleaving process can be appropriately executed even when the modulation level is adaptively changed. can do. Furthermore, noting that the error correction block is a fixed-length error correction block, puncturing processing for thinning out predetermined bits is applied to two or more parallel bit strings after convolutional interleaving processing. According to such a configuration, the target coding rate can be adaptively changed at the same time as the modulation multilevel number is adaptively changed.

A receiving apparatus according to an overview of the disclosure includes a demodulator that demodulates two or more parallel bit strings equal to the number of subcarriers, and a serial converter that converts two or more parallel bit strings output from the demodulator into serial bit strings. an intermediate parallel conversion unit for converting a serial bit string output from the serial conversion unit into two or more parallel bit strings; and two or more parallel bit strings output from the intermediate parallel conversion unit. a deinterleaving unit that applies a delay time; and a depuncture that interpolates predetermined bits of two or more parallel bit strings output from the intermediate parallel conversion unit and outputs two or more parallel bit strings in which the predetermined bits are interpolated. an intermediate serial converter that converts two or more parallel bit strings output from the depuncture unit into serial bit strings; and an error correction block based on the serial bit strings output from the intermediate serial converter. and a decoding unit for decoding.

In the summary of the disclosure, the receiving device converts the serial bit strings into two or more parallel bit strings in a stage after converting two or more parallel bit strings equal to the number of subcarriers into serial bit strings, A deinterleaving process (hereinafter referred to as a convolution deinterleaving process) that applies a different delay time to each of the two or more parallel bit strings is executed to convert the two or more parallel bit strings back into a serial bit string. According to such a configuration, the convolution deinterleaving process can be executed without depending on the modulation multilevel number, and the convolution deinterleaving process can be appropriately performed even when the modulation multilevel number is adaptively changed. can run to Furthermore, noting that the error correction block is a fixed-length error correction block, depuncture processing is applied to interpolate predetermined bits to two or more parallel bit strings before convolutional interleaving processing. According to such a configuration, the target coding rate can be adaptively changed at the same time as the modulation multilevel number is adaptively changed.

[Embodiment]
(Digital wireless transmission system)
A digital wireless transmission system according to an embodiment will be described below. FIG. 1 is a diagram showing a digital wireless transmission system 10 according to an embodiment. As shown in FIG. 1, the digital wireless transmission system comprises a transmitting device 100 and a receiving device 200. FIG.

In the embodiment, the digital wireless transmission system is a system supporting wireless transmission of 4K8K broadcast program material. Transmitting device 100 may be an FPU (Field Pickup Unit), and receiving device 200 may be a broadcasting station. OFDM (Orthogonal Frequency Division Multiplexing) and convolutional interleaving are applied in the digital radio transmission system 10 . In the digital radio transmission system 10, MIMO (Multiple-Input Multiple-Output) may be applied. The scheme adopted in the digital wireless transmission system 10 may be the TDD-SVD-MIMO (Time Division Duplex-Singular Value Decomposition-Multiple-Input Multiple-Output) scheme.

(Transmitter)
A transmission device according to an embodiment will be described below. FIG. 2 is a block diagram showing the transmitting device 100 according to the embodiment.

As shown in FIG. 2, transmitting apparatus 100 includes error correction coding section 101, coding S/P conversion section 103, interleaving section 105, puncturing section 107, coding P/S conversion section 109, It has an OFDM S/P conversion section 111 and an OFDM modulation section 113 .

Error correction coding section 101 generates an error correction block (hereinafter referred to as FEC (Forward Error Correction) block) by applying an error correction code to a transmission bit string. When puncturing processing (depuncture processing), which will be described later, is applied, the FEC blocks may be fixed-length FEC blocks. Although not particularly limited, error correction coding section 101 may use turbo code or LDPC (Low-Density Parity-check Code) as the error correction code. For example, a fixed-length FEC block may include a block header, main signal (transmission bit stream), BCH code parity, stuff bits, and LDPC code parity.

The encoded S/P conversion unit 103 constitutes an intermediate parallel conversion unit that converts a serial bit string forming an FEC block into two or more parallel bit strings (hereinafter referred to as parallel k bit strings). The value of k may be an integer of 2 or more. Although not particularly limited, the value of k may be the same as the number of bits forming the FEC block.

Here, the encoding S/P conversion unit 103 converts a serial bit string into a parallel k bit string with a predetermined number of bits as one unit. Although not particularly limited, the predetermined number may be one.

Interleaving section 105 configures an interleaving section that applies a different delay time to each of the parallel k bit strings output from encoding S/P conversion section 103 . Such processing may be referred to as convolutional interleave processing.

For example, the interleaving unit 105 has k buffers (buffers 105 ₁ to 105 _k ), and each buffer holds input bits for a predetermined delay time and then outputs the bits. do.

Puncturing section 107 performs puncturing processing for thinning out predetermined bits of at least part of the parallel k bit strings output from interleaving section 105 . Puncturing section 107 outputs two or more parallel bit strings (hereinafter referred to as parallel k' bit strings) from which predetermined bits are thinned. Here, a parallel k bit string (for example, an FEC block) input to puncturing section 107 may include a parallel k bit string to which puncturing processing is not applied. When puncturing is applied to parallel k bit strings, the value of k' is the value of k minus a predetermined number of bits. On the other hand, the value of k' is the same as the value of k if no puncturing is applied to the k bit strings in parallel.

The puncturing section 107 may thin out predetermined bits according to the final target coding rate. Here, the target coding rate is a term representing the coding rate of the transmitting apparatus 100, and the error correction coding rate applied to the error correction coding unit 101 described above (for example, turbo coding rate, LDPC code encoding rate). For example, puncturing causes the target code rate to be higher than the error correction code rate.

Encoding P/S conversion section 109 constitutes an intermediate serial conversion section that converts the parallel k′ bit string output from puncturing section 107 into a serial bit string.

Although not particularly limited, coding S/P conversion section 103, interleaving section 105, puncturing section 107, and coding P/S conversion section 109 may be referred to as encoders.

OFDM S/P conversion section 111 constitutes a parallel conversion section that converts a serial bit string output from encoding P/S conversion section 109 into parallel N bit strings equal to the number of subcarriers. The value of N is an integer of 2 or more and is the same as the number of subcarriers. The value of k mentioned above may be the same as the value of N or may be different from the value of N.

Here, the OFDM S/P conversion unit 111 converts a serial bit string into a parallel bit string, with the number of bits corresponding to the modulation multilevel number as one unit. For example, when the modulation multilevel number is 64QAM, the OFDM S/P converter 111 converts a serial bit string into a parallel bit string with 6 bits as one unit. Similarly, when the modulation multilevel number is 256QAM, OFDM S/P conversion section 111 converts a serial bit string into a parallel bit string with 8 bits as one unit.

OFDM modulation section 113 configures an OFDM frame based on the parallel bit strings output from OFDM S/P conversion section 111 . An OFDM frame is a frame composed of a predetermined number of carriers provided along the frequency axis and a predetermined number of OFDM symbols provided along the time axis. OFDM modulation section 113 transmits an OFDM frame (transmission signal) using each subcarrier. The OFDM modulation section 113 may perform addition of GI (Guard Interval), and may perform orthogonal modulation.

(receiving device)
A receiving device according to an embodiment will be described below. FIG. 3 is a block diagram showing the receiving device 200 according to the embodiment.

As shown in FIG. 3, receiving apparatus 200 includes OFDM demodulation section 201, OFDM P/S conversion section 203, decoding S/P conversion section 205, depuncturing section 207, deinterleaving section 209, decoding P/ It has an S conversion unit 211 and an error correction decoding unit 213 .

OFDM demodulation section 201 receives an OFDM frame (received signal) from transmitting apparatus 100 using each subcarrier. OFDM demodulation section 201 constitutes a demodulation section that demodulates parallel N bit strings equal to the number of subcarriers. OFDM demodulation section 201 may perform orthogonal demodulation and may perform GI removal.

The OFDM P/S converter 203 constitutes a serial converter that converts N parallel bit strings output from the OFDM demodulator 201 into serial bit strings. The processing of the OFDM P/S conversion unit 203 is the processing opposite to the processing of the OFDM S/P conversion unit 111 described above.

The decoding S/P conversion unit 205 constitutes an intermediate parallel conversion unit that converts a serial bit string output from the OFDM P/S conversion unit 203 into a parallel k′ bit string. The processing of the decoding S/P conversion unit 205 is the reverse processing of the processing of the encoding P/S conversion unit 109 described above.

Depuncturing section 207 interpolates predetermined bits for the parallel k′ bit string output from decoding S/P converting section 205 . Interpolation of the predetermined bits may be a process of substituting a value indicating that there is no soft decision result. The value indicating that there is no soft decision result may be a value that the log-likelihood ratio (LLR) is zero. Depuncturing section 207 outputs to deinterleaving section 209 a parallel k bit string in which predetermined bits are interpolated.

Deinterleaving section 209 configures a deinterleaving section that applies different delay times to each of the parallel k bit strings output from depuncturing section 207 . Such processing may be referred to as convolutional deinterleaving processing. The processing of deinterleaving section 209 is the reverse of the processing of interleaving section 105 described above.

For example, the deinterleaving unit 209 has k buffers (buffers 209 ₁ to 209 _k ), and each buffer holds input bits for a predetermined delay time and then converts the bits. Output.

Decoding P/S conversion section 211 constitutes an intermediate serial conversion section that converts a parallel k bit string output from deinterleaving section 209 into a serial bit string. The processing of the decoding P/S conversion unit 211 is the reverse processing of the processing of the encoding S/P conversion unit 103 described above.

Although not particularly limited, decoding S/P conversion section 205, depuncturing section 207, deinterleaving section 209, and decoding P/S conversion section 111 may be referred to as decoders.

Error correction decoding section 213 decodes the FEC block based on the serial bit string output from decoding P/S conversion section 211 . The processing of the error correction decoding unit 213 is the reverse processing of the processing of the error correction coding unit 101 described above.

(Task)
Problems related to the conventional technology will be described below. In the prior art, the convolutional interleaving process described above is performed after a serial bit stream is converted into a parallel bit stream corresponding to the number of subcarriers. Similarly, the convolutional deinterleaving process described above is performed on parallel bit strings corresponding to the number of subcarriers.

Against this background, in order to simplify the explanation, a case in which an OFDM frame is composed of 4 subcarriers×5 OFDM symbols will be taken as an example to explain the problems associated with the conventional technology.

First, a case of changing the modulation level of frame X+1 to 64QAM when the modulation level of frame X is 256QAM will be exemplified. In such a case, some OFDM symbols contained in frame X are shifted to frame X+1 when convolutional interleaving is performed, as shown in FIG. However, while the number of bits transmitted by subcarriers of OFDM symbols included in frame X is 8 bits, the number of bits transmitted by subcarriers of OFDM symbols in frame X+1 is 6 bits. Therefore, some of the bits transmitted on the subcarriers of the OFDM symbols included in frame X cannot be shifted to frame X+1. That is, the modulation multilevel number cannot be adaptively increased.

Second, a case will be exemplified where the modulation multilevel number of frame Y is 64QAM and the modulation multilevel number of frame Y+1 is changed to 256QAM. In such a case, some OFDM symbols contained in frame Y are shifted to frame Y+1 when convolutional interleaving is performed, as shown in FIG. However, while the number of bits transmitted by subcarriers of OFDM symbols included in frame Y is 6 bits, the number of bits transmitted by subcarriers of OFDM symbols in frame Y+1 is 8 bits. By shifting some of the bits transmitted by the subcarriers of the OFDM symbols included in frame Y to frame Y+1, it is possible to add 2 bits (= 8-6 bits) of stuff bits. It is necessary to manage the information elements (for example, the original number of bits) for removing the for each subcarrier of each OFDM symbol. As the number of subcarriers and the delay due to convolutional interleaving increase, the number of information elements for removing stuff bits also increases, so it is not easy to adaptively reduce the number of modulation levels.

As a result of intensive studies, the inventors found the above-mentioned problem, and performed convolutional interleaving processing not at the OFDM symbol stage but at the bit stage after error correction coding, thereby reducing the dependence on the modulation multilevel number. It has been found that convolutional interleave processing can be performed without the need for modulation, and modulation multi-values can be performed adaptively.

(Convolutional interleave processing)
Convolutional interleave processing according to the embodiment will be described below. FIG. 6 illustrates a case where one FEC block is composed of k bits. b(x,y) represents the coded bits, x represents the FEC block number, and y represents the bit number within the FEC block.

In such a case, interleaving section 105 of transmitting apparatus 100 applies different delay times to each of the parallel k bit strings output from coding S/P converting section 103 . For example, as shown in FIG. 6, interleaving section 105 applies a delay time equivalent to the processing time of one FEC block to the second bit in the FEC block, and applies the delay time to the third bit in the FEC block. A delay time corresponding to the processing time of two FEC blocks may be applied, and a delay time corresponding to the processing time of three FEC blocks may be applied to the fourth bit in the FEC block.

Further, different delay times may be applied cyclically to the bits within the FEC block, as shown in FIG. For example, the delay time d(x) applied to the xth bit may be defined by d(x) = (x-1) mod 4. The delay time applied to each bit number may be determined in a manner known to receiving apparatus 200 .

(Puncture processing)
The puncturing process according to the embodiment will be described below. FIG. 7 illustrates the puncturing process following the convolutional interleaving process described in FIG.

In such a case, puncturing section 107 of transmitting apparatus 100 executes puncturing processing for thinning out predetermined bits of at least part of the parallel k′ bit string. Accordingly, the target coding rate can be changed according to the number of bits. In other words, puncturing section 107 thins out predetermined bits according to the target coding rate. A predetermined bit may be referred to as a punctured bit.

For example, as shown in FIG. 7, puncturing section 107 performs b(1,3), b(2,3), b(3,3), . . . , b(0,k), (1,k), Predetermined bits such as b(2,k) may be thinned out. The number of predetermined bits is determined according to the target coding rate. For example, the vertical bit groups starting at b(1,1), b(2,1) and b(6,1) are non-puncture target, b(3,1), b(4,1) and vertical bits starting from b(5,1) may be punctured.

According to such puncturing processing, for example, even if the error correction coding rate is 1/3, it is possible to increase the target coding rate to 1/2 by thinning out predetermined bits through puncturing processing. be. For example, if the transmission bits are 10 bits and the error correction coding rate is 1/3, the error correction block is 30 bits, but if puncturing processing is performed for 10 bits, the target coding rate is 1. /2 (10/20) can be changed.

(Depuncture processing)
Depuncture processing according to the embodiment will be described below. FIG. 8 describes depuncture processing of receiving apparatus 200 that receives a received signal to which puncturing processing described in FIG. 7 is applied. In FIG. 8, b'(x,y) represents the soft decision result of the encoded bit, x represents the FEC block number, and y represents the bit number within the FEC block. .

In such a case, depuncturing section 207 of receiving apparatus 200 interpolates predetermined bits for parallel k' bit strings. Interpolation of the predetermined bits may be a process of substituting a value indicating that there is no soft decision result. The value indicating that there is no soft decision result may be a value that the log-likelihood ratio (LLR) is zero. A predetermined bit may be referred to as a depuncture bit.

For example, as shown in FIG. 8, the depuncture unit 207 performs b'(1,3), b'(2,3), b'(3,3), ..., b'(0,k), b' Predetermined bits such as (1,k), b'(2,k) may be interpolated. That is, depuncture section 207 performs b′(1,3), b′(2,3), b′(3,3), . A soft decision result (LLR) for a given bit such as '(2,k) may be set to zero. For example, vertical bit groups starting from b'(1,1), b'(2,1) and b'(6,1) are depuncture-asymmetric, b'(3,1), b' Vertical groups of bits starting from (4,1) and b'(5,1) may be depunctured.

(Convolution deinterleave processing)
The convolution deinterleaving process according to the embodiment will be described below. FIG. 9 illustrates the deinterleaving process following the depuncture process described in FIG.

In such a case, deinterleaving section 209 of receiving apparatus 200 applies different delay times to each of the k parallel bit strings. For example, as shown in FIG. 9, deinterleaving section 209 applies a delay time equivalent to the processing time of three FEC blocks to the first bit in the FEC block, and applies the delay time to the second bit in the FEC block. , a delay time corresponding to the processing time of two FEC blocks may be applied, and a delay time corresponding to the processing time of one FEC block may be applied to the third bit in the FEC block.

Further, different delay times may be applied cyclically to the bits within the FEC block, as shown in FIG. For example, the delay time d(x) applied to the x-th bit is determined so that the sum of the delay times applied by the transmitter 100 and the delay times applied by the receiver is equal between bit numbers. The delay time applied to each bit number may be determined in a manner known to receiving apparatus 200 .

(Action and effect)
In the embodiment, before converting a serial bit string into parallel N bit strings equal to the number of subcarriers, transmitting apparatus 100 converts serial bit strings forming an FEC block into parallel k bit strings. , performs a convolutional interleaving process that applies different delay times to each of the k parallel bitstreams to convert the k parallel bitstreams (parallel k' bitstreams when puncturing is assumed) into serial bitstreams. return. According to such a configuration, the convolutional interleaving process can be executed without depending on the modulation level, and the convolutional interleaving process can be appropriately executed even when the modulation level is adaptively changed. can do.

In the embodiment, receiving apparatus 200 transforms the serial bit strings into parallel k bit strings (in the case of depuncturing, After converting back to parallel k' bitstreams), a convolutional deinterleaving process is performed that applies different delay times to each of the k parallel bitstreams to convert the parallel k bitstreams back into serial bitstreams. According to such a configuration, the convolution deinterleaving process can be executed without depending on the modulation multilevel number, and the convolution deinterleaving process can be appropriately performed even when the modulation multilevel number is adaptively changed. can run to

In the embodiment, focusing on the fact that the FEC block is a fixed-length FEC block, transmitting device 100 applies puncturing processing to parallel k bit strings after convolutional interleaving processing, and receiving device 200 performs convolutional Depuncture is applied to the parallel k' bit strings before deinterleaving. According to such a configuration, the target coding rate can be adaptively changed at the same time as the modulation multilevel number is adaptively changed.

[Experimental result]
Experimental results relating to the embodiments will be described below. As experimental results, residual error bits after error correction decoding according to Example 1 and Comparative Example 1 were examined under the following conditions. Example 1 is an example to which the above-described convolutional interleaving process is applied, and Comparative Example 1 is a comparative example to which the above-described convolutional interleaving process is not applied. Comparative Example 1 has the same conditions except that the convolutional interleaving process is not applied.

Number of subcarriers: 860
Number of OFDM symbols that make up an OFDM frame: 24
Error correction code: turbo code Error correction block code length: 4908 bits (error correction coding rate = 1/3)
Code length after puncturing: 3276 bits (target coding rate = 1/2)
Convolutional interleave processing…Maximum delay time = 23
Delay applied to xth bit…d(x) = (x-1) mod 24
Transmission path: AWGN (Additive White Gaussian Noise)

Under these conditions, experiments were conducted using three OFDM frames, as shown in FIG. In the first OFDM frame, when the CNR (Carrier to Noise Ratio) is 15 dB, 64QAM is applied as the modulation level and 1/3 is applied as the coding rate. In the second OFDM frame, when the CNR is 20 dB, 256QAM is applied as the modulation multilevel number, and 1/2 is applied as the coding rate by applying puncturing. In the third OFDM frame, when the CNR is 15 dB, 64QAM is applied as the modulation multilevel number and 1/3 is applied as the coding rate. Furthermore, noise was generated in one OFDM symbol included in the second OFDM frame to lower the CNR to 10 dB.

In Example 1, no error bits remained after error correction decoding, whereas in Comparative Example 1 error bits remained after error correction decoding. In this way, even when adaptively controlling the modulation multilevel number and coding rate in three OFDM frames, the convolutional interleaving processing according to the embodiment distributes the bits that make up each FEC block in the time axis direction, and corrects errors. It was confirmed that the effect of the code is improved.

In addition, in the interleaving process described in the prior art, that is, the convolutional interleaving process in which different delay times are applied to OFDM symbols for each subcarrier, the modulation multilevel number and the coding rate are adaptively changed for each OFDM frame. It should be noted that it is not possible to

[Other embodiments]
While the present invention has been described in the foregoing disclosure, the discussion and drawings forming part of this disclosure should not be taken as limiting the invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

In the above disclosure, the encoding S/P conversion unit 103 and the decoding S/P conversion unit 205 exemplified a case in which when converting a serial bit string into a parallel k bit string, the parallel conversion is performed in 1-bit units. However, the above disclosure is not so limited. The unit for converting a serial bit string into a parallel bit string may be 2 or more bits.

The above disclosure exemplifies the case where the value of k is the number of bits that make up the FEC block. However, the above disclosure is not so limited. The value of k may be less than the number of bits forming the FEC block or greater than the number of bits forming the FEC block.

The above disclosure exemplifies cases where puncturing and depuncturing are applied. However, the above disclosure is not so limited. Puncturing and depuncturing may not be applied. In such a case, puncturing section 107 and depuncturing section 207 may be omitted in transmitting apparatus 100 and receiving apparatus 200 .

Although not specifically mentioned in the disclosure above, a program may be provided that causes a computer to execute each process performed by the transmitting device 100 and the receiving device 200 . Also, the program may be recorded on a computer-readable medium. A computer readable medium allows the installation of the program on the computer. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be, for example, a recording medium such as CD-ROM or DVD-ROM.

Alternatively, a chip configured by a memory storing a program for executing each process performed by the transmitting device 100 and the receiving device 200 and a processor executing the program stored in the memory may be provided.

DESCRIPTION OF SYMBOLS 10... Digital wireless transmission system 100... Transmission apparatus 101... Error correction coding part 103... Encoding S/P conversion part 105... Interleaving part 107... Puncturing part 109... Encoding P/S conversion part, DESCRIPTION OF SYMBOLS 111... OFDM SP conversion part 113... OFDM modulation part 200... Reception apparatus 201... OFDM demodulation part 203... OFDM PS conversion part 205... Decoding S/P conversion part 207... Depuncturing part 209... Deinterleaving part , 211 ... decoding P/S conversion unit, 213 ... error correction decoding unit

Claims (4)

an intermediate parallel conversion unit that converts a serial bit string constituting a fixed-length error correction block into two or more parallel bit strings;
an interleaving unit that applies different delay times to each of two or more parallel bit strings output from the intermediate parallel conversion unit;
a puncturing unit that thins out predetermined bits of at least a portion of two or more parallel bit strings output from the interleaving unit and outputs two or more parallel bit strings from which the predetermined bits are thinned;
an intermediate serial conversion unit that converts two or more parallel bit strings output from the puncturing unit into serial bit strings;
a parallel conversion unit that converts a serial bit string output from the intermediate serial conversion unit into two or more parallel bit strings equal to the number of subcarriers. The transmitting apparatus according to claim 1, wherein said puncturing section thins out said predetermined bits according to a target coding rate. a demodulator that demodulates two or more parallel bit strings equal to the number of subcarriers;
a serial conversion unit that converts two or more parallel bit strings output from the demodulation unit into serial bit strings;
an intermediate parallel conversion unit that converts a serial bit string output from the serial conversion unit into two or more parallel bit strings;
a depuncture unit that interpolates predetermined bits in two or more parallel bit strings output from the intermediate parallel conversion unit and outputs two or more parallel bit strings in which the predetermined bits are interpolated;
a deinterleaving unit that applies different delay times to each of two or more parallel bit strings output from the depuncturing unit;
an intermediate serial conversion unit that converts two or more parallel bit strings output from the deinterleaving unit into serial bit strings;
and a decoding unit that decodes a fixed-length error correction block based on the serial bit string output from the intermediate serial conversion unit. 4. The transmitting apparatus according to claim 3, wherein said depuncturing unit interpolates said predetermined bits according to a target coding rate.

Images