JP2022130066A - Electronic component and manufacturing method for the same - Google Patents

Abstract

To provide an electronic component in which a plurality of capacitors different in withstand voltage are incorporated.SOLUTION: An electronic component 1 includes: a first capacitor formed by conductor patterns 25, 31 and a dielectric film 4 located between these patterns; and a second capacitor formed by conductor patterns 26, 32 and a dielectric film 5 located between these patterns. The dielectric film 4 and the dielectric film 5 have different thicknesses from each other. Since the thicknesses of the dielectric film 4 and the dielectric film 5 are different from each other, it is possible to obtain breakdown voltages different from each other.SELECTED DRAWING: Figure 2

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component and its manufacturing method, and more particularly to an electronic component with a plurality of built-in capacitors and its manufacturing method.

An electronic component described in Patent Document 1 is known as a chip-type electronic component with a built-in capacitor. The electronic component described in Patent Document 1 forms a series circuit of a capacitor and an inductor using two conductor layers.

JP-A-2008-34626

However, when a plurality of capacitors are built in one electronic component, there may be cases where different withstand voltages are required for each capacitor.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an electronic component in which a plurality of capacitors having different withstand voltages are incorporated, and a method of manufacturing the same.

An electronic component according to the present invention is an electronic component comprising a plurality of conductor layers laminated on a substrate, wherein two conductor layers adjacent in the lamination direction among the plurality of conductor layers and a dielectric film positioned therebetween and a second capacitor formed of two conductor layers adjacent in the stacking direction among the plurality of conductor layers and a dielectric film positioned therebetween, the first The thickness of the dielectric film forming the second capacitor is different from that of the dielectric film forming the second capacitor.

According to the present invention, since the dielectric film forming the first capacitor and the dielectric film forming the second capacitor have different thicknesses, different breakdown voltages can be obtained.

In the present invention, each of the first and second capacitors has a first conductor layer of a plurality of conductor layers as a lower electrode, and a second conductor layer of a plurality of conductor layers as an upper electrode. It doesn't matter if it is. According to this, it is possible to form a plurality of capacitors having different breakdown voltages without increasing the number of laminated conductor layers. In this case, the thickness of the dielectric film forming the first capacitor is thinner than the thickness of the dielectric film forming the second capacitor, and the thickness of the upper electrode forming the first capacitor forms the second capacitor. It may be thicker than the thickness of the upper electrode. According to this, it is possible to reduce the step due to the difference in the thickness of the dielectric film.

In the present invention, the dielectric film forming the first capacitor is a first dielectric film, and the dielectric film forming the second capacitor is a second dielectric film different from the first dielectric film. It may consist of This makes it possible to arbitrarily select the film thicknesses and materials of the first and second dielectric films. Alternatively, the dielectric film forming the first capacitor is the first dielectric film, and the dielectric film forming the second capacitor is a laminated film of the first dielectric film and the second dielectric film. It may consist of According to this, it is possible to easily make the dielectric film forming the second capacitor thicker than the dielectric film forming the first capacitor.

The electronic component according to the present invention further comprises a plurality of terminal electrodes, the thickness of the dielectric film forming the first capacitor is thinner than the thickness of the dielectric film forming the second capacitor, and the plurality of conductor layers are inductors. a pattern, wherein the first capacitor is connected between any two of the plurality of terminal electrodes through the inductor pattern, and the second capacitor is connected between any two of the plurality of terminal electrodes without the inductor pattern; It does not matter what is connected. This makes it possible to increase the breakdown voltage of the second capacitor to which a high voltage can be applied.

A method of manufacturing an electronic component according to one aspect of the present invention includes steps of forming a first conductor layer having first and second regions on a substrate; covering with a first dielectric film; forming a second conductor layer on the first region of the first conductor layer through the first dielectric film; a step of covering the first dielectric film formed on the region 2 with a second dielectric film; and forming a third conductor layer. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films with different thicknesses.

A method of manufacturing an electronic component according to another aspect of the present invention includes the steps of: forming a first conductor layer having first and second regions on a substrate; with a first dielectric film; forming a second conductor layer on the first region of the first conductor layer through the first dielectric film; after removing the first dielectric film formed on the second region of the first conductor layer, covering the second region of the first conductor layer with a second dielectric film; and forming a second conductor layer on the second region of the first conductor layer via the second conductor layer. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films of different thicknesses or different materials.

A method of manufacturing an electronic component according to still another aspect of the present invention includes steps of forming a first conductor layer having first and second regions on a substrate; covering a region with a first dielectric film; selectively reducing a thickness of the first dielectric film formed over a second region of the first conductor layer; forming a second conductor layer on the first and second regions of the first conductor layer through the film. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films with different thicknesses.

As described above, according to the present invention, it is possible to provide an electronic component in which a plurality of capacitors having different withstand voltages are incorporated and a method of manufacturing the same.

FIG. 1 is a schematic plan view for explaining the structure of an electronic component 1 according to a first embodiment of the invention. FIG. 2 is a schematic cross-sectional view along line AA of FIG. FIG. 3 is a schematic plan view showing pattern shapes of the conductor layers M1 and MM. FIG. 4 is a schematic plan view showing the positions of vias provided in the insulating layer 11. As shown in FIG. FIG. 5 is a schematic plan view showing the pattern shape of the conductor layer M2. FIG. 6 is an equivalent circuit diagram of the electronic component 1. As shown in FIG. FIG. 7 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 8 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 9 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 10 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 11 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 12 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 13 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 14 is a process diagram for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 15 is a process chart for explaining the method of manufacturing the electronic component 1 according to the first embodiment. FIG. 16 is a schematic cross-sectional view for explaining the structure of the electronic component 1a according to the second embodiment. FIG. 17 is a process chart for explaining the method of manufacturing the electronic component 1a according to the second embodiment. FIG. 18 is a process chart for explaining the method of manufacturing the electronic component 1a according to the second embodiment. FIG. 19 is a process chart for explaining the method of manufacturing the electronic component 1a according to the second embodiment. FIG. 20 is a process chart for explaining the method of manufacturing the electronic component 1a according to the second embodiment. FIG. 21 is a schematic cross-sectional view for explaining the structure of an electronic component 1b according to a first modified example. FIG. 22 is a schematic cross-sectional view for explaining the structure of an electronic component 1c according to a second modification.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic plan view for explaining the structure of an electronic component 1 according to a first embodiment of the invention. 2 is a schematic cross-sectional view taken along line AA of FIG. 1. FIG.

The electronic component 1 according to the first embodiment is an LC filter, and as shown in FIGS. , 12. The pattern shapes of the conductor layers M1 and MM are shown in FIG. 3, the positions of the vias provided in the insulating layer 11 are shown in FIG. 4, and the pattern shape of the conductor layer M2 is shown in FIG. It is The material of the substrate 2 is not particularly limited as long as it is chemically and thermally stable, generates little stress, and can maintain the smoothness of the surface. Sapphire, aluminum nitride, MgO single crystal _, SrTiO3 single crystal, surface silicon oxide, glass, quartz, ferrite, organic film, etc. can be used. The surface of substrate 2 is covered with planarization layer 3 . Alumina, silicon oxide, or the like can be used as the planarization layer 3 .

The conductor layer M1 is the lowest conductor layer, and includes conductor patterns 21 to 26 as shown in FIG. Among them, the conductor patterns 21 to 24 are terminal electrode patterns, the loop-shaped conductor pattern 25 is both an inductor pattern and a capacitor lower electrode, and the conductor pattern 26 is a capacitor lower electrode. One end of the conductor pattern 25 is connected to the conductor pattern 21 . Also, the conductor pattern 26 is connected to the conductor patterns 23 and 24 . These conductor patterns 21 to 26 are formed by a thin seed layer S in contact with the flattening layer 3 and a plated layer P made of copper (Cu) or the like provided on the seed layer S and having a larger film thickness than the seed layer S. It is configured. The same applies to the conductor patterns located on the other conductor layers MM and M2, which are composed of a laminate of the seed layer S and the plated layer P. As shown in FIG. However, a part of the conductor layers located in the lower layers, for example, the conductor layer M1 and the conductor layer MM, may be a single layer film formed by a sputtering method or the like.

Among the conductor patterns 21 to 26, the conductor pattern 25 forming the lower electrode of the capacitor is covered with the first dielectric film (capacitor insulating film) 4 on the upper surface thereof, and the conductor pattern 26 forming the lower electrode of the capacitor. And part of the first dielectric film 4 is covered with a second dielectric film (capacitor insulating film) 5 . The first and second dielectric films 4 and 5 are made of an inorganic insulating material such as silicon nitride, and may be made of the same material or may be made of different materials. Also, the film thicknesses may be the same or different. As an example, in the first embodiment, both the first and second dielectric films 4 and 5 are made of silicon nitride, and the first dielectric film 4 is thicker than the second dielectric film 5. Thin thickness.

The conductor pattern 25 has a first area 25A and a second area 25B. Among them, a conductor pattern 31 is formed on the upper surface of the first region 25A with the first dielectric film 4 interposed therebetween. A conductor pattern 33 is formed on the upper surface of the second region 25B with a laminated film of the first dielectric film 4 and the second dielectric film 5 interposed therebetween. Furthermore, a conductor pattern 32 is formed on the upper surface of the conductor pattern 26 with the second dielectric film 5 interposed therebetween. The conductor patterns 31 to 33 belong to the conductor layer MM located between the conductor layers M1 and M2 and form the upper electrodes of the capacitor. As a result, a first capacitor having the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode, and a second capacitor having the conductor pattern 26 as a lower electrode and the conductor pattern 32 as an upper electrode. A capacitor and a third capacitor having the second region 25B of the conductor pattern 25 as a lower electrode and the conductor pattern 33 as an upper electrode are formed. The thickness of the conductor layer MM is thinner than the conductor layers M1 and M2, thereby enhancing the pattern accuracy of the conductor layer MM. The conductor layer M1 and the conductor layer MM are covered with an insulating layer 11 made of a resin material such as polyimide.

As shown in FIG. 4, the insulating layer 11 is provided with vias 41 to 48 that expose the conductor layers M1 and MM. Of these, the vias 41 to 44 are provided at positions exposing the conductor patterns 21 to 24 respectively, the vias 45 are provided at positions exposing the ends of the conductor pattern 25, and the vias 46 to 48 are provided at positions exposing the conductor patterns 31 to 33 respectively. is provided at a position exposing the

The conductor layer M2 is a second conductor layer provided on the surface of the insulating layer 11, and includes conductor patterns 51 to 59 as shown in FIG. Among them, the conductor patterns 51 to 54 are terminal electrode patterns, the loop-shaped conductor pattern 55 is an inductor pattern, the conductor patterns 57 and 59 are lead patterns for upper electrodes, and the meander-shaped conductor pattern 58 is an inductor pattern. is. Conductive patterns 51-54 are connected to conductive patterns 21-24 via vias 41-44, respectively. One end of the conductor pattern 55 is connected to the other end of the conductor pattern 25 via the via 45, the other end of the conductor pattern 55 is connected to the conductor pattern 57, and is connected to the conductor pattern 31 via the vias 46 and 48, respectively. , 33. Conductive pattern 57 is connected to conductive pattern 32 via via 47 .

FIG. 6 is an equivalent circuit diagram of the electronic component 1 according to the first embodiment.

As shown in FIG. 6, in the electronic component 1 according to the first embodiment, a capacitor C1 and an inductor L1 are connected in parallel between the terminal electrode E1 and the internal node N, and an inductor L1 is connected between the terminal electrode E2 and the internal node N. L2 is connected, a capacitor C2 is connected between the terminal electrodes E3 and E4 and the internal node N, and a capacitor C3 is connected between the terminal electrodes E1 and E2. The terminal electrode E1 corresponds to the conductor patterns 21 and 51, the terminal electrode E2 corresponds to the conductor patterns 22 and 52, the terminal electrode E3 corresponds to the conductor patterns 23 and 53, and the terminal electrode E4 corresponds to the conductor patterns 24 and 54. do. Also, internal node N corresponds to conductor pattern 57 . The capacitor C1 uses the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode. The capacitor C2 uses the conductor pattern 26 as a lower electrode and the conductor pattern 32 as an upper electrode. The capacitor C3 uses the second region 25B of the conductor pattern 25 as a lower electrode and the conductor pattern 33 as an upper electrode. Inductor L1 is composed of conductor patterns 25 and 55, and inductor L2 is composed of conductor pattern 58. FIG.

Thus, the electronic component 1 according to the first embodiment has three capacitors C1 to C3 built in the same chip. Here, the capacitor C1 uses the first dielectric film 4 as a capacitive insulating film, the capacitor C2 uses the second dielectric film 5 as a capacitive insulating film, and the capacitor C3 uses the first dielectric film. A laminated film of the body film 4 and the second dielectric film 5 is used as a capacitive insulating film. In the first embodiment, since the first dielectric film 4 is thinner than the second dielectric film 5, the capacitor C1 has the largest capacitance per unit area. While C3 has the lowest dielectric strength, capacitor C3 has the highest dielectric strength and capacitor C1 has the lowest.

Here, the capacitive insulating film of the capacitor C1 is designed to be the thinnest because, in addition to the large capacitance required for the capacitor C1, the capacitor C1 is not directly connected between the two terminal electrodes, and can be connected to an inductor or another capacitor. This is because the voltage to be applied is relatively suppressed because the two terminal electrodes are connected to each other through the . On the other hand, since the capacitor C3 is directly connected between the terminal electrodes E1 and E3 without an inductor or another capacitor, a relatively high voltage can be applied from the outside. Therefore, the capacitor C3 is required to have a higher breakdown voltage, and in order to achieve this, the capacitive insulating film of the capacitor C3 is designed to be the thickest. As for the capacitor C2, it is connected between the two terminal electrodes via an inductor or another capacitor instead of being directly connected between the two terminal electrodes like the capacitor C1. Since the capacitance is small, the withstand voltage is improved by using a thicker second dielectric film 5 .

As described above, in the first embodiment, since the film thicknesses of the capacitive insulating films of the capacitors C1 to C3 are individually set according to the required capacitance and withstand voltage, it is possible to achieve both electrical characteristics and withstand voltage. It becomes possible.

Next, a method for manufacturing the electronic component 1 according to the first embodiment will be described.

7 to 15 are process diagrams for explaining the method of manufacturing the electronic component 1 according to the first embodiment. In the manufacturing process of the electronic component 1, a large number of electronic components 1 are obtained using an aggregate board, but the manufacturing process shown in FIGS. 7 to 15 focuses on one electronic component 1.

First, as shown in FIG. 7, a flattening layer 3 is formed on a substrate (collective substrate at this point) 2 by sputtering or the like, and its surface is smoothed by grinding or mirror-finishing treatment such as CMP. do. After that, a seed layer S is formed on the surface of the planarizing layer 3 using a sputtering method or the like. Next, after a resist layer (not shown) is spin-coated on the seed layer S, the resist layer is patterned so that the seed layer S in the region where the conductor layer M1 is to be formed is exposed. In this state, a plated layer P is formed on the seed layer S by performing electrolytic plating using the seed layer S as a power supply. A laminate of the seed layer S and the plated layer P constitutes the conductor layer M1. In the cross section shown in FIG. 7, conductor patterns 25 and 26 are included in conductor layer M1. After that, the resist layer is removed and the seed layer S exposed on the surface is removed to complete the conductor layer M1. Removal of the seed layer S can be done by etching or ion milling.

Next, as shown in FIG. 8, a first dielectric film 4 is formed on the entire surface including the upper surface and side surfaces of the conductor layer M1. As the first dielectric film 4, for example, paraelectric materials such as silicon nitride (SiNx) and silicon oxide (SiOx) as well as known ferroelectric materials can be used. As a method for forming the first dielectric film 4, a sputtering method, a plasma CVD method, an MOCVD method, a sol-gel method, an electron beam vapor deposition method, or the like can be used. Next, as shown in FIG. 9, the conductor pattern 26 is exposed by patterning the first dielectric film 4 .

Next, as shown in FIG. 10, a conductor pattern 31 is formed on the upper surface of the first region 25A of the conductor pattern 25 with the first dielectric film 4 interposed therebetween by using a method similar to the method of forming the conductor layer M1. to form The conductor pattern 31 is also composed of a laminate of the seed layer S and the plated layer P. As shown in FIG. At this time, the first dielectric film 4 covering the second region 25B of the conductor pattern 25 remains exposed. As a result, a first capacitor C1 having the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode is formed.

Next, as shown in FIG. 11, the second dielectric film 5 is formed on the entire surface including the top surface and side surfaces of the conductor pattern 31 . The material and film formation method of the second dielectric film 5 may be the same as or different from those of the first dielectric film 4 . The film thickness of the second dielectric film 5 may be the same as or different from the film thickness of the first dielectric film 4. The thickness of the dielectric film 5 is set larger than that of the first dielectric film 4 . As a result, the conductor pattern 26 is covered with the second dielectric film 5 and the second region 25B of the conductor pattern 25 is covered with the laminated film of the first dielectric film 4 and the second dielectric film 5 .

Next, as shown in FIG. 12, by using a method similar to the method of forming the conductor layer M1, a conductor pattern 32 is formed on the upper surface of the conductor pattern 26 with the second dielectric film 5 interposed therebetween. A conductor pattern 33 is formed on the upper surface of the second region 25B of the pattern 25 with the first dielectric film 4 and the second dielectric film 5 interposed therebetween. The conductor patterns 32 and 33 also consist of a laminate of the seed layer S and the plated layer P. As shown in FIG. As a result, the conductor layer MM is completed, the second capacitor C2 is formed with the conductor pattern 26 as the lower electrode and the conductor pattern 32 as the upper electrode, and the second region 25B of the conductor pattern 25 is used as the lower electrode. , a third capacitor C3 having the conductor pattern 33 as an upper electrode is formed.

Next, as shown in FIG. 13, the second dielectric film 5 is patterned to form a via 5a that partially exposes the conductor pattern 31. Next, as shown in FIG. Next, as shown in FIG. 14, after forming the insulating layer 11 covering the conductor layers M1 and MM, vias 31a to 33a are formed in the insulating layer 11 by patterning the insulating layer 11. Next, as shown in FIG. As a result, the conductor patterns 31-33 are exposed at the bottoms of the vias 31a-33a, respectively. At this time, the depths of the vias 31a to 33a are such that the via 31a is the deepest and the via 33a is the shallowest. In order to reduce such a difference, the conductor layer MM should be formed such that the conductor pattern 31 is the thickest and the conductor pattern 33 is the thinnest.

Next, as shown in FIG. 15, a conductor layer M3 is formed on the insulating layer 11 by a method similar to the method for forming the conductor layer M1. In the cross section shown in FIG. 15, conductor patterns 55, 57 and 59 are included in conductor layer M2. Conductive pattern 55 is connected to conductive pattern 31 through via 31a, conductive pattern 57 is connected to conductive pattern 32 through via 32a, and conductive pattern 59 is connected to conductive pattern 33 through via 33a. Thereafter, as shown in FIG. 2, after forming the insulating layer 12 covering the conductor layer M2, terminal electrodes E1 to E4 connected to the conductor patterns 51 to 54, respectively, are formed. Part 1 is completed.

If the manufacturing process of the electronic component 1 described above is used, the first capacitor C1 having the first dielectric film 4 as a capacitive insulating film and the second capacitor C1 having the second dielectric film 5 as a capacitive insulating film can be produced. C2 and a third capacitor C3 having a laminated film of the first dielectric film 4 and the second dielectric film 5 as a capacitive insulating film can be formed. Moreover, the lower electrodes of the capacitors C1 to C3 are all located on the conductor layer M1, and the upper electrodes of the capacitors C1 to C3 are all located on the conductor layer MM. A plurality of capacitors can be made separately.

FIG. 16 is a schematic cross-sectional view for explaining the structure of the electronic component 1a according to the second embodiment.

As shown in FIG. 16, in the electronic component 1a according to the second embodiment, instead of omitting the second dielectric film 5, the film thickness of the first dielectric film 4 differs depending on the planar position. is different from the electronic component 1 according to the first embodiment. Since other basic configurations are the same as those of the electronic component 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.

In the second embodiment, the thickness of part of the first dielectric film 4 is reduced. Specifically, the film thickness is not reduced in the region 4a, the film thickness is reduced by one step in the region 4b, and the film thickness is reduced by two steps in the region 4c. Among the conductor patterns belonging to the conductor layer MM, the conductor pattern 31 is formed at a position overlapping with the region 4c, the conductor pattern 32 is formed at a position overlapping with the region 4b, and the conductor pattern 33 is formed at a position overlapping with the region 4a. ing. Accordingly, as in the first embodiment, the largest capacitance per unit area can be obtained in the first capacitor C1, and the highest dielectric strength voltage can be obtained in the third capacitor C3.

Next, a method for manufacturing the electronic component 1a according to the second embodiment will be described.

17 to 20 are process diagrams for explaining the method of manufacturing the electronic component 1a according to the second embodiment. In the manufacturing process of the electronic component 1a, a large number of a plurality of electronic components 1a are obtained using an aggregate board, but the manufacturing process shown in FIGS. 17 to 20 focuses on one electronic component 1a.

First, as described with reference to FIG. 7, after the flattening layer 3 and the conductor layer M1 are formed on the substrate 2, as shown in FIG. A dielectric film 4 is deposited. The thickness of the first dielectric film 4 is set thicker than the thickness in the first embodiment.

Next, as shown in FIG. 18, the portion of the first dielectric film 4 covering the first region 25A of the conductor pattern 25 and the portion covering the conductor pattern 26 are etched to reduce the film thickness. One step thinner. As a result, the first dielectric film 4 is divided into a region 4a having the original thickness and a region 4b having a thickness reduced by one step. The second region 25B of the conductor pattern 25 is covered with the region 4a of the first dielectric film 4. As shown in FIG.

Next, as shown in FIG. 19, the portion of the first dielectric film 4 that covers the first region 25A of the conductor pattern 25 is further etched to reduce the film thickness by one step. As a result, the first dielectric film 4 is divided into a region 4a having the original thickness, a region 4b having a thickness reduced by one step, and a region 4c having a thickness reduced by two steps. Conductive pattern 26 is covered with region 4 b of first dielectric film 4 .

Next, as shown in FIG. 20, a conductor layer MM composed of conductor patterns 31 to 33 is formed on the surface of the first dielectric film 4. Next, as shown in FIG. The conductor pattern 31 covers the first area 25A of the conductor pattern 25 through the area 4c of the first dielectric film 4, and the conductor pattern 32 covers the conductor pattern 25A through the area 4b of the first dielectric film 4. 26 , the conductor pattern 33 covers the second region 25 B of the conductor pattern 25 via the region 4 a of the first dielectric film 4 . This completes the capacitors C1 to C3. After that, the electronic component 1a according to the second embodiment is completed by executing the process described with reference to FIGS.

By using the manufacturing process of the electronic component 1a described above, it is possible to separately manufacture a plurality of capacitors having different breakdown voltages without using a plurality of dielectric films. Moreover, the film thickness of the dielectric film 4 can be finely adjusted by the etching amount.

FIG. 21 is a schematic cross-sectional view for explaining the structure of an electronic component 1b according to a first modified example.

As shown in FIG. 21, the electronic component 1b according to the first modification includes a conductor layer M1 including conductor patterns 61 and 62, a conductor layer MM including conductor patterns 71 and 72, and a conductor layer including conductor patterns 81 and 82. A structure having a layer M2, in which a first dielectric film 6 is provided between conductor patterns 61 and 71, and a second dielectric film 7 is provided between conductor patterns 72 and 82. have. Thus, the conductor patterns 61 and 71 and the first dielectric film 6 form a first capacitor, and the conductor patterns 72 and 82 and the second dielectric film 7 form a second capacitor. The first dielectric film 6 and the second dielectric film 7 have different film thicknesses. As illustrated in the electronic component 1b according to the first modification, the upper electrode of the first capacitor and the lower electrode of the second capacitor may be located on the same conductor layer (MM).

FIG. 22 is a schematic cross-sectional view for explaining the structure of an electronic component 1c according to a second modification.

As shown in FIG. 22, the electronic component 1c according to the second modification includes a conductor layer M1 including conductor patterns 61 and 62, a conductor layer MM including conductor patterns 71 and 72, and a conductor layer including conductor patterns 81 and 82. It has a layer M2 and a conductor layer M3 including conductor patterns 91 and 92, a first dielectric film 6 is provided between the conductor patterns 61 and 71, and a conductor pattern 82 and a conductor pattern 92. It has a structure in which a second dielectric film 8 is provided. Thus, the conductor patterns 61 and 71 and the first dielectric film 6 form a first capacitor, and the conductor patterns 82 and 92 and the second dielectric film 8 form a second capacitor. The film thicknesses of the first dielectric film 6 and the second dielectric film 8 are different from each other. As exemplified by the electronic component 1c according to the first modification, the lower and upper electrodes of the first capacitor and the lower and upper electrodes of the second capacitor have different conductor layers (M1, MM, M2, M3).

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.

For example, in the first and second embodiments, three dielectric films with different thicknesses are used to configure the capacitors C1 to C3. Capacitors may be configured, and four or more types of capacitors may be configured using four or more dielectric films having different film thicknesses.

1, 1a-1c electronic component 2 substrate 3 planarization layer 4, 6 first dielectric films 4a-4c regions 5, 7, 8 second dielectric films 5a, 31a-33a, 41-48 vias 11, 12 Insulating layers 21-26, 31-33, 51-55, 57-59, 61, 62, 71, 72, 81, 82, 91, 92 Conductor pattern 25A First region 25B Second region C1-C3 Capacitor E1 ~E4 terminal electrodes L1, L2 inductors M1, MM, M2, M3 conductor layer N internal node P plated layer S seed layer

Claims (9)

An electronic component comprising a plurality of conductor layers laminated on a substrate,
a first capacitor formed by two conductor layers adjacent in the stacking direction among the plurality of conductor layers and a dielectric film positioned therebetween;
a second capacitor formed by two conductor layers adjacent in the stacking direction among the plurality of conductor layers and a dielectric film positioned therebetween;
An electronic component, wherein the dielectric film forming the first capacitor and the dielectric film forming the second capacitor have different thicknesses. In each of the first and second capacitors, the first conductor layer of the plurality of conductor layers is used as a lower electrode, and the second conductor layer of the plurality of conductor layers is used as an upper electrode. 2. The electronic component according to claim 1. the thickness of the dielectric film forming the first capacitor is thinner than the thickness of the dielectric film forming the second capacitor;
3. The electronic component according to claim 2, wherein the thickness of said upper electrode forming said first capacitor is greater than the thickness of said upper electrode forming said second capacitor. the dielectric film constituting the first capacitor is made of a first dielectric film,
4. The dielectric film according to claim 1, wherein said dielectric film constituting said second capacitor is made of a second dielectric film different from said first dielectric film. electronic components. the dielectric film constituting the first capacitor is made of a first dielectric film,
4. The dielectric film according to any one of claims 1 to 3, wherein the dielectric film forming the second capacitor comprises a laminated film of the first dielectric film and the second dielectric film. electronic components. further comprising a plurality of terminal electrodes,
the thickness of the dielectric film forming the first capacitor is thinner than the thickness of the dielectric film forming the second capacitor;
The plurality of conductor layers includes an inductor pattern,
the first capacitor is connected between any two of the plurality of terminal electrodes via the inductor pattern;
6. The electronic component according to claim 1, wherein said second capacitor is connected between any two of said plurality of terminal electrodes without interposing said inductor pattern. forming a first conductor layer having first and second regions on a substrate;
covering the first and second regions of the first conductor layer with a first dielectric film;
forming a second conductor layer on the first region of the first conductor layer through the first dielectric film;
covering the first dielectric film formed on the second region of the first conductor layer with a second dielectric film;
and forming a third conductor layer on the second region of the first conductor layer via the first and second dielectric films. Method. forming a first conductor layer having first and second regions on a substrate;
covering the first and second regions of the first conductor layer with a first dielectric film;
forming a second conductor layer on the first region of the first conductor layer through the first dielectric film;
After removing the first dielectric film formed on the second region of the first conductor layer, the second region of the first conductor layer is covered with a second dielectric film. process and
forming a second conductor layer on the second region of the first conductor layer through the second dielectric film. forming a first conductor layer having first and second regions on a substrate;
covering the first and second regions of the first conductor layer with a first dielectric film;
selectively reducing the thickness of the first dielectric film formed on the second region of the first conductor layer;
and forming a second conductor layer on the first and second regions of the first conductor layer through the first dielectric film. Method.

Images