JP2022129677A - game machine - Google Patents

Abstract

To provide a game machine in which various performance control operations are further improved.SOLUTION: On the basis of a predetermined pulse signal, a performance motor is driven to rotate or stop. In a predetermined accessory performance, after the frequency of the pulse signal maintains a specified frequency, an accessory stops, having a deceleration time in which it gradually decreases.SELECTED DRAWING: Figure 60

Description

TECHNICAL FIELD The present invention relates to a game machine that performs lottery processing caused by game operations and executes image effects corresponding to the lottery results, and more particularly to a game machine that can stably execute powerful character object effects and image effects.

A pinball game machine such as a pachinko machine is equipped with a pattern starting port provided on a game board, a pattern display section for displaying a series of pattern variations by a plurality of display patterns, and a prize winning port in which an opening/closing plate is opened and closed. configured as follows. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the displayed symbols are changed in the symbol display unit for a predetermined period of time. After that, when the symbols stop in a predetermined manner such as 7, 7, 7, etc., a big hit state is entered, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a jackpot lottery that is executed on the condition that a game ball has entered the symbol start opening, and the above-described symbol variation operation is based on the results of this lottery. It is a thing. For example, when the lottery result is a winning state, a performance operation called reach action is executed for about 20 seconds, and then the special symbols are arranged. On the other hand, a similar ready-to-win action may be executed even in the case of a losing state, and in this case, the player will pay attention to the transition of the performance action while strongly hoping for a big win state. Then, when the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed a big hit state.

The pattern variation operation is normally executed in the liquid crystal display section (Patent Documents 1 to 4), but the pixels of H×V dots forming the liquid crystal display section are synchronized with the operation clock CK (=dot clock DCK). The display is updated by being driven. In order to smoothly execute the display update operation (frame update), the pulse widths of the horizontal synchronizing signal HS and the vertical synchronizing signal VS, and between the respective synchronizing signals HS and Vs and the transmission timing of the image signal are, for example, , a predetermined condition such as FIG. 42(g) is required.

In the illustrated drive conditions, first, the pulse width PWh of the horizontal synchronizing signal HS is 96 clocks CK, and the front porch FPh and the back port BPh required before and after the horizontal synchronizing signal PWh are respectively: 16 and 48 operation clocks CK are defined. On the other hand, the pulse width PWv of the vertical synchronizing signal VS is two lines, and the front porch FPv and the back port BPv required before and after the vertical synchronizing signal VS are defined as 19 lines and 33 lines, respectively. It is

Then, an external control device for controlling the liquid crystal display section outputs a horizontal synchronizing signal HS that satisfies the horizontal conditions (PWh, FPh, BPh) and a horizontal synchronizing signal HS that satisfies the vertical conditions (PWvh, FPvh, BPvh). , image signals corresponding to the number of pixels of the display screen are repeatedly supplied to the liquid crystal display section.

By the way, in addition to the pattern variation operation using the liquid crystal display, by appropriately moving a movable object called a character, an advance notice effect that gives an indeterminate notice of the lottery result may also be executed. In addition, even after the big win state is brought about, there are cases where the role production is executed in order to effectively excite the player.

Accessory objects are usually driven and controlled by stepping motors, but bipolar drive motors are exclusively used because motor control is easy (Patent Documents 5 and 6).

JP 2017-093633 A JP 2017-093632 A JP 2016-159030 A JP 2016-159029 A JP 2016-007258 A JP 2018-153304 A

By the way, in this type of game machine, there is a desire to make various effects complicated and rich, and in particular, there is a high demand for image effects using a liquid crystal display. In addition, there is a demand to increase the power of the performance of the role. For example, if the performance of a heavy role suddenly moving at high speed can be realized, the impact on the player will be extremely large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gaming machine in which various effects control operations centered on image effect control are further improved.

In order to achieve the above object, the gaming machine according to the present invention includes a performance control means for controlling a role product performance in which a role product moves in accordance with the rotation of a performance motor; and a driving means for generating a drive signal based on the pulse signal to drive the effect motor, and the effect motor is configured to be driven to rotate or stop based on a predetermined pulse signal, and a predetermined pulse signal. The performance of the character is configured such that the frequency of the pulse signal maintains a specified frequency, and then the character is stopped after a deceleration time that gradually decreases.

According to the above-described present invention, the production control operation is improved by smoothly realizing novel character production.

It is a perspective view showing the pachinko machine of the present embodiment. 2 is a front view showing a game area of the gaming machine of FIG. 1; FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1; FIG. It is drawing explaining the specification of a display apparatus. It is a block diagram explaining an internal configuration of a display. It is drawing explaining the circuit structure and operation|movement of an electric power feeding control circuit. 2 is a block diagram showing in some detail the circuit configuration of an effect control unit in the gaming machine of FIG. 1; FIG. It is drawing explaining the composite chip|tip which comprises a production|presentation control part. 5 is a block diagram showing an internal configuration of a CPU circuit shown in FIG. 4; FIG. The memory map of built-in CPU (production control CPU) of the CPU circuit is illustrated. 4 is a drawing for explaining various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) for the DMAC; 4A and 4B are diagrams for explaining an index space, an index table, a virtual drawing space, and a drawing area; 2 is a block diagram describing the internal configuration of a data transfer circuit together with related circuit configurations; FIG. 2 is a block diagram describing the internal configuration of a display circuit together with related circuit configurations; FIG. FIG. 10 is a drawing for explaining a data enable signal ENAB output from a VDP circuit; FIG. 4 is a flowchart for explaining power reset operation after CPU reset; FIG. 17 is a flowchart illustrating memory section initialization processing, which is a part of FIG. 16; FIG. 17 is a flowchart for explaining main introduction processing and interrupt processing, which are a part of FIG. 16; FIG. 10 is a flowchart for explaining CGROM initialization processing, which is part of the main installation processing; FIG. Fig. 10 is a flow chart illustrating the operation of another embodiment using interrupt handling; FIG. 19 is a flowchart for explaining the main introduction process following FIG. 18 and the process up to the steady process; FIG. FIG. 22 is a flowchart for explaining a steady process following FIG. 21; FIG. 4 is a diagram for explaining the configuration of a display list; FIG. FIG. 10 is a flowchart showing DL issuing processing for issuing a display list DL; FIG. FIG. 25 is a flowchart for explaining the operation when the DMAC is involved in the operation of FIG. 24; FIG. FIG. 26 is a flowchart for explaining an operation following the processing of FIG. 25; FIG. 4 is a flow chart for explaining steady-state processing when a preloader is used; FIG. 28 is a flow chart explaining a part of FIG. 27; FIG. FIG. 28 is a flowchart illustrating another portion of FIG. 27; FIG. 5 is a time chart showing the operation of each part of the VDP in an example that does not use a preloader; 4 is a time chart showing the operation of each part of the VDP in an example using a preloader; FIG. 11 is a block diagram showing the overall circuit configuration of another embodiment; Figure 33 is a block diagram showing a portion of Figure 32 in slightly more detail; FIG. 10 is a time chart for explaining the operation content of another embodiment; FIG. It is drawing explaining another Example. It is drawing explaining the Example which sets a setting value repeatedly. It is a drawing explaining a circuit configuration of an embodiment using a built-in audio circuit. 4 is a flowchart for explaining the initial setting operation of the audio circuit; FIG. 10 is a diagram for explaining another embodiment of the power reset operation after CPU reset; 4 is a time chart showing an example of memory READ operation and memory WRITE operation; It is drawing explaining another Example. 4A and 4B are diagrams for explaining a driving method of a general display device; It is drawing explaining a display list. It is drawing explaining a zoom advance notice. It is drawing explaining the process of CPU for implement|achieving rotation operation. It is drawing which shows the basis of a calculation formula. 4 is a time chart showing deformation operations of the backlight section and the liquid crystal display section when the power is turned on; 4 is a time chart showing another deformation operation of the backlight section and the liquid crystal display section when the power is turned on. FIG. 4 is a block diagram for explaining a circuit configuration for realizing performance of a character. The internal configuration of the serial port and the connection relationship between the motor driver and the sensor substrate are illustrated. It is drawing explaining the internal structure of a sensor board|substrate. It is a drawing explaining a motor driver. It is drawing explaining operation|movement of a bridge drive circuit. 4 is a time chart for explaining constant current control operation; Figure 3 shows a detailed view of a portion of the motor driver; FIG. 4 illustrates the relationship between the driving data received by the motor driver and the A-phase and B-phase driving currents. 2 is a block diagram showing the internal configuration of a motor driver; FIG. FIG. 4 illustrates the relationship between the stepping clock and the constant-current-controlled drive current. 3 is a block diagram showing the internal configuration of a motor controller; FIG. It is drawing explaining various drive systems. It shows the contents of timer interrupt processing, and is a detailed version of the contents of FIG. 22(b). 4 is a time chart for explaining the operation of the motor controller; 4 is a time chart for explaining the operation of a serial port; It is a drawing explaining a spiral shaft and an example of character production.

The present invention will be described in detail below based on examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular wooden outer frame 1 detachably attached to an island structure, and an inner frame 3 pivotally attached via hinges 2 fixed to the outer frame 1 so as to be openable and closable. It is configured. A game board 5 is detachably attached to the inner frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotably attached to the front side thereof so as to be openable and closable. In this specification, the glass door 6 and the front plate 7 are collectively referred to as a front door member. The inner frame 3 to which the front door member (the glass door 6 and the front plate 7) is pivotally attached is sometimes referred to as a game frame.

Illuminated lamps such as LED lamps are arranged in a substantially C shape around the outer periphery of the glass door 6 . On the other hand, a total of three speakers are arranged on the upper left and right positions of the glass door 6 and on the lower side. The two upper speakers are configured to output left and right channel R and L sounds, respectively, and the lower speaker is configured to output bass sounds.

An upper plate 8 for storing game balls to be shot is attached to the front plate 7, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a shooting handle are attached to the lower part of the inner frame 3. 10 are provided. A shooting handle 10 is interlocked with a shooting motor, and a game ball is shot by a hitting mallet that operates according to the rotation angle of the shooting handle 10.例文帳に追加

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. - 特許庁The chance button 11 is provided at a position where it can be operated with the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the shooting handle 10.例文帳に追加The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp lights up and becomes operable. Note that the button chance state is a game state provided as necessary.

A rotary switch-type volume switch VLSW is arranged below the chance button 11, and the player operates the volume switch VLSW to change the level from silent level (=0) to maximum level (=7). The speaker volume can be adjusted in eight steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by the staff, and the initially set volume is maintained unless the player operates the volume switch VLSW. Also, the abnormal notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial volume set by the staff or the volume set by the player.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for the card-type ball lending machine is provided, and a frequency display section for displaying the remaining card amount in three digits and a predetermined amount of game balls are provided. A ball lending switch for instructing lending and a return switch for instructing card return at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 consisting of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided substantially in the center thereof. Under the central opening HO, a movable effect body (not shown) is housed in a concealed state. We have realized the preview performance. Here, the notice performance is a performance that uncertainly notifies the occurrence of a big win state advantageous to the player, and the reliability of the notice performance means the probability of the occurrence of the big win state.

A main display device DS1 composed of a large liquid crystal color display (for example, 1280 pixels wide by 1024 pixels long) is arranged in the central opening HO. 800 pixels) liquid crystal color display is arranged. The main display device DS1 is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that variably displays specific symbols related to a big win state and also displays a background image and various characters in an animated manner. . This display device DS1 has special symbol display portions Da to Dc in the central portion and a normal symbol display portion 19 in the upper right portion. Then, in the special pattern display parts Da to Dc, a ready-to-win performance to expect the arrival of a big hit state is sometimes executed, and in and around the special pattern display parts Da to Dc, an appropriate advance notice performance is executed.

The sub-display device DS2 normally displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, during a predetermined notice effect, it moves to the left side of the drawing while changing the tilt angle to an angle that is easy for the player to see, and displays a predetermined notice image.

In other words, the sub-display device DS2 of the embodiment functions not only as a display device but also as a movable effect body for executing the advance notice effect. Here, the advance notice effect by the sub-display device DS2 is set to have a high degree of reliability, and the player pays attention to the moving action of the sub-display device DS2 with great anticipation. The sub-display device DS2 is also composed of a sub-liquid crystal display unit MONI and an LED backlight unit BL.

By the way, the game area where the game ball falls and moves includes the first symbol starting port 15a, the second symbol starting port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18. are arranged. Each of these winning holes 15 to 18 has a detection switch inside so that the passage of a game ball can be detected.

Above the first symbol starting port 15a, a production stage 14 is arranged so that the first symbol starting port 15 can win after the game ball entering from the introduction port IN moves in a seesaw or roulette shape. there is Then, when a game ball wins the first symbol starting port 15, the special symbol display portions Da to Dc are configured to start varying operations.

The second symbol start port 15b is configured to be opened and closed by an electric tulip provided with a pair of left and right opening and closing claws, and when the stop symbol after the change of the normal symbol display unit 19 is displayed as a winning symbol, a predetermined The opening/closing claw is opened for a period of time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays normal symbols, and when a game ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time, and is extracted when the game ball passes through the gate 18. A stop pattern determined by the selected random number for lottery is displayed and stopped.

The first big prize winning port 16a has a sliding board that advances and retreats in the front-rear direction, and the second big prize winning port 16b has an opening/closing plate whose lower end is pivotally supported and which opens forward. . Although the operations of the first big winning hole 16a and the second big winning hole 16b are not particularly limited, in this embodiment, the first big winning hole 16a corresponds to the first symbol starting hole 15a, and the second big winning hole 16b is configured to correspond to the first symbol starting port 15b.

That is, when the game ball wins in the first symbol start port 15a, the special symbol display portions Da to Dc start to fluctuate, and after that, when the predetermined jackpot symbols are arranged in the special symbol display portions Da to Dc, the first jackpot. A special game is started, and the slide board of the first big winning hole 16a is opened forward to facilitate the winning of game balls.

On the other hand, as a result of the fluctuation operation started by the winning of the game ball to the second symbol starting port 15b, when the predetermined big winning symbols are arranged in the special symbol display parts Da to Dc, the second big winning special game is started. The opening/closing plate of the second prize winning port 16b is opened to facilitate winning of game balls. The game value of the special game (jackpot state) varies depending on the jackpot symbols to be arranged, but which game value is given is determined in advance based on the lottery result corresponding to the winning timing of the game ball. It is determined.

In a typical jackpot state, after the opening/closing plate of the big winning hole 16 is opened, the opening/closing plate closes when a predetermined time elapses or when a predetermined number (for example 10) of game balls win. Such actions are continued up to, for example, 15 times, and are controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the special game ends will be in a high probability state (definite variable state). Granted.

FIG. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that implements the operations described above. Further, FIG. 3(b) is a circuit diagram showing the circuit configuration of the power monitor unit MNI arranged on the payout control board 25, and FIG. 3(c) shows the specifications of the main display device DS1 used in this embodiment. It is a drawing explaining.

First, based on FIG. 3(c), the specifications of the main display device DS1 used in the embodiment will be described. As described above, the display device DS1 is a liquid crystal color display of 1280 horizontal pixels by 1024 vertical pixels. (Differential Signaling) transmission line and received by the receiver RV (RVa+RVb). Therefore, in this embodiment, according to this dual link specification, the ODD signal is transmitted via the first transmission line LVDS1, and the EVEN signal is transmitted via the second transmission line LVDS2 ( lower right part of FIG. 3(a)).

Further, in this display device DS1, the operating clock CK (see FIG. 42) that defines the internal operation of the display device DS1 is defined to have a frequency in the range of 40 MHz to 70 MHz (typical value=54 MHz). This operating clock CK corresponds to the LVDS clock CLK, which will be described later. For convenience of explanation, the frequency of the operating clock CK is assumed to be a typical value of 54 MHz. Also, a configuration will be described in which the update time FR (Frame Rate) required to update the image of one frame is made approximately equal to 1/60 second at the operating clock CK of 54 MHz.

The display device DS1 has specifications such that two pixels adjacent to each other in the horizontal direction of the display screen are aligned in accordance with the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. are configured to be processed at the same time with the operation clock CK of . As a result, the pixel data of 1280 pixels in one horizontal line is updated in an operation time of 640/54 MHz=11.85 μs, and this operation is repeated for 1024 lines to produce an image of 1280×1024 pixels for one frame. The display will be updated. Note that the image is updated line by line in the non-interlaced manner, such as the 1st line, the 2nd line, . . . , the 1024th line.

However, as shown in FIG. 3(c), the specification of the display device DS1 is to provide a standby time (blank period) of 204 clocks in the horizontal direction as a typical value, and to provide a standby time (blank period) of 204 clocks in the vertical direction as a typical value. defines that a waiting time (blank period) for 42 lines is provided. Therefore, the actual screen update period FR considering these blank periods is (204+640)×(42+1024)/54 MHz≈16.66 mS in the calculation based on the above typical values, so the frame rate FR is about 1/ 60 Hz.

Note that the horizontal waiting time WTh and the vertical waiting time WTv each have a permissible range for typical values, and in practice, values different from the above typical values can be selected. However, since the frame rate FR = 1/60 seconds, it is necessary to accurately set the horizontal/vertical waiting time WTh/WTv so that (WTh+640) x (WTv+1024)/54 MHz = 1/60 seconds. .

On the other hand, the display device DS1 does not particularly need to receive the horizontal synchronizing signal HS and the vertical synchronizing signal VS, but requires the transmission of the H-level data enable signal ENAB when transmitting the ODD signal and the EVEN signal. That is, the data valid signal ENAB needs to be at the active level (H) at the timing when a significant signal (ODD/EVEN signal) is transmitted to the transmission lines LVDS1 and LVDS2.

Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the effect control board 23 and the main display device DS1 are dual-link-transmitted with the LVDS clock CLK having a frequency of 54 MHz (= 1/2 of the dot clock DCK). are LVDS-connected via a path (FIGS. 5 and 14(a)). In addition, in the VDP circuit 52 of this embodiment, a horizontal blank period WTh and a vertical blank period WTv that satisfy the specifications of the main display device DS1 are provided. ENAB is set to the active level (H level).

That is, as shown in FIG. 4(b), the data enable signal ENAB is configured to be at H level only during the horizontal display period THd in the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always at L level during the vertical synchronization period TV except for the vertical display period TVd. Note that the horizontal blank period WTh and the vertical blank period WTv adopt values different from their respective typical values (WTh=204/WTv=42), but specific design values are based on FIG. will be described later.

In any event, the data valid signal ENAB is repeatedly transmitted via the differential signal lines RA2/RB2 as discrete DE signals in each operating cycle of the LVDS clock CLK. The data valid signal ENAB shown in FIG. 4(b) and FIG. 4(c) is obtained by demodulating the DE signal, which is discrete data transmitted by LVDS, and the discrete DE signal is continuous on the time axis. is. In the differential signal lines RA2/RB, the vertical synchronizing signal VS and the horizontal synchronizing signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB). The device DS1 does not utilize the synchronization signals VS and HS.

However, in the display device DS1, transmission of the horizontal synchronization signal HS and the vertical synchronization signal VS is not prohibited at all. However, internal operations specified by these synchronization signals are not executed. That is, regardless of the received horizontal synchronization signal HS, the horizontal line feed timing of the display line is the falling timing of the data valid signal ENAB or the operating clock CK (corresponding to the LVDS clock CLK) after the rising timing of the data valid signal ENAB. (640 = 1280/2 in the embodiment), the optimal timing for the internal circuit of the display device DS1 is defined (downward arrow in FIG. 4B).

This point is the same for the vertical line feed timing after displaying an image for one frame. (downward arrow in FIG. 4(c)) and is not affected by the received vertical sync signal VS. Thus, in this embodiment, since it is not necessary to transmit the horizontal synchronizing signal HS and the vertical synchronizing signal VS to the display device DS1, the pulse widths PWh/PWv of the synchronizing signals HS and VS, the front port FPh/FPv, It is no longer necessary to optimally set the back port BPh/BPv, and the control burden on the effect control section 23 and the VDP circuit 52 is greatly reduced.

Further, as for the internal operation of the display device DS1, horizontal line feed and vertical line feed operations are executed at optimum timing based on its own internal configuration, thereby eliminating the possibility of unnatural display operations. Incidentally, in the case of a display device that operates based on the horizontal synchronizing signal HS and the vertical synchronizing signal VS received from the outside, the pulse width of the synchronizing signals HS and VS, the front porch period before and after the synchronizing signals HS and VS, If the back porch period is inappropriate, normal display operation may be impaired.

By the way, in FIG. 4A, the first differential signal LVDS1 using the differential signal lines RA0 to RA3 and RACLK transmits odd-numbered pixels (ODD signal on the A side), and the differential signal A second differential signal LVDS2 using lines RB0-RB3 and RBCLK carries the even numbered pixels (B-side EVEN signal). Thus, in this embodiment, by transmitting two types of ODD signal and EVEN signal through the dual-link transmission path, the frequency of the dot clock DCK can be reduced to 1/2, and the noise resistance can be reduced accordingly. It has excellent performance and can increase the transmission distance.

On the other hand, the main display device DS1 has a built-in conversion receiver RV for the ODD signal and the EVEN signal transmitted through the dual link transmission line, and restores the RGB signal from the two LVDS signals (ODD signal and EVEN signal). Then, an image of one frame (1280×1024 dots) is displayed. As described above, each of the RGB signals is composed of 8 bits, so a full-color image with a gradation of 2 ⁸ ×2 ⁸ ×2 ⁸ is displayed on the main display device DS1.

FIG. 5 is a block diagram showing, in particular, the internal configuration of the liquid crystal display unit MONI together with the relevant parts of the VDP circuit 52 for the display device DS1 composed of the main liquid crystal display unit MONI and the LED backlight unit BL. As shown, the ODD signal is transmitted to the LVDS-to-parallel converter RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-parallel converter RVa via the second LVDS line (B side). It is transmitted to the parallel converter RVb. Image data R0 to R5 and G0 are extracted from the 8-bit RGB data transmitted on the differential lines RA0/RB0, and image data G1 to G5 and B0 are extracted from the differential lines RA1/RB1. ~B1 is poured out.

Image data B2 to B5, DE signal, VS signal and HS signal are extracted from the differential lines RA2/RB2, and image data G6 to G7, R6 to R7, B6 to B7 is poured out. Here, the DE signal is nothing but the data valid signal ENAB. Also, as mentioned above, the extracted VS and HS signals are not used.

Next, the LVDS clock CLK on the differential lines RACK/RBCK is supplied to the PLL circuit to generate an operating clock CK having the same frequency of 54 MHz as the LVDS clock CLK. This operating clock CK defines the internal operation of the liquid crystal controller LCD_CTL. The liquid crystal controller LCD_CTL controls image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent to each other in the horizontal direction of the liquid crystal panel LCD. are collectively processed in synchronization with one operating clock CK.

Therefore, a pixel of 1280 (=640×2) dots in the horizontal direction will be processed in 11.85 μS (=640/54 MHz) of processing time corresponding to 640 operation clocks CK. Note that one pixel is composed of basic pixels of three colors of RGB, and the image data of the basic pixels of three colors of RGB each has a length of 1 byte and a gradation of 2 ⁸ ×2 ⁸ ×2 ⁸ . Image data of all pixels (1280 dots) of one line has a length of 3×1280 bytes as a whole.

As shown in FIG. 5, the liquid crystal controller LCD_CNT has a source driver SDV that drives 1280 source signal lines with drive signals of 2 ⁸ (=256) gradations and ON/OFF control of 1024 gate signal lines. The gate driver GDV is appropriately controlled. Specifically, the liquid crystal controller LCD_CNT performs an image updating operation at a frame rate FR=1/60 Hz by appropriately operating each unit based on the DE signal extracted from the LVDS transmission line and the operation clock CK. Realized. As previously identified, the DE signal corresponds to the data valid signal ENAB output by VDP circuit 52 .

In the case of this embodiment, the source driver SDV is configured by arranging 10 driver elements each having 384 output terminals. As described above, one line of all pixels (1280 dots) of the liquid crystal panel LCD is composed of RGB three-color basic pixels, and the total number is 3×1280. Therefore, ten driver elements are required to drive these pixels. Become. Image data DAT is sequentially supplied to these 10 driver elements from the liquid crystal controller LCD_CNT, and is appropriately transferred based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, analog-converted drive signals are supplied to 3840 source signal lines. As described above, the time required to update all the pixels (1280 dots) of one line of the liquid crystal panel LCD is 11.85 μS (=640/54 MHz).

On the other hand, the liquid crystal controller LCD_CNT supplies the gate start signal GS and the gate clock signal GCLK to the gate driver GDV to update the gate signal lines to be driven. Here, the gate driver GDV is configured by arranging four driver elements having 256 output terminals.

The update timing of the gate signal line is defined based on the fall timing of the DE signal and the operation clock CK. It is used as a clock (see FIG. 3(c)). Also, based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, the gate start signal GS is output at optimum timing, and the output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal line is counted by the operation clock CK, and is 42+1024 clocks in a typical value calculation (see FIG. 3(c)). However, as described above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see FIG. 15).

By the way, the above display operation is performed under the condition that a power supply voltage of 5 V is supplied to the main liquid crystal display unit MONI in the lighting state of the LED backlight unit BL. Therefore, in this embodiment, a power supply control circuit SPY is provided to operate the liquid crystal display unit MONI and the backlight unit BL in a consistent manner. The power supply control circuit SPY receives three types of DC voltages (3.3V, 5V, 12V) from the effect interface board 22, and various power supply control signals (STBY, PWM, PS1 , PS2) (see FIG. 7(a)).

Then, the power supply control circuit SPY supplies the DC voltage of 5V as the power supply voltage of the main liquid crystal display unit MONI at the optimum timing (see FIGS. 6(c) and 6(g)). In addition, the power supply control circuit SPY controls the power supply of a DC voltage of 12V as the power supply voltage of the backlight section BL, and controls the BL_EN terminal and the PWM terminal of the LED backlight section BL to appropriate H/L levels. achieves optimal lighting operation.

FIG. 6A is a circuit diagram showing the circuit configuration of the power supply control circuit SPY and the relationship between the backlight unit BL and the liquid crystal display unit MONI. As illustrated, the power supply control circuit SPY includes a first switch circuit having a transistor Tr1 and a MOS transistor Q1, a second switch circuit having a transistor Tr2 and a MOS transistor Q2, and a third switch having a transistor Tr3 and a MOS transistor Q3. A circuit, a fourth switch circuit having a transistor Tr4 and a MOS transistor Q4, and a buffer circuit SBUF for receiving various control signals.

The buffer circuit SBUF is a high-speed Schmidt buffer (for example, TC74VHC9125) whose power supply voltage is a DC voltage of 3.3 V supplied from the performance interface board 22, and operates in a non-inverted input/output relationship. That is, the production control CPU 63 of the composite chip 50 outputs power supply control signals (STBY, PWM, PS1, PS2) with a theoretical H/L width of 3.3V based on the power supply voltage of 3.3V. , the buffer circuit SBUF receiving this outputs control signals (STBY, PWM, PS1, PS2) of the same logic (see FIG. 7(a)).

As shown in FIG. 6(a), the four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are all connected to the ground via pull-down resistors Rpd, and the separation state of the connector and the , when each control signal is in a HiZ (high impedance) state such as when the power is turned on, all the control signals are set to L level.

Next, in the first to fourth switch circuits, the transistors Tr1 to Tr4 are all NPN type bipolar transistors and are driven to perform switching operations. That is, when the corresponding control signals PS1/STBY/PWM/PS2 are at H level, the respective transistors Tr1/Tr2/Tr3/Tr4 are turned on based on the voltage division ratio of the bias resistors, while the control signals PS1/STBY/ When PWM/PS2 is at the L level, no current flows through the bias resistor, so the OFF operation is performed.

Here, when the transistors Tr1/Tr4 are turned off, the collector outputs of the transistors Tr1/Tr4 are all higher than 3.3V (12V/5V). When the MOS transistor Q1 is ON and the transistors Tr2/Tr3 are OFF, the collector output of each transistor Tr2/Tr3 is approximately 12V. In this sense, each of the transistors Tr1 to Tr4 constitutes a level shift circuit that increases the logic H level of the power supply control signals (STBY, PWM, PS1, PS2) together with the bias resistor.

Bias resistors for the transistors Tr1 to Tr4 are R11+R12, R21+R22, R31+R32, and R41+R42, respectively, and a voltage defined by the voltage dividing ratio of each bias resistor is supplied to the base terminals of the transistors Tr1 to Tr4.

In this embodiment, since the above-described level shift circuits (Tr1 to Tr4) are provided, the power consumption of the effect control section 23 can be greatly suppressed while increasing the light emission luminance of the backlight. That is, while the power supply voltage (12V) of the backlight unit BL is set to the highest possible level, the logic H level of the power supply control signals (STBY, PWM, PS1, PS2) is set to an arbitrary low level (3.3V). can be set to

On the other hand, the MOS transistors Q1 to Q4 are all of the Pch type, and perform switching operations according to the ON/OFF states of the transistors Tr1 to Tr4. Become.

Specifically, the MOS transistor Q1 receives, at its source terminal S, a DC voltage of 12 V supplied by the effect interface board 22. When the transistor Tr1 is turned ON based on the control signal PS1 at H level, In response to this, the MOS transistor Q1 is also turned ON based on the voltage across the bias resistor Rb1 which is switched to an energized state, and a DC voltage of 12 V is output to the drain terminal D. FIG.

This DC voltage of 12 V is supplied to the backlight unit BL via an RC filter circuit and a Zener diode. The RC filter circuit consists of a 3.3 kΩ resistor and a 47 μF conductive polymer capacitor (hybrid capacitor in which the electrolyte is a fusion of conductive polymer and electrolyte instead of the electrolytic solution of the aluminum electrolytic capacitor). It is configured.

This hybrid capacitor has a rated voltage of 25V and is a cylindrical SMD (Surface Mount Device) having a diameter of 6.3 mm and a height of 5.8 mm. And the capacitance at 5V feeding is kept below -10% of the nominal value (47 μF). Also, the equivalent series resistance ESR is nominally 50 mΩ.

In a normal circuit configuration, a ceramic capacitor (0.1 μF) such as an MLCC (Multilayer Ceramic Capacitor) is connected in parallel to a 47 μF electrolytic capacitor. It realizes ring operation and does not consume the layout space of other circuit elements.

Incidentally, no other smoothing capacitors or decoupling capacitors are arranged within a radius of at least 20 mm from the conductive polymer capacitor. In addition, in this embodiment, the decoupling capacitor is surface-mounted, and the through-hole mounting method is not adopted unlike the ordinary electrolytic capacitor, so there is also an advantage that the layout space can be reduced.

In addition, on the top surface of the surface-mounted cylindrical shape, a numerical value “47” indicating capacitance and a rank symbol “E” indicating a rated voltage of 25 V are written, and the negative polarity direction is indicated by a black symbol. , you can easily check the parts on the board by visual confirmation.

Moreover, in this embodiment, an element having an ON resistance between the source S and the drain D of 25 mΩ or more and 35 mΩ or less is used as the MOS transistor Q1. Therefore, for example, even if a drive current (drain current ID) of 2.5 A is constantly applied, the voltage drop in the MOS transistor Q1 is 0.1 V or less, and the power loss is 0.22 W (=2.5*2.5 *35/1000). Note that the ON resistance is the result of measurement under pulse driving at VGS=-10V and ID=-4.5A.

Further, the voltage of the drain terminal D of the transistor Q1 is received at the source terminals S of the transistors Q2 and Q3. Therefore, when the transistors Tr2/Tr3 are turned on based on the H level control signals STBY/PWM while the MOS transistor Q1 is in the ON state, the voltage across the bias resistors Rb2/Rb3 which are switched to the conductive state in response to this is applied. Then, the MOS transistors Q2 and Q3 are also turned ON. Therefore, a DC voltage of 12 V is output to the drain terminals D of the MOS transistors Q2 and Q3 via the ON-state transistor Q1.

This DC voltage of 12V is output from the drain terminal D of the MOS transistor Q2 as the control signal STBY, and is output from the drain terminal D of the MOS transistor Q3 as the control signal PWM. The control signal STBY is supplied to the BL_EN terminal (back light enable) of the backlight section BL in the pull-down state by the pull-down resistor Rpd, and the control signal PWM is the PWM signal of the backlight section BL in the pull-down state by the pull-down resistor Rpd. supplied to the terminal (pulse width modulation).

In this embodiment, by setting the pull-down resistors Rpd to about 33 kΩ, the current flowing through the pull-down resistors Rpd due to the DC voltage of 12 V (STBY/PWM) is suppressed to about 0.36 mA. Therefore, it is not necessary to select expensive elements as the MOS transistors Q2 and Q3, and in this embodiment, elements having an ON resistance between the source S and the drain D of 2.5Ω or more and 3.8Ω or less are used. . Note that the ON resistance is the measurement result of pulse driving at VGS=-4.5V and ID=-100mA.

Next, the backlight unit BL will be described. The backlight unit BL includes N×M light emitting diodes (LEDs) arranged vertically and horizontally, and outputs a negative logic drive pulse to generate N×M LEDs. and a driver DVL for synchronously driving the light-emitting diodes to light up. This driver DVL has a BL_EN terminal that defines whether to enable internal operations or not, and a PWM terminal that defines the duty ratio of negative logic driving pulses with positive logic in the range of 10% to 100%. and output terminals LED1 to LEDn for outputting drive pulses.

As described above, the BL_EN terminal is supplied with the control signal STBY from the power supply control circuit SPY, and the PWM terminal is supplied with the control signal PWM. When the control signal STBY is at the H level (12V), the internal circuit of the driver DVL operates and the output terminals LED1 to LEDn can output drive pulses. This driving pulse becomes a negative logic pulse obtained by logically inverting the control signal PWM.

As described above, the drive pulse in the embodiment is a negative logic pulse obtained by inverting the logic of the control signal PWM supplied to the PWM terminal. becomes longer and the average current flowing through the light emitting diodes increases, so that the backlight becomes brighter. On the other hand, the closer the duty ratio is to 10%, the lower the average current of the light emitting diodes and the darker the backlight.

Therefore, by appropriately changing the duty ratio of the control signal (control pulse) PWM, it is possible to change the emission intensity of the backlight. For example, the backlight may be dimmed in a demo state where no player is present. However, in this embodiment, in order to avoid such complexity of light emission control, the duty ratio of the control signal is maintained at 100%. The H level (12V) is constantly maintained. Therefore, the output terminals LED1 to LEDn of the driver DVL constantly maintain the L level in the operating state of the backlight section BL.

By the way, both the BL_EN terminal and the PWM terminal are grounded via a pull-down resistor Rpd. Therefore, when the MOS transistor Q2 is in the OFF state and the control signal STBY is in the HiZ state, the driver DVL is in the non-operating state and the output terminals LED1 to LEDn are in the HiZ state. Lights out.

Further, when the MOS transistor Q3 is in the OFF state and the control signal PWM is in the HiZ state, even if the control signal STBY is at H level, the duty ratio is maintained at 0% so that the output terminal LED1 to LEDn maintain the H level (12V) and all the light emitting diodes are turned off. Therefore, when power is turned on when significant image data is not transferred, or when the power supply control circuit SPY malfunctions, the backlight is turned off, thereby avoiding unnatural image display. It is based on the same intention that the pull-down resistors Rpd are connected between the four input terminals of the buffer circuit SBUF and the ground.

Next, the relationship between the fourth switch circuit having the transistor Tr4 and the MOS transistor Q4 and the main liquid crystal display unit MONI will be described. As described above, the transistor Tr4 of the fourth switch circuit is turned ON/OFF based on the H/L level of the control signal PS2.

On the other hand, the MOS transistor Q4 receives, at its source terminal S, a DC voltage of 5 V supplied by the effect interface board 22, and when the transistor Tr1 is turned ON, the bias resistor Rb4 is turned on in response. Based on the voltage across the MOS transistor Q4, the MOS transistor Q4 is also turned ON to output a DC voltage of 5V to the drain terminal D.

This DC voltage of 5V is supplied to the liquid crystal display MONI shown in FIG. 5 via an RC filter circuit and a Zener diode, and is used as a power supply voltage for the liquid crystal display MONI. In this embodiment, an element whose ON resistance between the source S and the drain D is 48 mΩ or more and 65 mΩ or less is used as the MOS transistor Q4. Therefore, for example, even if a drive current (drain current ID) of 1.5 A is constantly applied, the voltage drop in the MOS transistor Q1 is 0.1 V or less, and the power loss is 0.15 W (=1.5* 1.5*65/1000). The ON resistance is the result of measurement under pulse driving at VGS=-4.5 and ID=-2.5A.

Next, the circuit operation of the power supply control circuit SPY will be described with reference to FIGS. 6(b) to 6(j). After the power is turned on, the composite chip 50 starts the control operation (timing T1 in FIG. 6(d)) through an assert period in which the system reset signal SYS is maintained at L level. Then, the effect control CPU 63 of the composite chip 50 transitions the control signals PS1 and PS2 to H level 1000 mS after the timing T1 (timing T2).

Then, based on the H-level control signal PS1, the MOS transistor Q1 is turned on, and the supply of DC 12V to the backlight section BL is started. Also, based on the control signal PS2 of H level, the MOS transistor Q4 is turned on, and the supply of DC 5V to the liquid crystal display unit MONI is started. However, at this timing T2, the control signals STBY and PWM are both at the L level, so the backlight section BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no possibility that an unnatural image will be displayed.

Next, the effect control CPU 63 starts the initialization operation of the display clock and the display circuit 74 after about 5 ms has passed from the timing T2. The contents of this control will be described in detail later, but these operations are one of the initialization operations before the operation of the VDP circuit 52 is started. No output.

After that, the effect control CPU 63 appropriately initializes the display register, and then starts the operation of the display circuit 74 and the LVDS circuit 80 (timing T4). Therefore, after timing T4, the LVDS signal as a significant image signal is repeatedly output to the display device DS1 every 1/60th of a second (see FIG. 6(f)).

However, at the timing T4, the control signal PWM is maintained at the L level, so the backlight does not emit light. That is, the effect control CPU 63 transitions the control signal STBY to H level at timing T3 to control the driver DVL to an operable state. Since the duty ratio of the pulse is 0%, the backlight unit BL is maintained in the off state.

On the other hand, after starting the operation of the display circuit 74 and the LVDS circuit 80 (SS4 in FIG. 21), the effect control CPU 63 shifts the control signal PWM to the H level at the timing T5 after 300 ms or more has passed (FIG. 21 SS6), the backlight unit BL is transitioned to a light emitting state with a duty ratio of 100%. When the operation at timing T5 is executed by timer interrupt processing, for example, at timing T5, the liquid crystal display unit MONI has already repeatedly generated the LVDS signal as a significant image signal every 1/60 second. Since the image signal is received, an image based on the image signal is displayed. That is, since the steady process (ST4 to ST14 in FIG. 22) is started immediately after the process of step SS6 in FIG. 21, the initial screen based on the display list DL is displayed at time T5.

However, as shown in FIG. 21, when the effect control CPU 63 executes the standby process of 300 ms (step SS5 in FIG. 21), at timing T5, the display list DL has not yet been issued. is a screen based on the VRAM (frame buffer FBa) after power-on. Therefore, in consideration of this point, it is preferable to zero-clear the VRAM (particularly the frame buffers FBa and FBb) after power-on. There is no problem at all because it is only for a moment at the opening of the hall. That is, immediately after the process of step SS6 in FIG. 21, the normal process (ST4 to ST14 in FIG. 22) is started, and the initial screen based on the display list DL is displayed.

By the way, in this embodiment, the program is designed so that the program execution time from timing T2 to timing T4 is within 20 ms. This recommends that the display device DS1 used in the embodiment should start transmitting an image signal (LVDS signal) within a predetermined time τ (for example, 20 mS) after the liquid crystal display unit MONI is powered on. It is from.

In this embodiment, the control signal PS2 is used to delay the power supply timing to the liquid crystal display unit MONI by about one second, which is also based on the above requirement. After starting the power supply, it is very impossible to start transmitting the LVDS signal within a predetermined time τ (for example, 20 ms) due to the assertion period and program execution time (processing time of SP1 to SP10) (timing T4 reference).

Although the main display device DS1 has been described in detail above, the operation of the sub display device DS2 is substantially the same. The backlight unit BL is configured to operate in a consistent manner so that inappropriate display does not occur.

42 based on the horizontal synchronizing signal HS and the vertical synchronizing signal VS received from the VDP circuit 52. In FIG. However, it is also preferable to employ a configuration in which the sub-controller DS2 also operates based on the data valid signal ENAB, not based on the horizontal synchronizing signal HS or the vertical synchronizing signal VS. The data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, not in the form of discrete DE signals (see the lower right part of FIG. 14(a)).

Next, returning to FIG. 3A, the overall circuit configuration of the pachinko machine GM will be described. As shown in FIG. 3( a ), this pachinko machine GM includes a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) together with AC24V, and a main unit responsible for centrally and centrally responsible for game control operations. A control board 21, a presentation interface board 22 on which a circuit element SND for voice presentation is mounted, and a lamp presentation, a voice presentation, and an image presentation are collectively executed based on a control command CMD received from the main control board 21.例文帳に追加A performance control board 23, a liquid crystal interface board 24 positioned between the performance control board 23 and the display devices DS1 and DS2, and a payout motor M are controlled based on a control command CMD' received from the main control board 21 to play the game. It is mainly composed of a payout control board 25 for putting out balls and a shooting control board 26 for shooting game balls in response to the player's operation.

The effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are directly connected through male connectors and female connectors without wiring cables. Therefore, even if the circuit configuration of each electronic circuit is complicated and advanced, the storage space for the entire board can be minimized, and noise resistance can be enhanced by shortening the connection line.

As shown, the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22 . Here, each of the control commands CMD and CMD' has a 16-bit length, but is divided into two 8-bit lengths and transmitted in parallel.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25 . Also, the performance control board 23 is equipped with a composite chip 50 in which computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 are built. Therefore, these control boards 21, 25, 23, the circuits mounted on the effect interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are collectively functionally referred to in this specification as , the main control unit 21, the performance control unit 23, and the payout control unit 25. Note that the effect control unit 23 and the payout control unit 25 are sub-control units for the main control unit 21 .

Further, the pachinko machine GM is roughly divided into a frame-side member GM1 surrounded by a dashed line in FIG. The frame-side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof, so that the game hall can be used for a long period of time regardless of model changes. fixedly installed in the On the other hand, the board-side member GM2 is replaced in response to the model change, and the new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame side member 1 are board side members GM2.

As shown in the dashed frame in FIG. 3A, the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, a motor/ A lamp drive board 37 is included, and these circuit boards are each fixed in place on the inner frame 3 . On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with the display devices DS1, DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3 arranged centrally in one place.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC 24V power distributed from the game hall, and each DC voltage is sent via the central connection connector C2 to the production interface. Power is distributed to the face substrate 22 . In addition, the three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltage (35V, 12V, 5V) distributed to the payout control board 25 is configured to be distributed to the main control board 21 together with the backup power supply BAK via the central connection connector C1.

DC 35V is used as a drive power source for the ball feed solenoid and the launch solenoid, and for the electric tulip (variable prize winning device) and the electromagnetic solenoid that opens and closes the big prize opening 16 for the game ball shooting operation. In addition, DC 12V is used as the drive power supply for the LED lamps and motors controlled from each control board, and the power supply voltage for the digital amplifier, while DC 5V is used for the one-chip microcomputer of the payout control board 25 and the main control board 21 and the power supply voltage of the logic elements mounted on each control board. In addition, after the DC 5V is level-dropped by the DC/DC converter of the production interface board 22, the level-dropped voltages of various levels are used as power supply voltages for various computer circuits (composite chip 50, audio processor 27, etc.). used.

The backup power supply BAK is a DC5V DC power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and an electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged during game operation by a DC voltage of 5 V received from the payout control board 25. It is

On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so the main control unit 21 and the payout control unit 25 can The game operation can be restarted after the power is turned on. The backup power supply board 33 is provided with an electric double layer capacitor capable of retaining the contents of the internal RAM of each one-chip microcomputer for at least several days.

By the way, in the present embodiment, unlike the conventional equipment configuration, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is configured to be generated not by the power supply board 20 but by the power supply monitoring unit MNT of the payout control board 25. It is As shown in FIG. 3B, the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies AC 24V received from the power supply board 20, a photodiode D that emits light upon receiving the output of the full-wave rectifier circuit, and the power supply board 20. A phototransistor TR which is powered by a DC voltage of 5V received from a photodiode D and is turned ON based on the light emission of the photodiode D, and an output section which outputs an H-level detection signal ABN (power failure signal) based on the ON operation of the phototransistor TR. and The photodiode D and the phototransistor TR constitute a photocoupler PH.

In the above configuration, the photocoupler PH is quickly turned on after the power is turned on, so that the power failure signal ABN becomes the normal level (H). However, after that, if the AC power supply abnormally drops for some reason (normally, the power supply is cut off), the photocoupler PH changes to the OFF state, and the power supply abnormality signal ABN changes to the abnormal level (L). This power failure signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the central connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal level power supply abnormality signal ABN executes a backup process for storing necessary information in its own built-in RAM. As described above, the information in the built-in RAM is maintained by the backup power supply BAK, so the game operation before the power shutdown can be resumed after the power is turned on.

As shown in FIG. 3A, the effect interface board 22 is equipped with a sound circuit SND such as a sound processor 27, and the effect control board 23 is equipped with computer circuits such as a VDP circuit 52 and a built-in CPU circuit 51. A combined chip 50 is mounted. Hereinafter, the built-in CPU circuit may be abbreviated as a CPU circuit.

The performance interface board 22 is equipped with reset circuits RST3 and RST4 for detecting an increase in the power supply voltage and generating various reset signals RT3 and RT4 when the power is turned on. First, the reset circuit RST3 generates a reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. FIG. The reset signal RT3 resets only the voice memory 28 and is transmitted to the effect control board 23 as it is.

As shown in FIG. 7(a), the reset signal RT3 transmitted to the performance control board 23 is AND-operated with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and is output to the CPU circuit as the system reset signal SYS. 51 and the VDP circuit 52 are reset (see FIGS. 7A and 7D).

After the power is turned on, the reset signal RT3 generated by the reset circuit RST3 maintains the L level for a predetermined time as a power reset signal, and then rises to the H level. However, if one or more of the DC voltage of 12 V or DC voltage of 5 V subsequently drops (usually when power is cut off), the system reset signal SYS also drops to L level in response to the level drop of the reset signal RT3. As a result, the CPU circuit 51 and the VDP circuit 52 of the effect control board 23 are put into a non-operating state.

Since this system reset signal SYS also changes based on the output of the WDT circuit 58 (which is normally H level), the output of the WDT circuit 58 may change when the reset signal RT3=H due to program runaway or the like. Corresponding to the drop to L level, the system reset signal SYS also changes to L level to abnormally reset the CPU circuit 51 and the VDP circuit 52 (see FIG. 7(d)).

On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply board 20 . This reset signal RT4 resets the power of the audio processor 27 as a power reset signal when the power is turned on.

As illustrated, the reset circuit RST4 is also supplied with the system reset signal SYS sent back from the performance control board 23, so that when the CPU circuit 51 or the VDP circuit 52 is abnormally reset, the system is synchronized with the abnormal reset of these circuits. Then, the audio processor 27 is also abnormally reset. As a result, the sound effect returns to the initial state together with the image effect and the lamp effect, and there is no possibility that the unnatural sound effect will continue.

Next, reset circuits RST1 and RST2 are mounted in the payout control board 25 as the frame-side member GM1 and the main control unit 21 as the board-side member GM2, respectively. A computer circuit is configured to be power reset.

Thus, in this embodiment, the reset circuits RST1 to RST4 are arranged in the main control section 21, the payout control section 25, and the performance interface board 22, respectively, and the system reset signal SYS is generated between the circuit boards. never transmitted. That is, since there is no wiring cable for transmitting the system reset signal SYS, the risk of abnormal resetting of the computer circuit due to noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each incorporate a watchdog timer, and do not receive regular clear pulses from the CPUs of the control units 21 and 25. If so, each CPU is forced to reset.

Further, the main control unit 21 is provided with an initialization switch SW that can be operated by a staff member. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

In addition, as described above, the one-chip microcomputer of the main control unit 21 and the payout control unit 25 receives the power failure signal ABN from the power supply monitor MNT arranged in the payout control unit 25, thereby to initiate the necessary termination processing.

As shown in FIG. 3A, the main control unit 21 receives, from the payout control unit 25, a winning ball count signal indicating the payout operation of game balls, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN. receiving. The status signal CON includes, for example, a supply shortage signal, a dispensation shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

In addition, the main control unit 21 receives switch signals from detection switches built into the winning holes 16 to 18 on the game board, and drives solenoids such as electric tulips. Solenoids and detection switches are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21 . In addition, each switch signal indicating the winning state to the symbol start port 15 is converted into a switch signal of TTL level or CMOS level by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21 .

As described above, the effect interface board 22 receives DC voltages (5V, 12V, 35V) of various levels from the power supply board 20 via the central connection connector C2 (FIGS. 3A and 3B). 7(a)). A DC voltage of 12 V is used as a power supply voltage for the digital amplifier 29 and as a drive voltage for LED lamps and the like. In addition, the DC voltage of 35V is used as a drive voltage for a solenoid that is distributed to appropriate places in the game frame and reciprocates the movable object.

On the other hand, the DC voltage of 5V is supplied as a power supply voltage for circuit elements in various locations on the production interface board 22, and is also supplied to two DC/DC converters DC1 and DC2 to generate 3.3V and 1.0V ( See FIG. 7(a)). The generated DC voltages of 3.3 V and 1.0 V are supplied to the audio processor 27 as power supply voltages for I/O (input/output) and chip core, respectively. Also, the DC voltage of 3.3 V is the base voltage of the power reset signal RT4 generated by the reset circuit RST4.

The DC voltage of 5V distributed to the effect interface board 22 is distributed to the effect control board 23 together with 3.3V generated by the DC/DC converter DC1. Then, the DC voltage of 3.3V distributed to the performance control board 23 is supplied to the composite chip 50, the PROM 53 and the CGROM 55 as a power supply voltage.

As shown in FIG. 7(a), two DC/DC converters DC3 and DC4 are arranged on the effect control board 23, and based on the DC voltage 5V supplied to each, 1.5V and 1.05V. is generating Here, the DC voltage of 1.05 V is the power supply voltage for the chip core of the composite chip 50 , and the DC voltage of 1.5 V is the power supply voltage for I/O (input/output) with the DRAM 54 . Therefore, the DC voltage of 1.5 V is also supplied to the DRAM 54 as a power supply voltage.

As shown in FIG. 3( a ), the effect interface board 22 receives the control command CMD and the strobe signal STB from the main control section 21 and transfers them to the effect control board 23 . More specifically, as shown in FIG. 7(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. . Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the effect control CPU 63 acquires the control command CMD based on the interrupt processing program (interrupt handler) started upon receiving the received interrupt signal IRQ_CMD.

As shown in FIG. 7A, the input buffer 44 of the effect interface board 22 receives switch signals for the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and outputs each switch signal to the CPU of the effect control board 23. It is transmitting to circuit 51 . Specifically, the 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and the 1-bit length indicating the ON/OFF state of the chance button 11 are transmitted to the CPU circuit 51 .

The effect interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and . As shown, an output buffer 42 is arranged corresponding to the lamp driving board 30 , and an input buffer 43 a and an output buffer 43 b are arranged corresponding to the motor lamp driving board 31 . Note that in FIG. 7A, the input buffer 43a and the output buffer 43b are collectively referred to as the input/output buffer 43 for the sake of convenience. The input buffer 43a receives the outputs SN0 to SNn of the origin sensors for grasping the current positions of the characters as movable effects (rotational positions of the effect motors M1 to Mn), and transmits the outputs to the CPU circuit 51 of the effect control board 23. there is

The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with driver ICs of the same kind. is forwarding to Specifically, the serial signals are a lamp (motor) drive signal SDATA and a clock signal CK. , the performance motors M1 to Mn perform a role performance.

In the case of this embodiment, the lamp effect is executed by three lamp groups CH0 to CH2, and the lamp drive board 37 outputs the lamp drive signal SDATA0 of CH0 via the frame relay boards 35 and 36 as a clock. It is received in synchronization with the signal CK0. A series of lamp drive signals SDATA0 transmitted as a serial signal are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state all at once.

The above points also apply to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. , the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 31 receives the lamp drive signal transmitted in clock synchronization to drive the lamp group CH2, and receives the motor drive signal transmitted in clock synchronization to A performance motor group M1 to Mn composed of a plurality of stepping motors is driven. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronism with the clock signal CK1. , the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Next, the audio circuit SND will be explained. As shown in FIG. 7(a), the effect interface board 22 includes a voice processor (voice synthesis circuit) 27 for reproducing voice signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the effect control board 23. , an audio memory 28 for storing compressed audio data, which is the original data of the audio signal to be reproduced, and a digital amplifier 29 for receiving the audio signal output from the audio processor 27 are mounted.

The voice processor 27 includes a WDT circuit that automatically resets the set value of the internal circuit to a default value (initial value) when the internal circuit malfunctions, and a voice control register SRG. Then, the audio processor 27 accesses the audio memory 28 based on the operation parameters (set values by the audio commands) received from the effect control CPU 63 to the audio control register SRG, and reproduces and outputs the necessary audio signals. .

As shown in FIG. 7A, the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store data of 1 Gbit (=2 ²⁶ ×16).

The voice control register SRG is divided into register banks 1 to 6, which are specified by register numbers 00H to FFH, respectively. Therefore, the predetermined setting operation is realized by specifying the register bank and then writing the operation parameter of 1 byte length to the voice control register SRG of the predetermined register number (1 byte length) by the effect control CPU 63. be.

In the case of this embodiment, the register numbers (00H to FFH) of the voice control register SRG correspond to the address space CS3 of the effect control CPU 63. For example, the voice control register SRG of the register number XXH is set to the operating parameter YYH. In this case, the effect control CPU 63 writes XXH to the zero address of the address space CS3, and then writes YYH to the first address. That is, the effect control CPU 63 writes XXH and YYH to the data bus in this order. In this specification, the subscript H and the prefixes 0X/0x indicate that the numerical values are represented in hexadecimal notation.

Further, in this specification, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51 that can respectively define the memory type including the presence or absence of volatility and the data bus width (8/16/32 bits). means (excluding internal memory). These address spaces CS0-CS7 are selected by different chip select signals CS0-CS7, and are configured so that the READ/WRITE control signals that function during READ/WRITE access can be optimized according to the memory type. Note that this setting operation is executed for the bus state controller 66 .

FIG. 7(e) illustrates the setting operation to the voice register SRG by the effect control CPU 63, and shows the contents of the 2-bit length address bus A1-A0 and the 1-byte length data bus D7-D0. there is In this embodiment, the chip select signal CS3 is set at power-on so as to automatically become active when accessing the address space CS3, which will be described later with reference to FIGS. 9 and 16. FIG.

In any case, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by a 13-bit length phrase number NUM (000H to 1FFFH), and a series of background data. A maximum of 8192 types (=2 ¹³ ) of one piece of music (BGM), a group of dramatic sounds (announcement sounds), etc. are stored in association with the phrase number NUM. This phrase number NUM is specified by a set value (operating parameter) of a voice command transmitted from the performance control CPU 63 to the voice control register SRG of the voice processor 27 .

As described above, the audio memory 28 having the above configuration is power reset by the reset signal RT3, and the audio processor 27 is power reset by the reset signal RT4. As shown in FIG. 7(c), the reset signal RT4 rises to H level after a predetermined assertion period ASRT (L level section) after power-on. function automatically to perform initialization sequence processing. This initialization sequence process is an internal operation that is executed according to a predetermined procedure, and the effect control CPU 63 cannot access the sound register SRG during the operation of the initialization sequence process.

When the initialization sequence processing as an internal operation is completed, the interrupt signal IRQ_SND to the CPU circuit 51 changes to L level, and the CPU circuit 51 (effect control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND. Then, the interrupt signal IRQ_SND is returned to H level based on a predetermined instruction, the details of which will be described later with reference to FIG. 18(c).

As shown in FIG. 7(a), the data bus and address bus of the CPU circuit 51 of the effect control section 23 extend to a clock circuit (real time clock) 38 and effect data memory 39 mounted on the liquid crystal interface board 24. I'm listening. The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus. (having an address value) can be accessed arbitrarily.

The effect data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to the 16-bit address bus of the CPU circuit 51 and the lower 16-bit data bus. In the state where the chips are selected in , game performance information and other information stored in the SRAM (performance data memory) 39 are appropriately R/W-accessed from the CPU circuit 51 . In the address space CS4 selected by the chip select signal CS4, since addresses 0 to 15 are assigned to the clock circuit 38, the SRAM 39 does not use them.

The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is turned off, the timekeeping operation of the clock circuit 38 is continued, and the game performance information stored in the performance data memory 39 is permanently stored (imparted non-volatility). The clock circuit (RTC) 38 is configured to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). The RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. Uses alarm interrupts to update game performance information.

As shown on the right side of FIG. 7A, the effect control board 23 includes a composite chip 50 containing a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program for the CPU circuit 51, A DRAM (Dynamic Random Access Memory) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 storing a large amount of CG data required for control of effects are installed.

As will be described later with reference to FIG. 10, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0 in this embodiment. A DRAM (Dynamic Random Access Memory) 54 composed of DDR (Double-Data-Rate 3) is positioned in an address space CS5 selected by a chip select signal CS5.

FIG. 8(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the production control section 23, including related circuit elements. As shown, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a CPU circuit 51 that generates image data based on the issued display list DL to drive the display devices DS1 and DS2. A VDP circuit 52 is built in. The CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays transmission/reception data between them.

Although the VDP circuit 52 incorporates an audio circuit SND that exhibits the same function as the audio processor 27, the audio circuit SND is not utilized in the first embodiment described below. However, if the audio circuit SND incorporated in the VDP circuit 52 is utilized as in the last-described embodiment, the arrangement of the audio memory 28 and the audio processor 27 becomes unnecessary.

First, the CPU circuit 51 receives the oscillation output (for example, 100/3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies the frequency (for example, by 8) to generate a CPU operating clock of about 266.7 MHz (FIG. 14). (b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking measures against EMI (Electromagnetic Interference) for preventing radio interference/electromagnetic interference.

By the way, in the case of this embodiment, the CPU operating clock can be generated based on the output of an oscillator OSC2, which will be described later, instead of the oscillator OSC1, and the oscillator OSC1 can be dispensed with. However, in the configuration in which the oscillator is unified, the frequency multiplication ratio of the PLL circuit is the same fixed value (for example, 5) as in the case of the system clock described below. It becomes 200 MHz (=40 MHz×5) which is the same as the system clock.

Such a configuration has the advantage that the built-in CPU circuit 51 and the VDP circuit 52 have a common operation cycle, but it goes against the demand for speeding up the operation of the CPU as much as possible. In other words, since the VDP operation cannot be speeded up beyond a certain level, it is not possible to reliably meet the demand for speeding up the CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operation cycles of the VDP circuit 52 and the CPU circuit 51 respectively. Further, by providing a separate oscillator OSC1, it is possible to improve the EMI countermeasures described above.

Based on the above, the VDP circuit 52 will be explained. The VDP circuit 52 receives the oscillation output (40 MHz) of the oscillator OSC2, which is different from the oscillator OSC1, at the PLLREF terminal, multiplies the frequency by the PLL (Phase Locked Loop) circuit, and , as system clocks of the VDP circuit 52 . The frequency multiplication ratio of the PLL circuit is fixedly defined by a setting value to a predetermined setting terminal, and in this embodiment, the setting value to the setting terminal (3-bit PLLMD terminal) is a fixed value of 5. The system clock of the circuit 52 is 200 MHz (=40 MHz×5) (see FIG. 14(b)).

In this embodiment, the dot clocks DCK _A to DCK _C that define the operations of the display circuits 74A to 74C and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. there is In other words, the output (40 MHz) of oscillator OSC2 functions as a reference clock for the entire VDP circuit 52 .

As will be described later with reference to FIGS. 14 and 15, the display circuits 74A to _74C normally drive display devices having different specifications, respectively. _C must correspond to the specifications of the display device to be driven. Based on this requirement, in this embodiment, the display circuits 74A to 74C receive any one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC and use it as the dot clocks DCK _A to DCK _C. It is configured so that

When this configuration is utilized, the design of the multiplication ratio and frequency division ratio described later and the setting processing for the VDP register RGij are unnecessary, and the frequencies of the dot clocks DCK _A to DCK _C can be easily optimized. . That is, a dedicated oscillation circuit DCLKA for the oscillation frequency F DOT1 is provided corresponding to the dot clock frequency F _DOT1 of the main display device DS1, and a dedicated oscillation circuit _DCLKA for the oscillation frequency F _DOT2 is provided corresponding to the dot clock frequency F _DOT2 of the sub display device DS2. It is also possible to provide an oscillator circuit DCLKB.

However, when adopting such a configuration, dedicated oscillation circuits are required corresponding to the number of display devices, which complicates the device configuration. Therefore, in this embodiment, in order to simplify the device configuration, the dot clocks DCK _A /DCK _B for the display circuits 74A/74B are generated based on the oscillation output (40 MHz) of the oscillator OSC2. Specifically, as shown in FIG. 14B, for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to predetermined multiplication processing (×108) and frequency division processing (1 /40) to generate a dot clock DCK _A with a frequency of 108 MHz.

Similarly, for the display circuit 74B that drives the sub-display device DS2, the frequency F _dot = 27 MHz dot clock DCK _B is generated. Designing these multiplication ratios and frequency division ratios is rather complicated, and it would be easier to provide a dedicated oscillation circuit. is not provided.

In any case, the dot clocks DCK _A to DCK _C are set individually for each of the display circuits _74A to _74C . DCK" may be referred to. Also, in the following description, the dot clocks DCK _A and DCK _B may be abbreviated as "dot clocks DCK" for convenience.

Since the present embodiment does not employ a low-speed LVDS output configuration, the LVDS clock CLK of the LVDS signal output via the display circuit 74A also undergoes the same generation process as that for the dot clock DCK _A , and has a frequency of 108 MHz. and However, since this embodiment employs a dual-link transmission line, the actual frequency of the LVDS clock CLK is 54 MHz as described with reference to FIG. Note that when a single link transmission line is employed, the frequency of the LVDS clock CLK is 108 MHz.

As described above, in this embodiment, the oscillation output (40 MHz) of the oscillator OSC2 is used as the reference clock for the system clock, dot clock DCK, and DDR clock. Therefore, considering this importance, the oscillator OSC2 is operated at the same power supply voltage of 3.3 V as the VDP circuit 52, and the reference clock is operated on the condition that the output enable terminal OE is at H level (=3.3 V). is configured to oscillate. In the unlikely event that the power supply voltage 3.3V falls below a predetermined level, since normal performance operations cannot be expected thereafter, a non-maskable interrupt (NMI) is generated.

Also, the composite chip 50 is provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, whether a boot program (initial setting program) to be executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL =H) or stored in other memory (HBTSL =L). As shown in the figure, in this embodiment, HBTSL is set to L level, and address zero in the address space CS0 of the effect control CPU 63 is assigned outside the CGROM. assigned to.

On the other hand, when the HBTSL terminal is set to H level (see the broken line), zero address in the address space CS0 of the effect control CPU 63 is assigned to the CGROM 55 . In this case, the memory type and bus width (64/32/16 bits) of the CGROM 55 are specified based on the input values to the HBTBWD terminal of 2-bit length and the HBTRSL terminal of 4-bit length, respectively. These points will be further described later with reference to FIG.

Next, the CPUIF circuit 56 that relays transmission/reception data between the CPU circuit 51 and the VDP circuit 52 will be described. As shown in FIG. 8A, the CPUIF circuit 56 includes a control memory (PROM) 53 for nonvolatilely storing control programs and necessary control data, and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. , and are configured to be accessible from the CPU circuit 51 . As described above, the control memory (PROM) 53 is positioned in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is positioned in the address space CS6 selected by the chip select signal CS6. It is

The work memory (RAM) 57 reserves a DL buffer BUF for temporarily storing a display list DL containing a series of instruction commands specifying one frame of each of the display devices DS1 and DS2. In the case of this embodiment, the series of instruction commands include a texture load command such as a TXLOAD command for reading and decoding image materials (textures) from the CGROM 55, and a VRAM area (index texture setting commands such as the SETINDEX command, which has functions such as specifying the space) in advance, and primitive drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space. , environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to be actually drawn on the display device among the images drawn in the virtual drawing space by the drawing commands, and the index table IDXTBL for managing the index space. includes an index table control system command (WRIDXTBL) for

FIG. 12(c) shows a virtual drawing space (±8192 in the horizontal X direction and ±8192 in the vertical Y direction), a drawing area that can be arbitrarily set in the virtual drawing space, and outputs to the display devices DS1 and DS2. The relationship between the actual drawing areas in the frame buffers FBa and FBb that temporarily store the image data to be processed is shown.

Next, the CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) that forcibly resets the CPU, a built-in RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area for the CPU, and a DMAC (Direct Memory Access) that realizes data transfer without going through the CPU 63. Controller) 60, a serial input/output port (SIO) 61 having a plurality of input ports Si and output ports So, a parallel input/output port (PIO) 62 having a plurality of input ports Pi and output ports Po, and It includes an operation control register REG in which set values are set to control the operation. However, in this embodiment in which the external WDT circuit 58 is provided, the watchdog timer (WDT) built in the CPU circuit 51 is not utilized.

In this specification, for the sake of convenience, the term input/output port is used, but in the effect control unit 23, the input/output port includes an input port and an output port that operate independently. This point also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (effect interface board 22) through an input/output circuit 64p. It receives the switch signal of the button 11, the control command CMD, and the interrupt signal STB. A 3-bit encoder output and a 1-bit switch signal are supplied to a parallel input/output port (PIO) 62 via an input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input/output circuit 64p, thereby activating the reception interrupt process. Therefore, the effect control CPU 63, which grasps the control command CMD based on the reception interrupt process, controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD through the effect lottery and the like in a unified manner. will do.

Although not particularly limited, in this embodiment, an SMC circuit (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp effects and motor effects. The SMC circuit 78 is a composite controller incorporating an LED controller and a motor controller, and is configured to output a serial signal in clock synchronization. Also, the motor controller is configured to output latch pulses at arbitrary timings based on the values set in the predetermined control register 70, and to input serial signals in a clock-synchronized manner.

Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC circuit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. . Further, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are serially input in a clock synchronous manner.

As described with reference to FIG. 7A, clock signals CK0-CK2, drive signals SDATA0-SDATA2, and operation control signals ENABLE0-ENABLE2 pass through output buffers 41-43 to predetermined drive substrates 30, 31, . 37. Further, the origin sensor signals SN0 to SNn are serially input to the SMC circuit 78 from the motor lamp drive board 31 via the input/output buffer 43. FIG.

However, it is not essential to use the SMC circuit 78 in this embodiment. That is, since the CPU circuit 51 has a built-in general-purpose serial input/output port SIO61, it is also possible to use these ports to execute lamp effects and motor effects.

Specifically, as indicated by broken lines in FIG. 8A, in the configuration indicated by broken lines, the clock signals CK0 to CK2, CK2, Drive signals SDATA0 to SDATA2 are output, and operation control signals ENABLE0 to ENABLE2 are output via the input/output circuit 64p. For convenience, they are expressed as input/output ports and input/output circuits, but what actually functions are output ports and output circuits.

Here, the serial output port SO is configured with a built-in 16-stage FIFO register (see FIG. 50(a)). Then, the DMAC circuit 60 is activated upon receiving an operation start instruction (see FIG. 22(b) ST18) from the effect control CPU 63, and from the lamp/motor drive table (see FIG. 22(b)), the necessary drive data is sequentially and DMA transferred to the FIFO register of the serial output port SO. The drive data stored in the FIFO register are serially output from the serial output port SO in clock synchronization. The DMAC circuit has a plurality of (for example, 7) DMA channels. Lamp driving data is DMA-transferred by the third DMA channel with lower priority, and the motor is driven by the first DMA channel with the highest priority. It is configured to DMA transfer data.

The operation control register REG built in the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit length register with a register number (address value) after 0xFF400000. (see FIG. 10). Therefore, there is a possibility that an irrational value is set in the operation control register REG due to the influence of noise or the like.

However, for example, the composite chip 50 can be abnormally reset by intentionally executing an infinite loop process to activate the external WDT circuit 58 . In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij of the VDP circuit 52 is also returned to the default value (initial value). This eliminates the abnormal state.

FIG. 7(b) is a circuit configuration related to this reset operation and is a drawing for explaining a reset mechanism that is characteristic of this embodiment. In this specification, the VDP register denoted as RGij is not the operation control register REG built in the CPU circuit 51, but any one of the control register group 70 (see FIG. 10) that controls the internal operation of the VDP circuit 52. means Also, the system control circuit 520 shown in FIG. 7B means an internal control circuit of the VDP circuit 52 that functions based on the set value of the VDP register RGij (one of the control registers 70 of FIG. 10). (See FIG. 7(a)). The VDP register RGij is positioned in the address space CS7 selected by the chip select signal CS7 in the address map of the effect control CPU63.

Based on the above, the reset mechanism will be described. As shown in FIG. is configured to be resettable. However, in this embodiment, the built-in WDT is not activated as indicated by the dashed line, so the input terminal and the output terminal of the OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK receives from the parallel input/output port (PIO) 62 a predetermined keyword string (a code string for resetting). ), the reset signal RST is output.

The internal circuit of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the circuits other than the display circuit of the VDP circuit 52. It is configured to receive reset signals of the first to third reset paths from gates G2 to G4.

First, the OR gate G2 whose input/output terminals are directly connected is related to the first reset path, and is configured to system-reset the entire CPU circuit 51 based on the system reset signal SYS bar. Also, the OR gate G3 is related to the second reset path, and receives the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK, and can reset the entire VDP circuit 52 based on the OR logic. is configured to

This second reset path is used not only for the power reset operation when the power is turned on, but also for the effect control CPU 63 that detects a predetermined abnormality to abnormally reset the entire VDP circuit 52 to return it to its initial state. Specifically, when it is determined that a serious abnormality has occurred based on a predetermined status register RGij that indicates the internal operation of the VDP circuit 52, the reset signal RST is generated from the pattern check circuit CHK. , the entire VDP circuit 52 is abnormally reset. The display circuit 74 is abnormally reset in the second reset path→the third reset path via the OR gate G4.

On the other hand, the internal circuits built in the VDP circuit 52 are configured to be able to be reset individually when necessary through the fourth reset path. The individually resettable internal circuits include an index table IDXTBL, a data transfer circuit 72, a preloader 73, a display circuit 74, a drawing circuit 76, an SMC circuit 78, and an audio circuit SND shown in FIG. An ICM circuit shown at 13 is included.

A method for realizing individual reset operations is as described in the lower part of FIG. Thus, it is reset via the fourth reset path 4A→the third reset path.

Each internal circuit (72, 73, 74, 76, SND, . After writing, (2) a predetermined VDP register RGij (system command register) is reset individually by writing a second reset value (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by the fourth reset path 4B, but also by writing a reset value to a predetermined VDP register (circuit setting command register). 4 reset path 4C).

Since this embodiment has the above-described configuration, not only does the entire VDP circuit 52 automatically return to the initial state when the power is turned on or when the program runs out of control, but each part is returned to the initial state as necessary to prevent an abnormal situation from occurring. recovery can be achieved. For example, when the drawing circuit 76 is frozen without READ/WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see FIG. 22(d)). ST16a reference). The same applies to the preloader 73 and the data transfer circuit 72. In the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 29), and is reset via the fourth reset path 4B. Then the data transfer circuit 72 is initialized (see ST27 in FIG. 24 and FIG. 29).

As for the display circuit 74, when the display timing of every 1/60th of a second continues underrun (Underrun), in which display data cannot be generated in time, the fourth reset path 4A or the fourth reset path 4B is switched. The display circuit 74 is individually initialized via this (see ST10c in FIG. 22). Note that these individual reset operations will be further described later with respect to the program processing described after FIG.

The reset mechanism that is characteristic of this embodiment has been described above. The setting value of returns to the same default value after power-on.

Next, returning to the internal configuration of the CPU circuit 51, the description of the characteristic circuit configuration will be continued. FIG. 9 is a block diagram showing in some detail the internal configuration of the CPU circuit 51. As shown in FIG. The CPU circuit 51 includes many characteristic circuits in addition to the built-in RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

First, CPU circuit 51 implements the Harvard architecture by having separate CPU fetch buses for instructions and CPU memory access buses for data. Therefore, the fetch operation in which the CPU core (rendering control CPU) 63 reads an instruction from the memory and the memory access operation do not conflict with each other, and high-speed processing is realized by continuing the fetch operation.

Further, the CPU core 63 is configured with a plurality of (for example, 15) register banks RB0 to RB14, and is configured to select whether or not to use them. In an operating state in which the use of the register bank RBi is permitted, at the start of interrupt processing, the register values (each 32-bit length) of the internal registers of the CPU (eg, 19 registers) are automatically saved in the empty register bank RBi. be done.

Further, when a predetermined return instruction is executed at the end of interrupt processing, for example, 19 pieces of saved data are automatically restored to the corresponding built-in registers. Therefore, it is not necessary to execute the PUSH instruction 19 times at the start of interrupt processing and the POP instruction 19 times at the end of interrupt processing as in a normal configuration, and high-speed processing is realized.

Further, the CPU circuit 51 of the embodiment realizes a Harvard cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, and when accessing the same address, cached By using this data, we are aiming to further speed up program processing. By providing the bus bridge 65, the controller for the peripheral bus (1), the controller for the peripheral bus (2), and the controller for the peripheral bus (3), the internal bus and the peripheral bus (1) are provided. ), peripheral bus (2), and peripheral bus (3) are connected as appropriate.

Next, in the circuit configuration of FIG. 9, the bus state controller 66 operates based on an appropriate set value in the operation control register REG to perform memory READ operations with various memory devices connected to the CPU circuit 51 and memory read operations. This is the part that optimizes WRITE operations. The memory READ operation and memory WRITE operation are executed, for example, at the operation timings illustrated in FIG. The operation timing of WRITE data written to the WRITE data bus (32 bits) and control signals such as chip select signals CS0 to CS7 is based on the values set in the operation control register REG, corresponding to the characteristics of each memory device. Defined as appropriate.

Since the READ data bus and the WRITE data bus are provided separately, high-speed operation is realized by the Harvard architecture described above. In this specification, the address bus (28 Bit), READ data bus (32 Bit), and WRITE data bus (32 Bit) are referred to as the internal bus, peripheral bus (1) to peripheral bus (3), etc. shown in FIG. In order to distinguish it from the external bus, it may be generically called an external bus.

FIG. 10 shows the address spaces CS0-CS7 selected by the chip select signals CS0-CS7, and shows the address map for the effect control CPU 63 accessed via the bus state controller 66. FIG. . First, each of the address spaces CS0 to CS7 is defined to have a maximum of 64 Mbytes (=0x4000000H=67108864).

As described above, the address spaces CS0 to CS7 mean external memories for the CPU circuit 51, which can define the memory type including the presence or absence of volatility, and the data bus width (8/16/32 bits). do. In this embodiment, as shown in FIGS. 9B and 10, the control memory (PROM) 53 has an address space CS0, the audio control register SRG of the audio processor 27 has an address space CS3, the internal registers of the clock circuit 38 and The SRAM 39 is positioned in the address space CS4, the external DRAM (DDR) 54 is positioned in the address space CS5, the work memory 57 is positioned in the address space CS6, and the VDP register RGij is positioned in the address space CS7. A description of the address spaces CS1 and CS2 will be omitted.

By the way, as can be seen from FIG. 10, the address spaces CS0 to CS7 are secured not only at address values 0x00000000 to 0x1FFFFFFF (cache valid space) but also at address values 0x20000000 to 0x3FFFFFFF (cache invalid space). When the address bit A29=1, the cache is invalidated according to the internal operation of the CPU circuit 51, while when the address bit A29=0, the cache is validated. It is designed to

Therefore, in this embodiment, even if the value of bit A29 is either 1 or 0 in all 32-bit address information (bits A31 to A0), the remaining 31 bits (bits A31 to A30 and bits A28 to A0) If the values are the same, they point to the same location in the same memory. For example, the same data is read from the zero address of the work memory 57 even if the address 0x18000000 is read-accessed and the address 0x38000000 is read-accessed. When the address 0x18000000 is read-accessed, the read data is stored in the cache, and FIG. 9B illustrates the cache valid/invalid access operation.

However, it is also possible to invalidate the cache operation of the instruction cache and/or the operand cache based on the value set in the predetermined operation control register REG. However, in this embodiment, after the power is turned on, the cache operations of the instruction cache and the operand cache are validated, and the cache invalidation space is accessed as necessary to invalidate the cache operations.

Continuing the description of the memory map in FIG. 10, from 0x40000000 onwards is an internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are assigned to the cache address array space. Addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are assigned to built-in peripheral modules, specifically, to the operation control register REG of the CPU circuit. The address range of the internal RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing the description of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multi-function timer unit MTU count external signals supplied to the CPU circuit 51, or count by multiplying or dividing the internal clock. This is a circuit that counts clocks and generates an interrupt signal or the like when the counted result reaches a predetermined value. Although not particularly limited, this embodiment utilizes the multifunction timer unit MTU to generate a 1 ms interrupt signal and a 20 μS interrupt signal. Also, by utilizing the multi-function timer unit MTU, a clock timer TM for measuring the elapsed time after resetting the CPU is realized.

Next, the interrupt controller INTC receives internal interrupts from the VDP circuit 52, the DMAC circuit 60, the multi-function timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, IRQ_RCT, etc., and based on a predetermined priority. It is a circuit that activates interrupt processing (interrupt handler). IRQ_CMD is a command reception interrupt signal for receiving the control command CMD, IRQ_SND is a termination interrupt signal indicating that the voice processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command reception interrupt IRQ_CMD has the highest level of interrupt priority. The order is IRQ_RCT (see FIG. 18(d)). All of these are maskable interrupts, and the unmaskable interrupt NMI is output to the effect control CPU 63 when the reference clock is not output from the oscillator OSC2, as described above.

In any interrupt process, the register values (32-bit length each) of a plurality of built-in registers of the CPU are automatically saved in any one of the empty register banks RBi. Then, when a predetermined restore instruction is executed at the end of interrupt processing, the saved data is automatically restored to the corresponding built-in register.

Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment transfers from the transfer source (Source) to the transfer destination (Destination) in a predetermined DMA transfer mode for each predetermined data transfer unit based on the set value in the predetermined operation control register REG. In addition, it is a circuit that repeats data transfer a predetermined number of times. A plurality of channels of DMAC0 to DMACn having the same internal configuration are prepared and can operate in parallel. However, the priority is determined (channel 0 > . . . > channel n), and during parallel operation in the channel arbitration operation mode, the operation of DMACi with a higher priority is prioritized by channel arbitration at predetermined timing.

As for the utilization of the DMAC circuit 60, for example, in the embodiment in which the serial output port SO functions (see the dashed line in FIG. 10A), the operation control register REG of the CPU circuit 51 stores the head address of the lamp/motor drive table. (head value of transfer source address), address of input register of serial output port SO (fixed value of transfer destination address), data transfer unit (8 bits), and number of transfers are specified. Then, the DMAC circuit 60, which has received the operation start instruction from the predetermined operation control register REG, DMA-transfers the driving data to the predetermined transfer destination address while updating the transfer source address. Then, when all DMA transfers are completed, a DMAC interrupt (operation end interrupt) is generated.

This point is substantially the same in the case of the embodiment in which the DMAC circuit 60 issues the display list DL (FIGS. 25 and 29(c)). That is, the effect control CPU 63 stores the head address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in a predetermined operation control register REG of the CPU circuit 51. Then, the number of transfers and other conditions are set. Note that these points will be discussed further below with respect to FIG.

By the way, in general, DMA transfer modes include a cycle steal transfer mode in which DMA operations do not occupy the memory bus, such as releasing the bus control right in the middle of a unit operation (R operation/W operation) of DMA transfer, and a cycle steal transfer mode in which DMA operations do not occupy the memory bus. Burst transfer (pipeline transfer) mode in which the bus control right is not released until the specified number of transfers is completed, such as continuous operation or W operation, and while DMA transfer requests (demands) received from other devices are active A demand transfer mode that continues the DMA operation can be considered. However, the DMAC circuit 60 of this embodiment functions in a cycle steal transfer mode in which at least one cycle of memory release period is provided between read access activation (R operation) and write access activation (W operation) during DMA transfer. By doing so, the operation of the effect control CPU 63 is prevented from being hindered.

FIG. 11 is a diagram for explaining the cycle steal transfer operation (a1) and the pipeline transfer (a2). As shown in FIG. 11(a1), the DMAC circuit 60 functioning in the cycle steal transfer mode operates with at least one cycle between read access activation (R) and write access activation (W) of one data transfer. In this empty cycle, the effect control CPU 63 can use the bus. As is clear from the comparison between FIGS. 11(a1) and 11(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one-operand transfer) is completed. In the transfer mode, the bus is released to the CPU for each read access, so the operation of the CPU is not greatly delayed.

Then, for example, when the display list DL is issued to the VDP circuit 52, in an embodiment using the DMAC circuit 60, the data transfer unit (1 operand) of one cycle is set to 32×2 bits, and the display list DL is stored. While appropriately increasing the source address of the built-in RAM 59 (+8 for each operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 13) of the data transfer circuit 72 specified by the fixed address. running

As will be described later, in the embodiment, by adding the required number of NOP (no operation) commands to the display list DL, the overall data size is set to a fixed value (for example, 4×64=256 bytes, or its integer 32 bits×2 times of one operand transfer is repeated 32 times (or an integer multiple thereof) to complete the issue of the display list DL. Note that even if the drawing circuit 76 executes the NOP command, it is in a no operation state and virtually nothing changes.

Further, when classifying operation modes with respect to DMA transfer conditions, generally, single operand transfer (see FIG. 11(b1)), continuous operand transfer (see FIG. 11(b2)), and non-stop transfer (see FIG. 11(b3) See).

Here, the single-operand transfer is the point in time when the byte count, which counts the number of transferred bytes, becomes zero, after repeating the transfer of one operand each time a DMA transfer request is given, as shown in FIG. and means the mode of operation in which a DMA interrupt request occurs. Next, continuous operand transfer means an operation mode in which DMA transfer is repeated until the byte count becomes zero with one DMA request, as shown in FIG. 11(b2).

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time a single operand transfer is completed. transfer continues (channel arbitration mode of operation). Therefore, in this embodiment, the single operand transfer method is adopted for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. During parallel operation, the DMACi of the optimum channel is used so as to achieve channel arbitration with the priority of, for example, motor data>display list DL>lamp data.

On the other hand, non-stop transfer is an operation mode in which channel arbitration is not executed, and as shown in FIG. be In this embodiment, in memory section initialization processing (SP8 in FIG. 16) at power-on, programs and data are DMA-transferred by non-stop transfer.

The CPU circuit 51 has been described above. Next, the VDP circuit 52 will be described. , a main display device DS1, and a sub display device DS2 are connected. The DRAM 54 is preferably composed of DDR3 (Double-Data-Rate3 SDRAM).

Here, the DRAM 54 receives the DDR clock generated based on the oscillation output (40 MHz) of the oscillator OSC2, as shown in FIG. 14(b). Further, the DRAM 54 of the embodiment has a built-in refresh counter (Refresh Counter), and the self-refresh function (Self-Refresh Operation) is activated at the time of initial setting (SP4 in FIG. 16). No refresh control operation is required.

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory with a storage capacity of about 62 Gbits. is configured to obtain Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is resolved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) method conforming to SerialATA.

Regardless of whether or not the HSS method conforming to SerialATA is adopted, the NAND type flash memory is mechanically more stable than the hard disk and is capable of high-speed access. Compared with DRAM and SRAM (Static Random Access Memory), there is a problem in random accessibility. Therefore, in this embodiment, a group of compressed data (CG data) is preloaded into the DRAM 54 prior to the drawing operation, thereby realizing smooth random access of the CG data during the drawing operation. ing. Incidentally, the access speed decreases in the order of built-in VRAM>external DRAM>CGROM.

More specifically, the VDP circuit 52 includes a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by an effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. A built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, a data transfer circuit 72 for executing data transmission/reception between each part inside the chip and data transmission/reception with the outside of the chip, and the built-in VRAM 71 have Source and Destination. An index table IDXTBL capable of specifying address information, a preloader 73 capable of executing a preload operation for READ access to the CGROM 55 prior to the drawing operation, and a graphics decoder for decoding (decoding/decompressing/decompressing) compressed data read from the CGROM 55. (GDEC) 75, a rendering circuit 76 for generating image data for one frame of each of the display devices DS1 and DS2 by appropriately combining still image data and moving image data after decoding (expanding), and operation of the rendering circuit 76. A geometry engine 77 that generates a stereoscopic image by appropriate coordinate transformation, and a three-system system that reads image data from the frame buffers FBa and FBb generated by the drawing circuit 76 and executes appropriate image processing in parallel. (A/B/C) display circuits 74A to 74C, an output selection unit 79 that appropriately selects and outputs the outputs of the three-system (A/B/C) display circuits 74, and an image output by the output selection unit 79 LVDS section 80 for converting data into LVDS signals, SMC circuit 78 capable of serial data transmission/reception, CPUIF section 81 for relaying data transmission/reception with CPUIF circuit 56, and CG bus IF section 82 for relaying data reception from CGROM 55. , a DRAMIF section 83 for relaying data transmission/reception with the external DRAM 54, and a VRAMIF section 84 for relaying data transmission/reception with the built-in VRAM 71 (see FIG. 8A). An audio circuit SND is also incorporated.

8B shows the relationship between the CPUIF section 81, the CG bus IF section 82, the DRAMIF section 83, the VRAMIF section 84, the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. FIG. As shown, the CG data acquired from the CGROM 55 is transferred to the preload area of the external DRAM 54 via the data transfer circuit 72 and the DRAM IF unit 83 as preload data, for example.

However, the above-described preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, and may be the built-in VRAM 71 as well. Therefore, for example, in an embodiment in which no preload operation is performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and VRAMIF section 84 (FIG. 8(b)).

By the way, in this embodiment, the built-in VRAM 71 stores the image data specifying the expansion area of the compressed data read from the CGROM 55 and the ARGB information (32 bits=8×4) of each of W×H display pixels of the display device. A frame buffer area to store the depth information of each display pixel and a Z buffer area to store the depth information of each display pixel are required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of three primary colors.

Here, each area of the built-in VRAM 71 is indirectly accessed based on various instruction commands (textures, sprites, etc. described above) described in the display list DL by the effect control CPU 63, but the READ/WRITE access , it is troublesome to specify the destination address and the source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after resetting the CPU, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for the drawing operation is secured, and an index number is assigned to each index space. allows access based on the index number.

Specifically, after resetting the CPU, the built-in VRAM 71 is roughly divided into three types of memory areas, and the necessary number of index spaces are secured in each memory area. By constructing an index table IDXTBL (see FIG. 12A) that stores index spaces and index numbers in association with each other, subsequent operations based on the index numbers are realized.

This index space needs to be (1) added after initial processing, and conversely (2) freed. Therefore, when the addition/release effect control CPU 63 operates, a flag that can determine whether or not it is the timing at which the addition/release processing can be performed, and whether or not the processing such as addition/release has actually been completed. A region FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c). The index table IDXTBL is divided into three corresponding to (a1,a2)(b)(c) (FIG. 12(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a). But it's okay. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as the AAC area (a).

In this embodiment, the built-in VRAM 71 comprises (a) an AAC area having an index space and its index number automatically assigned by internal processing and having a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits×128 lines. The unit space is divided into a page area in which an index space can be secured within the range of integral multiples thereof, and (c) an arbitrary area in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily. (See FIG. 12(b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space head address STx of the index space arbitrarily set in the arbitrary area (c) has 0 in the lower 11 bits, and has a predetermined number of bits (2048 bits=256 bytes). Must be in units.

After resetting the CPU, the maximum value of the address space required for each area and the top address of the area (lower 11 bits=0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area ( b) is secured, and the remaining memory area becomes the arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 52, the maximum value of the address space of the AAC area is defined in units of 2048 bits, and the maximum value of the address space of the page area is an integer multiple of the unit space of 4096 bits×128 lines. It is said that

Next, the necessary number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When the optional area (c) is used, the horizontal size Hx of the index space handling two-dimensional data can be arbitrarily set as a multiple of 256 bits in order to facilitate the internal operation of the VDP circuit 52. Its vertical size is a fixed value (eg, 2048 lines).

In any case, the first and second AAC areas (a1, a2) are automatically given an index space and an index number by the VDP circuit 52. Therefore, for example, the SETINDEX command, which is a texture setting command, If the AAC area (a) is specified as the decoding destination, the TXLOAD (texture load) command for reading CG data from the CGROM 55 only needs to specify the source address of the CGROM 55 and the horizontal and vertical sizes after expansion (decoding). It will be. Therefore, in the present embodiment, still images (textures) such as characters that temporarily appear in advance notice effects and I-stream moving images are decoded to the AAC area (a).

Since this AAC area (a) is provided with a memory cache function, for example, when the same texture in the CGROM 55 is read out to the AAC area (a) a plurality of times, from the second time onwards: The decoded data cached in the AAC area (a) can be used, and redundant READ accesses and decode processing can be suppressed. However, when the AAC area (a) is used up, the old data is automatically destroyed. Only specific textures that are used repeatedly are acquired in the second AAC area (a2).

Examples of repeatedly used textures include a character that appears repeatedly during a predetermined advance notice effect, and a background image when the background screen is composed of a still image. In such a case, set the decoding destination to the second AAC area (a2) with the SETINDEX command of the texture setting commands, and decode the textures such as characters and background images to the second AAC area (a2) with the TXLOAD command. After that, the decoding result is protected by not using the second AAC area (a2).

Then, after specifying the decoding destination to the second AAC area (a2) with the SETINDEX command, if you execute the same TXLOAD command to reacquire the acquired texture, the acquired texture will hit the cache. , READ access to the CGROM 55 and the time required for the decoding process can be eliminated. As will be described later, such a cache hit function is exhibited even in preload data prefetched in the preload area. A cache hit in the area is meaningful in that it is the decompressed data after decoding.

By the way, the term "texture" generally refers to the texture and feel of the surface of an object. , is used as a concept including not only image data to be pasted on drawing primitives such as triangles and squares, but also image data after decoding. When image data is to be copied (hereinafter referred to as movement for convenience) within the built-in VRAM 71, the original image data is set as a texture by the SETINDEX command of the texture setting commands, and then the SPRITE command is executed. will be executed.

By executing the sprite command, the Source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 12(c). If the correspondence relationship between the area and the index space that becomes the frame buffer is set in advance by environment setting commands (SETDAVR, SETDAVF) and texture setting commands (SETINDEX), for example, the sprite command can be used to access the virtual drawing space. By drawing, the source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 12(c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b) and an arbitrary area (c), each of which has an appropriate number of index spaces. and each index space is specified by an independent index number for each region (a)(b)(c). The index number is, for example, 1 byte long, and the page area (b) (excluding the AAC area (a) automatically assigned by the internal circuit) and the arbitrary area (c) are rendered in the range of 0 to 255. The control CPU 63 can freely assign index numbers.

Therefore, in this embodiment, as shown in FIG. 12(a), a pair of frame buffers FBa are secured in an arbitrary area (c) for the display device DS1, and index numbers 255, 254 is given. That is, an index space 255 and an index space 254 that are toggled to be used are secured as the frame buffer FBa for the main display device DS1. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of pixels in the horizontal direction of the display device DS1. Since each pixel is specified by 32-bit ARGB information, the horizontal size 1280 means 32×1280=40960 bits (a multiple of 256 bits).

For the display device DS2, another pair of frame buffers FBb are secured in the arbitrary area (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of pixels in the horizontal direction of the display device DS2. Also in this case, each pixel is specified by 32 bits of ARGB information, so the horizontal size 480 means 32×480=15360 bits (a multiple of 256 bits).

The reason why the frame buffers FBa and FBb are secured in the arbitrary area (c) is that the arbitrary horizontal size can be set in the arbitrary area (c) as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because, as described above, by matching the number of horizontal pixels of the display devices DS1 and DS2, no waste occurs in the reserved area. On the other hand, in the page area (b), only horizontal/vertical sizes that are integral multiples of the unit space of 128 pixels×128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280×vertical size 1024 is the valid data area for the main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only the area of horizontal size 480×vertical size 800 becomes an effective data area for the sub-display device DS2 (FIG. 12(c), FIG. 22). (e)).

The above points will be further described later, but in any case, the frame buffers FBa and FBb are alternately used as the drawing areas for the drawing circuit 76, and the double buffers (255/254, 252/251) are alternately used. Each double buffer (255/254, 252/251) is alternately used as a display area for the display circuits 74A, 74B. In this embodiment, since the Z-buffer for storing the depth information of the display pixels is not used, a missing number (253) occurs. Index spaces 253 and 250 provide Z-buffers for display devices DS1 and DS2.

Also, in this embodiment, when an additional index space (memory area) is to be secured in the optional area (c) in which the frame buffers FBa and FBb are secured, an index number starting from 0 is given. . Although it is not limited in any way, in this embodiment, as a work area for the notice effect, in which a effect image composed of a character or other still image is made to appear in a part of the display screen in an appropriate rotational posture as necessary, An index space (0) is secured in the arbitrary area (c).

However, the use of a work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, it is possible to secure an index space with dimensions that are multiples of a square unit space of horizontal size 12 ⁸ (=4096 bits)×vertical size 128, so it is suitable for handling small effect images. .

By the way, in this embodiment, the background image is composed of moving images, and the image effects are realized almost exclusively by moving images. In particular, a large number (usually 10 or more) moving images are drawn at the same time during the variable presentation. Each of these moving images is stored in the CGROM 55 in a compressed state as a series of moving image frames. and Here, an I frame (Intra coded frame) means a frame in which an input image is directly compressed independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame for which forward predictive coding is performed, and requires an I-frame or P-frame positioned in the past in terms of time.

Therefore, in this embodiment, the IP stream moving image is developed in the page area (b) instead of the AAC area (a) where there is a concern that the old data will be destroyed. That is, a number of index spaces (IDX ₀ to IDX _N ) are secured in the page area (b) that can secure index spaces of multiple dimensions of horizontal size 128×vertical size 128, and a series of video frames are The same index space IDXi corresponding to MVi is always used for decoding. That is, the moving picture MV1 is developed in the index space IDX1, the moving picture MV2 is developed in the index space IDX2, and similarly, the moving picture MVi is developed in the index space IDXi.

More specifically, the moving picture MVi is specified in advance by the SETINDEX command that "the decoding destination of the IP stream moving picture MVi is the index space (i) of the index number i in the page area (b)". A TXLOAD command is executed to acquire one moving image frame of the IP stream moving image MVi.

Then, one moving image frame (either of a series of moving image frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , one frame of the acquired moving image is decoded and developed in the index space (i) of the page area (b).

On the other hand, in this embodiment, I-stream moving pictures are handled in the same way as still pictures. Run the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and then the automatically started GDEC 75 develops the decoded data in the first ACC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Identified by command.

By the way, IP stream moving images MVi and I stream moving images MVj are generally composed of N moving image frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 in which the k-th (1≤k≤N) video frame is stored and the horizontal/vertical size after development. Although not limited in any way, in an embodiment in which still pictures are hardly used, most of the 48 Mbyte address space (approximately 30 Mbytes) of the built-in VRAM 71 is assigned to the page area (b). In an embodiment in which still images are hardly used, only the first AAC area (a1) is secured as the AAC area, the second AAC area (a2) is not secured, and the cache hit function of the AAC area is used. do not use either.

It is also conceivable to provide a dedicated GDEC (graphics decoder) circuit in order to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is incorporated in the VDP circuit 52, it is sufficient to instruct the GDEC circuit of the head address of the compressed moving image data in the decoding process of the compressed moving image data composed of N compressed moving image frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, incorporating a plurality of such dedicated GDEC circuits for each compression algorithm further complicates the internal configuration of the VDP circuit 52 . Therefore, in this embodiment, software GDEC is used, and decoding processing is realized by software processing corresponding to each compression algorithm for data such as IP stream moving images, I stream moving images, still images, and other α values. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time that matters is mainly the access (READ) time from the CGROM 55 .

Next, returning to FIG. 8A, the data transfer circuit 72 uses the resources (storage media) inside the VDP circuit and the external storage media as transfer source ports or transfer destination ports, and transfers data between them. This is a circuit that performs data transfer operations in a DMA (Direct Memory Access) manner. FIG. 13 is a block diagram showing the internal configuration of this data transfer circuit 72 together with related circuit configurations.

As shown in FIG. 13, the data transfer circuit 72 is configured to transmit/receive data to/from the CGROM 55, DRAM 54, and built-in VRAM 71 via an integrated connection bus ICM having a router function. The CGROM 55 and DRAM 54 are accessed via the CG bus IF section 82 and the DMAM IF section 83 .

On the other hand, the CPU circuit 51 issues the display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT incorporated in the data transfer circuit 72 . The CPU circuit 51 and the data transfer circuit 72 are bi-directionally connected. When the display list DL is issued, the transfer port register TR_PORT is used as a data write port for receiving one unit of data constituting the display list DL. Function. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control section 72d.

As shown, the effect control CPU 63 can WRITE access the transfer port register TR_PORT via the CPUIF unit 81, while the DMAC circuit 60 directly accesses the transfer port register TR_PORT when utilizing the DMAC circuit 60. WRITE access. A series of instruction commands written in the transfer port register TR_PORT (that is, a series of instruction commands forming the display list DL) are processed in 32-bit units by a CPU bus containing a FIFO buffer with a FIFO structure (32 bits x 130 stages). It is configured to be automatically stored in the control unit 72d.

In addition, the data transfer circuit 72 executes data transmission/reception operations on transmission paths of three channels ChA to ChC, and has a FIFO buffer of FIFO structure (64 bits×N stages) ChA control circuit 72a (N=130 stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

Then, the instruction command string (display list DL) accumulated in the CPU bus control unit 72d is sent to the drawing circuit 76 or It is transferred to the preloader 73 . As indicated by the arrow, the display list DL is transferred from the CPU bus control section 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. configured to be

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72c are specialized for the transfer operation of the display list DL. 72b or ChC control circuit 72c, respectively, to the drawing circuit 76 or the display list analyzer of the preloader 73 as part of the display list DL.

The drawing circuit 76 then starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 performs necessary preload operations based on the transferred display list DL. The CG data of the CGROM 55 is read ahead into the preload area secured in the DRAM 54 by the preload operation, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed in relation to the TXLOAD command etc. is secured in the DRAM 54. stored in the DL buffer area BUF'.

On the other hand, a ChA control circuit 72a and a connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. FIG. In addition, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71 that requires the address information of the index table IDXTBL. Specifically, the ChA control circuit 72a, for example, (a) transfers the compressed data of the CGROM 55 to the built-in VRAM 71, or (b) preloads (prefetches) the compressed data of the CGROM 55 and transfers it to the external DRAM 54. and (c) transferring pre-read data in the preload area to the built-in VRAM 71 .

Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c. ST8 in FIG. 22, PT11 in FIG. 27) and the transfer operation of the rewrite list DL' (PT10 in FIG. 27) can be executed in parallel. In addition, the ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously. For example, the processing of step PT10 in FIG. can be executed by However, since there is only one transfer port register TR_PORT, at the timing when one of the transfer port registers TR_PORT is being used by one of them (72b/72c), the other (72c/72b) can access the transfer port register TR_PORT. can't.

During operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the embodiment in which the preloader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b. (See FIG. 28(b)).

As described above, the data transfer circuit 72 of this embodiment has a data transfer source arbitrarily selected from various storage resources and a data transfer destination arbitrarily selected from various storage resources. It provides high-speed data transfer between As can be seen from FIG. 13, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPUIF section 56, CG bus IF section 82, and DRAMIF section 83. FIG.

And, like the amount of data to be acquired at one time from the CGROM 55 (memory sequential READ), the amount of data transfer with the external device in which the ChA control circuit 72a functions is the display in which the ChB control circuit 72b and the ChC control circuit 72c function. The list DL is huge compared to the case of the list DL, and the amount of data transfer is greatly different from each other.

Here, it is conceivable that the unit data amount and the total transfer data amount can be finely set for these various types of data transfer. inhibited. Therefore, in the present embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to an integral multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operations. Realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to integral multiples of this.

Therefore, the instruction command string of the display list DL accumulated in the FIFO buffer of the CPU bus control unit 72d for each 32 bits is transferred to the ChB control circuit 72b and the ChC control circuit 72c at the timing when the total amount reaches the minimum data amount Dmin. and stored in each FIFO buffer.

The display list DL consists of a series of instruction commands. In this embodiment, the command length of the display list DL is an integer N times 32 bits corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It is composed only of (N>0) instruction commands. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can quickly and smoothly start command analysis processing (DL analyze). It should be noted that the command length of 32-bit integer N times does not necessarily mean that all of them are significant bits, but that it is 32-bit integer N times including non-significant bits (Don't care bits).

Next, the preloader 73 will be explained. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72c), and preloads the CG data on the CGROM 55 referenced by the TXLOAD command into the DRAM 54. It is a circuit that transfers to the preload area of . In addition, the preloader 73 stores in the DL buffer BUF' of the DRAM 54 the rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in relation to this TXLOAD command. Note that the DL buffer BUF' and the preload area are secured in advance during the initial processing after CPU reset (SS3 in FIG. 21).

The rewrite list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b when the drawing operation of the drawing circuit 76 is started. ). The drawing circuit 76 then executes the drawing operation based on the rewrite list DL'. Therefore, based on the TXLOAD command or the like, the CG data that should originally be obtained from the CGROM 55 is obtained from the preload area of the DRAM 54 as preload data preloaded in the preload area. In this case, the preload data can be used repeatedly as long as it is not overwritten, and the preload data hit in the preload area is reused repeatedly.

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, the above cache hit function works effectively. Also, since the external DRAM 54 has a large storage capacity, it is possible to preload multiple frames of CG data at once, for example. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the read-ahead operation of the CG data is appropriately set within the range of integral multiples of the operation period δ during the intermittent operation of the VDP circuit 52. Multiple preloading is realized with

However, in the following description, for the sake of convenience, an embodiment without multiple preloading will be described, so the preloader 73 of the embodiment completes the preloading operation for one frame during one operation period (.delta.). As will be described later with reference to FIG. 22, in this embodiment, the operation cycle δ of the VDP circuit 52 during intermittent operation is 1/30 second, which is twice the cycle of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command strings of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. This is a circuit for drawing an image of one frame of each of the display devices DS1 and DS2 in a frame buffer formed in the VRAM 71. FIG.

As described above, in the embodiment in which the preloader 73 functions, the reference destination of the CG data of the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. FIG. Therefore, sequential access to CG data that occurs during execution of drawing by the drawing circuit 76 can be executed quickly, and high-resolution moving images with rapid motion can be drawn without problems. In other words, according to this embodiment, it is possible to use an inexpensive SATA module as the CGROM 55 and execute complex and advanced image effects.

By the way, regardless of whether the preloader 73 is activated or not, the drawing circuit 76 cannot detect any garbled data when the display list DL or the rewrite list DL' is transferred. In addition, it is possible that the drawing circuit 76 freezes due to noise or the like, and the READ/WRITE access to the built-in VRAM 71 stops abnormally. Therefore, in this embodiment, when the drawing circuit 76 detects an irrational instruction command (analyze-disabled bit arrangement) or when there is no READ/WRITE access to the built-in VRAM 71 for a certain period of time, a drawing abnormal interrupt (drawing error interrupt is enabled). This point will be described later with reference to FIG. 22(d).

Next, as described with reference to FIG. 12, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a readout area, and the two areas are alternately switched between uses. to use. Also, in this embodiment, since two display devices DS1 and DS2 are connected, as shown in FIG. 12, two sections of frame buffers FBa/FBb are secured. Therefore, the drawing circuit 76 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1, and draws the drawing area (writing area) of the frame buffer FBa for the display device DS2. Then, one frame of image data is drawn. Note that when image data is written in the drawing area, the display circuit 74 reads the image data in the other read area (display area) and outputs it to each of the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads the image data in the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 14(a)). The final image processing includes, for example, scaler scaling processing for enlarging/reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. Digital RGB signals (total of 24 bits) that have undergone these image processes are normally output together with the horizontal synchronizing signal HS and the vertical synchronizing signal VS.

As shown in FIG. 14(a), in this embodiment, three systems of display circuits A/B/C that execute the above operations in parallel are provided, and each display circuit 74A to 74C corresponds to each The image data in the frame buffers FBa/FBb/FBc are read out and the final image processing is executed. However, since there are two display devices in this embodiment, the frame buffer FBc is not secured and the display circuit 74C does not function.

Here, when confirming the specifications of the main display device DS1, the main display device DS1 transmits odd-numbered pixels (ODD) and even-numbered pixels (EVEN) adjacent to each other in the horizontal direction through separate LVDS (Low Voltage Differential Signaling) transmission lines. It must be received by the receiver RV (RVa+RVb). The frequency of the operating clock CK of the main display device DS1 must be about 40 to 70 MHz (typical value 54 MHz), and the horizontal/vertical The directional wait times WTh/WTv need to be set. Furthermore, at the timing of outputting the image data (ODD/EVEN signal) to the main display device DS1, it is necessary to output the active level data enable signal ENAB.

Therefore, the display circuit 74A needs to output a signal that satisfies all the above specifications. 15(a) to 15(e) illustrate various signals output from the display circuit 74A. First, it is necessary to determine the frequency of the dot clock (LVDS clock) DCK. The designed dot clock DCK in the circuit 52 is 108 MHz (=54×2).

In a display panel LCD of 1280 horizontal dots×1024 vertical lines (see FIG. 15(f)), two pixels adjacent to each other on the left and right are processed at once in synchronization with the operating clock CK of 54 MHz. is equivalent to operating with a dot clock DCK of 108 MHz.

Various operating parameters that define the operation of the display circuit 74A are defined based on the dot clock DCK having a frequency of 108 MHz. First, it is necessary to set the horizontal/vertical standby times WTh/WTv so that (WTh+640)×(WTv+1024)/54 MHz≈1/60 seconds. , (WTh+1280)×(WTv+1024)/108 MHz≈1/60 second.

In addition, it is necessary to consider the permissible range of the specifications of the display device DS1 for the waiting times WTh/WTv in the horizontal/vertical directions. Therefore, in the present embodiment, the horizontal standby time WTh is counted by the dot clock DCK of 108 MHz to be 382 clocks, and the vertical standby time WTv is 59 lines. Therefore, the time required to update the image of one frame is (382+1280)*(59+1024)/108 MHz=16.666 mS, and the frame rate FR is 1/60 second.

This relationship defines the update period FR [seconds] of the display device DS1. Using the frequency F _dot of the dot clock DCK, the number of horizontal synchronization cycles THc, and the number of vertical synchronization lines TVl, which will be described later, FR=THc×TVl/ _Fdot . Here, if the update period FR is too long, an abnormality such as flicker may occur. seconds] < 1.05/60.

Corresponding to this setting, the data enable signal ENAB is set to L level for the standby time WTh (=382/108 MHz) corresponding to 382 clocks in the image updating operation of each line, and then to the active state corresponding to 1280 clocks. The interval (=1280/108 MHz) is active level (H) (FIG. 15(c)). As shown in FIGS. 15(d) and 15(e), during the active period of the data valid signal ENAB, the image is updated at a predetermined time (11.85 μS=1280/108 MHz) for pixels of 1280 dots per line. Image data is output to complete the operation. That is, 1280 pixel data are output in synchronization with 1280 dot clocks DCK. Since a full-color image with a gradation of 2 ⁸ ×2 ⁸ ×2 ⁸ is displayed on the display device DS1, the pixel data of one pixel has a 3×8 bit length.

By the way, in this embodiment, the main display device DS1 outputs the vertical synchronizing signal VS and the horizontal synchronizing signal HS, although they are not required. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WTh. 15(a) and 15(b) show respective operating cycles for convenience of understanding. Also, in FIG. 15(f), circle marks are shown at the upper left and lower right vertices of a rectangular frame specified by TH×TV (=1083×1662 clocks) to indicate “start of display operation” and “start of display operation”. "end" is described, but this o mark means "start of V blank" which defines the operation cycle of the display circuit 74A, which is started every 1/60th of a second. Since the 1083×1662 clock that defines the display operation coincides with 1/60 second, the elapsed time from "start of display operation" to "end of display operation" (operation cycle of display circuit 74A) is 1/60 second. is. "V blank start" will be described later with reference to FIG.

Returning to FIG. 14, the output selection section 79 of the embodiment divides the output signal of the display circuit 74A into dual links that divide the 108 MHz dot clock DCK by two, and , to the LVDS unit 80b (see FIG. 14(a) and FIG. 5). Each of the LVDS sections 80a and 80b converts the image data (24-bit digital RGB signals in total) into first and second LVDS signals, and transmits a clock signal (54 MHz=108/2) to the first and second LVDS signals. In addition, all five pairs of differential signals LVDS1 and LVDS2 are output to the main display device DS1 via two paths (see FIG. 14(a) and FIG. 4).

As described above, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for one adjacent pixel are processed at the same timing. It coincides with the 108 MHz dot clock DCK output by circuit 74A.

The display circuit 74A that generates the image to be transmitted to the main display device DS1 has been described above, but the display circuit 74B generates image data to be transmitted to the sub display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and transmitted to the sub-display device DS2 together with the vertical synchronization signal VS and the horizontal synchronization signal HS.

The data valid signal ENAB is also transmitted along with the synchronization signals VS and HS via the digital RGB section 80c, but each of these signals is transmitted as a continuous signal instead of discrete values as in the case of the LVDS transmission line. of course (see FIG. 14(a)).

By the way, in the case of this embodiment, each of the display circuits 74A to 74B is provided with underrun counters URCNTa to URCNTc for counting Underrun abnormalities in which display data generation was not made in time with respect to the display timing (FIG. 15). reference). The counter values of the underrun counters URCNTa to URCNTc are automatically added for each VBLANK when an underrun abnormality occurs.

Next, the SMC circuit 78 (Serial Management Controller) is a composite controller containing an LED controller and a Motor controller. Then, it outputs an LED drive signal and a motor drive signal in synchronization with the clock signal to the LED/Motor driver (driver IC with a built-in shift register) mounted on the external board, while outputting the latch pulse at an appropriate timing. configured for output.

Regarding the internal circuit and its operation of the VDP circuit 52 described above, the operation contents to be executed by the internal circuit are defined by the operation parameters (set values) set in the control register group 70 by the effect control CPU 63, and the execution of the VDP circuit 52 The state can be specified by reading the operation status value of the control register group 70 . The control register group 70 means a large number of VDP registers RGij mapped in an address space (0 to FFFFFH) of about 1 Mbyte on the memory map of the effect control CPU 63. WRITE (setting) operation of operation parameters and READ operation of operation status values are executed (see FIG. 8(b)).

The control register group 70 (VDP register RGij) includes "system control registers" in which initial setting values related to system operations such as interrupt operations are written, and the AAC area (a) and page area (b) in the built-in VRAM. , an "index table register" relating to building or changing the index table IDXTBL, and a "data transfer a "GDEC register" for specifying the execution status of the graphics decoder 75; a "drawing register" in which instruction commands and setting values relating to the drawing circuit 76 are written; and setting values relating to the operation of the preloader 73 are written. A "preloader register", a "display register" in which setting values relating to the operation of the display circuit 74 are written, an "LED control register" in which setting values relating to the LED controller (SMC circuit 78) are written, a motor controller (SMC It includes a "motor control register" in which settings for the circuit 78) are written, and a "sound control register SRG" in which settings for the sound circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

In any event, in the following description, one or a plurality of registers RGij included in the control register group 70 may be referred to by the individual names described above, or may be generically referred to as VDP registers RGij. The effect control CPU 63 controls the internal operation of the VDP circuit 52 by writing an appropriate set value to a predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL updated at appropriate time intervals and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 63 is in charge of the lamp effect and the motor effect, the VDP register RGij also includes an LED control register and a motor control register.

Next, a unified effect control operation for image effect, sound effect, motor effect, and lamp effect realized by the composite chip 50 incorporating the CPU circuit 51 and the VDP circuit 52 will be described.

In the case of this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 16A) due to power-on or an abnormal reset, and an initial setting process (SP1 to SP1) by an initial setting program (boot program) Pinit. Through SP9), it is configured to shift to the main control process (SP10) by the effect control program Main and the interrupt processing program (vector handler) Vopt. As for the main control processing, FIG. 18(a) describes the processing contents of the introduction part, and FIG. 22(a) describes the processing contents of the body part. The processing of step SP27 in FIG. 18 does not include the processing of steps SS1 to SS3 in FIG. 21(a).

Based on the above, the power-on reset operation will be described with reference to FIG. 16(a). When the system reset signal SYS maintains the L level for a predetermined period (assertion period) such as when power is turned on, all the operation control registers REG and all the VDP registers RGij are automatically set to predetermined default values.

After that, when the system reset signal SYS changes to H level (negate level) (see timing T1 in FIG. 6(d)), in this embodiment, the clock timer TM ( The operation of FIG. 9(a) is started (SP1). Also, the 32-bit data from the top address of the address space CS0 is set in the program counter PC of the effect control CPU 63, and the following 32-bit data is set in the stack pointer SP (SP1). Note that in FIGS. 10 and 17(c), the top area of the memory that stores the initial values of the program counter PC and stack pointer SP is referred to as the vector table VECT.

As shown in FIG. 16(b), the vector table VECT stores vector numbers specifying priority levels, interrupt factors, etc., and address information in association with each other. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the start address of the interrupt processing program executed at the time of the NMI interrupt is stored as address information. It is A vector number 64 is an internal interrupt (VDP_IRQ0) from the VDP, and as address information, the start address of the interrupt processing program executed at the time of the VDP_IRQ0 interrupt is stored.

Since the interrupt priority is as shown in FIG. 18(d), in the columns of vector numbers smaller than vector number 64, the control command reception interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 mS timer interrupt are shown in the interrupt processing program. Each head address is stored. On the other hand, in columns of vector numbers larger than vector number 64, start addresses of interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) having lower priority than VDP_IRQ1 are stored.

In the vector table VECT, vector numbers 0 and 1 define setting values that should be automatically set to the program counter and stack pointer of the CPU at power-on reset. As shown in FIG. 16B, in this embodiment, 4-byte data "****" is set in the program counter PC as an internal operation at the time of power-on reset (reset assertion period), and 4-byte data " ++++" is set to the stack pointer SP. Note that "****" is the top address value of the initial setting program Pinit (SP1 to SP9 in FIG. 16) nonvolatilely stored in the address space CS0, and "++++" is reserved in the built-in RAM 59. It is also the address value of the top or end of the stack area that functions in the LIFO (Last-In First-Out) method.

In this embodiment, since the register bank RBi is effectively utilized, the stack area is not consumed during interrupt processing, and a large memory capacity is not required. That is, in this embodiment, the stack area is exclusively used for function processing and subroutine processing.

As a result of the above operations, the effect control CPU 63 then executes the initial setting program Pinit described after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that defines the operation of the bus state controller 66 (FIG. 9). The initial value of this operation control register REG is a value that is automatically set during the reset assert period (the period shown in FIG. 7(d) in which the system reset signal SYS maintains L level). The slowest READ access operation (default access operation) is set so that READ access can be performed without problems even when configured with memory devices.

Therefore, in order to change this default access operation to an optimum access operation, first, an optimum value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (FIG. 9) with respect to the address space CS0 ( SP1). That is, the initial setting program Pinit (SP1 to SP9), the effect control program MainB (SP10 and below), the memory READ operation when accessing the PROM53 storing constant data etc., in order to optimize according to the memory device, the bus width In addition to setting the presence or absence of page access, the chip select signal CS0, READ control signal, WRITE control signal and other operation timings are optimally set (see FIG. 40).

As a result of the above settings, the processing after step SP2 is executed by optimally memory READing the program stored in the address space CS0. Therefore, next, the performance control CPU 63 performs predetermined operation control that defines the operation of the bus state controller 66 (FIG. 9) for the VDP register RGij in order to optimize the READ/WRITE access operation when accessing the VDP register RGij. An optimum value is set in the register REG (SP2).

As described above, in this embodiment, the VDP register RGij is located in the address space CS7 of the effect control CPU 63. Therefore, a predetermined operation timing of the chip select signal CS7 and other control signals is optimally set. A predetermined value is written in the operation control register REG.

Subsequently, the register value of a specific VDP register RGij is read, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is confirmation determination that the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal. It is a judgment whether or not it is possible to accept it.

Then, if it can be confirmed that the system clock has stabilized by the device code reading process (SP3), the normal operation of the VDP circuit 52 can be expected thereafter, so the setting process for the predetermined VDP register RGij is executed (SP4 ~SP6). In the processing of step SP4, first, the endian setting (big/little) and the data bus width are set when accessing the VDP register RGij from the effect control CPU 63 (SP40). The interrupt significance level (H/L) is set for (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) (SP41).

In this embodiment, the most significant bit of the setting value is set to big endian to be stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits. If the values are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

Further, in the process of step SP4, the frequency of the display clock is set based on the set value in the predetermined system control register RGij (SP42-SP44). Specifically, for the display circuit 74A and the display circuit 74B, generation of the dot clocks DCKA and DCKB based on the 40 MHz reference clock (output of the oscillator OSC2) is set in each of the predetermined system control registers RGij. (SP42), and the multiplication ratio and frequency division ratio for this reference clock are appropriately specified for each display circuit (SP43). Also, the start of operation of the display circuit 74B is set in a predetermined system control register RGij so as to be synchronized with the start of operation of the display circuit 74A (SP44). Furthermore, the LVDS sampling clock is set to be the same as the dot clock DCKA of the display circuit A (SP43).

In these processes, the dot clock DCK is set separately for the display circuit 74A and the display circuit 74B, and the frequency of the dot clock DCKA for the main display device DS1 applied to the display circuit 74A is 108 MHz as described above. is set to On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz corresponding to 480 horizontal pixels by 800 vertical pixels.

In step SP4, the LVDS unit 80 is set to be used as a dual link (a pair of LVDS transmission lines) (SP45). The operating state is switched from the masked state (Defult state) in which zero is output to the unmasked state according to the output of the display circuit 74 (SP45). When the LVDS unit 80 is used as a single link (single LVDS transmission line), the setting to that effect is made in the process of step SP45.

As shown in FIG. 6(f), as a result of the process of step SP45, the operation of the LVDS section 80 is switched from the default state to the non-masked state. SS4 in FIG. 21), the LVDS units 80a and 80b are supplied with the ODD signal and the EVEN signal via the output selection unit 79, and the LVDS signals (LVDS1/LVDS2) are supplied to the display device DS1 via the dual link. ) is transmitted (see FIG. 14(a)). The LVDS sampling clock is set to 108 MHz, which is the same as the dot clock DCKA of the display circuit A. However, since the dual link configuration is adopted in this embodiment, the LVDS sampling clock in each dual link is set to 54 MHz. (see Figure 4).

Further, in the process of step SP4, it is set to operate the DDR (DRAM 54) based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 8A) (SP46). As described with reference to FIG. 8A, the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal. In addition, by setting an appropriate value in a register built into the DDR (DRAM 54), the self-refresh function of the DRAM 54 is enabled (Self-Refresh Operation), and other settings for normal operation of the DRAM 54 are made ( SP47). With the above processing, the DRAM 54 is brought into a state of being able to operate normally, and the subsequent data transfer operation from the PROM 53 to the DRAM 54 (SP8) and the execution of the control program transferred to the DRAM 54 (SP10) are realized without any problems. will be

Subsequently, address spaces CS1 to CS6 are defined to implement the memory map shown in FIG. 10 (SP5). As described above, the address space CS3 is assigned to the internal registers of the audio processor 27, the address space CS4 is assigned to the internal registers of the RTC 38 and the address space of the SRAM 39, and the address space CS5 is assigned to the external DRAM (DDR). 54, and the address space CS6 is assigned to the work memory 57 of the built-in CPU.

Since it is fixedly defined that the VDP register RGij is assigned to the address space CS7, definition processing of the address space CS7 is unnecessary. Further, the address space CS0 is preliminarily defined to be located at the address 0x000000000 or later in the memory map of the CPU circuit 51. Based on this definition, the address space CS0 is secured in the CGROM 55 or other memory. The H/L level of the HBTSL terminal determines whether it is applied to the device.

As described above, in this embodiment, the HBTSL terminal=L, indicating that the address space CS0 is defined in addition to the CGROM 55. FIG. Since the specific bus width of the control memory 53 other than the CGROM 55 and the optimum access operation have already been set in step SP1, the processing of step SP5 is unnecessary for the address space CS0.

Subsequently, for the address spaces CS1 to CS6 defined in the process of step SP5, a predetermined value is written in a predetermined operation control register REG regarding the bus width and presence/absence of page access when accessing each address space CSi (SP6 ). Also, in order to optimally set the chip select signal CSi and others, a predetermined value is written in a predetermined operation control register REG (SP6). These processes are the same as the processes of steps SP1 and SP2. By writing to the operation control register that defines the operation of the bus state controller 66 (FIG. 9), the chip select signal CSi, READ control signal, WRITE Control signals and other operation timings are optimally set.

Subsequently, the abnormal reset is avoided by outputting a clear signal to the WDT circuit 58 that has already started operating (SP7). This is in consideration of the fact that the WDT circuit 58 automatically starts operating after the power is turned on, and after that, the same processing is repeatedly executed. The processing of step SP9 is stored in the control memory 53 as a subroutine SP7, but until the end of step SP9, the subroutine SP7 of the control memory 53 is called. Another transferred subroutine SP7' is called and executed.

Subsequently, among the programs and data stored in the address space CS0, the vector handler Vopt (interrupt processing program) shown in FIGS. The variable D with an initial value and the constant data C are transferred to the external DRAM 54 and internal RAM 59 (SP8). The variable D with an initial value means initial value data stored in a predetermined variable area. This memory section initialization process (SP8) is a process of transferring programs and data in order to speed up the effect control process, and is a process of avoiding access to the ROM, which is inferior in access speed.

Then, a setting is made to indicate that the register bank RBi is to be used (SP9). Therefore, after that, the register banks RB0 to RB14 function during interrupt processing, which speeds up the interrupt processing and reduces the consumption of the stack area.

The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 17(c)). After the execution of the initial setting program Pinit is finished, the main control process by the effect control program Main is executed (SP10). Here, execution of the main control process means execution of the "production control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer process of step SP8 (see FIG. 16(b)).

The processing of the "production control program Main" is divided into main introduction processing shown in the upper part of FIG. 18(a) and FIG. 21, and main body processing shown in the lower part of FIG. 21 and FIG. 22(a). Specific contents will be described with reference to FIG. 18(a) and FIGS. 21 and 22. Prior to this, the memory section initialization process (SP8) will be described. As shown in FIG. 17(a), in the memory section initialization process (SP8), the DMACs of a plurality of channels are initialized to stop operation. It should be noted that this process is merely a formal process just in case.

When the above processing is completed, the DMACi of a predetermined channel is activated, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is transferred to the internal RAM 59 by a non-stop transfer method (see FIG. 11(b3)). DMA transfer. In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, even when the external DRAM 54 malfunctions, an appropriate abnormality handling process can be performed.

Subsequent processing is also the same, and is executed by a non-stop transfer method using the DMACi of a predetermined channel, and the error recovery processing program Piram is DMA-transferred to the built-in RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the built-in RAM 59, the peripheral circuits can be reliably reset in the error recovery processing. For example, if the error recovery processing program Piram is transferred to, for example, the external DRAM 54 other than the internal RAM 59, the external DRAM 54 cannot be reset during the error recovery processing.

Next, the effect control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes lottery data used for effect lottery, and lamp drive data and motor drive data in various drive data tables shown in FIG. 22(b). Also, the variable D having an initial value is DMA-transferred to the external DRAM 54 (SP65).

Finally, the clear data is written to the beginning of the variable area B of the external DRAM (SP66). Assuming that this head address is ADb, in the subsequent DMA transfer processing, after initializing the transfer source address as ADb and the transfer destination address as ADb+1, each address value ADb, ADb+1 is incremented and this clear data is diffused, the variable area B is cleared (SP67).

The processes of steps SP61 to SP66 and step SP67 described above are all similar operations, as shown in FIG. 17(b). That is, first, regarding the DMACi of a predetermined channel, the DMA transfer conditions are (1) cycle steal transfer mode, (2) non-stop transfer method, and (3) update the address values of Source and Destination by increments. SP68).

Next, the initial values of the source address of the transfer source and the destination address of the transfer destination are set (SP69), the transfer size is set, interrupts are disabled (SP70), and the DMA transfer operation is started (SP71). ). Note that the settings in steps SP68 to SP71 are all realized by a setting operation to a predetermined operation control register REG.

In the initialization processing of this memory section, interrupts for the end of DMA transfer are disabled (SP70). and waits for the end of the DMA transfer (SP72). However, considering the processing time until the end of the operation, the clear signal is repeatedly output to the WDT circuit 58 (SP73). At the end of the DMA transfer, the DMACi is set to stop based on the setting operation to the predetermined operation control register REG.

Next, the operation contents of the main control process (main introduction process+main body process) will be described with reference to FIGS. 18(a) to 22. FIG. As for the main control processing (main introduction processing + main body processing), the main introduction processing (SP20 to SP27) is described in the upper part of Fig. 18(a) and Fig. 21, and the initial stage which is part of the main body processing The setting process (SS1 to SS6) is described at the bottom of FIG. The contents of the regular processing (ST4 to ST14), which are the rest of the main body processing, are shown in FIG.

As shown in FIG. 18A, in the main installation process, first, the bus width and ROM device type of the CGROM 55 are specified (SP20). Specifically, as shown in FIG. 19(a), a predetermined VDP register RGij (for example, CG bus Status register) specifying the operating state of the CG bus that controls the interface with the CGROM 55 is read-accessed (SP80 ), it is determined whether or not the CG bus can be set for operation (SP81).

Here, if the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is in the process of resetting, meaning that the set value to the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), ( Operation parameters such as 1) enable/disable of each device section SPAi, (2) ROM device type, and (3) data bus width are set in a predetermined VDP register RGij (SP82).

As shown in FIG. 18(a), in this embodiment, the CGROM 55 can be divided into a plurality of areas (device sections). can be selected. As memory devices, for example, (1) SATA module (AHSI/F) adopted in this embodiment, (2) memory element adopting parallel I/F (Interface) type, (3) sequential I/F type adopting Although they are roughly classified into memory devices, etc., memory devices can be specifically selected for each of the roughly classified memory devices, and the data bus width and the like can be arbitrarily defined.

Next, predetermined operation parameters are set in predetermined VDP registers RGij in order to optimize memory READ operations with memory devices selected for each device section (SPA0 to SPAn) (SP83). The operation parameters include set values that define the operation timings of the chip select signal and other control signals (such as the READ control signal). Further, when a memory element adopting the sequential I/F format is selected, the output timing of the address latch, the number of read clocks, etc. are also specified in order to realize the operation shown in FIG. 19(b).

Therefore, the CGROM 55 can be configured by combining different types of memory devices. However, in this embodiment, the CGROM 55 is configured using only SATA modules, only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

In any case, when the setting processing of steps SP82 and SP83 is completed, a predetermined value is written in a predetermined VDP register RGij in order to make the setting processing effective (SP84). This is in consideration of the fact that it takes a certain amount of time for the internal circuits of the CG bus to operate in response to the setting processing of steps SP82 and SP83. (see SP80) becomes 0.

Therefore, after that, the CG bus Status register is repeatedly read-accessed (SP85), and the process is finished after confirming that the value of the Status register returns from 1 to 0 (SP86). It should be noted that the process of step SP66 may be ended when the value of the Status register does not return from 1 to 0 regardless of the number of determinations made a predetermined number of times. However, in that case, since the game process starts in a state in which the CGROM cannot be normally accessed, the WDT circuit 58 is activated at some timing after that, and the composite chip 50 enters an abnormal reset state. In this case, the power-on reset operation is executed again.

On the other hand, after the process of step SP20 in FIG. 18 is normally executed, internal circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing. (SP21).

Next, for the multi-function timer unit MTU, after starting a predetermined timer measurement operation (SP22), the internal interrupt and the internal interrupt are set to an interrupt enabled state by writing a permission setting value to a predetermined operation control register REG. (SP23).

As a result, after that, various interrupts shown in FIG. 18(d) can occur. Normally, at this timing, the audio processor 27 has finished its initialization sequence, so the end interrupt signal IRQ_SND should have fallen to the L level, as shown in FIG. 7(c). Therefore, the interrupt processing shown in FIG. 18(c) is started, and the effect control CPU 63 initializes the error flag ERR to 1, and READ accesses the address space CS3 (SP30), and the predetermined sound of the sound processor 27 The value of the register SRG is obtained and it is determined whether the initialization sequence has ended normally (SP31).

If the initialization sequence is not completed normally, the effect control CPU 63 writes a reset command to a predetermined voice register SRG of the voice processor 27 (SP32), and is initialized to 1. set the error flag ERR to 2 (SP33). This error flag ERR defines whether or not to execute the speech processor initialization process (SP26), and the error flag ERR=1 is the execution condition of step SP26.

On the other hand, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND=H level. Lower to L level. As a result, the process of FIG. 18(c) is re-executed.

The above describes an exceptional case in which the initialization sequence is not normally completed, but normally, following step SP31, the process of step SP32 is executed, and the effect control CPU 63 stores a predetermined sound register SRG, By writing a predetermined value, the termination interrupt signal IRQ_SND is returned from L level to H level (SP34).

Finally, by writing a predetermined value to a predetermined voice register SRG, READ/WRITE access to all voice registers SRG is permitted (SP35). As a result of this processing, necessary setting processing can be executed in the subsequent voice processor initialization processing (SP26).

An example of the Maskable Interrupt corresponding to the interrupt permission setting in step SP23 has been described above, but a non-maskable interrupt based on the oscillation stop of the oscillator OSC2 can be activated at any timing. As described above, the operating clock (CPU system clock) of circuits other than the built-in CPU (performance control CPU 63) is generated by frequency-multiplying the output clock of the oscillator OSC2 using a PLL (Phase Locked Loop). If the oscillation of VDP circuit 52 is stopped, normal operation of VDP circuit 52 is impossible.

On the other hand, the operation clock of the effect control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by the PLL, and the program processing can be continued. Moreover, the interrupt processing program is stored in the built-in RAM 59 . Therefore, the effect control CPU 63 notifies the occurrence of the abnormal situation by sound or lamp (SP28), and continues outputting the clear signal to the WDT circuit 58 (SP29). The anomaly notification is, for example, a voice notification saying, "An abnormal situation has occurred. Please contact the person in charge as soon as possible." The reason why the clear signal is continuously output to the WDT circuit 58 is to avoid an abnormal reset operation. That is, in the event of a serious abnormality in which the oscillator OSC1 stops operating, even if the abnormality reset processing is repeated, the device cannot be expected to return to normal.

18(b) and 18(c) have been described above, the description will be continued by returning to FIG. 18(a). In step SP24, in order to protect the program area of the external DRAM 54, the required area is set to be write-inhibited. Next, the clock circuit 38, which is battery-powered when the power is cut off, is checked for normal operation when the power is turned off, and the alarm interrupt is set again just in case (SP25).

Then, under the condition that the error flag ERR=1, necessary set values are written into the built-in register (speech register SRG) of the speech processor 27 to execute initialization processing (SP26). When the error flag ERR=0, the process waits for a predetermined time until the error flag ERR=1, but when the limit time is exceeded, the WDT circuit 58 is activated to shift to infinite loop processing.

Next, the power supply control circuit SPY is controlled to prepare for starting the display device DS1, and the necessary set values are written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP27). . Note that the processing of step SP27 is shown in detail as the processing of steps SP50 to SP57 in FIG.

Although the embodiment in which the termination interrupt signal IRQ_SND is received from the audio processor has been described above, it is also preferable to omit the interrupt processing of FIG. 18(c). FIG. 20 shows a modified embodiment, in which a 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

FIG. 20 shows a part of the 1 ms timer interrupt processing, and realizes four stages of operation based on the value (0/1/2/3) of the operation management flag FLG whose initial state is zero. is doing. The IRQ_SND output terminal of the audio processor 27 is in an open state, and the IRQ_SND input terminal of the CPU circuit 51 is fixed at H level.

In the 1mS timer interrupt processing, first, when it is determined that the operation management flag FLG=0 in the processing of step SP42, it is confirmed that the initialization sequence of the audio processor 27 has been completed normally (SP43). If the operation has been completed normally, the interrupt signal (IRQ_SND) is cleared by writing a predetermined value to a predetermined voice register SRG (SP46), and the operation management flag FLG is set to 1 (SP47). The processing of steps SP43 and SP46 is the same as the processing of steps SP31 and SP34 in FIG. 18(c).

On the other hand, if the initialization sequence has not ended normally, the voice processor 27 is caused to start the initialization sequence by writing a reset command to a predetermined voice register SRG (SP44), and the operation management flag FLG is set to zero. Return (SP45). The processing of step SP44 corresponds to the processing of step SP32 in FIG. 18(c).

Normally, after the processing of step SP47, the operation management flag FLG=1, so in the next 1 ms timer interrupt, writing a predetermined value to a predetermined voice register permits access to all voice registers (SP48). ), and the operation control flag FLG is set to 2 (SP49). The processing of step SP48 corresponds to the processing of step SP35 in FIG. 18(c).

Next, in the 1 ms timer interrupt with the operation control flag FLG=2, as in the case of step SP26 in FIG. Initialization processing is executed (SP50), and the operation management flag FLG is set to 3.

The operation management flag FLG=3 means a normal voice control state, and by setting the necessary operation parameters in the necessary voice register SRG, the voice control is advanced (SP52).

As described above, the normal end of the initialization sequence of the audio processor 27 is confirmed by the interrupt processing caused by the interrupt signal (IRQ_SND) (SP31 in FIG. 18(c)) and by the 1 ms timer interrupt processing (FIG. 20). SP43) of the method has been described, but the method is not limited to these methods in any way. For example, as part of the processing of step SP26 in FIG. 18, it is also suitable to determine whether the initialization sequence of the audio processor 27 has been completed normally.

Since the outline of the main introduction process (SP20 to SP26 in FIG. 18) has been described above, the details of the process of step SP27 (startup preparation process + initialization process) and the main body process will be described below based on FIGS. The operation of the processing (SS1 to SS6 and ST4 to ST14) will be explained.

As shown in FIG. 21, the effect control CPU63 first determines the clock timer TM as the process of step SP27, and that one second has elapsed since the start of operation of the effect control CPU63 (timing T1 in FIG. 6(d)). , while outputting a clear signal to the WDT circuit 58 (SP50). This is to maintain the display device DS1 in a non-operating state until the VDP circuit 52 starts to operate substantially. In addition, since a clear signal is output to the WDT circuit 58, activation of the WDT circuit 58 is reliably prevented, and there is no possibility that the initialization processing up to this point will be wasted, such as an abnormal reset of the composite chip 50 (the significance of this is is the same in the following standby processing).

Next, the effect control CPU 63 changes the control signals PS1 and PS2 to the power supply control circuit SPY from L level to H level (SP51). This process is the operation at timing T2 shown in FIG. 6(g) and FIG. 6(h), and the control signals PS1 and PS2 are maintained at H level thereafter.

When the control signal PS1 becomes H level, the MOS transistor Q1 is turned on, and the power supply voltage 12V is supplied to the backlight section BL. However, at this timing T2, the BL_EN terminal and the PWM terminal of the driver DVL of the backlight section BL are both at the L level, so the backlight section BL does not emit light.

Further, when the control signal PS2 becomes H level, the MOS transistor Q4 is turned on, and the power supply voltage 5 is supplied to the liquid crystal display unit MONI. However, at this timing T2, since the backlight section BL is in the off state, there is no possibility that an unnatural image will be displayed.

When the process of step SP51 is finished, next, the effect control CPU 63 defines the refresh mode based on the set value of the predetermined VDP register RGij, and also sets the refresh cycle of the built-in VRAM 71 and the row address (refresh address). An initial value is set, and the internal VRAM 71 is initialized (SP52).

The VRAM 71 of the embodiment is composed of a DRAM (Dynamic Random Access Memory), and electric charges stored in memory cells are gradually lost due to leakage current inside the element. Therefore, in this embodiment, for example, a distributed refresh method is adopted in which refresh is performed row by row, and all the rows (ROW) in the element are refreshed at the refresh cycle defined in the processing of step SP52 to eliminate the charge in the memory cells. is prevented. Therefore, even if there is a memory cell that has not been accessed for a long time in VRAM 71, there is no possibility that the data therein will be lost. Note that the refresh mode is not limited to the distributed refresh method, and a centralized refresh method can also be adopted.

Next, a necessary set value is written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP54). Note that this processing is nothing but an operation of hardware resetting the corresponding internal circuit.

Subsequently, the control signal STBY to the power supply control circuit SPY is changed from L level to H level (SP56). This processing is the operation at timing T3 shown in FIG. 6(i), and the H level of the control signal STBY is maintained thereafter. At this timing T3, the driver DVL of the backlight unit BL has already been supplied with the power supply voltage of 12V (timing T2), so the driver DVL becomes operable. However, since the control signal PWM still maintains the L level, the backlight section BL does not emit light.

Next, execution of the process of step SP4 in FIG. 16 and execution of the process of step SP54 in FIG. 21 are confirmed by read-accessing a predetermined VDP register (status register STS) RGij (SP57). Specifically, first, it is confirmed by the status register STS(1) that the display clock set in the processing of step SP4 in FIG. 16 is stabilized.

Next, it is confirmed by the status register STS(2) that the initialization of the display circuit has been normally completed corresponding to the process of step SP54. Subsequently, in the processing of step SP45, it is confirmed by the status register STS(3) that the initialization of each part LVDS1/LVDS2 of the LVDS circuit 80 set to dual link has been normally completed. Then, when it is confirmed that all the initializations have been completed normally, the main installation process ends (SP57).

Subsequently, subsequent processing will be described with respect to an embodiment in which the preloader does not function. As shown in FIGS. 21 to 22(a), the main body processing includes VDP initial setting processing (SS1 to SS6) executed after CPU reset, and then regular processing (ST4 to ST14).

Since the steady process (ST4 to ST14) is started at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), the operation cycle δ of the steady process is 1/30 second. This operating cycle δ is nothing but the substantial operating cycle δ of the VDP circuit 52 that operates intermittently under the control of the effect control CPU 63 . The reason why the judgment condition is set to VCNT≧2 is to take into account the possibility that the steady process (ST4 to ST14) is abnormally prolonged and the timing of VCNT=2 is missed. is designed so that it does not occur.

Based on the above, the VDP initialization process will be described. As shown in FIG. 21, in this embodiment, in the VDP initial setting process, the built-in VRAM 71 with a storage capacity of 48 Mbytes is divided into an ACC area (a), a page area (b), and an arbitrary area (c) having appropriate storage capacities. ) and appropriately (SS1). Specifically, for the ACC area (a1, a2) and the page area (b), the top address of each area and the required total data size are set in a predetermined index table register RGij (SS1). Then, the reserved ACC area (a1, a2) and the remaining area not included in the page area (b) become the arbitrary area (c).

Here, the lower 11 bits of the area start addresses of the first and second ACC areas (a1, a2) and the page area (b) must be 0, but they can be arbitrarily selected in units of 2048 bits. (1 address = 1 byte, selection for each 256 addresses). Also, the total data size is arbitrarily selected within the range of integral multiples of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

Thus, in this embodiment, certain conditions are set for setting the ACC area (a1, a2) and the page area (b). This is for the purpose of facilitating the internal operation of the VDP circuit 52 while eliminating the area. In other words, if the storage capacity of the built-in VRAM 71 is recklessly increased, there is concern that the manufacturing cost will rise and the chip area will increase. This is because the processing time for VRAM access cannot be shortened due to complication. It is for the same reason that certain restrictions are placed on securing the index space described below.

Continuing the explanation based on the above, following the processing of step SS1, necessary index spaces IDXi are secured for the page area (b) and the arbitrary area (c) (SS2). Specifically, by setting necessary information in a predetermined index table register RGij, an index space IDXi for each area (b) and (c) is secured.

For example, when index space IDXi is provided in page area (b), multiple information of arbitrary horizontal size Hx and arbitrary vertical size Wx (vertical and horizontal multiple information for unit space) ) is set in a predetermined index table register RGij (SS2).

As described above, the index space IDXi of the page area (b) has a horizontal size of 128×vertical size of 128 lines as a unit space, and one pixel is specified by 32-bit information. Based on the setting of the size Wx, an index space IDXi of data size (bit length)=32×128×Hx×128×Wx is secured. The head address (space head address) of the index space IDXi in the page area (b) is automatically assigned internally.

When the index space IDXi is provided in the arbitrary area (c), an arbitrary start address (space start address) STx and information on multiples of an arbitrary horizontal size Hx corresponding to an arbitrary index number i are specified. is set in the index table register RGij (SS2). Arbitrary means that the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 11 bits of the start address STx are 0, and is arbitrarily determined in units of 2048 bits. As described above, the vertical size of the arbitrary area is fixed to 2048 lines, so based on the setting of the horizontal size Hx, after the start address STx, the data size (bit length) = 2048 × Hx index A space has been secured.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces each having a horizontal size of 1280×vertical lines of 2048 are set in one or a plurality of predetermined index table registers RGij, each specifying an index number. , as the frame buffer FBb of the sub-display device DS2, a pair of index spaces of horizontal size 480×vertical lines 2048 are set in one or more predetermined index table registers RGij, each specifying an index number. If the number of horizontal pixels of the display device does not match the integer multiple of 256 bits/32 bits, the horizontal size of each index space should be larger than the number of horizontal pixels of the display device and 256/32=8 , to minimize wasted memory space.

As described above, the necessary number of index spaces IDXi are generated by setting the necessary size information and address information in the predetermined index table registers RGij for the page area (b) and the arbitrary area (c). (SS2). In response to this setting process (SS2), an index table IDXTBL for specifying the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 12(a), the index table IDXTBL stores the start address of each index space IDXi together with other necessary information. ) is referred to when acquiring data from (see FIG. 13). Since the index space IDXi of the AAC area (a) is automatically generated when necessary and automatically destroyed, the setting process of step SS2 is unnecessary.

As shown in FIGS. 12(a) and 12(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and index numbers are assigned to each pair. In an embodiment that does not use the Z-buffer, a pair of index spaces 255 and 254 assigned index numbers 255 and 254 are reserved as the frame buffer FBa. A pair of index spaces 252 and 251 to which index numbers 252 and 251 are assigned are secured as the frame buffer FBb. In this embodiment, a work area with index number 0 (index space 0) is also secured in the arbitrary area (c).

Also, in this embodiment, the necessary number of index spaces IDXi for decoding IP stream moving images are secured in the page area (a), and the index number i is assigned. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is reserved. Then, according to the necessity of the image effect (fluctuation effect and advance notice effect), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL, After that, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 12(a) shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL. and other necessary information are automatically set. In this embodiment, this AAC area (a) is used as a decoding area for textures such as still images.

The above operation of securing the index space is realized mainly by setting the index table register RGij included in the control register group 70. Following the processing of steps SS1 to SS2, another VDP register RGij is set to: By executing the necessary setting operation (SS3), the steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 30 and 31 is made possible.

In this embodiment, the required setting process (SS3) includes at least SS30 to SS39. Note that steps SS30 to SS37 do not limit the order of processing, and can be executed in any order regardless of the order of explanation below.

In this embodiment, first, predetermined operation parameters (the number of lines and the number of pixels) are written in a predetermined display register RGij that defines the operation of the display circuit 74, thereby obtaining the number of display lines and the number of display lines for each of the display devices DS1 and SD2. The number of horizontal pixels is set (SS30). In this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024 lines. The number of horizontal pixels of the sub-display device DS2 is 480 dots, and the number of display lines is 80 rows. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the effective data area (broken line portion in FIG. 22(e)) to be read-accessed by the display circuits 74A and 74B are specified in each of the frame buffers FBa and FBb. .

Next, by writing predetermined operation parameters (THc, WTh) to a predetermined display register RGij that defines the operation of the display circuit 74, for each display device DS1, SD2, the cycle number THc of the horizontal period TH, A horizontal standby time WTh is set (SS31). Further, by writing predetermined operation parameters (TVl, WTv) to predetermined display registers RGij, the number of lines TVl of the vertical cycle TV and the vertical standby time WTv are set for each of the display devices DS1, SD2 (SS32). ).

As described with reference to FIG. 15, for the main display device DS1, the number of cycles THc in the horizontal period TH is set to 1662, and the number of lines in the vertical period TV TVl is set to 1083. Also, the horizontal waiting time WTh=382 and the vertical waiting time WTv=59 lines are set. On the other hand, for the sub display device DS2, for example, the number of cycles in the horizontal period TH is set to THc=519, the number of lines in the vertical period TV is set to TVl=867, the horizontal standby time WTh is set to 39, and the vertical standby time WTv is set to 67 lines. be done. Note that THc-WTh=519-39=480 and TV1-WTv=867-67=800, which match the number of pixels of the sub-display device (480 horizontal×800 vertical).

In any case, the frequency F _dot (=108 MHz) of the dot clock DCK is determined by the processing of step SP4 in FIG. As a result of defining THc (=1662) and the number of lines TVl (=1083) of the vertical period TV, the display period of one frame is determined as THc× _TVl /Fdot. Specifically, the display period of one frame is 1083×1662/108 MHz=16.667 mS, and the frame rate FR is determined to be 1/60 second.

For the sub display device DS2, for example, based on the frequency F _dot of the dot clock DCK = 27 MHz, the number of cycles THc of the horizontal cycle TH = 519, and the number of lines TVl of the vertical cycle TV = 867, 519 × 867/ It is determined that 27MHz=16.66mS.

Next, in this embodiment, regarding the sub-display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS33). Also, regarding the sub display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS34).

As described above, the main display device DS1 does not require the horizontal synchronizing signal HS or the vertical synchronizing signal VS, so the above processing (SS33 to SS34) for the main display device DS1 is unnecessary. However, if the setting process of steps SS33 to SS34 is omitted, the default values set at the time of power reset function. Therefore, the display device 74A also outputs the horizontal synchronizing signal HS and the vertical synchronizing signal VS in practice. It will be.

According to the default value, for example, a horizontal synchronizing signal HS with a pulse width of 40 clocks, which becomes active level 16 clocks after the V blank start timing, is output, and becomes active level in synchronization with the V blank start timing. A vertical synchronizing signal VS for three lines is output.

In this operation, a horizontal synchronization signal HS having a horizontal front porch HPv=16, a pulse width PWh=40, and a horizontal back porch BPv=326 is output to the main display device DS1 during a horizontal standby time WTh=382 clocks. Also, it means that a vertical synchronization signal VS having a vertical front porch HPv=0, a pulse width PWv=3, and a vertical back porch BPv=56 is output during the vertical standby time WTv=59 lines. However, as described above, these synchronization signals are ignored in the main display device.

In order to prevent the synchronizing signals HS and VS from being output based on the default values, a configuration may be adopted in which a predetermined system control register RGij is set so that the horizontal synchronizing signal HS and the vertical synchronizing signal VS are not output. When such mask setting is provided, the output terminal of the horizontal synchronizing signal HS and the output terminal of the vertical synchronizing signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

Subsequently, a predetermined system control register RGij is set to allow the V blank interrupt (SS35). As a result, in this embodiment, the VBLANK start interrupt shown in FIG. 22(c) is generated corresponding to the V blank start timing that occurs every 16.667 mS=1/60 second. This V blank interrupt timing defines the start timing of the regular processing (ST5 to ST14) of the effect control CPU 63, and also means the start timing of the display period for the display circuits 74A and 74B (end timing of the previous display period). .

Next, a predetermined operation parameter (address value) is written in a predetermined display register RGij to specify the vertical display start position and horizontal display start position for each of the frame buffers FBa and FBb (SS36). As a result, the effective data area whose vertical and horizontal dimensions are specified in the process of step SS34 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and the display start position is (0, 0) in the example shown in FIG. 22(e).

Here, the "display area" means an index space (frame buffers FBa, FBb) from which image data should be read in order for the display circuits 74A, 74B to drive the display devices DS1, DS2. means either one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read the image data only in the "effective data area" specified in steps SS30 and SS36 in the display area (0) or the display area (1).

Next, the display register RGij (DSPAINDEX) relating to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) relating to the display circuit 74B driving the sub-display device DS2 are set to "display area (0)". and "display area (1)" to define each display area (SS37).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as "display area (0)", and the index number in the VRAM arbitrary area (c) 255 index space 255 is defined as "display area (1)" (SS37).

Also, regarding the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is set to "display area (0)", and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is set to "display area ( 1)” (SS37). It should be noted that defining the "display area" in the initial processing (SS3) is not particularly limited. You can switch. It is also preferable to zero-clear the respective display areas (0) and (1) of the frame buffer FBa and the frame buffer FBb at this timing. is never displayed.

In this embodiment, after the initial setting including the above processing (SS30 to SS37) is completed, next, the set value of the predetermined system control register RGij is prevented from being changed by the influence of noise or the like after that. A predetermined prohibition value is set in the seed prohibition setting register RGij (first prohibition setting SS38).

Here, the setting values for which future writing is prohibited include: (1) setting values related to the display clock DCK of the display devices DS1 and DS2; (2) setting values related to the LVDS sampling clock; (4) Synchronous relationship between the plurality of display devices DS1 and DS2 (that the display circuit 74B is subordinate to the operation cycle of the display circuit 74A), etc. are included. Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is also suitable to use it as needed.

Next, by setting a predetermined prohibition value in the type 2 prohibition setting register RGij, the VDP register RGij of the initial setting system is write-prohibited (second prohibition setting SS39). Here, the prohibited registers include the VDP register RGij related to step SP4 and steps SS30 to SS37.

On the other hand, by setting a predetermined prohibition value in the third type of prohibition setting register RGij, it is possible to prohibit many VDP registers, including the VDP registers related to the setting processing of steps SS1 to SS3 (see the 3 prohibition setting). However, it is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily released by writing a release value to a predetermined release register RGij, and the set value can be changed during steady operation. is also possible.

After the above processing is completed, next, in the processing of step SP52 in FIG. 21, the status register (4) is referred to regarding the end of initialization of the built-in VRAM 71 that defines the refresh cycle, and the operation is stable ( Normal end of initialization) is confirmed (SS40).

By the above processing, it is confirmed based on the values of the status registers (1) to (4) that the built-in VRAM 71, the display circuit 74, and the LVDS circuit 30 have all completed the initialization processing normally. Then, by writing a specified value to a predetermined display register RGij (DSPACTL/DSPBCTL), the operation of the display circuits 74A and 74B is started (SS4a), and a predetermined system control register RGij (SYSDSPLVDS1MD/SYSDSPLVDS2MD) is started. By writing a specified value to , output data from the display circuit 74A is output from the LVDS circuit 80 (LVDS1/LVDS2) (SS4b).

This operation is nothing but the processing at timing T4 in FIG. 6(e), and in this embodiment, the program is designed so that the processing of steps SS4a to SS4b is executed within a predetermined time τ (for example, 20 mS) from timing T2. It is When the display circuits 74A, 74B and the LVDS circuit 80 start operating (timing T4), the clock timer TM is restarted from zero (SS4c). Note that the processing procedure of steps SS4a to SS4b is not necessarily limited. Even if the processes of steps SS4a and SS4b were executed in reverse order, the LVDS circuit 80 would only output idle image data for a moment at most, and furthermore, the backlight unit BL would be turned off, so there would be no effect. No problem.

In any case, in this embodiment, the display circuit 74 enters the V-blank start state every 1/60 second and the LVDS circuit (LVDS1/LVDS2) 80 is set to By operating, the display operation shown in FIG. 15 is repeated. In FIG. 15, the start timing of the display operation and the end timing of the display operation indicated by ◯ indicate the V-blank start timing.

Based on this V-blank start timing, the horizontal reference point TH0 (=horizontal reference time) and vertical reference point (=vertical reference time) TV0 in the operation of the display circuit 74 are defined. waits without outputting the image data corresponding to each pixel of the display device until the horizontal standby time WTh has elapsed from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait from the vertical reference point TV0 until the vertical standby time WTv elapses without outputting the image data corresponding to each pixel of the display device.

Also, since the display circuit 74B operates in synchronization with the display device 74A (SP4 in FIG. 16), the start and end timings of the display operation for the sub-display device DS2 are the same as those for the main display device DS1. Therefore, by setting the frame period (519×867/27) for the sub-display device DS2 to be shorter than the frame period (1083×1662/108) for the sub-display device DS2, when the V-blank starts, the sub-display device DS2 Set to complete the update process.

After completion of the processing of step SS4 having the above significance, next waits for 300 mS to elapse based on the clock timer TM (SS5). Transition (SS6). As a result, the backlight unit BL becomes a light emitting state, and the liquid crystal display unit MONI, which has started operation before this, starts display operation based on the image data received from the display circuit 74A. At this timing, since no display list has been issued, the contents of the VRAM are displayed as they are, as described above. Therefore, it is preferable to entrust the processing of steps SS5 to SS6 to the timer interrupt processing (see the broken line). A predetermined initial screen is displayed on the device DS1.

Next, the rest of the main body processing, which is the steady processing that is repeatedly executed at predetermined time intervals, will be described with reference to FIG. 22 . As shown in FIG. 22, the operation of the effect control CPU 63 is the main control process (a), the timer interrupt process (b) that starts every 1 ms, and the reception interrupt process (not shown) that starts in response to the control command CMD. , VBLANK interrupt processing (c) that is activated by receiving the VBLANK signal generated at the start timing of the V blank (vertical blanking period) of the display device DS1, and drawing abnormal interrupt processing ( d) and Note that the description of the 20 μs interrupt processing is omitted.

In the reception interrupt process, the control command CMD received from the main control section 21 is stored in a predetermined reception buffer so that it can be referred to in the main control process (ST13), and the process ends. In the VBLANK interrupt processing (FIG. 22(b)), the interrupt counter VCNT is incremented (ST15) for each VBLANK interrupt. After grasping the operation start timing, the interrupt counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 22(b), the timer interrupt process includes a process (ST18) for acquiring an origin sensor signal and the like to proceed with the motor effect, and a ramp effect progress process (ST19). ing. The lamp effect and the motor effect are controlled based on the effect scenario that centrally manages all the effect operations, and when the effect start time managed by the effect counter EN is reached, the motor drive table and the motor drive table are changed in the effect scenario update process (ST11). A lamp drive table is specified.

After that, the motor effect progresses based on the specified motor drive table, and the lamp effect progresses based on the specified motor drive table. As explained above, in some embodiments, the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect progresses every 1 ms, but the ramp effect progresses at an appropriate timing longer than 1 ms.

On the other hand, as shown in FIG. 22(d), in the abnormal drawing interrupt process, READ access is made to the status register RGij indicating the operation state of the drawing circuit 76 to identify the cause of the interrupt. Specifically, (1) the abnormal drawing interrupt due to the detection of an abnormal instruction command (bit garbled) or (2) the abnormal drawing interrupt due to the abnormal operation (freeze) of the drawing circuit 76 is specified (ST16a). If the abnormal drawing interrupt is detected based on the detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value to a predetermined system control register RGij (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in FIG. 7(b).

Next, after confirming the normal completion of the individual reset operation with a predetermined status register RGij, a group of operation parameters that define the operation of the drawing circuit 76 are reset in the predetermined drawing register RGij, and the process ends (ST16c). . After adjusting the stack area for storing the return address (clearing process for erasing the return address after the interrupt processing), the process proceeds to step ST13 (ST16c).

On the other hand, in the case of an abnormal drawing interrupt due to an abnormal operation of the drawing circuit 76, the WDT circuit 58 is activated and the entire composite chip 50 is reset by shifting to infinite loop processing (ST16d). If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK, and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 7B). . In this case, after confirming the normal completion of the reset operation of the VDP circuit 52, the processing of steps ST4 and ST13 is performed. In order to avoid reading the control command CMD as much as possible, it is better to proceed from step ST4 to step ST13, including other cases.

When the entire composite chip 50 is reset, the presentation up to that point disappears and the presentation control is completely returned to the initial state (power-on state), but when only the VDP circuit 52 is reset, the reset operation of the VDP circuit 52 Although a predetermined standby time occurs until is completed, a series of effect control can be continued. In addition, since the effect control CPU 63 controls the image effect, the lamp effect, and the sound effect in a unified manner, there is no unnatural deviation in each effect.

The initial setting processing of steps SS1 to SS3 described above is executed based on the initial value setting table SETTABLE (see FIG. 36) that associates the register address value of the VDP register RGij with the setting value of the register RGij. be done. Since the initial setting process has been described above, next, before describing the steady process (ST4 to ST14), the steady operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 is shown in FIGS. A schematic description will be given based on FIG. 31(b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 30 and 31. In the embodiment in which the preloader 73 is not used, the display list DLi completed by the effect control CPU 63 is as shown in FIG. In the operation cycle (T1), the drawing circuit 76 is issued, and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle T1+δ, so that the image data are displayed on the basis of the subsequent drawing operations of the display devices DS1 and DS2. , becomes a display screen that the player perceives.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. 31(a), the display list DLi completed by the effect control CPU 63 is issued to the preloader 73 in its operation cycle (T1), and the preloader 73 , interprets the display list DLi, performs the necessary look-ahead operations, and rewrites a portion of the display list DLi to complete the rewrite list DL'. The pre-read CG data and rewrite list DL' are stored in appropriate locations in the DRAM 54. FIG.

Next, the drawing circuit 76 acquires the rewriting list DL' from the DRAM 54 in the next operation period (T1+.delta.), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewriting list DL'. . Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle (T1+2δ), thereby enabling subsequent drawing of the display devices DS1 and DS2. Based on the action, it becomes a display screen that the player perceives.

The intermittent operation of the VDP circuit 52 has been briefly described above, but in order to realize the operations shown in FIGS. is repeatedly referred to, until the operation start timing is reached, and when the operation start timing (V blank start timing skipped by one) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady operation is started. In this embodiment, first, it is determined whether or not an operation start condition for starting steady operation is satisfied (ST5). This determination timing is the timing of T1, T1+δ, T1+2δ, . The display timing of the display device DS2 is set at the initial setting (ST3) so as to follow the display timing of the display device DS1.

Since the operation start condition determined by the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is used, first, an embodiment (FIG. 22) in which the preloader 73 is not used will be described. In this case, the circuit configuration and program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 30(a). That is, based on the display list DL1 completed in the operating cycle (T1), the drawing circuit 76 should finish the drawing operation during the operating cycle (T1 to T1+δ). However, for example, like the display list DL3 completed in the operation cycle (T1+2δ) of FIG. In addition, regarding the display circuit 74, there is a possibility that an underrun abnormality has occurred in which display data is not generated in time with respect to the display timing.

The determination process of step ST5 takes this situation into consideration, and the effect control CPU 63 accesses the status register RGij (a kind of the control register group 70) indicating the operation state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether or not necessary operations have been completed, and whether or not there is an Underrun abnormality. The presence or absence of Underrun abnormality is determined based on underrun counters URCNTa to URCNTc. In an embodiment that does not utilize the preloader 73, for example, at timing T1+.delta. in FIG. to confirm.

Then, if the operation start condition is not satisfied (abnormal/unsuitable), the abnormality flag ER that counts the number of abnormalities is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER is determined in the processing of steps ST9 and ST10 together with other serious abnormality flags ABN. On the premise that the serious abnormality flag ABN is in a reset state, if the number of consecutive abnormalities is not large (ER≤2), Effect command analysis processing is executed in the same manner as in the normal state (ST13).

In the case of an underrun abnormality, steps ST6 to ST8 are similarly skipped. Then, by writing a predetermined clear value to a predetermined system control register RGij, the display clock DCK (frequency) and the display circuit 74 are initialized (ST10c). After confirming the normal completion of this initialization process, the frequency of the display clock DCK and the values of the group of system control registers RGij that define the operation of the display circuit 74 are reset to the specified values (ST10c). , effect command analysis processing is executed (ST13).

In the effect command analysis process (ST13), it is determined whether or not the control command CMD is received from the main control board 21. If the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes start preparation processing for a new variable performance based on the control command CMD instructing the start of the variable performance, and error notification start processing based on the control command CMD indicating the occurrence of an error. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

In the above, the case where the minor underrun abnormality or the operation start condition is not met and the abnormality flag ER is ER≤2 has been described. In such a case, the display circuit 74 Toggling the display area read by (ST6) and display list creation processing (ST7) are skipped, and the production scenario does not progress (see ST8 to ST12). This is to prevent output of image data in the frame buffers FBa and FBb that are incomplete. Therefore, for example, in the operation cycle (T1+3δ) of FIG. 30(a), the image effect does not progress, and the original screen (the screen based on DL2) is redisplayed, causing a frame drop.

Here, in order to avoid dropping frames, a configuration of waiting until an operation start condition is satisfied is also conceivable. However, there are many control processes (ST6 to ST12) to be executed by the effect control CPU 63, and it is necessary to secure the processing time for each. there is

However, even if a frame drop occurs, the progress of the image rendering will only be delayed by about 1/30 to 2/30 of a second compared to the ramp rendering and motor rendering progressing by the interrupt processing (FIG. 22(b)). Yes, and the player is unaware of this. Moreover, when a frame is dropped, the effect scenario process (ST11) including the process of updating the effect counter EN and the sound progress process (ST12) are also skipped, so that the ready-to-win effect, the advance notice effect, and the accessory that are started after that are skipped. In the production, there is no possibility that the start timing of the image production, sound production, lamp production, motor production, etc. is shifted.

That is, in the production scenario, the start timing of image production, sound production, lamp production, and motor production and the content of production to be executed thereafter are centrally managed. Since the timing is controlled, the synchronization of various effects will not be lost. For example, when there is an effect operation that combines an explosion sound, an explosion image, a character object movement, and a lamp flash operation, each of the above effect operations is correctly started in synchronization even after a frame drop occurs. be.

In the above, the case of a relatively minor abnormality has been explained. After the determination, an infinite loop state is established (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, the composite chip 50 including the effect control CPU 63 is abnormally reset, and then the initial processing (SS1 to SS3) is re-executed, thereby preventing the occurrence of an abnormal situation. It is hoped that the root cause will be eliminated.

Since this reset operation is executed by activating the WDT circuit 58, the entire composite chip 50 including the CPU circuit 51 is reset (FIG. 7(b)). Therefore, in order to avoid resetting the CPU circuit 51, the effect control CPU 63 outputs a predetermined keyword string (for example, three pieces of 1-byte data) to the pattern check circuit CHK, and outputs the reset signal RST to the VDP circuit 52. is also suitable (see ST100 in FIG. 36). Also in this case, after confirming the normal completion of the reset operation of the VDP circuit 52 (ST101), the processing of steps ST4 and ST13 is performed.

In any event, since the sound circuit SND is also abnormally reset at the time of this abnormality, the image effect, sound effect, lamp effect, and motor effect all return to their initial states. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no danger of disappearance of the big win state or disappearance of prize balls.

Abnormalities have been described above, but in reality, the abnormalities described above rarely occur, even if they are minor. Based on this, the "display areas" of the frame buffers FBa and FBb for storing the image data to be read by the display circuit 74A and the display circuit 74B are toggled (ST6). As described above, "display area (0)" and "display area (1)" are defined in advance in the initial processing (ST3). 'display area' specifies which of display area (0)/display area (1).

By executing step ST6, the display circuit 74A alternately outputs image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) at each operation cycle δ. The data is read out to drive the display device DS1. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) every operation cycle δ, and displays the sub display device DS2. will drive. As described above, the display circuit 74 actually performs READ access only to the effective data area in the display area (0)/display area (1).

In any case, in this embodiment, since the "display area" is switched for each operation cycle, the display circuits 74A and 74B display the image data completed by the drawing circuit 76 in the immediately preceding operation cycle on the display devices DS1 and DS2. will start the output process to However, since the process of step ST5 is started at the start of the vertical blanking period (V blank) of the main display device DS1, the image data output process actually starts after the vertical blanking period is completed. will be In FIG. 30(a), the arrows shown in the column of the display circuit indicate the operation cycle of this output process.

When the processing of step ST6 having the above significance is completed, the effect control CPU 63 subsequently completes the display list DL specifying the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the RAM 59 is secured and the display list DL is completed there (see FIG. 13).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are set to an integer N times the command length of 32 bits (N>0). It is limited to only instruction commands for As described above, an instruction command composed of 32-bit integer N times may include a Don't care bit.

In this way, the display list DL of the embodiment is composed only of instruction commands whose command length is an integer N times 32 bits (N>0). It is always an integral multiple of the minimum command length unit (32 bits=4 bytes). Furthermore, in this embodiment, considering the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is set to an integer multiple (1 or more) of the minimum data amount Dmin and Adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes, and so on.

Here, depending on the complexity of the content of the presentation, it is also suitable to adjust to 256 bytes or 512 bytes as appropriate. The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not executing such complicated image effects.

However, this method is not limited in any way, and if the number of display devices is three or more, or if the game machine executes complicated image effects including the sub-display device DS2, it is adjusted to 512 bytes or 768 bytes. be done. In addition, the data volume value of the display list DL is adjusted to 256 bytes at the time of normal rendering, and the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes only when executing a special rendering. is also preferred.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. As an adjustment method, after the 32-bit length EODL command, a simple method (A) that fills the missing area with a 32-bit length NOP (No Operation) command, or after filling the missing area with a 32-bit length NOP command , and finally a standard method (B) that describes a 32-bit long EODL command. The data volume value (total amount of data) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to obtain an integral multiple of the minimum data amount Dmin. A non-adjustment method (C) that secures the transfer amount of is also conceivable.

Here, when adopting the standard method (B), first, the command counter CNT is initialized to a specified value (64-1 corresponding to 256 bytes), and every time a significant instruction command is written to the DL buffer area BUF Another possible method is to decrement the command counter CNT as appropriate, write a NOP command until the command counter CNT becomes zero, and write an EODL command at the end after writing a series of significant instruction commands. In the case of this embodiment, the instruction command is limited to a command length N times an integer of 32 bits (N>0). Subtraction processing corresponding to N is performed.

On the other hand, when the simplified method (A) is adopted, when creating the display list DL, it is sufficient to first fill the entire list buffer area (DL buffer BUF) with NOP commands. seems to be excellent. Also, from the viewpoint of simplicity, the no-adjustment method (C) seems to be superior. However, in this embodiment, the standard method (B) is basically adopted, and the actual amount of data from the top of the display list DL to the EODL command, that is, the amount of data up to the EODL command is always transferred to the data transfer circuit 72. is adjusted to be an integral multiple of the minimum data amount Dmin.

This takes into consideration an embodiment that utilizes the preloader 73. If the simple method (A) or non-adjustment method (C) is adopted, the amount of actual data in the display list DL up to the EODL command will be random. This is because the transfer of the rewrite list DL′ rewritten by the preloader 73 to the DRAM 54 and the transfer of the rewrite list DL′ from the DRAM 54 to the drawing circuit 76 are hindered. The ChA control circuit 72a of the data transfer circuit 72 functions when the rewrite list DL' is transferred to the DRAM 54, and the ChB control circuit 72b functions when the rewrite list DL' is transferred to the drawing circuit 76 (FIG. 28). ), in either case, only the rewrite list DL' up to the EODL command is transferred.

The advantages of the standard method (B) for adjusting the data volume values of the display list DL have been described above. Therefore, the use of the simplified method (A) and the no-adjustment method (C) is not prohibited at all.

However, in the following description, the details of the display list DL will be described with reference to FIG. 23 on the premise that the standard method (B) is adopted in principle regardless of whether the preloader 73 is used.

Although not particularly limited, in this embodiment, the display list DL first describes an instruction command string (L11 to L16) for the main display device DS1, and then writes an instruction command string (L17 to L20) for the sub display device DS2. I am trying to describe it. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Incidentally, FIG. 23 actually shows the procedure by which the effect control CPU 63 writes the instruction command in the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 23, at the top of the display list DL, an environment setting instruction command (SETDAVR) is written to set the upper left base point address (X, Y) on the index space IDX for the frame buffer FBa of the display device DS1. Define (L11). As described with reference to FIG. 12(a), in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Usually, by setting the base point address (X, Y)=(0, 0) corresponding to the effective data area for the display circuit 74, the frame buffer FBa is used by the drawing circuit 76 from the head position. .

In FIG. 12(c), the actual drawing area on the lower left side is indicated by L11. 0) means specified starting from position. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies the actual drawing area are not yet determined, and are determined by an instruction command (SETINDEX) L13, which will be described later. The instruction command L11 also designates whether or not to use the Z buffer.

Next, the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set in the virtual drawing space by the instruction command (SETDAVF) of the environment setting system, and the W x H dimension is set. is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn by a drawing instruction command (such as a sprite command) (see FIG. 12(c)). .

By means of this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area in which drawing contents are actually reflected on the display device DS1 and other non-drawing areas. The instruction command L12 (SETDAVF) associates the actual drawing area whose starting position (base point address) is defined by the instruction command L11 with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines a W×H real drawing area starting from the base point address corresponding to the drawing area in the virtual drawing space in the frame buffer FBa (the index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and the actual drawing area are defined to have the same dimensions as the effective data area for the display circuit 74 (FIG. 22(e)).

After the drawing circuit 76 executes the instruction commands L11 and L12, of the drawing contents drawn in the virtual drawing space, only those included in the drawing area are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawn contents of the part protruding from the drawing area and the part described as the work area in FIG. 12C are not directly reflected in the frame buffer. Note that when a work area is secured in the virtual drawing space, a non-drawing area in the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 defines where the content to be drawn should be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, an index space IDX that serves as a "writing area" for drawing content based on the current display list DL is identified (L13). Specifically, the SETINDEX command, which is a command of the texture setting system, requires that (1) the frame buffer FBa is secured in an arbitrary area, and (2) an arbitrary index space IDX _N serving as a "write area" is set. An index number N on the region is specified.

For example, when N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically would have been defined to be index space IDX ₂₅₅ .

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 12(a)), and one of them is designated by switching in a toggle manner (L13). This index number is the index number other than the display area (0)/(1) specified in step ST6 of the main control process. For example, when the display area (0) is specified for the display circuit 74 in the process of step ST6, the display area (1) becomes the “write area” for the drawing circuit 76. FIG.

As described above, after the correspondence relationship between the actual drawing area (W×H logical space) and the drawing area (W×H virtual space) is generally defined by the instruction command L11 and the instruction command L12, The instruction command L13 (SETINDEX) specifically specifying the index space IDX associates the W×H virtual space with the W×H logical space in the specific index space IDX.

In other words, the contents to be virtually drawn in the W×H virtual space based on a series of instruction commands from now on are the internal VDP that defines the correspondence between the virtual space and the internal VRAM 71 real addresses. Based on the conversion table, it becomes the image data of the built-in VRAM 71 (frame buffer).

Subsequently, an instruction command for executing a frame buffer clear process for filling the specified index space IDX with black, for example, is described as a "write area" (L14, L15). This is nothing but erasing processing of the image data written in the frame buffer FBa two operation periods before.

Specifically, the SETFCOLOR command, which is a type of environment setting command, is used to select, for example, black color, and the RECTANGLE command, which is a primitive drawing command, is used to specify that the rectangular area should be filled. The RECTANGLE command specifies the XY coordinates of the upper left end point and the lower right end point of the drawing area set in the virtual drawing space (virtual space corresponding to the frame buffer FBa) (see FIG. 12(c)). .

With the above processing, the rendering preparation processing is completed. Next, instruction commands for rendering appropriate textures such as still images and one frame of moving images in the virtual rendering space are listed. Typically, first, the index space IDX to which the texture is to be developed is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command, which is the instruction command of the texture load system, is written, and the predetermined Textures are described in the display list DL so as to be developed in a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of IP stream moving images. Therefore, for example, the index space IDX in which the background video should be developed is specified as the index space IDX ₀ of the page area (b) by the SETINDEX command of the texture setting system, and then the TXLOAD command of the texture load system is described. do. In the TXLOAD command, it is necessary to specify the start address of the CGROM 55 (texture source address) and the data size after expansion (horizontal×vertical) for the video frame to be loaded this time.

When the TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first captured in the AAC area (a), and then transferred to the page area ( b) in the index space IDX ₀ . Next, this one animation frame will be drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "the index space IDX ₀ of the page area (b) is the texture to be processed subsequently", but the If you do, you can omit this SETINDEX command.

In any case, in a state where "the index space IDX ₀ of the page area (b) is the texture to be processed later" is specified, next, parameters for alpha blend processing are set, and so on. Write an instruction command for an appropriate inter-rendering operation system. Note that the α-blending process relates to a transparent/semi-transparent process between an image already written in the drawing area (frame buffer FBa) and an image to be overwritten from now on. Therefore, like the moving image frame of the background moving image, in the drawing operation of the first frame, it is not necessary to use the instruction command of the inter-drawing arithmetic system.

Next, by using the sprite command, which is a primitive drawing system instruction command, "the texture of the index space IDX ₀ of the page area (b) (one video frame of the background video)" is placed in the appropriate place (rectangular destination area) in the virtual drawing space. Describe the sprite command to draw in. For the sprite command, it is necessary to specify the upper left corner point and the lower right corner point of the destination area of the virtual drawing space.

This destination area is the whole or a part of the drawing area (virtual space defined on the virtual drawing space) previously associated with the actual drawing area (FBa) by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or more. Note that the case where the Destination area is larger than the entire rendering area is, for example, the case where the background moving image is zoomed up.

With the above processing, the drawing of the moving image frame of the background moving image is completed. The display list DL is configured to draw various textures superimposed on the background moving image. As described above, a large number of moving images are required during the variable rendering. The command (NEWPIX) will be described.

For example, regarding the second IP stream video, after allocating an additional index space IDX ₁ in the page area (b) with the NEWPIX command, this index space IDX ₁ is specified (SETINDEX), and the second Instruct the development of one frame of the video (TXLOAD), and place the developed texture in the appropriate place in the drawing area (SPRITE). Normally, the Destination area in this case will be part of the drawing area.

After that, the index space IDX _k is secured one after another by the NEWPIX command, and then, while executing appropriate α-blending processing, if a plurality of IP streams are drawn in the drawing area, the drawing contents in the drawing area are , is sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When a plurality of N IP stream moving images are rendered, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of variable effects is completed, the DELPIX command is used to release the index space IDX that is deemed unnecessary among the many index spaces IDX ₁ to _IDXk secured in the page area (b). The unnecessary index space IDX should be deleted.

When drawing a still image or an I-stream video, use the SETINDEX command to specify that these textures are to be decoded in the AAC area (a), and then execute the TXLOAD command to load the AAC area. The texture acquired in (a) is then developed in the ACC area (a) by the automatically activated GDEC 75 . Then, the developed texture can be drawn in the proper place of the drawing area by the sprite command. The first AAC area (a1) or the second AAC area (a2) is used depending on whether or not the cache hit function is used.

In the explanation so far, each texture is directly drawn in the drawing area of the main display device DS1, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided so as not to overlap the drawing area already reserved for the display device DS1 (FIG. 12(c)), and this drawing area is associated with the work area of the built-in VRAM 71, an intermediate drawing area can be obtained. A suitable drawing area can be constructed to complete an appropriate effect image. Here, the reason why the drawing area for the display device DS1 does not overlap is that the later association setting is prioritized for the overlapping area, and the drawing contents for that area are not reflected in the frame buffer FBa.

As shown in FIG. 12(c), the working area of this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, at the timing of rendering using this working area, an instruction command for associating the rendering area for the rendering image (see FIG. 12(c)) with the working area (actual rendering area of index space IDX ₀ ) is issued first. Note the columns (SETDAVR, SETDAVF, SETINDEX). As shown in FIG. 12(c), the rendering area for the effect image is secured in an area that is not included in the rendering area for the main display device DS1.

After that, it is sufficient to list instruction commands similar to the instruction command string L16 regarding the frame buffer _FBa to complete an appropriate effect image in the index space IDX0. In the case of this embodiment, since the effect image is composed of a still image, an instruction command ( _SETINDEX ) is written so that the decoded data is developed in the first AAC area (a1). A primitive drawing system instruction command (SPRITE) with a suitable place in the drawing area as the Destination is used. It should be noted that such an operation is repeated once or multiple times according to the content of the effect.

Then, after positioning index space IDX ₀ , which completes the effect image, as a texture (SETINDEX), the effect image (texture) of index space IDX ₀ is drawn in the proper place of the drawing area of DS1 for the main display device by the sprite command. do it. In such a case, it is conceivable to decompose the effect image in the index space IDX ₀ into triangular drawing primitives, rotate them to an appropriate angle, and draw them in the drawing area. Note that the texture rotation angle is associated with, for example, the reliability of the advance notice effect.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above. It is the same. That is, the starting XY coordinates of the frame buffer FBb are specified, (L17) is defined (usually X=0, Y=0), and the sub-display device DS2 is displayed on the virtual drawing space shown in FIG. 12(c). A drawing area is defined (L18).

By the way, in this embodiment, after the generation of the image data for the main display device DS1 is completed, the process shifts to the generation processing for the sub display device DS2. You can freely set the drawing area without any problem even if it overlaps with the drawing area of . Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area with the SPRITE command, the setting of the operation parameter (Destination area) of the SPRITE command, etc. It can be standardized to some extent.

After the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the double-buffered display device DS2, an index space that serves as a "write area" for drawing contents based on the current display list DL. Identify the IDX (L19). The index number of this index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0)/(1) specified in step ST6 of the main control process.

After that, instruction command strings L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command strings L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space _IDX0 .

As described above, the instruction commands L11 to L22 forming the display list DL are all limited to commands having an integral multiple of 32 bits in the present embodiment. As described above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) as dummy commands are added. After that, it ends with the EODL command (L24). That is, the embodiment of FIG. 23 adopts the standard method (B) described above.

However, even if the standard method (B) is adopted, it is not essential to fix the total data amount of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, if the total data amount of the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special performance period), the total data amount of the display list DL may be added with the NOP command. , adjusted to N×256 bytes of 512 bytes or more. As described above, when the standard method (B) is adopted, the end of N×256 bytes is terminated with the EODL command.

The configuration of the display list DL has been described in detail above, and the effect control CPU 63 issues the completed display list DL of fixed byte length to the VDP circuit (ST7-ST8). FIG. 24 is a flowchart for explaining the DL issuing process (ST8 in FIG. 22) in which the effect control CPU 63 directly WRITE-accesses the transfer port register TR_PORT of the transfer circuit 72 and issues the display list DL to the drawing circuit 76. FIG. The transfer port register TR_PORT is a kind of data transfer register RGij that defines the operation contents of the data transfer circuit 72 .

In order to implement the DL issuing process, first, it is necessary to set necessary set values in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72 . Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified in a predetermined data transfer register RGij. Although the contents of the setting are not particularly limited, here, it is assumed that the data transfer operation is executed while checking the remaining amount of the FIFO buffer in relation to the CPU IF section 56 via the ChB control circuit 72b and the CPU bus control section 72d. Set (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in a predetermined data transfer register RGij. As described above, in this embodiment, the total data amount of the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. Note that the total amount of data=256×N is also integer N times the minimum data amount Dmin of the data transfer circuit 72 . Normally, the multiple N is 1 or 2, but in the following explanation, it will be explained as N=1.

Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit long register, the effect control CPU 63 executes a register WRITE operation to the transfer port TR_PORT every 32 bits. It will be. Therefore, the value of the management counter CN for managing the number of times of register WRITE is initialized to 64 (ST21). If the non-adjustment method (C) is adopted, at this timing, the data transfer amount that is an integral multiple of the minimum data amount Dmin is determined and the management counter CN is set.

Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the predetermined drawing register RGij that defines the operation of the drawing circuit 76 is set. Based on the value, the drawing operation is started (ST23). As a result, after that, the effect control CPU 63 guarantees quick and smooth Analyze processing by the drawing circuit 76 (display list analyzer) with respect to the instruction command sequence for register WRITE operation to the transfer port TR_PORT.

It should be noted that the fact that the instruction commands listed in the display list DL are limited to those with a command length of 32-bit integral multiples also effectively contributes to the quick and smooth Analyze processing. Timings t1, t2, t3, and t4 in FIG. 30(a) indicate the operation timings of step ST23. Since the display list DL issuing process (ST8) ends quickly, FIGS. 30 and 31 do not show the time span required for the issuing process.

Subsequently, it is confirmed whether or not the setting in step ST22 has functioned (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes more processing time than the register WRITE operation (setting operation) by the effect control CPU 63. because there is no If the operation does not start even after waiting for a predetermined period of time, the serious abnormality flag ABN is set and the DL issuing process ends (ST25). As a result, the WDT circuit 58 then functions and the composite chip 50 is abnormally reset (ST10).

In order to avoid resetting the CPU circuit 51, the effect control CPU 63 may output a predetermined keyword string to the pattern check circuit CHK, and may abnormally reset only the VDP circuit 52 based on the reset signal RST. As mentioned above.

However, since the setting in step ST22 is normally completed quickly, the FIFO buffer (32 bits×130 stages) of the CPU bus control section 72d is confirmed not to be full (ST26). , the instruction command is written to the transfer port TR_PORT line by line from the top line constituting the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processing of steps ST26 to ST29 is repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, the minimum data amount Dmin is defined in the data transfer circuit 72, so the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer. transfer operation.

In any case, in this embodiment, the DL issuance processing (ST28) is quickly completed. In the determination, there may be cases where the FIFO buffer Full state is not resolved even after waiting for a predetermined time. In such a case, after setting initialization data in a predetermined VDP register RGij to initialize the drawing circuit 76 and the data transfer circuit 72, the serious abnormality flag ABN is set and DL issuance processing is started. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and have completed a certain amount of processing. (1) set all internal parameters that may be set by the display list DL to their initial values, (2) set all internal control circuits to their initial states, and (3) (4) initializing the cache state of the AAC area; Similarly, the initialization processing of the data transfer circuit 72 includes initialization processing of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

Although the contents of the drawing register RGij are maintained in the initialization process of step ST27, the contents of a predetermined drawing register may be initialized. Predetermined drawing registers cleared to initial values include (a) an execution control register for setting the start of drawing execution (see ST23 in FIG. 24), (b) a status register indicating the execution status of the drawing circuit 76, and ( c) Contains a status register that identifies the position of the display list currently being processed.

In any case, as a result of setting the serious anomaly flag ABN, the WDT circuit 58 and the effect control CPU 63 then function, and the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a), so the drawing circuit 76 and the data transfer circuit 72 are not necessarily required. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, as a result, recovery from the abnormality can be expected. It is also preferred to do

This point is the same in the processing of step ST25, and after initializing the data transfer circuit 72 and the drawing circuit 76, it is preferable to return to the processing of step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of re-executions of the DL issuance process is counted, and if the number of re-executions exceeds the limit value, the serious abnormality flag ABN is set and the DL issuance process is terminated.

FIG. 24(b) is a confirmation illustration of the normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and an operation based on each instruction command is executed. This operation is executed in parallel with the display list DL issuing process and the data transfer operation of the data transfer circuit 72 (ST26 to ST30).

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read out from the CGROM 55 and acquired in the AAC area (a). Later data is expanded in a predetermined index space. Also, depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76. will be

Next, the case where the display list DL is issued through the DMAC circuit 60 will be described with reference to FIG. Of the first to fourth DMA channels built in the DMAC circuit 60, the third DMA channel is used, although not limited in any way.

In the embodiment of FIG. 25, first, a predetermined data transfer register RGij and a predetermined drawing register RGij are each set to a clear value to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the error process of step ST27 in FIG. 24, the internal circuit of the data transfer circuit 72 including the FIFO buffer is initialized, and the status bit of the data transfer register indicating the progress of data transfer is initialized. Thus, the bit indicating that the entire data transfer is being initialized has a predetermined value.

The same applies to the drawing circuit 76, and (1) setting the internal parameters to the initial values, (2) setting the internal control circuit to the initial state, (3) initializing the GDEC 75, (4) ) includes processing to initialize the cache state of the AAC area. Also, in the initialization processing of the drawing circuit (ST20 in FIG. 25), the predetermined drawing register RGij may be initialized. Incidentally, in the processing of FIG. 24, such initialization processing may be executed first.

In the process of FIG. 25, the normal completion of the initialization process is confirmed by reading a predetermined status register RGij that identifies the operating states of the data transfer circuit 72 and the drawing circuit 76 (ST21). If the initialization is not possible, the serious abnormality flag ABN is set and the process ends (ST22). However, such a situation almost never occurs in practice.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are set in a predetermined data transfer register RGij. Although the contents of the setting are not particularly limited, here, the transfer protocol from the CPUIF section 56 to the ChB control circuit 72b and the transfer protocol to the CPU bus control section 72d are set to follow the settings in the DMAC circuit 60 (ST23). ).

Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 24, the data total amount=256. Note that when the non-adjustment method (C) is adopted, at this timing, the total transfer size that is an integer multiple of the minimum data amount Dmin is determined and set. Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). Timings t1, t2, t3, and t4 in FIG. 30(a) are also operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The processing for starting the operation of the DMAC circuit 60 is as shown in FIG. ST40). The detailed contents of the operation are the same as the process shown in FIG. 26, and are divided into the process of prohibiting DMAC transfer (ST53) and the subsequent standby process (ST54).

Such processing is provided because (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in main control processing and timer interrupt processing (FIG. 22); and (2) in another embodiment in which the process of step ST5 in FIG. 22 is not provided, even if the DMAC circuit 60 that has started issuing the display list DL cannot finish the DL issuing operation within its operation period (δ). Considering what is possible.

In such an exceptional situation, if a new setting value (such as a contradictory setting value) is additionally set to the DMAC circuit 60 in operation, normal DMA operation cannot be ensured at all, and serious trouble may occur. Although it is a concern, providing the process of step ST40 ensures normal operation based on subsequent set values. That is, even in the modified embodiment that partially modifies the present embodiment, it is possible to realize normal DMA operation thereafter regardless of the preceding trouble.

After executing the processing of step ST40 having the above significance, next, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in FIG. 9, the cycle steal transfer mode is selected and one operand transfer is 32-bit transfer×2 times. Also, the Source address is the address of the list buffer area (DL buffer BUF) of the RAM 59 and should be recognized as increasing sequentially, while the Destination address is the transfer port TR_PORT and should be a fixed value. .

Next, the top address of the DL buffer BUF of the RAM 59 is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). ). Also, after setting the total transfer size, that is, the total amount of data of the display list DL to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the explanation so far is based on the premise that the actual bit length of all instruction commands is an integral multiple of 32 bits. However, since the display list DL and the configuration of the instruction command are not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, including the case of adopting the non-adjustment method (C), in the process of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the total transfer size setting process is executed. Here, an appropriate transfer amount MOD is defined based on the settings for one-operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72 .

Specifically, if the one-operand transfer setting is N bytes×M times, the transfer amount MOD is adjusted to an integer multiple of N×M (bytes) and an integer multiple of Dmin (bytes). be done. For example, if N×M=8×4 and Dmin=256, the arbitrary value X (=300) bytes is adjusted to the transfer amount MOD (=512) bytes.

As described above including the general theory, the DMA operation of the DMAC circuit 60 starts the cycle steal transfer operation as shown in FIG. In that case, every 32 bits are transferred to the transfer port TR_PORT. The transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, subsequent to the process of step ST45, the transfer operation of the data transfer circuit 72 is started and the process ends (ST27). After that, the data transfer circuit 72 receives the instruction command string of the display list DL from the DMAC circuit 60 in units of the minimum data amount Dmin, and transfers it to the drawing circuit 76 . The drawing circuit 76 then executes the drawing operation based on the instruction command of the display list DL. Therefore, after the process of step ST27, the effect control CPU 63 can start the process of step ST11 in FIG. , lamp effects and motor effects can be controlled.

FIG. 25(c) illustrates the content of this operation. Prior to DMA transfer, the operation of the drawing circuit is started (ST25), the display list analyzer of the drawing circuit 76 quickly and smoothly executes the Analyze processing, and other operations such as the GDEC 75 and the geometry engine 77 Based on this, one frame of image data is generated for each of the display devices DS1 and DS2 in the frame buffers FBa and FBb.

By the way, the configuration of FIG. 25 in which the DL issuing process ends with the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 32 and 33, when another CPU controls the sound effect, the lamp effect, and the motor effect, normal operation of the DMAC circuit 60 and the data transfer circuit 72 is performed after the process of step ST27. It is preferable to check FIG. 26 is an operation subsequent to step ST27 in FIG. 25, and is a flowchart for explaining normal operation confirmation processing.

First, a predetermined status register is referred to confirm that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). It also confirms that the data transfer circuit 72 has completed the transfer operation (ST51). Normally, the DL issuing process of FIG. 25 is completed through such a route.

On the other hand, even if it waits for a predetermined time, . If the operation of the DMAC circuit 60 is not completed or the transfer operation of the data transfer circuit 72 is not completed, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. to initialize the DL issuing process (ST52). This is an operation based on the fact that the processing for issuing the display list DL has not ended normally. be.

That is, in this case as well, the drawing circuit 76 has already started operating and has completed a certain amount of processing. (2) to set all internal control circuits to the initial state; (3) to initialize the GDEC 75; (4) to initialize the cache state of the AAC area It includes converting

Next, after prohibiting a new DMA transfer operation (ST53), it waits for the completion of the transfer operation of one operand being executed (ST54). As described above, in this embodiment, 32-bit transfer×2 times is used as one operand to avoid abrupt initialization of the DMAC circuit 60 in operation.

After this preparatory work is completed, the DMAC circuit 60 is initialized by setting a clear value in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST52). Then, the serious anomaly flag ABN is set, and the DL issuing process ends. In this case, since recovery from the abnormality can be expected by the processing of steps ST52 and ST55, it is preferable to return to step ST20 in FIG. 25 and re-execute the DL issuing processing without setting the serious abnormality flag ABN. be. However, if the number of re-executions of the DL issuance processing (ST23 to ST27) is counted and the number of re-executions exceeds the limit value, it is necessary to set the serious abnormality flag ABN and finish the DL issuance processing.

Next, main control processing when using the preloader 73 will be described with reference to FIG. The processing of FIG. 27 is similar to the processing of FIG. 22, but first, the contents of the start condition determination (ST5') are different. That is, in the embodiment using the preloader, at the start of each operation cycle, READ access is made to the status information of the drawing circuit 76 and the preloader 73 to confirm that the drawing operation based on the display list DL1 is completed and that the display list DL2 is completed. is completed (ST5').

As shown in the time chart of FIG. 31(a), the preloader 76, for example, based on the display list DL1 issued in the operation period (T1), performs a prefetch operation (preload operation) during the operation period (T1 to T1+δ). should have finished. Also, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operation cycle (T1+δ to T1+2δ) based on the operation start command specified in the operation cycle (T1+δ), for example.

Therefore, in (ST5'), the status information of the VDP register RGij relating to the drawing circuit 76 and the preloader 73 is read-accessed to confirm the normal operation. FIG. 31(a) shows a state in which normal operation is confirmed at the determination timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but the preload operation is not completed at the determination timing of the operation cycle T1+3δ. .

Then, when such an abnormality occurs, the abnormality flag ER is incremented (ER=ER+1), and the process of step ST9 is performed. Therefore, as in the case of the embodiment of FIG. 22, frame drop occurs. That is, the same screen is displayed again because the display area switching process (ST6) is skipped. The operating period (T1+3δ to T1+4δ) shown in FIG. 30(a) indicates the operating state.

If the start condition is not satisfied in step ST5', the drawing circuit 76 is not operated because the drawing operation start instruction (PT10) based on the rewrite list DL' is not executed for the drawing circuit 76. state and no new display list is generated. In FIG. 31(a), timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), more precisely, the timing of step ST26 in FIG.

The case where the judgment in step ST5' is not suitable has been described above, but in the normal case, after the display areas of the frame buffers FBa and FBb are toggled (ST6), the rewrite list DL is sent to the drawing circuit 76. ' is started (PT10). The specific contents are as shown in FIG. The rewrite list DL' is acquired and the drawing operation is executed.

Before explaining the flow chart of FIG. 28 which realizes this operation, the operation of the preloader 73 is confirmed. has been completed, and the prefetched data has already been stored in the preload area secured in the external DRAM 54 . Also, the source address of the texture load command (TXLOAD) described in the display list DL is rewritten to the address of the preload area, and stored in the DL buffer BUF' of the external DRAM 54 as the rewrite list DL'. ing.

In this rewriting process, the total data amount of the display list DL does not change, and the total data amount of the rewriting list DL' is the same as that of the display list DL. Also, the display list DL is created by the standard method (B), and the end of the rewrite list DL' is the EODL command as in the case of the display list DL.

28 based on the above, the effect control CPU 63 first sets a clear value in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, and activates the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). This process has the same content as the process of ST20 in FIG. Next, it is confirmed that the initialization processing has been completed normally (ST21), and if the initialization is not completed even after a predetermined time has passed, the serious abnormality flag ABN is set and the processing ends (ST21). ST22).

Since the initialization of the data transfer circuit 72 and the drawing circuit 76 normally ends normally, the transmission route inside the data transfer circuit 72 is set to a predetermined data transfer register RGij (ST23). Specifically, data is set to be transferred from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the start address of the DL buffer BUF' of the external DRAM 54 storing the rewrite list DL' is set in a predetermined data transfer register RGij (ST24).

Also, for this rewrite list DL', the total transfer size is set in a predetermined data transfer register RGij (ST25). As described above, the total data amount of the rewrite list DL' is the same as the total data amount of the display list DL, specifically, 256 bytes, for example.

Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST26). Timings t1, t2, t3, and t4 in FIG. 30(a) are also operation timings of step ST26. Then, the data transfer circuit 60 is started to operate based on the set value in the predetermined data transfer register RGij, and the process is finished (ST27). After that, the effect control CPU 63 is not particularly concerned with the operation of the data transfer circuit 72 or the drawing circuit, and shifts to the display list generation process (ST7) that will be executed in the next operation cycle.

On the other hand, the drawing circuit 76, which starts operating at the timing of step ST26, executes a drawing operation based on the rewrite list DL' to generate image data based on the rewrite list DL' in the frame buffers FBa and FBb. In this operation, the drawing circuit 76 does not make READ access to the CGROM 55, but only makes READ access to the preload area, so that a series of drawing operations can be completed quickly.

Since the contents of the processing of step PT10 have been described above, returning to FIG. 27, the description will be continued. It is created based on the standard method (B) (ST7). For example, in the operating cycle (T1) shown in FIG. 31(a), the display list DL referred to by the drawing circuit 76 is created in the operating cycle (T1+.delta.), which is the next cycle.

Next, the effect control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). Specific operation contents are as shown in FIG. First, with respect to the embodiment (FIG. 22) that does not use the preloader 73, the effect control CPU 63 issues the display list DL directly to the drawing circuit 76 (FIG. 24) and via the DMAC circuit 60. 29(b) and 29(c) show almost the same operation except that the issue destination is the preloader 73. .

FIG. 29(a) is a flow chart for explaining the operation of FIG. 29(b), which is almost the same as the flow chart of FIG. However, it is set that data will be transferred from the CPUIF section 56 via the ChC control circuit 72c, and that the CPU bus control section 72d will perform the data transfer operation while checking the remaining capacity of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set in a predetermined data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij that defines the operation of the preloader 73 (ST23).

As a result, after that, the preloader 73 executes necessary analysis (Analyze) processing for each instruction command written by the effect control CPU 63 to the transfer port TR_PORT, and detects an instruction command (TXLOAD) for READ access to the CGROM 55. , the texture is preloaded and stored in the preload area of the DRAM 54 . Also, the rewrite list DL' in which the source address of the texture is changed is stored in the DL buffer area BUF' of the DRAM 54. FIG.

Timings t1, t3, and t5 in FIG. 31(a) actually indicate the operation timings of step ST23 in FIG. However, even in this embodiment, if some kind of abnormality occurs during the process of issuing the display list DL, the processes of steps ST25 and ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuing process (ST20 to ST30) is re-executed within a possible range. The initialization processing of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area in which the preload data is newly stored.

Although the case where the preloader 73 is used and the case where the preloader 73 is not used have been described in detail above, the specific operation contents are not particularly limited. FIG. 30(b) shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the drawing circuit 76 with a delay of one operation period δ instead of the generated operation period. In such an embodiment, rendering circuit 76 can use substantially the entire time of one operating period (.delta.), thereby reducing the possibility of frame dropping.

Also, FIG. 31(b) shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the preloader 73 with a delay of one operation cycle instead of the generated operation cycle. In this case, the preloader 73 can use substantially the entire time of one operation period (δ) to perform the preload operation, again reducing the possibility of frame dropping.

In the explanation so far, the composite chip 50 is used, but the performance control CPU 63 and the VDP circuit 52 do not necessarily have to be integrated into one element. Furthermore, in the above embodiment, the entire production control is controlled by a single CPU (production control CPU 63), but the upstream CPU and the downstream production control CPU 63 cooperate with each other to produce A control action may be performed.

32-33 are block diagrams illustrating such an embodiment. As illustrated, in this embodiment, the upstream effect control CPU controls the sound effect, the lamp effect, and the motor effect. On the other hand, the CPU circuit 51 on the downstream side controls only the image effect based on the control command CMD' received from the effect control CPU.

In the case of adopting such a configuration, the CPU circuit 51 does not need to execute the processing of step ST12 in FIG. 22(a) and the processing of FIG. 22(b). A list DL can be generated, and a more complex and advanced image presentation such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more N×256 bytes by adding dummy commands. .

Further, since the operation of the CPU circuit 51 on the downstream side is specialized for image rendering control, it is possible to confirm that the drawing operation is completed after issuing the display list DL. The lower part of FIG. 24 shows an example of operation control in this case. If the drawing operation is not completed even after the limit time is exceeded, the serious abnormality flag ABN is set and the process is terminated (ST32). Since the processing of the CPU circuit 51 on the downstream side is only image effect control, it may simply wait for the completion of the drawing operation in an infinite loop.

When adopting such a configuration, the start condition determination (ST5) of FIG. 22(a) can be repeated for a predetermined time. Even with this configuration, if the delay in completion of the drawing operation is not so long, the only problem that arises is the delay in switching between the display area (0) and the display area (1). That is, like the operation cycle T1+3δ shown in FIG. 34(a), in one operation cycle in which the display operation is repeated twice, only the first half is in a frame drop state, and the latter half is displayed as a normal frame.

This point is the same when using a preloader, and the start condition determination (ST5') of FIG. 27(a) can be repeated for a predetermined time. If there is a slight delay, only the first half of the operation cycle T1+3δ shown in FIG. However, if the completion of the drawing operation is significantly delayed, a complete frame drop will occur as in the operation period T1+3δ in FIG. will start up. This point is the same when the preloader is not used.

Further, when the control operation of the CPU circuit 51 is specialized for image effect control, in an embodiment employing DMA transfer, as shown in the lower part of FIG. and the completion of the operation of the DMAC circuit 60 (ST50'-ST52'). If any of the operations does not end normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processes as those of steps ST53 to ST55 (ST55' to ST57') are executed. be. Also in this case, it is preferable to re-execute the DL issuing process a predetermined number of times.

An embodiment has been described above in which the frame buffers FBa and FBb of the main display device DS1 and the sub display device DS2 construct index spaces of horizontal sizes that completely match the number of horizontal pixels of each display device. FIG. 35(a) shows this relationship for confirmation, and the drawing area (W×H) on the virtual drawing space and the effective data area (actual drawing area W×H) on the index space are , both correspond to the number of horizontal/vertical pixels of the display device.

In such a correspondence relationship, the drawing operation to the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W×H). , the drawing image (W′×H′) exceeding the drawing area (W×H) is shifted in time to render the actual drawing area W×H It is possible to move the contents drawn on the screen vertically/horizontally/diagonally as appropriate.

Also, in order to execute such an effect, for example, as shown in FIG. 35(b), an index space having a horizontal size W larger than the number of horizontal pixels of the display device may be provided. In this case, the drawing area W×H in the virtual drawing space defined by the instruction command L12 (SETDAVF) of the display list DL is larger than the actual drawing area w×h corresponding to the number of horizontal/vertical pixels of the display device. set. In the lower part of FIG. 35(b), the actual drawing area w×h is indicated by a right-sloping line.

The vertical and horizontal dimensions of the actual drawing area w×h are specified as the number of display lines and the number of horizontal pixels of the display device in the process of step SS30 in FIG. 21, the vertical/horizontal display start position is set in a predetermined display register.

On the other hand, the base point address (X, Y) in the index space is set in a predetermined drawing register by the display list instruction command L11. As described above, specifically, the upper left base point address in the index space IDX is defined as (0, 0), for example, by the instruction command L11 (SETDAVR) of the environment setting system. Then, if the upper left end point of the actual drawing area w×h is appropriately moved in the steady process, the drawing contents of the actual drawing area W×H indicated by the right sloping line in the lower part of FIG. will move accordingly.

As described with reference to FIG. 21, the VDP register RGij related to steps SS30 to SS37 is set to write prohibition after initial setting (second prohibition setting SS39). By writing a release value to the VDP register RGij of , this prohibition setting is released.

By the way, in the above-described embodiment, the predetermined system control register RGij and the predetermined VDP register RGij of the initialization system are uniformly set to the write-disabled state by utilizing the first and second types of prohibition setting registers. (See SS38 and SS39 in FIG. 21) to prevent the set values in these registers from being changed by the influence of noise or the like. However, it is also preferable to repeat the setting process at predetermined time intervals for the set values of the important system control registers RGij without setting such write prohibition.

FIG. 36 is a drawing for explaining the processing in such a case. The set values to be set in the initial setting processing (SS1 to SS3) are summarized in a set value table SETTABLE stored in the control memory 53 (PROGMROM). ing. Although descriptions are omitted in steps SS1 to SS3 in FIG. 21, (a) the initial setting process is executed based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE. 21 is substantially the same as the content described below.

In any embodiment, the set value table SETTABLE is composed of a plurality of sets (N sets) each including the register address value of the VDP register RGij and the set value to the register RGij. Although not particularly limited, the register address value is fixed to a 16-bit length, and the set value is fixed to a 32-bit length. ×Nbit) length, and there are N VDP registers RGij.

However, in the embodiment of FIG. 21, the initial value setting table SETTABLE is read-accessed only once and all of the N VDP registers RGij are initialized only once, whereas in the embodiment of FIG. The N VDP registers RGij are divided into N1 VDP registers RGij that are initialized only once, and N2 VDP registers RGij that are repeatedly initialized every 1/30 second after the first initialization. classified. However, even in the embodiment of FIG. 36, the processing of steps SS5 to SS6 is executed only once after the power is turned on.

In the embodiment of FIG. 36, the set values that are repeatedly initialized include (1) set values for DMA transfer operation, (2) set values for VRAM, (3) set values for interrupts, and (4) display (5) setting values for the drawing circuit 76;

(1) The setting value related to the DMA transfer operation is, for example, a setting value that is a precondition for the operating conditions defined in step ST41, and is fixed regardless of the difference in operating conditions in FIGS. This is the default setting that is applied globally. Specifically, (a) a threshold value (for example, 1/2 of the total number of stages) indicating how many FIFO buffers (N stages) built in the DAMC circuit 60 are released before requesting a transfer to the transfer source, ( b) Includes setting values such as whether or not to perform a handshake operation with the transfer destination or transfer source (for example, No).

Also, (2) the set value of the VRAM includes the refresh cycle of the refresh operation. The built-in VRAM 71 operates at this refresh cycle, thereby preventing spontaneous discharge of stored data. Next, (3) set values related to interrupts are values that specify the error type that causes an interrupt request and the output terminal of the interrupt signal (internal terminal of the built-in CPU). If it freezes, an abnormal drawing interrupt will occur to the CPU circuit 51 (interrupt enabled state, see FIG. 22(d)); It contains set values such as what happens (see FIG. 22(c)).

In this embodiment, the composite chip 50 in which the CPU circuit 51 and the VDP circuit 52 are integrated is used. 51 is connected to an external interrupt input terminal.

(4) Setting values for the display circuit include (a) horizontal/vertical start positions of each frame buffer (see SS36), (b) setting values for the horizontal synchronization signal of each display device, and (c) each display device. (d) set values for the scaler; (e) set values for the number of horizontal pixels and the number of display lines of each display device (SS30);

(5) The setting value for the drawing circuit 76 includes the setting value for the freeze time until the abnormal drawing interrupt occurs. This set value is set, for example, as an integral multiple of the cycle of the vertical synchronization signal. As explained in FIG. 22(d), when the drawing circuit 76 does not access the VRAM during the freeze period defined here, the drawing circuit 76 is individually reset (ST16b), and the operation parameters for the drawing circuit 76 are set to It is reset (ST16c).

As described above, in this embodiment, important setting values are repeatedly reset at predetermined time intervals. Therefore, even if the setting values become garbled due to noise or other factors, the abnormality can be detected immediately. be recovered. Also, in this embodiment, unlike the embodiment of FIG. 21, the prohibition setting register RGij of the first type and the second type is not set to the write prohibition state. , can be freely rewritten.

As described above, in the embodiments so far, (1a) the operation freeze state of the drawing circuit 76 after a predetermined freeze time has passed, or (1b) when the drawing circuit 76 detects an irrational instruction command in the display list DL, , the drawing circuit 76 of the VDP circuit 52 generates a drawing abnormal interrupt to the CPU circuit 51 (see FIG. 22(d)). Then, at the time of the abnormal drawing interrupt, after determining the cause of the interrupt (ST16a in FIG. 22(d)), a configuration (ST16c to ST16d) is adopted in which the processing according to the determination result is executed.

However, according to experiments by the present inventors, even under severe operating conditions with a lot of noise, the abnormal drawing interrupt rarely occurs. Therefore, in order to reduce the control load, it is necessary to shift uniformly to infinite loop processing (see FIG. 27(b)) without providing interrupt cause determination processing (ST16a), or to pattern check circuit CHK (see FIG. 27B). 7(b)) is also suitable (see ST17a in FIG. 27(c)).

In this case, the WDT circuit 58 is activated after a predetermined period of time, and the entire composite chip 50 is reset, or only the VDP circuit 52 is immediately reset (FIG. 7(b)). reference). When the VDP circuit 52 is reset based on the reset keyword output process (ST17a), normal completion of the reset operation is confirmed, and after arranging the stack area for storing the return address (ST17b), For example, the process is shifted to step ST4 or ST13.

In addition, in the present embodiment, an abnormality determination process (ST5 in FIGS. 22 and 27) is provided to determine the completion of the operation of the drawing circuit 76 every 1/30 second. A drawing abnormality interrupt process (FIG. 27(d)) may be provided in which nothing is actually executed. As shown in FIG. 27(d), in this configuration, an IRET (Interrupt Return) instruction is immediately executed at the time of an abnormal drawing interrupt to return to the main control processing. become. However, in this embodiment, the number of dropped frames is counted by the abnormality flag ER in the process of step ST5 in FIGS. The configuration of (d) is substantially the same as the configurations of FIGS. 27(b) and 27(c).

Also, in order to further reduce the control load, it is also preferable to set the VDP circuit 52 to the abnormal drawing interrupt disabled state at the time of initialization (see step SS3 in FIG. 21). If the default state at power-on is to disable drawing abnormal interrupts, (a) write a predetermined system control register RGij to set a permission/prohibition value that defines permission/prohibition of abnormal interrupts; Either the prohibition state is set, or (b) the prohibition value is repeatedly written to the system control register RGij at predetermined time intervals.

At first glance, this configuration seems to be superior to the configurations of FIGS. 27(b) and 27(b). However, for all models of this type of gaming machine, (a) drawing error interrupts are uniformly set to a prohibited state, (b) are uniformly set to a permitted state, and then for each model From the viewpoint of generalization of the control program, it is better to select the configuration of FIG. 22(d) or one of the configurations of FIGS. 27(b) to (d). In the former configuration (a), it is necessary (complicated) to change the initial setting routine (see step SS3 in FIG. 21) for each model.

As a further modified embodiment, it is also preferable to utilize an audio circuit SND built into the composite chip 50. FIG. FIG. 37 is a block diagram illustrating such an embodiment. As is clear from comparing FIG. 37 with FIG. 7, this embodiment does not require the audio processor 27 and the audio memory 28, and the data bus (for 8 bits) and address bus (for 2 bits) of the CPU circuit 51 , no external wiring to the audio circuit is required. In addition, since there is no transmission line for the underflow signal UF, the composite chip can be prevented from being erroneously reset abnormally due to noise superimposed on this UF transmission line.

Also, in this embodiment, the audio data to be stored in the audio memory 28 is stored in the CGROM 53 in correspondence with the elimination of the audio memory 28 . FIG. 38(d) shows the storage contents of the CGROM 53. The CGROM 53 contains sound ROM header information, phrase header information HD, a large number of phrase data PH obtained by compressing a group of audio data, and an audio circuit. A number of sound commands SCMD, which define the operation of the SND, are permanently stored.

As shown, the sound ROM header information is stored from the top address SNDst, followed by the phrase header information HD of the data size HDvl is stored from the top address HDst. Phrase data PH of data size PHvl is stored from the leading address PHst, and sound command SCMD of data size SCMDvl is stored from the leading address SCMDst.

Here, the sound ROM header information specifically includes the top address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the top address PHst of the phrase data area PH, and the size of the phrase data area PH. It means the data size PHvl, the start address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. These pieces of information are acquired by the internal circuit of the audio circuit SND when the power is turned on (see step SD4).

Further, the phrase header information HD and phrase data PH are transferred to the external DRAM 54 when the power is turned on, thereby speeding up subsequent READ access (step SD6). Thus, in this embodiment, the audio processor 27 and the audio memory 28 are eliminated to reduce the size and manufacturing cost. overcoming its weaknesses.

Based on the above, the initial setting process at power-on will be described with reference to FIG. 38(a). These processes are executed as part of the process of step SS3 in FIG.

As described with reference to FIG. 7B, when the power is turned on or when the WDT 58 is activated and an abnormal reset occurs, the audio circuit SND is hardware-reset through the reset path 2 (step SD1). Also, when the effect control CPU 63 detects an abnormality in the sound circuit SND, the sound circuit SND is hardware-reset through the reset route 4B or 4C (step SD1). It should be noted that the sound circuit SND may be hardware-reset together with other circuits (72, 73, 74, .

In any of these cases, after confirming that the reset operation has been completed normally (step SD2), the effect control CPU 63 first sets the head address SNDst of the sound data area to the system control of the sound circuit SND. It is set in the register RGij (step SD3). Next, by setting a predetermined value in a predetermined system control register, the sound ROM header information HD is stored in the internal circuit. The sound ROM header information HD consists of the six elements (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl) described above, as shown in FIG. 38(c).

Then, it confirms that the processing up to this point has been performed normally, and if it cannot be terminated normally, the audio circuits are individually reset through the reset route 4B or 4C. Normally, however, normal termination can be confirmed, so the data transfer circuit 72 is used to transfer the phrase header information HD and the phrase data PH to the external DRAM 54 (step SD6). The data transfer circuit 72 is appropriately designated with a transfer destination start address BGN, a transfer source start address HDst, a total transfer data amount HDvl+FDvl, and the like.

Next, the fact that the phrase header information HD and the phrase data PH exist in the external DRAM 54, not in the CGROM 55, is set in a predetermined system control register RGij (step SD7). A data start address BGN (sound RAM start address) is set in a predetermined system control register (step SD8). After that, when the other initial setting processing is completed (step SD9), the voice control operation becomes possible.

As described above, the sound ROM header information, that is, the six pieces of information (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl) are stored in the internal circuit of the audio circuit SND (step SD4). , the effect control CPU 63 can indicate necessary information such as phrase data by a value relative to the head address BGN of the sound RAM. to perform the necessary audio processing. Since voice data such as phrase data is read-accessed from the external DRAM 54 instead of the CGROM 55, even highly complicated voice effects can be realized smoothly.

Although various embodiments have been described in detail above, the present invention is not limited to the pinball game machine or the reel game machine, and the specific contents of the description do not limit the present invention. In particular, regarding the backlight unit BL and the liquid crystal display unit MONI, the circuit configuration and operation timing of the power supply control circuit (FIG. 6) and the corresponding control processing in FIG. It does not limit the invention and can be changed as appropriate.

For example, although the control signals PS1 and PS2 are used in the embodiment, the control signal PS1 is not particularly required when the driver DVL having the BL_EN terminal and the PWM terminal is used as the backlight section BL. Moreover, since the control signals STBY and PWM are used, the control signal PS2 can also be omitted. If the control signals PS1 and PS2 are omitted, the power supply voltages of 12V and 5V will be supplied to the backlight section BL and the liquid crystal display section MONI from the time the power is turned on.

However, in order to meet the specifications of the liquid crystal display unit MONI, which requires transmission of significant image signals quickly (within 20 ms, for example) after the power is turned on, the control signal PS2 is used to delay the power supply start timing of the power supply voltage of 5V. is preferred. FIG. 47 is a time chart for explaining such an embodiment. While the control signal PS1 is omitted, the output from the display circuit 74 is synchronized with the timing T4 at which the LVDS circuit 80 starts outputting, and the liquid crystal display section It shows an embodiment in which the power supply voltage of 5V is started to the MONI. Also in this case, for example, if the timer interrupt is used to turn on the backlight unit BL with a delay of 300 mS from the timing T4, an unnatural image is displayed without clearing the frame buffers FBa and FBb to zero. there is no risk of

Further, in the embodiments so far, a considerable waiting time (>1000+300mS) is provided until the backlight is turned on. It is also preferable to advance the output start timing as much as possible. For example, as shown in FIG. 48, following the operation of step SP45 for setting the Dual Link of the LVDS circuit and other settings, step SS4 (for starting the operation of the display circuit 74 and the LVDS circuit 80 (LVDS1/LVDS2) SS4a+SS4b) is also preferably performed. As described above, the execution order of steps SS4a and SS4b is arbitrary.

In this case, since the process of step SS4 is executed without executing the process of step SS3, meaningless image signals are transmitted. problem does not arise. That is, in a state where the backlight unit BL is turned off, as long as the processing of steps SP41 to SP44 is preceded, each processing related to the display operation executed in steps SP4 to SP10 can be switched in an appropriate order.

In particular, the dual link setting and other setting processing (SP41) for the LVDS circuit 80 (LVDS1/LVDS2) may be collectively performed at the timing of step SP54 in FIG. 21 instead of the timing of step SP4 in FIG. . The setting processing performed collectively includes setting that the data to be output from the LVDS1 circuit/LVDS2 circuit is the output (ODD/EVEN) of the display circuit 74 for the LVDS circuit 80 of the dual link configuration. Further, from the execution timing of this step SP54, a predetermined display register RGij (DSPACTRL) and a predetermined system control register RGij (SYSDSPLVDS1MD, SYSDSPLVDS2MD) are set to start the operation of the display circuit 74 and the LVDS circuit 80. can be

At the register setting timing of step SP54, the system control register RGij (SYSDSPLVDSLNK, SYSDSPLVDS1CFG1, SYSDSPLVDS2CFG1) is set to indicate that the data of the display circuit 74 is to be output by LVDS (see SP4). It is also preferably arranged to initiate operation of the display circuit 74 and the LVDS circuit 80 . It should be noted that the output operation (SS4) of the LVDS circuit 80 may be started immediately before timing T4 in FIG. 47 after executing the processing of steps SP42 to SP44 and step SP46.

However, as described above, the processing of steps SP46 to SP47 relating to the external DRAM (DDR) 54 must always precede the processing of step SP8.

As for the power-on reset operation, the power-on reset operation shown in FIG. 16 was started based on the information of the vector table VECT secured after the address 0x00000000 of the control memory 53, but the HBTSL terminal is set to H level. Along with this, it is also preferable to place the vector table VECT in the top area of the CGROM 55 . FIGS. 39(a) and 39(b) illustrate address maps in such a case, and the address space CS0 of the effect control CPU 63 is secured in a part of the CGROM 55 (head area).

The main body of the CGROM 55 is not accessed by the effect control CPU 63 (inaccessible), and is exclusively accessed by the VDP circuit 52, so it is not located in the address space CSi. As described above, the main body of the CGROM 55 can also be composed of a plurality of memory devices. In such a case, the processing of step SP20 in FIG. By doing so, optimum READ access that matches the characteristics of the memory device becomes possible.

In any case, when the HBTSL terminal is set to H level, the memory type of the CGROM 55 and the bus width (64/32/16 bits) correspond to the 2-bit long HBTBWD terminal, It must be specified in advance based on the fixed input value to the HBTRSL terminal of 4-bit length.

In this embodiment, following the vector table VECT, bus parameters for optimizing READ access from the CGROM 55 must be stored in the head area of the CGROM 55 . Although it is not essential, it is also preferable to store obfuscation parameters for deciphering the performance control program when it is obfuscated in order to make illegal analysis difficult.

When such a configuration is employed, the following operations 1 to 4 are automatically executed without program processing during the reset assert period after the power supply is reset. First, the bus width of the address space CS0 is identified based on the input value to the HBTRSL terminal, and the memory type is automatically identified based on the input value to the BTBWD terminal, and set in a predetermined VDP register RGij. (operation 1). The types of memory in this case are broadly classified into memory elements adopting a parallel I/F (Interface) type and memory elements adopting a sequential I/F type.

Next, the obfuscation parameters stored in the CGROM 55 are loaded, and the information necessary for canceling the obfuscation is automatically set in the internal circuit (operation 2). Also, the bus parameters stored in the CGROM 55 are automatically acquired in the VDP register RGij (operation 3). This operation 3 is an operation corresponding to the program processing of step SP63 in FIG. 19, and is automatically executed by the internal circuit.

Finally, the operation corresponding to the program processing of step SP64 in FIG. 19 is automatically executed by the internal circuit to implement the bus parameters set in operations 1 to 3 (operation 4). Then, at the timing when the bus parameter setting is executed, the values of the program counter PC and the stack pointer SP are automatically set based on the information in the vector table, and the execution of the boot program (initial setting program) is started. be.

According to the configuration shown in FIG. 39(a), the program processing of step SP1 of FIG. 16(a) is not necessary, and the operations 1 to 4 are automatically executed, so the program processing load is greatly reduced. . Also in this case, programs and data following the vector handler Vopt are transferred to appropriate RAM areas based on the operation of the initial setting program Pinit.

The programs and data after the vector handler Vopt do not necessarily have to be stored in the top area of the CGROM 55, and may be stored in the control memory 53, for example (FIG. 39(b)). Also, the programs and data following the vector handler Vopt do not necessarily need to be transferred to the RAM area, and if they are not transferred, the memory section initialization processing (SP8 in FIG. 16) in the initialization setting program becomes unnecessary.

Also, it is not necessary to match the V blank timing with the transmission end timing of significant image data. That is, there is no need to terminate the transmission of the image data at the timing of the lower left end point (o mark) of the display area shown in FIG. 15(f). In short, it suffices if the specification of the standby time WTh/WRv and the specification of the horizontal/vertical synchronization signal HS/Vs required by the display device are satisfied.

FIG. 41(a) is a diagram for explaining such an embodiment, and shows, for example, the operation of the display circuit 74A. Also in this embodiment, the frequency F _dot of the dot clock DCK is defined as 108 MHz in accordance with the specifications of the main display device DS1. Also, in order to match the frame rate FR to 1/60 seconds, it is necessary to set THc×TVl/F _dot =1/60. The number THc is 1662 clocks, and the number of vertical synchronization lines TVl is 1083 lines.

Further, in the illustrated embodiment, the horizontal synchronizing signal HS and the vertical synchronizing signal VS are output according to the specifications of the display device so as to be compatible with general display devices. In the illustrated example, the pulse width of the horizontal synchronizing signal HS is 100 clocks, the horizontal front porch FPh is designed to be 110 (=10+100) clocks, and the horizontal back porch BPh is designed to be 172 clocks. The pulse width of the vertical synchronizing signal VS is designed to be 10 lines, the vertical front porch FPv is designed to be 20 (=10+10) lines, and the vertical back porch BPv is designed to be 291 lines.

However, in the embodiment shown in FIGS. 41(a) and 41(b), the vertical standby time WTv is 49 lines and the horizontal standby time WTh is 372 clocks in order to finish the output operation before the V blank start timing indicated by the circle. . Therefore, according to this embodiment, the V-blank start timing comes after the time (154 μs) for 10 lines has elapsed after the image update processing for one frame is completed, and the image update processing can be reliably performed under any operating conditions. (See FIG. 41(b)).

Such an operation functions particularly well in display circuits that operate incidentally in synchronization with other display circuits, such as the display circuits 74B and 74C that accompany the operation of the display circuit 74A. FIGS. 41(c) to 41(e) are drawings for explaining this point, and illustrate the case where the V blank period T2 in the display circuit 74B is longer than the V blank period T1 in the display circuit 74A (T1 <T2).

In such a case, if the V blank period T1 in the display circuit 74A is caused to accompany the operation of the display circuit 74A, the V blank will start before the output of the image data in the display circuit 74B is completed. A defect or an unnatural display operation may occur (FIG. 41(d)). On the other hand, if the display circuit 74B is operated independently, it will not be possible to match the operation timing of the drawing circuit synchronized with the operation of the display circuit 74A.

Therefore, when the V blank period T2 of the display circuit 74B associated with the operation of the display circuit 74A is longer than the V blank period T1 of the display circuit 74A, the display device In B, the standby time (vertical blank period) should be set short so that there is a sufficient spare time after the image data is output. In this case, unless the standby time is set extremely short, a normal liquid crystal display device can perform the display operation without any problem.

For example, even if the V blank period T3 of the display circuit 74B associated with the operation of the display circuit 74A is shorter than the V blank period T1 of the display circuit 74A, an extra standby period occurs after the V blank period T3. As long as the waiting time as a whole does not become extremely long, the display operation is realized without any problem.

Although the embodiments of the present invention have been described in detail above, the specific description does not limit the present invention. For example, in the embodiments, dual-link transmission lines (a pair of LVDS transmission lines) have been exclusively described, but in order to simplify the equipment configuration, it is also preferable to adopt a single-link transmission line (single LVDS transmission line). is.

In the case of a single link transmission line, if the frequency of the dot clock DCK is 108 MHz, the frequency of the LVDS clock CLK is also 108 MHz. Also in this case, it is preferable that the dot clock DCK and the LVDS clock CLK be generated in the same generation process using the oscillator OSC2 as a common supply source.

In addition, unlike the above-described embodiment, the system clock of the VDP circuit 52 and the CPU operating clock of the CPU circuit 51 are supplied from a single oscillator OSC2 in common to simplify the circuit configuration. is suitable. If the multiplication ratio of the PLL circuit is commonly set based on the setting value of the common setting terminal (3-bit PLLMD terminal), the frequency setting process becomes unnecessary, which is more effective.

In this case, it is preferable to use the system clock with the highest frequency allowed by the internal circuit of the VDP circuit 52 and set the same frequency as the CPU operation clock, although this is somewhat contrary to the demand for speeding up the CPU operation clock. .

For example, if the oscillation frequency of the oscillator OSC2 is 40 MHz, by setting the setting terminal (3-bit PLLMD terminal) to 5, the system clock and CPU operating clock are commonly set to 200 MHz (= 40 MHz x 5). can. This configuration eliminates the need for the oscillator OSC1, simplifies the circuit configuration, and eliminates the somewhat complicated setting process for the VDP register. There is also an advantage that the VDP circuit 52 and the CPU circuit 51 have the same operating cycle.

Finally, let's talk about video production. As described above, in this embodiment, most of the variable effects are realized using moving images instead of still images. Also, during the fluctuating effect, a plurality of moving images are running in parallel, except for special cases such as blackout notices.

<Initial processing>
In order to execute moving image effect, in the present embodiment, in the initial processing after power-on, an AAC area and a page area are secured (SS1 in FIG. 21), and one or more pages specified by an index number are stored in the page area. Index space is reserved.

Specifically, one or a plurality of page areas each having an integer N times the basic size of 4096 bits×128 lines of unit space are secured, and a unique index number is assigned to each of them (SS2 in FIG. 21). In this embodiment, one pixel is represented by 32 bits (ARGB8888), so the unit space of the page area is 128 pixels×128 lines.

In addition, as explained above, the index space within the page area can be released or added as required. Also good.

By the way, in this embodiment, the AAC area secured in the initial processing is used as a decoding area for still images and I-stream moving images. In this case, if the load command TXLOAD, which specifies the memory read of the image material (texture), specifies the size after decompressing the texture (one frame of video or still image), the start address of the decoding area and the horizontal size are automatically set. Reserved in the AAC area.

<Playback of IP stream video during normal operation>
After the above initial processing, one or a plurality of moving image effects are executed at appropriate timings. Here, the following commands CM1 to CM5 are required as instruction commands to the drawing circuit in the display list DL that instructs the reproduction of the IP stream moving image.

FIG. 43(a) illustrates the main part of the display list DL, and is the same as the instruction command string L16 of FIG. An embodiment using a page area as a decoding area will be described below, but an arbitrary area can also be used. In this case, the page area can be read as an arbitrary area. However, the index space of the page area has an arbitrary horizontal size×vertical size of 2048 lines, which is wasteful in the vertical direction.

(1) Texture command SETINDEX (CM1)
First, the texture command SETINDEX (CM1) specifies whether to use an arbitrary area or a page area as the decoding area. do. More specifically, the texture command SETINDEX to which the necessary operation parameters are added is described in the display list DL, the "page area" and "texture" are selected, and the index number i specifying the index space to be used is set. stipulate.

When using the arbitrary area, select "arbitrary area" and "texture" with the texture command SETINDEX, and specify the index number i for specifying the index space of the arbitrary area.

(2) Load command TXLOAD (CM2)
Next, a load command TXLOAD (CM2) for designating memory read of material is used to designate loading of necessary textures (unit frames constituting moving images) from CGROM. Specifically, the load command TXLOAD to which the necessary operation parameters are added is described in the display list DL. Then, the VDP circuit 52 loads the designated texture from a predetermined area of the CGROM, decodes the texture, and expands the decoded data in the index space i of the page area.

The operation parameters added to the load command TXLOAD include (1) whether to decode textures (unit frames that make up a moving image) as the first frame or as continuation frames, and (2) after texture expansion. (3) vertical size after texture development; (4) texture source address (starting address of CGROM where texture is stored);

(3) Basic information set command SETTXATR (CM3)
Next, describe the basic information set command SETTXATR (CM3) with necessary operation parameters in the display list DL, and set the color mode of the texture to ARGB8888 mode (1 pixel is 32 bits long). Set basic information for

Necessary information is also set for blend processing between pixels. Blending processing means mixing RGB values that define the color of each pixel and α values that define the degree of transparency, etc., with pixels that have already been drawn in a frame buffer or the like. In this embodiment, since a plurality of moving images are always operated in parallel during the variable presentation, an α-blending operation regarding transparency and the like is required.

(4) Inter-pixel blend calculation system command (CM4)
Therefore, the display list DL describes a command (CM4) of the inter-pixel blend calculation system to which necessary operation parameters are added, and the α blend calculation formula and others are specified by the necessary operation parameters.

(5) Sprite command SPRITE (CM5)
Next, a sprite command SPRITE (CM5) added with necessary operation parameters is sent to the display list DL in order to paste the texture developed in the index space i to the appropriate place in the virtual drawing space (see FIG. 12(c)). Describe. This sprite command SPRITE designates the upper left vertex (X0, Y0) and the lower right vertex (X1, Y1) of the virtual drawing space specifying the paste destination of the texture.

Also, regarding the texture to be pasted on the rectangular area specified by the upper left vertex (X0, Y0) and lower right vertex (X1, Y1), the UV values in the texture UV coordinate space, that is, (U0, V0) and ( U1, V1) are specified. Note that the texture to be pasted has already been specified by the texture command SETINDEX, so there is no need to specify the texture itself again.

Also, instead of the sprite command SPRITE, a triangular polygon command TRIANGLE can be used to draw the texture with an inclination. However, regarding the triangular polygon command TRIANGLE, the tilt/rotation notice effect will be described later.

<Playback of I-stream video during normal operation>
In the case of an I-stream moving image, it is sufficient to load the texture to be decoded (the unit frame constituting the I-stream moving image) into the AAC area, as in the case of still image reproduction. That is, the texture command SETINDEX (CM1) is unnecessary, and the configuration of the display list DL is as follows. Commands CM3 and CM4 are also normally required, but their description is omitted to avoid redundant explanation.

(1) Load command TXLOAD (CM2)
A load command TXLOAD to which an operation parameter is added is written in the display list DL to specify that a texture (a unit frame constituting an I-stream moving image) is to be loaded from a predetermined area of the CGROM to the AAC area. Then, the VDP circuit 52 automatically decodes the loaded texture and develops the decoded data in the automatically secured space of the AAC area. (2) Sprite command SPRITE (CM5)

Subsequently, a sprite command SPRITE to which necessary operation parameters are added is described in the display list DL in order to paste the texture developed in the automatically secured space of the AAC area to the proper place in the virtual drawing space. As described above, the sprite command SPRITE specifies the upper left vertex and the lower right vertex of the virtual drawing space that specify the paste destination of the texture.

Instead of the sprite command SPRITE, the triangular polygon command TRIANGLE can be used to draw the texture in an inclined posture.

Also, if you want to scale the texture, you can write the complement command SETTXSMPLNG before the sprite command SPRITE. If the texture sampling method (point sampling/bilinear filtering) is specified by the complement command SETTXSMPLNG, the complement processing when enlarging/reducing the texture is specified.

Enlargement processing and reduction processing are automatically performed based on the upper left vertex and lower right vertex of the virtual drawing space specified by the sprite command SPRITE. That is, it is automatically enlarged or reduced based on the size of the rectangular space defined by the upper left vertex and lower right vertex. Then, if point sampling is selected, the enlargement process is simply performed tessellated and the reduction process is performed by pixel decimation. On the other hand, if bilinear filtering is selected, the information of the unspecified pixel is the weighted average of the information of the specified surrounding pixels.

<Minor fluctuation effects and enlargement/reduction effects of pending images>
By the way, in the gaming machine of this embodiment, when the number of winning balls into the symbol start port exceeds four, the variable effect is put on hold, and a hold image (still image sprite, I stream or IP stream video) indicating the number of holds is displayed. displayed on the display device.

In this case, it is preferable from the standpoint of presentation that the holding image is subtly changed vertically and horizontally, rotated, or enlarged/reduced so as to suggest the result of the lottery as to whether or not the game is a big hit. By adopting such a configuration, by preparing only one still image or moving image, it becomes possible to produce various effects, and the amount of CG data can be suppressed.

Rotation of a pending image (still image sprite or streamed movie) is performed by the triangular polygon command TRIANGLE. On the other hand, minute fluctuations and enlargement/reduction effects are realized by specifying the pasting position and pasting area of reserved images (still image sprites and streamed moving images) with the sprite command SPRITE. Then, in the display list for enlargement/reduction, it is necessary to describe the complement command SETTXSMPLNG prior to the sprite command SPRITE.

<Dialogue notice>
The dialogue forewarning effect means a forewarning effect in which, after starting the display of the dialogue characters, the voice effect of the dialogue sound is started after a predetermined time delay. By deliberately delaying the voice effect, the impact of the preceding character display can be enhanced.

In this dialogue animation effect, a group of dialogue characters are displayed in order one character at a time or one unit at a time. In some cases, the character image is displayed prior to the start of display of the group of serif characters. Moreover, it is also preferable to start outputting the dialogue sound after providing a silent period of a predetermined time after starting the display of the dialogue characters.

Also, the character image may be displayed after the dialogue characters are displayed. In this case, after the display of the dialogue characters is started, the speech production of the dialogue sound is started with a predetermined delay, and then the character image is displayed. It becomes a flow of In this case, it is preferable that the preceding voice effect corresponding to the serif characters should correspond to the character image to be displayed thereafter. Also, the character image may be displayed after providing a silent period of a predetermined time after the execution of the voice effect.

When the dialog preview effect is executed with the IP stream moving image, at least the following commands are described in the display list DL issued prior to the audio effect.

First, a texture command SETINDEX (CM1) is used to set the loading destination of a texture (for example, frames constituting an IP stream moving image) to, for example, a page area.

Next, with the TXLOAD command (CM2), textures (unit frames that make up a moving image) are loaded from CGROM into the page area, necessary information related to alpha blending operation is set (CM3, CM4), and finally, the page area Paste the loaded texture to a predetermined rectangular area in the virtual drawing space with the sprite command SPRITE (CM5). Here, it is preferable to change the moving image playback position by appropriately moving the rectangular area of the pasting destination.

It should be noted that when the speech preview effect is executed with the IP stream moving image, the load command TXLOAD, the complement command SETTXSMPLNG, and the sprite command SPRITE are used. If there is no enlargement/reduction processing, the complementary command SETTXSMPLNG is omitted.

<Notice of blackout>
The darkening notice means an effect in which the entire display screen suddenly changes from the previous display mode during a series of variable effects, and a darkening image appears in which the entire screen or almost the entire screen becomes completely dark. In this advance notice effect, after the preceding moving picture effect is finished, a display list DL for displaying a darkened image for a predetermined time is issued, and then the following advanced moving picture effect is started as a advance notice of the preceding moving picture. A first mode and a second mode in which a darkening image appears as a part of the moving image at the start of the development moving image effect without using the display list DL for displaying the darkening image.

Also, it may be configured to execute a predetermined effect suggesting the degree of expectation for winning during the display of the darkened image. Furthermore, the darkened image is not limited to one in which almost the entire display screen is completely dark, and may be a visibility-reduced image that reduces the visibility of the display screen up to that point. Specifically, it is a black image having transparency.

FIG. 43(b) illustrates the configuration of the display list DL for realizing the darkening image of the first mode. First, the end point address in the index space is specified for the frame buffer FBa secured in an arbitrary area (L11). A drawing area of the display device DS1 is defined as a virtual drawing space (L12). Specifically, the coordinates of the upper left base point and the lower right base point of the virtual drawing space are set in predetermined registers.

Next, the index number of the frame buffer FBa to be used in the current cycle is toggled and specified (L13). Also, the SETFCOLOR command is used to set black (L14), and the rectangle drawing command (RECTANGLE) is used to specify that the entire drawing area of the display device DS1 should be painted in black (L15).

This is exactly the same as the instruction commands from L11 to L15 shown in FIG. 23, and normally the commands in FIG. After describing the NOP command, describe the EODL command, and adjust the total amount of data including the EODL command to an integer multiple of 4 x 64 bytes.

It is also preferable to superimpose one or a plurality of motion picture effects on the darkened image. In this case, the instruction commands CM1 to CM5 described in FIG. 43(a) are additionally described.

Note that, in the case of the black change notice of the second mode, the moving image frames that realize the preceding moving image effect and the following extended moving image effect are indicated by the instruction commands CM1 to CM5 described in FIG. 43(a). identified by

<Zoom Up/Down Notice>
The zoom advance notice means an effect in which a suitable character moves appropriately on the display screen while being zoomed up or down (see FIG. 44(a)). Such a zoom notice can be realized with a still image of a character, but in this embodiment, since a character with different facial expressions and movement of the whole body is used, a moving image effect is used.

In FIG. 44(a), the characters appearing in the zoom preview are represented by "A", which looks like a still image, for the sake of convenience. A person/animal character is drawn.

Continuing the description based on the above, for example, a 3-second moving image at 30 fps (frames per second) has 30×3=90 moving image frames FR1 to FR2n in which the zoom preview character is zoomed up and then zoomed down. -1.

Since the display list DL that draws each of the 90 moving picture frames FRi is configured as shown in FIG. 23 and FIG. It can be pasted at the appropriate place in the virtual drawing space by the command sprite. Therefore, it is possible to move the zoom preview character on the display screen simply by appropriately moving the designation of the pasting position. Since the zoom up/down operation is realized as a moving image, enlargement/reduction control is unnecessary in the display list.

On the other hand, when the zoom preview character is realized with a single still image, the sprite command SPRITE is used to appropriately enlarge or reduce the rectangular space defined by the upper left vertex and lower right vertex of the virtual drawing space.

<Tilt/rotation notice>
The tilt/rotation advance notice means, for example, an effect of appropriately tilting or rotating the original images FR1 to FR2n−1 in an upright state as shown in FIG. 44(a). In FIG. 44(b), for example, N moving image frames FR1 to FRn to be zoomed in are sequentially rotated clockwise.

In order to realize such a tilt/rotation notice, a rectangular image (texture that constitutes a still image or video frame FRi) is divided into triangular polygons, and each triangular polygon is divided by the triangular polygon command TRIANGLE (CM5). It needs to be pasted in place in the virtual drawing space, either upright or tilted.

In the following description, for the sake of convenience, a rectangular image (still image or moving image frame FRi) is not scaled up or down. . In this case, more diverse presentations are possible without increasing the amount of CG data.

Now, FIG. 45(c) shows a state in which a rectangular image (still image or moving image frame FRi) composed of horizontal W×vertical H pixels having four vertices is divided into first polygons and second polygons. It is In this embodiment, execution of a single triangular polygon command TRIANGLE draws four vertices collectively in an upright or tilted state.

However, in order to realize such an operation, the operation parameters to be added to the triangular polygon command TRIANGLE include the number of polygon vertices (information 1) to be drawn with one triangular polygon command, whether only the shape or texture is included. setting (information 2), polygon rendering method for triangular polygons (information 3), XY coordinates of each vertex on the virtual rendering space (information 4), UV values in the UV coordinate space of the texture corresponding to information 4 (information 5), is included.

In this embodiment, one triangular polygon command draws four vertices of a rectangular shape and pastes a texture (movie frame) on them. Information 2, information 4, which is the XY coordinate values for the four vertices, and information 5, which is the UV values, are defined.

The drawing method includes (1) triangle fan drawing for setting common vertices for all triangular polygons, and (2) final drawing edge, followed by drawing a triangle surrounded by the specified vertices. Triangle strip drawing and (3) triangle list drawing, in which triangular polygons are drawn independently, can be selected.

As shown in FIG. 45(c), in the triangle strip drawing method, vertex 0→vertex 1→vertex 3 are drawn in order, and then vertex 3→vertex 1→vertex 2 are drawn in order. On the other hand, in the triangle fan drawing method, vertex 1 of the common vertex is selected and drawn in order of vertex 1→vertex 3→vertex 0, followed by drawing in order of vertex 1→vertex 2→vertex 3. .

However, since the rectangular image in question here is not a stereoscopic 3D image but a two-dimensional 2D image, culling processing for erasing unnecessary portions does not matter. Although there is not much difference, in this embodiment, triangle strip drawing is selected. Although the term "rectangular image" is used in this specification, it goes without saying that the image is rectangular including the transparent portion, and the image outline is not necessarily rectangular.

Based on the above, the operation of the effect control CPU 63 for calculating the operation parameters of the triangular polygon command TRIANGLE will be described with reference to FIG. 45(a). First, four vertices are specified when the center of a rectangular image composed of horizontal W×vertical H pixels is placed at the origin of the virtual drawing space (ST61).

As shown in FIG. 12(c), in the virtual drawing space, the X coordinate is positive in the right direction from the origin, and the Y coordinate is positive in the downward direction from the origin. , vertex 0 (-W/2, -H/2), vertex 1 (W/2, -H/2), vertex 2 (W/2, H/2), vertex 3 (-W/2 , H/2).

Next, by matrix calculation using the rotation matrix of FIG. 45(b), the four vertices after the rectangular image at the origin position is rotated clockwise by the rotation angle θ are calculated (ST62). Note that the clockwise direction in the rotation matrix is the counterclockwise direction in the virtual rendering space, so the rotation angle is actually -θ. This rotation angle is always the rotation angle from the upright texture regardless of the progress of the moving image. That is, even if the texture is rotated at a constant speed at the rotation angle θ1, the rotation angle is not the constant value θ1, but, for example, θ1→2*θ1→3*θ1→4*θ1→5*θ1 . must be incremented sequentially.

Next, the four vertices (X, Y) calculated in step ST62 are moved to arbitrary destinations (ST63). Specifically, if the coordinates of the destination of the center point of the rectangular image are (X0, Y0), the calculations of X=X+X0 and Y=Y+Y0 are executed for each of the four vertices to obtain the four vertices after rotation. Determine the coordinates of the vertex.

Finally, the operation parameter (4) of the triangular polygon command TRIANGLE is added, and correspondingly, the operation parameter (5 ) is added. The same is true for information (1) to (4).

Note that the motion parameter (4), which is the XY coordinates of each vertex in the virtual rendering space, changes appropriately according to the progress of the moving image, and the display content of the rectangular image (texture) also changes. The motion parameter (4) is always the same, since the vertical and horizontal dimensions of the upright texture do not change.

In the present embodiment, the above calculations are executed each time the tilt/rotation notice effect display is issued. This point is rather complicated for the effect control CPU 63 , and it is conceivable to designate only the rotation angle and arrangement position of the texture to the VDP circuit 52 .

However, if such a configuration is adopted, the VDP circuit 52 needs to perform a rotation matrix calculation, increasing the calculation load. Therefore, in order to reduce the computational load of the VDP circuit 52, which requires other complicated arithmetic operations, the effect control CPU 63 calculates the coordinate position in this embodiment.

However, in order for the effect control CPU 63 to perform the matrix calculation, it is not only necessary to arrange trigonometric function calculation routines (library for trigonometric functions) in the memory 53, but also a certain amount of processing time is required. It is preferable to provide a device for speeding up the processing.

FIG. 45(d) shows an embodiment in which the computational load is reduced. The distance (radius r) from the center point of the rectangular image to each vertex and the reference angle α ( 45(e)) and shows an embodiment that performs the necessary calculations based on.

First, the radius r and the reference angle α of the four vertices of the texture when the center of a rectangular image composed of horizontal W×vertical H pixels is arranged at the origin of the virtual drawing space are specified (ST71).

Next, the coordinate values of the four vertices when rotated by the rotation angle θ in the counterclockwise direction are calculated based on the conversion formula shown in FIG. 45(f) (ST72). Incidentally, the calculation process of the conversion formula of FIG. 45(f) is shown in FIG.

Next, if the destination coordinate values of the four vertices (X, Y) calculated in the process of step ST72 are (X0, Y0), the operations of X=X+X0 and Y=Y+Y0 are executed for each of the four vertices. Then, the coordinates of the four vertices after rotation are determined (ST73).

Finally, the operation parameters (1) to (5) are added to complete the triangular polygon command TRIANGLE, which is added to the display list DL (ST74).

Incidentally, FIGS. 45 and 46 exemplify vertically long rectangular images (textures) in an upright state, but if the textures are formed in a square shape, using the root symbol SQR, H=W=r*SQR ( 2), which simplifies the conversion formula of FIG. 45(f). Also, since there is a relationship of Cos(θ)=Sin(90+θ), the conversion formula of FIG. 45(f) can be expressed only by the radius r, the rotation angle θ, and the Sin function value.

Therefore, it is preferable to prepare a SIN table Angle Table (see FIG. 46(c)) that stores the respective Sin function values for the rotation angles -180 degrees to 0 degrees to 180 degrees. , the trigonometric function calculation routines need not be stored in the memory 53, and the processing speed of the trigonometric function calculation can be increased.

Although the present invention is not limited to specific descriptions, it is preferable that a display defining the operation of the display circuit is performed prior to the data generation processing (SS4a) and the data output processing (SS4b). The frequency of the clock (F _dot ) should be specified. It is also preferable that the setting process for the LVDS circuit is executed prior to the data output process (SS4b). Also, the LVDS signal is preferably transmitted to the display circuit via a single LVDS transmission line or a pair of LVDS transmission lines.

In any configuration, the display device includes a display drive circuit (MONI) for driving a group of display elements forming the display screen, and a lighting circuit (BL) for illuminating the display screen based on the LVDS signal. , and the data generation process (SS4a) and the data output process (SS4b) are preferably executed before the lighting circuit (BL) starts the lighting operation. Here, it is preferable that the image control means controls the operation of the illumination circuit (BL) with a plurality of control signals.

Prior to starting the illumination operation, the image control means defines the horizontal period (TH) required for the display drive circuit (MONI) to draw one line of display elements, and defines the operation of the display circuit. It is preferably defined based on the number of horizontal cycles (THc) of the display clock. Preferably, the horizontal period (TH) is divided into a timing at which image data is transmitted and a timing at which image data is not transmitted. A predetermined number of lines (TVl) relating to the operation of the display driving circuit (MONI) is defined, and the number of lines (TVl) is equal to the horizontal period (TH) and the display driving circuit (MONI) for one frame. and the frequency (F _dot ) of the display clock that defines the operation of the display circuit, FR=THc×TVl/F _dot is preferably defined. is.

Next, FIG. 49 is a drawing for explaining still another embodiment for realizing the motor effect, in which the motor effect is executed without using the SMC circuit 78 and the input/output circuit 64s. This motor performance is realized by four motor drivers DV1 to DV4 that drive the four stepping motors MO1 to MO4, and a sensor board 86 that serially transmits a sensor signal SEN such as an origin sensor to the CPU circuit 51. be.

The operation contents of the motor drivers DV1 to DV4 are centrally controlled by the performance control CPU 63 of the CPU circuit 51 that executes the performance control program. (Motor Controller) 85 drives and controls. In this specification, drive control is a concept including rotational drive for advancing the rotational position and stop drive for maintaining the stop position.

As described above, the VDP circuit 52 of the composite chip 50 has a built-in SMC circuit 78 (Serial Motor Controller), and it is preferable to use this SMC circuit 78 to drive the motor drivers DV1 to DV4. However, in this embodiment, by using the motor controller 85 with higher performance, not only the control load of the effect control CPU 63 is significantly reduced, but also high-speed and advanced motor effects are realized.

That is, in the present embodiment, the stepping motors MO3 and MO4 are appropriately rotationally driven to execute a notice effect of suddenly starting or stopping the character, or a notice effect of moving the character at a speed exceeding the free fall. However, even if these innovative motor effects are executed, drive control that does not cause problems such as stepping out is realized. Here, step-out means a phenomenon in which the motor does not rotate normally in response to the stepping pulse output by the motor driver DV (input pulse signal received by the stepping motor). can occur.

The circuit configuration of FIG. 49 that achieves the above effects will be described in detail below. First, the stepping motors MO1 to MO4 are all bipolar stepping motors, and bidirectional drive currents are passed through the A-phase and B-phase motor windings (bipolar drive). In Cited Documents 5 and 6, a unipolar type motor is used exclusively for the purpose of simplifying the drive circuit. It uses a bipolar motor that can

Corresponding to the above configuration, the motor drivers DV1 to DV4 for driving the respective motors all incorporate driving circuits capable of bipolar driving. It also has an internal circuit capable of executing constant current control between the maximum current MAX and the minimum current MAX-δ in the 100% drive mode. The motor drivers DV1-DV2 are controlled by the SIO port 61 (serial port) and the PIO port 62 (parallel port) built in the CPU circuit 51, and the motor drivers DV3-DV4 are controlled by the motor controller 85. there is The motor controller 85 is controlled by an SIO port 61, a PIO port 62, and a compare match timer CMT built into the CPU circuit 51. FIG.

50(a) shows the internal configuration of the SIO port 61 incorporated in the CPU circuit 51. FIG. Here, the SIO port 61 is configured to be able to execute SPI (Serial Peripheral Interface) system, that is, a three-wire serial transmission/reception operation synchronized with the shift clock SCK. This SIO port (serial port) 61 is composed of a total of six identical circuits (CH0 to CH5). SPI communication path. On the other hand, the serial port SIO_1 of CH1 and the motor controller 85 are connected by the second SPI communication path.

First, the internal configuration of the SIO port 61 will be described. a 16-stage FIFO data register SCFTDR capable of storing up to 16 bytes of transmission data; a 16-stage FIFO data register SCFRDR capable of storing up to 16 bytes of reception data; and a transmission/reception controller CTL that operates the internal circuit of the SIO port 61 based on various control parameters set by the production control CPU63, and the production control CPU63 as the transmission/reception controller CTL and an interface circuit BUSIF for relaying various data when accessing the .

In this embodiment, the N*8-bit transmission data stored in the FIFO data register SCFTDR by the effect control CPU 63 is automatically transferred to the transmission shift register SCTSR each time the 8-bit length serial transmission process ends. The operation is initially set so that serial transmission processing continues until the FIFO data register SCFTDR becomes empty. Also, the reception data serially received by the reception shift register SCRSR is initially set to be stored in the FIFO data register SCFRDR every time it reaches 8 bits.

The transmission/reception controller CTL can output various interrupt signals indicating an overrun error BRI, a reception error ERI indicating a framing error or a parity error, a reception FIFO data full RXI, a transmission FIFO data empty TX1, etc. to the effect control CPU 63. is configured to

Hereinafter, the serial port 61 of CH0 will be referred to as SIO_0, and the serial port of CH1 will be referred to as SIO_1. FIG. 50(b) shows the connection relationship between the serial port SIO_0, the motor drivers DV1 and DV2, and the sensor board 86. FIG.

The serial port SIO_0 operates based on the operating parameters set in the transmission/reception controller CTL by the effect control CPU63. Specifically, the transmission shift register SCTSR serially transmits the driving data SDATA with a maximum length of 2×8 bits stored in the FIFO data register SCFTDR by the effect control CPU 63 every 8 bits in synchronization with the shift clock SCK. In this embodiment, the baud rate of the serial port SIO_0 is set to, for example, 250 kbps, and the transmission time of the 16-bit length drive data SDATA is 16/(250*10 ³ )=0.064 mS.

The motors MO1 and MO2 are two-phase excited in this embodiment, but each 8-bit drive data SDATA is a 4-bit excitation data ( PHASE instruction) and a 4-bit set value (current instruction value) that defines the drive current to be supplied to the motor windings A/B.

Each motor driver DV1, DV2 synchronizes the drive signal corresponding to the excitation data (4 bits) included in the drive data SDATA (8 bits) received from the serial port SIO_0 with the stepping clock LATCH received from the PIO port 62. Then, the motors MO1 and MO2 are driven with the drive current corresponding to the current instruction value (4 bits) indicated by the drive data SDATA. The current command value (4-bit length) allows 16 different current commands including 0%, and the output torque increases in proportion to the driving current based on the current command value. In this sense, the current command value means torque setting.

In this embodiment, the driving data SDATA and the stepping clock LATCH are output every 1 mS, so the motors MO1 and MO2 rotate stepwise every 1 mS at the fastest. Since the drive data SDATA can be updated every 1 mS, the motors MO1 and MO2 will perform the fastest 1000 steps per second.

On the other hand, when it is desired to rotate the motors MO1 and MO2 slowly, the same unupdated drive data SDATA is continuously output a plurality of times, or a standby period is provided during which neither the drive data SDATA nor the shift clock SCK is output. When the same drive data is output N times in succession, it is preferable that the current instruction value during stop driving from the second time to the N-1th time be smaller than the current instruction value of the first time. be. This is because while the output torque increases in proportion to the driving current, the power consumption also increases greatly in correspondence with the driving current, so that wasteful power consumption during stop driving is suppressed.

By the way, in this embodiment, 16 shift clocks SCK are output every 1 ms. The 16 shift clocks SCK are output from the motor driver DV1 and the motor driver DV2 as shown in FIGS. 49 and 50(b). , and are commonly supplied to the sensor substrate 86 .

As shown in FIG. 51(a), the sensor substrate 86 is mounted with a shift register 90 whose internal configuration is shown in FIG. 51(b). A total of 8-bit sensor signal SEN is serially transmitted in synchronization with SCK. Therefore, in this embodiment, the 8-bit sensor signal SEN is sent to the serial port SIO_0 based on the top eight shift clocks SCK out of a total of 16 shift clocks SCK that the serial port SIO_0 outputs every 1 ms. will be obtained. The sensor signal SEN includes an origin sensor signal indicating that the reference point on the rotation shaft of each motor MO1, MO2 has passed a predetermined origin position, and a sensor signal CHK indicating that the accessory wants to reach a predetermined position. include.

Next, FIG. 50(c) shows the connection relationship between the serial port SIO_1 and the motor controller 85. As shown in FIG. In this embodiment, the motor controller 85 outputs stepping clocks (pulse signals) to the drivers DV3 and DV4, respectively, and the motors MO3 and MO4 rotate stepwise in synchronization with the received stepping clocks. ing. Further, the motor driver 85 is configured to acquire the rotational positions of the motors MO3 and MO4 and the sensor signal CHK indicating that the accessory has reached the target position.

The motor controller 85 receives various control data MOSI from the serial port SIO_1 in synchronization with the shift clock SCK received from the serial port SIO_1, and serially transmits the sensor signal MISO to the serial port SIO_1. The motor controller 85 also receives an operating signal SS generated by the compare match timer CMT. This operating signal SS indicates that the motor controller 85 and the serial port SIO_1 are executing the serial transmission/reception operation.

As described in the upper left part of FIG. 49, the compare match timer CMT starts counting the reference clock based on the control of the effect control CPU 63, and when the count value reaches a predetermined upper limit MX, the compare match occurs. The effect control CPU 63, which is configured to output an interrupt signal and receives the interrupt signal, terminates the count operation of the compare match timer CMT.

The above operation is repeatedly executed every 1 mS under the control of the effect control CPU 63, and the operating signal SS indicating that the counting operation is in progress is logically inverted and transmitted to the motor controller 85. Here, the pulse width of the operating signal SS is determined to be an optimum value within 1 mS corresponding to the time required for serial transmission/reception processing by the serial port SIO_1 of CH1. In this sense, the operating signal SS is also the operating signal of the serial port SIO_1, and its pulse width is determined by the product of the pulse period of the reference clock and the upper limit value MX of the compare match operation.

Although not particularly limited, the baud rate of the shift clock SCK is set to 250 kbps for the serial port SIO_1 as well. In this embodiment, the control data MOSI that is intermittently serially transmitted is limited to a maximum of 16*8 bits corresponding to the storage capacity of the FIFO data register SCFTDR, and the transmission time of the drive data MOSI is , is limited to 16*8/(250*10 ³ )=0.512 ms at maximum. Since 32 shift clocks SCK are required to acquire the origin sensor signal, the operating time for serial reception is 32/(250*10 ³ )=0.128 mS. In this embodiment, one serial transmission is limited to 16*8 bits in consideration of the operation period of 1 ms, but it can be set to be longer by increasing the baud rate.

The control data MOSI includes a series of instruction data INS1 that defines a series of operations of the stepping motors MO3 and MO4, and a current instruction data INS2 that defines the maximum value MAX of the drive current to be applied to the drive windings. . Then, the binary signals SETx and SETy generated based on the current instruction data INS2 are supplied to the setting circuit LMT, and the motor drivers DV3 and DV4 are set to 100% based on the predetermined level analog signal output from the setting circuit LMT. In the driving mode, the constant current control operation is executed within the range of minimum value MAX-δ and maximum value MAX. A drive mode (standby operation mode) of less than 100% can also be adopted, but this point will be described later.

In general, when a stepping motor is rotated at high speed, the output torque decreases due to the delay in the start-up when the drive current is switched. While applying a drive voltage (35 V), by executing constant current control that chops the motor drive current, stable high-speed rotation is realized.

FIG. 52(a) is a block diagram showing the internal configuration of the motor drivers DV1 and DV2. As shown, the motor drivers DV1 and DV2 have an SCK terminal for receiving the shift clock SCK from the serial port SIO_0, an RCK terminal for receiving the stepping clock LATCH from the PIO port 62, and an SI terminal for receiving the control data SDATA from the serial port SIO_0. , a SCLR terminal and a STANDBY terminal that receive the reset signal RESET from the PIO port 62, a VREF_A terminal and a VREF_B terminal that receive an analog signal that defines the maximum current MAX in 100% constant current control, and a frequency of the internal clock for constant current control. The OSCM terminal receives a specified signal, the VM terminal receives a motor drive voltage of 35V, the VCC terminal outputs a constant voltage of 5V generated by stepping down the DC voltage of 35V received from the VM terminal, and the current detection for constant current control. The RS_A and RS_B terminals to which resistors RS_A/RS_B (for example, 0.33Ω) are connected, the OUT_A ± terminals that output drive current to the A-phase winding of the stepping motor, and the drive current to the B-phase winding of the stepping motor. It is configured with OUT_B ± terminals for output and a G− terminal that enables the internal circuit to operate by receiving an L level voltage.

A conductive polymer capacitor of 33 μF is connected to the VM terminal, which receives a DC voltage of 35 V, as illustrated. As described above, in this specification, a conductive polymer capacitor means a hybrid capacitor in which an electrolyte in which a conductive polymer and an electrolytic solution are fused is arranged instead of the electrolytic solution of an aluminum electrolytic capacitor. . This conductive polymer capacitor is a cylindrical surface-mount product having a rated voltage of 50 V, a diameter of 6.3 mm and a height of 7.7 mm.

And the capacitance at 5V feeding is kept below -10% of the nominal value (33 μF). Also, the equivalent series resistance ESR is nominally 40 mΩ.

Unlike the general circuit configuration, the drivers DV1 and DV2 in FIG. It provides the desired smoothing and decoupling behavior without consuming layout space for other circuit elements. That is, no additional smoothing capacitors or decoupling capacitors are arranged within a radius of at least 20 mm from the conductive polymer capacitor.

Also, on the top surface of the surface-mounted cylindrical shape, a numerical value "33" indicating the capacitance and a symbol "H" indicating the rated voltage 50 V are written, and the negative polarity direction is indicated by a black symbol. Since it is specified, it is possible to easily check the parts on the board by visual confirmation.

As shown, the motor drivers DV1 and DV2 include a torque control unit (torque control, VREF comp, Bridge A NF level set) that controls the output torque based on the voltage of the RS_A terminal and the RS_B terminal, and an 8-bit shift register (shift register), constant voltage generation section (VCC_REG), central control section (Main control Logic), oscillation section such as internal clock (oscillator, Internal oscillator), bridge drive circuit (Motor output stage Bridge A/B ), an overheat detection circuit (TSD), an overcurrent detection circuit (ISD), and a power-on reset circuit (POR) for a 35V power supply.

In order to drive the motor driver having the above circuit configuration, the control data SDATA (8 bits) supplied to the SI terminal consists of excitation data (4 bits PHASE instruction) instructing stepping operation for one step, and motor winding and a current instruction value (4 bits) that defines the drive current to be passed through the lines A/B.

Further, since the SCLR terminal and the STANDBY terminal are maintained at H level after receiving the reset signal RESET of L level at the time of power-on, the internal circuit is in a steady operable state. As shown in the figure, the G- terminal is constantly at the L level, so the reset operation can be performed after the power is turned on.

In addition, the VREF_A terminal and the VREF_B terminal are supplied with an indicated voltage obtained by dividing the constant voltage of 5V output from the VCC terminal. , for example, 545 mA.

As described above, the current instruction value included in the control data SDATA has a 4-bit length, and the maximum current value can be set in 16 steps including 0%. Therefore, based on this set value, the actual maximum current can be set to 94% of the MAX value, 86% of the MAX value, 5% of the MAX value, in addition to 100% of the MAX value. becomes. Therefore, in the description of the constant current control described below, the maximum current in the arbitrary % drive mode is particularly referred to as the current upper limit value NF. For example, the current upper limit value NF in the N % drive mode has a relationship of MAX*N/100 with respect to the maximum current MAX.

As described above, in this embodiment, during low-speed rotation in which the same drive data is continuously output a plurality of N times in an operation cycle of 1 ms, the current instruction values for the first and N times are set to 100%, to the (N-1)th time, for example, to 25%, thereby suppressing power consumption. In this case, the current upper limit value NK is NF=0.25*MAX with respect to the maximum current MAX, so power consumption is significantly suppressed (approximately 6.2%).

As shown in FIG. 52, the OSCM terminal is connected to a resistor of 2.7 KΩ that supplies a constant voltage of 5 V and a capacitor of 330 pF that is connected to the ground line, thereby controlling the frequency of the internal clock that manages constant current control. is set to about 1578 kHz. The frequency of the internal clock defines the detection cycle of the drive current, and is preferably set to 1300 kHz to 1800 kHz in control method 1, which will be described later, in order to perform constant current control of the motor drive current.

As described above, the motor drive current is increased/decreased between the maximum value MAX and the minimum value MAX-δ as constant current control in the 100% drive mode. Here, the constant current control cycle (chopping cycle T _chop ) can be set appropriately. It is preferable to set the period T _chop to 8 to 12 μS, and in this embodiment, the chopping period T _chop of constant current control is set to 10 μS.

As shown in FIGS. 52(b) and 52(c), in this embodiment, in the 100% drive mode, the motor drive current starts increasing from the start of the chopping cycle, and after reaching the MAX value of 545 mA, the following will continue to decrease until the beginning of the chopping cycle of . As described above, if the drive mode is set to less than the 100% drive mode, the power consumption is suppressed by properly decreasing the MAX value.

Next, FIGS. 52(d) and 52(e) are circuit diagrams showing a BridgeA drive circuit and a BridgeB drive circuit for driving the drive windings A/B. B), the internal configuration, the current detection resistors RS_A/RS_B, and the motor drive voltage of 35V. As shown in the figure, in any drive circuit, P-type MOS transistors U1 and U2 on the high-voltage side and N-type MOS transistors L1 and L2 on the low-voltage side form an H bridge that realizes bipolar driving.

In the embodiment, the A-phase winding and the B-phase winding of the bipolar stepping motor each have a winding inductance value of, for example, 4.2 mH and an internal resistance of 21Ω. Therefore, when the motor driving voltage is 35 V, the steady-state current (saturated DC current) flowing through each winding is 35/21=1.7 A, which greatly exceeds the rated current (1 A) of this motor. However, in this embodiment, by executing constant current control that limits the maximum current to 545 mA, the reduction in torque is avoided and the stepping motor rotates at high speed.

FIG. 53(a) is a diagram for _explaining the operation of the bridge drive circuit (Motor output stage Bridge A/B). Fig. 10 is a drawing showing a discharge operation; As shown in the figure, SLOW discharge is an operation to discharge the coil current via transistors L1 and L2 on the low voltage side, while FAST discharge causes the transistors that were OFF during the CHRGE operation to transition to ON. This is an operation to turn off the transistor that was in the ON state.

SLOW discharge is superior to FAST discharge in that the current ripple is small and the average current is large. . Therefore, in this embodiment, for the purpose of rotating the stepping motor at high speed, the coil discharge current is optimized by combining SLOW discharge with a high average current and FAST discharge suitable for high speed operation.

In this embodiment, since the stepping motor is driven in a bipolar manner, the operating states of the transistors are the ON/OFF state shown in FIG. is appropriately switched to the ON/OFF state shown in FIG. 52(c).

Based on the above, the charge operation and discharge operation shown in FIG. 53(a) will be further described. The transistors U2 and L1 at the corner positions are turned off. Assuming that the inductance L of the coil winding is 4.2 mH and the internal resistance R is 21Ω, the reciprocal R/L of the time constant of the coil is 5000 (the time constant is 0.2 mS).

Therefore, if the initial coil current at the start of the CHARGE operation is _I0 and the motor drive voltage is 35V as E, the coil current I at the elapsed time t from the start of the CHARGE operation is I=E/R+( _I0 -E/R )*EXP(-5000*t), and if I ₀ =0.5 [A], then I≈1.67-1.17*EXP(-5000+t) [A]. The current detection resistor RS_A/RS_B is, for example, 0.33Ω, which is much lower than the internal resistance R=21Ω and can be ignored.

On the other hand, assuming that the initial coil current at the start of SLOW discharge is _I0 , the coil current I at elapsed time t from the start of SLOW discharge operation is I _{= I0} *EXP(-5000*t). 0.5 [A], then I≈0.5*EXP(-5000+t) [A]. Assuming that the initial coil current at the start of FAST discharge is _I0 , the coil current I at elapsed time t from the start of FAST discharge operation is I=-E/R+( _I0 +E/R)*EXP(-5000* t), and if I ₀ =0.5 [A], then I≈−1.67+2.17*EXP(−5000+t) [A].

FIG. 53(c) shows respective discharge curves for _SLOW discharge and FAST discharge. , a SLOW discharge with a slow current decrease. Incidentally, in this embodiment, since the stepping motor is driven in a bipolar manner, the direction of the coil drive current is switched by the FAST discharge operation. The coil drive current will shift to 0.5A.

In this embodiment, the maximum current MAX in the 100% drive mode is set to 545 mA, but in FIG. 53(c), the amplitude width of the maximum current indicated by the large arrow is ±500 mA for convenience of drawing. . Also, the amplitude width of the constant current control executed between 500 mA and the very close minimum current is indicated by small arrows.

FIG. 54(a) is a time chart for explaining the constant current control operation combining the CHARGE operation, SLOW operation, and FAST operation explained in FIG.

FIG. 54(a) illustrates the control method 1 employed in the motor drivers DV1 and DV2 of FIG. 52, in which the control transitions in the order of CHARGE→SLOW→FAST in one chopping cycle T _chop . . In the illustrated operation, the chopping period T _chop is set to 10 μs, which is equivalent to 16 internal clocks with a frequency of about 1.6 MHz, as in the case of FIG. 52(b). As described above, when the control method 1 is adopted, it is preferable to set the chopping cycle T _chop to about 8 to 12 μs.

In the illustrated control method 1, in the CHARGE operation, after the drive current Iout reaches the current upper limit value NF, the operation shifts to the SLOW operation. are migrating. This control method 1 has the advantage of being able to secure a fixed operation time for the FAST operation. It goes without saying that this control method 1 may also be employed in the motor drivers DV3 and DV4 shown in FIG.

Next, FIG. 54(b) shows control method 2 in which the control transitions in the order of CHARGE→FAST→SLOW in one chopping cycle T _chop . In the illustrated operation, the chopping period T _chop is 13.56 μS, which is equivalent to 16 internal clocks with a frequency of about 1.18 MHz. Although not particularly limited, when the control method 2 is employed, it is preferable to set the constant current control period (chopping period) to about 6 to 25 μs in this type of motor control.

In the CHARGE operation, after the drive current Iout reaches the current upper limit value NF, first, it shifts to the FAST operation, and when it drops to a predetermined threshold TH, it shifts to the SLOW operation. This control method 2 has the merit that the start current of the SLOW operation can be fixed by the threshold value TH, and the required average current can be secured. However, the internal clock should be 640 kHz to 2400 kHz in order to avoid delays in detection of the current upper limit and threshold.

In this control method 2, it is not always necessary to set the threshold TH fixedly, and it is preferable to appropriately change the threshold TH in accordance with current decay conditions and the like so as to maintain a predetermined average current. preferred. Although this control method 2 is employed in the motor drivers DV3 and DV4 shown in FIG. 57, the control method 2 may also be employed in place of the control method 1 in the motor drivers DV1 and DV2 shown in FIG. is of course.

FIG. 55 shows in detail part of the motor drivers DV1 and DV2 in order to explain the configuration of the control data SDATA serially transmitted to the motor drivers DV1 and DV2. Specifically, FIG. 55 shows the torque control unit (torque control, VREF comp, Bridge A NF level set) of FIG. 52, an 8-bit length shift register, and a central control unit (Main control logic ) and are extracted and illustrated.

As described above, the control data SDATA includes the excitation data (PHASE instruction value 4 bits) that instructs stepping operation for one step, and the current instruction value ( 4 bits) and . These 8-bit data are parallel-converted and stored in a storage register, then latched by an input circuit (logic input gate) in synchronism with a step clock LATCH, and are also latched by a central control unit ( (Motor Control Logic).

The central control unit (Motor Control Logic) generates a PHASE signal based on the excitation data (4 bits), and defines the current upper limit value NF in constant current control based on the current instruction value (4 bits). . Here, the current upper limit value NF matches the maximum current MAX in the 100% drive mode, but becomes the current upper limit value corresponding to the drive mode in the less than 100% drive mode.

Since the output torque corresponds to the drive current flowing through the coil windings, the higher the drive current, the higher the output torque. Therefore, in this embodiment, as described above, the current upper limit value NF is switched as necessary to suppress wasteful power consumption.

Further, depending on the excitation data of 4-bit length included in the control data SDATA, it is possible to adopt an appropriate excitation mode such as 2-phase excitation or 1-2-phase excitation. is energized. As is apparent, when the same excitation data is serially transmitted repeatedly, the stepping motor does not step (progress), but is stopped to maintain its stopped state. Therefore, as described above, during this stop drive, the current instruction value (4 bits) is lowered to suppress power consumption.

The stopping drive is executed as constant current control based on the upper limit value NF even after the serial transmission of the excitation data (PHASE indication value 4 bits) is stopped. Also, even when only the stepping clock LATCH is periodically supplied after the transmission of the excitation data is stopped, constant current control based on the excitation data and the current instruction value stored in the storage register Stop driving is repeated.

FIG. 56 shows the drive data DATA, shift clock SCK, and stepping clock LATCH received by the motor drivers DV1/DV2 from the serial port SIO_0, and the A phase and B phase output by the motor drivers DV1 to DV2 to the stepping motors MO1/MO2. and the drive current Iout. The drive current is under constant current control by the control method 1 described in FIG. 53, and the constant current control operating state at the chopping period T _chop =10 μS is shown in a sawtooth shape.

The PHASE signal corresponds to the transition of the excitation data (4 bits) for the A phase and the B phase. D, and clockwise rotation CW is realized. All of the current instruction values (4 bits) are 1111, and the stepping motors MO1/MO2 are operating in the 100% drive mode at this timing.

As described above, the serial port SIO_0 outputs the shift clock SCK at a baud rate of 250 kbps, so the serial transmission of the excitation data (4 bits) and current command value (4 bits) is completed in 32 μs. On the other hand, since the PIO port 62 outputs the stepping clock LATCH every 1 ms, the current vector A, the current vector B, the current vector C, and the current vector D shown in FIG. A large gap of the order of magnitude (=1000-32) will exist.

FIG. 57 is a block diagram showing the internal configuration of motor drivers DV3-DV4. As shown in the figure, this motor driver DV3/DV4 has DMODE0 to DMODE2 terminals that receive the excitation method setting data (3 bits), CW/CCW terminals that receive the designation of the rotation direction, CLK terminals that receive the stepping clock, A RESET terminal for receiving a reset signal, an ENABLE terminal for receiving permission/prohibition instructions for permitting/prohibiting the motor driving operation, and an RSA terminal and an RSB terminal to which a detection resistor (for example, 0.33Ω) for detecting the motor driving current is connected. , VREFA and VREFB terminals that receive a set voltage that defines the current upper limit value NF in constant current control, a VM terminal that receives a motor drive voltage of 35V, a VCC terminal that outputs an internally generated constant voltage of 5V, and an internal clock. It has an OSCM terminal for regulation, an MO terminal capable of monitoring the progress of the PHASE signal, an LO terminal capable of monitoring the internal error state, and OUTA± and OUTB± terminals for outputting the drive current Iout. It is configured.

The motor drivers DV3/DV4 include an oscillation circuit (Motor Oscillator, OSC-Clock Converter) that generates an internal clock based on the element connected to the OSCM terminal, and a constant voltage of 5V based on the drive voltage of 35V received at the VM terminal. A constant voltage circuit (VCC regulator) to be generated, a current control circuit (Current Reference Setting, Current Level Set) that regulates the upper limit current NF of constant current control based on the voltage received at the VREFA terminal and the VREFB terminal, and an externally received A signal decoding circuit (Signal Decode Logic) for generating internal signals corresponding to various commands, a pair of monitoring circuits (Current Comp) for monitoring the motor drive currents Iout of phases A and B, and drive windings A/B A pair of drive circuits (H-bridge) that drives the, overheat detection circuit (TSD), overcurrent detection circuit (ISD), 35V power supply power-on reset circuit (Power-On Reset), and the operation of each part and a central control logic (motor control logic).

As shown in the figure, the VM terminal that receives a DC voltage of 35 V is connected to the same 33 μF conductive polymer capacitor as in FIG. A hybrid capacitor with a different electrolyte is connected. As in the case of FIG. 52, this conductive polymer capacitor is also a cylindrical surface-mount product having a rated voltage of 50 V, a diameter of 6.3 mm and a height of 7.7 mm. Then, a desired decoupling operation can be realized by simply arranging a single capacitor for each motor driver (DV3, DV4). The numerical value “33” indicating the capacitance, the symbol “H” indicating the rated voltage of 50 V, and the black symbol indicating the negative polarity are also as described with reference to FIG.

On the other hand, the OSCM terminal is connected to a 5.1 kΩ resistor connected to a constant voltage of 5 V and a 270 pF capacitor connected to the ground, and the frequency of the internal clock that manages constant current control is set to 1.18 MHz. ing. Therefore, in this embodiment, the chopping frequency is, for example, 1.18/16=73.75 kHz, and constant current control is executed at a chopping period of 13.56 μS.

Also, voltages corresponding to the setting signals SETx and SETy (see FIG. 49) of the current upper limit value received from the motor controller 85 are commonly supplied to the VREFA terminal and the VREFB terminal via the setting circuit LMT. (See FIG. 49). Specifically, the set voltage of the setting circuit LMT when the electronic switch SW is ON is 0.78 V, while the set voltage when the electronic switch SW is OFF is 0.1685 V. is set.

The motor drivers DV3/DV4 are configured to determine the current upper limit value NF in constant current control corresponding to this set voltage of 0.78/0.16V. About phase and B phase, it becomes about 473mA/102mA in common corresponding to ON/OFF of switch circuit SW.

Corresponding to the above circuit configuration, in this embodiment, for example, in the constant current control during the motor presentation, the motor is driven and controlled so that the current upper limit value NF is 473 mA, and for example, the standby operation before the start of the motor presentation In the middle, useless power consumption is suppressed by performing standby control in which the current upper limit value NF is 102 mA, which is 1/4 or less than before. In principle, power consumption during standby control is about 4.65% of that during drive control.

Next, the DMODE0 to DMODE2 terminals that define the excitation method are configured to be able to supply 3-bit length setting data. In the motor drivers DV3/DV4, not only two-phase excitation (see FIG. 58(a)) that changes the drive current Iout in a rectangular shape but also a 1-phase excitation that slightly relaxes the pulse waveform by inserting a 0% drive state. Two-phase excitation (see FIG. 58(b)) or microstep excitation that changes the drive current Iout in a substantially sinusoidal shape by changing the current upper limit NF between +100% drive and -100% drive in multiple steps. It is configured so that the operation can also be specified.

Here, the closer the drive current Iout to a sine wave, the smoother the stepping motor rotates, which is excellent in this respect. However, unlike a precision machine, it is understood that the performance of a character in this type of game machine does not require the smooth rotation of a precision machine. In addition, it is more effective to perform high-speed rotation with a large step angle than with a small step angle for smooth rotation.

Therefore, in this embodiment, the stepping motor is excited in two phases or one-two phases based on the setting data supplied to terminals DMODE0 to DMODE2. Here, in order to rotate the motor at high speed, 2-phase excitation with a large step angle is more advantageous than 1-2-phase excitation. The setting data may be a control value by software processing, but in this embodiment, it is a fixed value by hardware. there is

However, in the following description, given setting data (001) is fixedly supplied to the DMODE0 to DMODE2 terminals of the motor drivers DV3/DV4, every time the stepping clock CLK is received from the motor controller 85, It is assumed that the stepping motor is excited in two phases. That is, the motor drivers DV3/DV4 operate as shown in FIG. 58(a).

Next, the CW/CCW terminal, the CLK terminal and the ENABLE terminal are supplied from the motor controller 85 with 1-bit direction instruction data, a stepping clock CLK for stepping the stepping motor by one step, A permission signal ENABLE for permitting the driving operation is appropriately supplied. Since the RESET terminal is constantly at L level, it is always operable through an internal NOT circuit (see FIG. 49).

58(a) and 58(b) illustrate the stepping clock CLK and the drive current Iout of the A-phase winding and the B-phase winding during the two-phase excitation operation and the 1-2 phase excitation operation. It is. When the clockwise rotation CW is instructed, the driver internal circuit operates so that the drive current Iout shifts rightward on the time axis in accordance with the stepping clock CLK. On the other hand, when the counterclockwise rotation CCW is instructed, the driver internal circuit operates so that the drive current Iout shifts leftward on the time axis in accordance with the stepping clock CLK. That is, each time the stepping clock CLK is received, the current levels and current directions of the drive currents Iout(a) and Iout(b) change. As shown in the figure, in 2-phase excitation, the current direction changes each time stepping clock CLK is received, and in 1-2 phase excitation and microstep excitation (not shown), the current level changes each time stepping clock CLK is received. .

Here, the stepping clock CLK is supplied from the motor controller 85 at a proper timing and at a proper speed. Each time the stepping motor is received, it rotates by one step angle θ [degree]. Therefore, when N stepping clocks CLK are received, the stepping motor rotates by N*θ [degrees], and the stepping motor rotates by an angle corresponding to the number of stepping clocks CLK.

Here, when N stepping clocks CLK are supplied requiring time T, it takes time T [seconds] to rotate N*θ [degrees], and the rotational angular velocity is N * θ/T [Degree per Second]. The stepping motor used in this embodiment is 2-phase excited and the step angle θ is, for example, 7.5 degrees. will be required.

Therefore, when the pulse speed of the stepping clock CLK is V [PPS (Pulse Per Second)], the 48 pulses CLK required for one rotation of the motor are supplied at 48/V [S]. The motor rotates 60*V/48 in one minute, which is 60*V/48 [rpm] when converted to motor rotation speed rpm (rotations per minute).

By the way, also in the motor drivers DV3/DV4, constant current control is executed based on the current upper limit value NF. However, as described with reference to FIG. 57, the current upper limit value NF is either 473 mA or 102 mA in this embodiment, depending on whether it is during drive control during the movable effect or during standby control before the start of the movable effect. , is changed by the motor controller 85 as appropriate.

FIG. 58(c) shows, for example, the operation of constant current control when transitioning from standby control to drive control. In any control state, based on control method 2 shown in FIG. It shows that the constant current control of CHARGE→FAST→SLOW is executed. On the other hand, FIG. 58(d) shows, for example, a case where drive control is shifted to standby control. Constant current control is performed.

Even if the stepping clock CLK is interrupted, the motor drivers DV3/DV4 continue constant current control based on the predetermined upper limit current NF, so the motors MO3 and MO4 are stopped and driven to remain stopped.

Next, FIG. 59 is a block diagram showing the internal configuration of the motor controller 85 that controls the operation of the motor drivers DV3/DV4. The motor controller 85 includes four internal circuits (circuits surrounded by dashed lines in FIG. 59) having the same configuration for controlling four motor drivers. When controlling four motor drivers, each motor driver drives four stepping motors. called an axis.

Corresponding to this expression, the motor controller 85 includes an X-axis circuit, a Y-axis circuit, a Z-axis circuit, and a U-axis circuit of the same configuration, which are surrounded by dashed lines in FIG. In this embodiment, only the X-axis and Y-axis circuits are used.

Here, the X-axis circuit drives and controls the motor driver DV3 that drives the stepping motor MO3, and the Y-axis circuit drives and controls the motor driver DV4 that drives the stepping motor MO4. The operations of the X-axis circuit and the Y-axis circuit are effect-controlled by the effect control CPU 63 via the serial port SIO_1.

Based on the above, when confirming the circuit configuration of FIG. 59, the motor controller 85 serially receives the control data MOSI from the serial port SIO_1 in synchronization with the shift clock SCK, and serially transmits the sensor signal MISO to the serial port SIO_1. is doing. In addition, it receives a reset signal RESET from the PIO port 62 and an operating signal SS whose valid period is L level from the compare match timer CMT.

In addition, the X-axis circuit of the motor controller 85 supplies the motor driver DV3 with a stepping clock OUTx (CLK), a setting signal SETx that defines the upper limit current, and a direction instruction that defines the direction of rotation (CW/CCW). Data DIRx and an operation enable signal ENABLEx are transmitted. On the other hand, the Y-axis circuit of the motor controller 85 supplies the motor driver DV4 with a stepping clock OUTy (CLK), a setting signal SETy that defines the upper limit current, a direction binary signal DIRy that defines the direction of rotation, An operation enable/disable command ENABLEy is transmitted.

Here, when the operation enable signals ENABLEx and ENABLEy are at L level, the outputs of the four MOS transistors forming the H bridge of the drive circuit built in the motor drivers DV3/DV4 are all in the HiZ state, and the motor drive is stopped. It is forbidden. Therefore, the performance control CPU 63 transmits predetermined control data to the motor controller 85 prior to the start of the motor performance by the stepping motors MO3/MO4, and the motor controller 85 sends the motor driver DV3/DV3 an H level operation. It is necessary to control so that the enable signals ENABLEx and ENABLEy are output. However, in order to eliminate the complexity, it is sufficient to execute the above operation only once when the power is turned on. Therefore, such an embodiment will be described below.

Returning to FIG. 59 and continuing the description of the motor driver 85, the motor controller 85 is capable of both SPI (Serial Peripheral Interface) communication and I ² C (Inter-Integrated Circuit) communication with the CPU circuit 51. However, in this embodiment, as described at the beginning, the serial transmission/reception operation is performed by SPI communication.

The motor controller 85 includes an SCL terminal SDA terminal that functions during I2C communication, DS0 ^- DS1 terminals that receive a device selection number, an SS terminal that receives an operating signal SS, an SCK terminal that receives a shift clock SCK, A MOSI terminal that receives control data MOSI, a MISO terminal that outputs a sensor signal MISO, a CSTA terminal that indicates the simultaneous start of a plurality of motors (all or part of the X/Y/Z/U axes), and an interrupt has been activated. RST terminal for receiving a reset signal, CLK terminal for receiving a reference clock for specifying internal operation, and ^IFSEL terminal for specifying whether the serial communication operation mode is SPI or I2C. It is configured.

As shown, the DS0-DS1 terminals are fixed to 00, for example, so the device number assigned to the motor controller 85 is 0. The motor controller 85 of the embodiment is configured such that a plurality of motor controllers can be connected in parallel to one serial port SIO_1, and the device number is used to specify any one of the motor controllers.

In this embodiment, the IFSEL terminal is fixed at H level, so that the motor controller 85 operates in SPI mode. Therefore, in this embodiment, the SCL and SDA terminals are disabled. However, it is of course possible to operate in the I ² C mode, and the following operation can be realized even in the I ² C mode.

As shown, the CLK terminal is supplied with a reference clock having a frequency of about 9.8 MHz generated by an oscillation circuit. The RST terminal is supplied with the reset signal RESET from the PIO port 62, and the SS terminal is configured to be supplied with the operating signal SS from the compare match timer CTM. The shift clock SCK and control data MISO are output to the SCK and MOSI terminals from the corresponding circuit of the serial port SIO_1, and the sensor data MISO is serially transmitted from the MISO terminal to the reception shift register SCRSR of the serial port SIO_1. be done.

Next, the X-axis circuit of the motor controller 85 will be described. As shown in FIG. 59, the X-axis circuit includes an OUTx terminal for outputting a step clock CLK to the motor driver DV3, a DIRx terminal for outputting direction indication data, a P2x terminal for outputting an operation enable signal ENABLEx, and an upper limit current. and a P3x terminal for outputting a setting signal SETx.

The X-axis circuit also has a P0x terminal for receiving an origin sensor signal indicating whether or not the character object driven by the motor MO3 is at the origin position, and a P0x terminal for receiving an origin sensor signal indicating whether or not the character object has reached the target position. and a P1x terminal for receiving the sensor signal.

The Y-axis circuit has the same configuration as the X-axis circuit described above, except that DV3 is replaced with DV4 as the motor driver, and MO3 is replaced with MO4 as the stepping motor. In this embodiment, the Z-axis circuit and the U-axis circuit are not used, but if they are used, the four stepping motors can be driven and controlled synchronously or independently.

Corresponding to the above P0x terminal, P1x terminal, P2x terminal, P3x terminal, the motor controller 85 has built-in general-purpose input/output ports capable of input/output operations, and based on commands from the performance control CPU 63 A general-purpose port control circuit is built in to perform input/output operations required for general-purpose input/output ports. A general-purpose input/output port can be used as both an input port and an output port. Therefore, in this embodiment, the P0x and P1x terminals are the input terminals of the general-purpose input ports P0 and P1, and the P2x and P3x terminals are the input terminals of the general-purpose input ports P0 and P1. , are initialized to be the output terminals of the general-purpose output ports P2 and P3.

The motor controller 85 also includes a plurality of registers that can arbitrarily set the number of output clocks of the stepping clock CLK output from the OUTx terminal, the output clock cycle (the clock speed of the stepping clock CLK), and the like. ing. The motor rotation speed is determined by the clock speed of the stepping clock CLK, and the rotation angle is determined by the number of output pulses of the stepping clock CLK. It is configured to output at any clock speed.

As described above, the motor drivers DV3/DV4 rotate the motor MO3 by one step for each step clock CLK. The rotation speed of the motor MO3 changes according to the clock output cycle of CLK.

By the way, according to the motor controller 85, acceleration control and deceleration control are optional, and not only rectangular drive without acceleration/deceleration control (FIG. 60(a)) but also trapezoidal drive shown in FIG. 60(b) is possible. is. The rectangular drive shown in FIG. 60(a) is adopted when the rotation speed of the motor is relatively slow. match the speed. Note that rectangular driving is easy to control and can be handled by program processing by a CPU, so it is used not only for motors MO3 and MO43 but also for driving motors MO1 and MO2 via the serial port SIO_. .

On the other hand, the trapezoidal drive shown in FIG. 60(b) is adopted when the motor rotation speed is high, and the pulse speed of the stepping clock CLK gradually increases linearly from the starting pulse speed to reach the target value of operation. reach pulse speed. After that, after rotating by the necessary amount at the operation pulse speed, the pulse speed of the stepping clock CLK gradually linearly slows down from the operation pulse speed, reaches the start pulse speed, and the motor stops. According to this trapezoidal drive, the sudden start or stop of the motor rotation can be avoided, so that abnormal operation such as stepping out can be avoided.

As shown, the pulse velocity increases linearly in steps of three or more and decreases linearly in steps of three or more. As shown in FIG. 60(b), such trapezoidal driving requires complex changes in the pulse period of the stepping clock CLK, which is not easy to implement by CPU program processing. Therefore, in this embodiment, by utilizing the motor controller 85, the motors MO3 and MO4 can be rotated at high speed while avoiding the sudden start and stop of the motors MO3 and MO4 without increasing the control load of the CPU. ing. As will be described later, in this embodiment, a predetermined accessory is lowered/raised at a higher speed than a natural fall during a predetermined presentation.

As shown in FIG. 60(c), in rectangular driving, it is necessary to specify not only the number of output pulses but also operation parameters such as the start/end speed FL, target speed FH, acceleration rate, and deceleration rate. Operation parameters are set in built-in registers described below by the effect control CPU 63 .

As shown in FIG. 59, the built-in registers of the motor controller 85 include N type 1 registers, M type 2 registers, and N pre-registers in which setting values for the type 1 registers can be set in advance. It is included. Then, when the motor operation based on the first type register is completed, the preset value of the corresponding pre-register is automatically transferred to the first type register, and a new motor operation can be started. Therefore, in this embodiment, after the operation parameter is set in the first type register, even for the continuous motor operation, by setting the operation parameter in the pre-register, a series of motor operations can be quickly set.

Here, the first type registers and the pre-registers include a register RFH (R1) for setting the target speed FH, a register RUR (R2) for defining the acceleration rate, a register RDR (R3) for defining the deceleration rate, a slowdown point , a register RWV (R5) that defines the number of output pulses, and six registers that can specify an operation mode (R6). The slowdown point means the timing at which the deceleration process is started, and the number of pulses for executing the deceleration operation is defined in the register RDP. Note that the register RDP that defines the slowdown point and the register RDR that defines the deceleration rate are used alternatively, and when the deceleration rate is defined, the slowdown point is automatically determined.

Since the operation parameters described above can be set in the first type registers and pre-registers, not only the operation mode after an intermediate stop, but also the target speed, acceleration rate, deceleration rate, number of output pulses, etc. in the re-rotation operation can be set in the pre-registers. can be reserved for

The second type registers include a register RFL that defines the initial speed FL at the start of motor rotation and the final speed FL before stopping, a register RMD that can set the motor operation mode, and an environment setting register RENV. ing. Here, the operation modes of the motor include continuous movement in the CW [clockwise] direction (MD1), continuous movement in the CCW [counterclockwise] direction (MD2), relative movement in the CW direction (MD3), and continuous movement in the CCW direction. Relative movement (MD4), CW positioning movement that moves in the CW direction until sensor detection (MD5), CCW positioning movement that moves in the CCW direction until sensor detection (MD6), Timer movement that moves for the time specified by the timer (MD7) , and any one of motor operations (MD1) to (MD7) is defined by setting a predetermined operation parameter in the mode setting register RMD.

In this embodiment, the sensors to be detected in the operation mode (MD5) and the operation mode (MD6) include an origin sensor that indicates whether or not the role object is positioned at the origin position, and an origin sensor that indicates whether the role object is positioned at the target position. and a target position sensor that indicates whether or not. Therefore, according to the present embodiment, it is possible to define the returning motion toward the origin position and the advancing motion toward the target position as one motion mode. In the operation mode (MD5) and operation mode (MD6), the motor continues to rotate at the operating speed set by the speed register RFH. After that, when the sensor signal is detected, the number of pulses set in the pulse number register RWV is output. to stop.

On the other hand, in relative movement in the operation mode (MD3) or the operation mode (MD4), the operation speed is defined by the speed register RFH, and the number of pulses set in the pulse number register RWV is output and stopped. In this case, not only rectangular drive but also trapezoidal drive is possible. In the case of trapezoidal drive, rotation is started in the manner set by the acceleration rate register RUR and rotated at the operating speed specified by the speed register RFH. After that, the operation is finished in the mode set by the deceleration rate register RDR. In the trapezoidal drive, an operation (instantaneous start+deceleration stop) without acceleration control or an operation (acceleration start+instantaneous stop) without deceleration control is possible.

Further, in the continuous movement specified in the operation mode (MD1) or the operation mode (MD2), the rotation continues at the operation speed specified by the speed register RFH, and the rotation ends when a stop command is received. Then, in any operation mode, the operation is started by receiving a start command. That is, the motor controller 85 is configured to operate upon receiving various commands including a start command and a stop command from the performance control CPU 63 .

Here, the commands that the effect control CPU 63 can output to the motor controller 85 include, in addition to the stop command (CM0), a plurality of start commands (CM1) with different start modes, and a plurality of start commands (CM1) with different start modes. It includes a remaining amount start command (CM2), a plurality of speed change commands (CM3) with different change modes, and an output command (CM4) for outputting predetermined data from a general-purpose output port. In this embodiment, the output command (CM4) is used to output the enable signal ENABLEx and the current upper limit setting signal SETx to the general-purpose output ports P2 and P3.

In the relative movement operation modes defined in the operation mode (MD3) and the operation mode (MD4), the number of remaining pulses is managed by a built-in remaining pass counter REST. The effect control CPU 63 can also stop the motor halfway at an appropriate timing by reading the number of remaining pulses from the remaining pass counter REST. The remaining amount start command prescribes a restart after this halfway stop.

Also, in the environment setting register RENV included in the second type register, a count-up time TCUP and a count-down time TCDW for realizing countdown control described later with reference to FIG. 60(d) can be set. One of four options can be selected for each of the count-up time TCUP and the count-down time TCDW.

Above, various registers that can be WRITE-accessed by the effect control CPU 63 have been described. The control CPU can grasp the operating state of the motor controller 85 .

FIG. 61(a) shows the contents of timer interrupt processing executed every 1 ms by the effect control CPU 63, and is a detailed version of the contents of FIG. 22(b). FIG. 62 is a time chart for explaining the serial transmission procedure to the motor controller 85 based on the process of FIG. 61(a).

In the 1 ms timer interrupt process, first, a pulse-like latch signal LOAD is output to the sensor board 86, and a stepping clock LATCH is output to the motor drivers DV1 and DV2 (RT1). Upon receiving the latch pulse LOAD, the shift register 90 of the sensor substrate 86 latches the sensor signal. In addition, the motor drivers DV1 and DV2 that have received the stepping clock LATCH drive/stop motors MO1 and MO2 based on the 8-bit data (current instruction value+PHASE setting) obtained by the previous timer interrupt.

Next, the effect control CPU 63 stores the previous data obtained in the data register SCFRDR of the serial port SIO_0 in a predetermined area of the memory (R2). As described above, in this embodiment, the serial data serially received by the previous timer interrupt is acquired in the memory at the time of the next timer interrupt, so the first acquired data (RT2) after power-on is naturally ignored. As described at the beginning, the serial data serially received in the reception shift register SCRSR is initialized so that it is automatically accumulated in the FIFO data register SCFRDR of the FIFO structure each time it reaches 8 bits.

Subsequently, it is determined whether or not the motor performance is being performed by the motors MO1 and MO2 (RT3). Then, if motor performance is being performed by the motors MO1 and/or MO2, drive data SDATA (16 bits) for stepping the motors MO1 and MO2 is set in the FIFO data register SCFTDR of the serial port SIO_0 (RT4). The drive data SDATA (16 bits) consists of 8 bits, ie, the PHASE set value (4 bits) and the current instruction value (4 bits) for each of the motors MO1 and MO2, so the total is 16 bits.

As described above, the drive data SDATA does not necessarily need to be updated every 1 ms, and when the motor rotation speed is slow, the same PHASE set value is used a plurality of times N times. In this case, the PHASE set value for the N times is always the same, but the current instruction values from the second time to the (N-1)th time are preferably at a suppression level of 25% drive, for example. At this throttle level, the power consumption is in principle 1/16=6.25%.

In addition, in order to realize the operation of FIG. 60(d), which will be described later, prior to starting a series of rotation operations, the PHASE set value (transmission value at the time of final rotation) that maintains the stopped state and the upper limit level of current An instruction value (100% drive) and drive data SDATA are set in the FIFO data register SCFTDR.

For example, when the motors MO1 and MO2 start rotating synchronously, the driving data SDATA of 8 bits each and 16 bits in total are prepared in the FIFO data register SCFTDR. Prior to the start of rotation, this driving data SDATA is serially transmitted a plurality of times, thereby performing stop driving at the upper limit level. This operation is to absorb the inertia of the accessory and prevent troubles such as stepping out, so it is not necessary for accessories that start at a low speed or light accessories.

On the other hand, if the motors MO1 and MO2 are not in the motor presentation, the drive data SDATA for stopping the motors MO1 and MO2 in the stopped state are set in the FIFO data register SCFTDR (RT5). The drive data SDATA for stop drive is composed of a PHASE setting value (previous transmission value) for maintaining the stop state and a current instruction value of a suppression level (for example, 25% drive).

Also in this case, in order to realize the operation of FIG. Drive data SDATA composed of a current instruction value (100% drive) is transmitted an appropriate number of times in advance, and stop drive at the upper limit level is executed. Since this action is also for absorbing the inertia of the character, it is not necessary for the character that stops slowly or the character that is light.

Subsequently, the effect control CPU 63 starts serial transmission/reception processing of the serial port SIO_0 with respect to the drive data SDATA (16 bits) set in the FIFO data register SCFTDR of the serial port SIO_0 (RT6). As a result, the serial port SIO_0 outputs a total of 16 shift clocks SCK until the FIFO data register SCFTDR becomes empty. It is transferred to the drivers DV1 and DV2.

As described with reference to FIG. 56, the driving data SDATA transmitted at this timing is executed by the stepping clock LATCH output at the next timer interrupt.

In addition, since the shift clock SCK is also supplied to the sensor board 86, the sensor signal SEN is serially received by the reception shift register SCRSR of the serial port SIO_0 in synchronization with the first eight shift clocks SCK, and the received data is stored in the FIFO data register SCFRDR. Since a total of 16 shift clocks SCK are output, the stored data is a total of 16 bits long, but only the first 8 bits are the significant sensor signal SEN, and the remaining 8 bits are idle 00H. (See FIG. 51(b))

In this embodiment, since the baud rate is 250 kbps, 16 shift clocks SCK are about 16/250 k=0.064 mS, and the processing can be completed in a very short time in the timer interrupt operation period of 1 mS. See the upper part of FIG. 63). Also, since the effect control CPU 63 only starts the serial transmission process (R6) and does not wait for the completion of the serial transmission, the processes of steps R1 to R6 are completed in an instant. It should be noted that the fact that serially received data is entrusted to the next timer interrupt process also contributes to the shortening of the processing time.

By the way, after the motor effect of CH0 is completed, as indicated by the dashed line in FIG. 61, the processes of steps RT4 and RT6 may be skipped without executing the process of step RT5. In this case, the motors MO1 and MO2 are repeatedly driven to stop by constant current control based on the final PHASE set value and current set value.

When the above processing of the serial port SIO_0 is completed, the effect control CPU 63 activates the compare match timer CMT to start outputting an operating signal SS having a pulse width of, for example, about 0.8 mS (RT7). As shown in the upper left part of FIG. 49, the compare match timer CMT transitions the operating signal SS to H level in response to the start of the counting operation of the clock signal. is initialized to generate a CMT interrupt when the

Then, in the CMT interrupt process, the effect control CPU 63 stops the count operation of the compare match timer CMT, so that the operating signal SS returns from H level to L level. As described above, the effect control CPU 63 is concerned only with the rising edge and the falling edge of the operating signal SS, so there is no risk of adverse effects such as depriving the processing time of other effect control processes.

After raising the operating signal SS to H level, the effect control CPU 63 acquires the sensor signal MISO from the motor controller 85 (RT8). FIG. 62(a) is a time chart showing this acquisition procedure. In synchronization with eight shift clocks SCK, device numbers S7 to S6=00, operation types S5 to S4=11, read target UZYX axes S3 to By setting S0=0010 or S3 to S0=0001, it is specified that the motor controller 85 with the device number 00 acquires the X-axis or Y-axis sensor signal.

Next, in synchronization with the subsequent eight shift clocks SCK, a sensor signal related to the motor MO3, which is the X axis (or a sensor signal related to the motor MO4, which is the Y axis) is acquired. That is, the X-axis and Y-axis sensor signals are acquired by repeating the operation of FIG. 62(a) twice. As shown in FIG. 59, among the general-purpose input/output ports, only port P0 (P0x terminal, P0y terminal) and port P1 (P1x terminal, P1y terminal) are set as input ports. Of the received data D7 to D0, only D1 and D0 are significant data. Then, the effect control CPU saves the acquired sensor signals D1 and D0 in appropriate places in the memory, and utilizes them for subsequent motor effects.

However, as described above, the operation modes that the performance control CPU 63 can specify to the motor controller 85 include CW positioning movement (MD5) that moves in the CW direction until sensor detection, and CCW positioning movement that moves in the CCW direction until sensor detection. Since the operation mode of movement (MD6) is included, the effect control CPU 63 does not need to grasp the sensor signal, and therefore the process of step RT8 can be omitted.

In any case, next, the effect control CPU 63 serially transmits the control data MOSI of up to 8×16 bits that defines the motor operation of the motors MO3 and MO4 based on whether the motor effect is being performed by the motors MO3 and MO4. It is set in the FIFO data register SCFTDR of port SIO_1 (RT9). If the motor effect is being executed, the control data for the effect rotation drive that realizes this is set in the FIFO data register SCFTDR. Control data for driving is set.

After the processing of steps RT8 to RT9 is completed as described above, next, the serial transmission processing of the serial port SIO_1 is started (RT10). 62(b) and 62(c) illustrate the procedure for serially transmitting the control data MOSI to the motor controller 85 from the serial port SIO_1.

First, FIG. 62(b) is a time chart showing the output procedure when the enable signal ENABLE and the setting signal SET are output from the general-purpose output ports P2 and P3. As shown in the figure, device numbers S7 to S6 = 00, operation types S5 to S4 = 10, write target UZYX axes S3 to S0 = 0010, or S3 to S0 = 0001 in synchronization with eight shift clocks SCK. defines that the motor controller 85 with device number 00 outputs a control signal for the X-axis (motor driver DV3) or the Y-axis (motor driver DV4).

Next, it outputs a control signal for the motor driver DV3 (or a control signal for the motor driver DV4) in synchronization with the subsequent eight shift clocks SCK. By repeating the operation of FIG. 62(b) twice in this case, the output of the control signals for the X-axis and the Y-axis is completed. As shown in FIG. 59, among general-purpose input/output ports, only port P2 (P2x terminal, P2y terminal) and port P3 (P3x terminal, P3y terminal) are set as output ports. Of the output data D7 to D0, significant data are only D3 (=SET) and D2 (=ENABLE).

As described above, in this embodiment, the current upper limit value NF for constant current control has two levels, H level for rotation drive and L level for stop drive, according to the H/L level of the setting signal SET. is controlled to SET=H level during performance of a character, and is controlled to SET=L during standby for performance.

Next, FIG. 62(c) is a time chart for explaining the transmission processing of commands defining the operation of the motor controller 85 and the setting processing of operation parameters in the built-in register. Since the various commands (CM1) to (CM4) that define the operation of the motor controller 85 are all 8-bit configurations, the processing in the upper part of FIG. 62(c) is completed. That is, when transmitting a command, first, in synchronization with eight shift clocks SCK, device numbers S7 to S6 = 00, operation types S5 to S4 = 00, command target UZYX axes S3 to S0 = 00**, is transmitted serially, it is announced that commands for the X-axis (MO3) and/or the Y-axis (MO4) in the motor controller 85 with the device number 00 will be transmitted.

Next, 8-bit length command data is transmitted in synchronization with the following 8 shift clocks SCK. If S3-S0=0001, the command is related to the X axis (MO3). If S3-S0=0010, the command is related to the Y-axis (MO4). It becomes a command for the Y-axis (MO3+MO4).

Command transmission has been described above. When setting operation parameters in various registers, the upper part of FIG. Following the part, the lower part needs to be processed. Specifically, when setting operation parameters to the registers, first, device numbers S7 to S6 = 00, operation types S5 to S4 = 00, command target UZYX axes S3 to S3, in synchronization with eight shift clocks SCK. By serially transmitting S0=00**, it is announced that the register setting values for the X-axis (MO3) and/or Y-axis (MO4) in the motor controller 85 with the device number 00 will be transmitted.

Next, an 8-bit register number is transmitted in synchronization with 8 shift clocks SCK. After that, in synchronization with 16 shift clocks, the set values (16-bit long operating parameters) to the register specified by the register number are serially transmitted.

The lower part of FIG. 63 describes the serial reception processing and subsequent serial transmission processing at the serial port SIO_1. A total of 16*2 shift clocks SCK are required for X-axis and Y-axis serial reception, and 8*16 shift clocks SCK are required for serial transmission of 8*16-bit control data MOSI, so operation at a baud rate of 250 kbps The processing time is 10*16/250k=0.645 mS, and all the processing is completed in about half of one cycle of the timer interrupt, which is 1 mS.

However, the effect control CPU 63 finishes the process only by starting the serial transmission process (R11) and does not wait for the completion of the serial transmission, so the process of steps R7 to R11 ends in an instant.

FIG. 64(a) shows stepping motors MO3 and MO4 driven by motor drivers DV3 and DV4, spiral shaft BAR rotationally driven by motors MO3 and MO4, and screw groove GV corresponding to the screw thread of spiral shaft BAR. A role object AMU provided together with a guide groove, and a guide member GD that grips the guide groove GV of the role object AMU and guides the linear movement of the role object AMU are illustrated.

Since the guide groove GV of the role object AMU is held so as to be linearly movable by the guide member GD, the role object AMU is linearly moved corresponding to the rotation of the spiral shaft BAR. Here, the spiral shaft BAR and the guide member GD are arranged in a hidden state in the vertical direction at the left and right positions of the game board. ing. In the illustrated example, the two character objects AMU, AMU are in a separated state and can be moved independently, but it is also suitable to connect the two character objects.

As described above, the stepping motors MO3 and MO4 are both 2-phase excited and the step angle θ is 7.5 degrees. From 360/7.5=48, each of the motors MO3 and MO4 rotates once upon receiving 48 step clocks CLK. On the other hand, the rotation pitch of the spiral shaft BAR rotating corresponding to the rotation of the motors MO3 and MO4 is 24 mm, and the character AMU moves by L=24 mm corresponding to one rotation of the motor.

Therefore, in order to achieve the movement distance TOTAL [mm], the number of rotations of the motor TOTAL/L=TOTAL/24 [times] is required, and the number of steps of the step clock CLK required for this rotation is TOTAL/24. *48=TOTAL*2. Here, assuming that the pulse speed of the stepping clock CLK is PS [PPS: pulse per second], the time required to output the number of steps TOTAL*2 is TOTAL*2/PS [seconds].

In this embodiment, the pulse speed PS of the stepping clock CLK can be stably output up to about 2900 pps. For example, when the pulse speed PS=2900 pps, the time T [seconds] required to achieve the movement distance TOTAL [mm] is TOTAL*2/PS=TOTAL/1450 [seconds] (Formula 1). The moving speed of the character object corresponding to the pulse speed PS=2900 pps is 2900/48*24=1450 mm/S in this embodiment, which is 1 m/S or more.

By the way, the free fall is not related to the weight of the substance, and the relation of fall distance=1/ ² *g*t2 is established. where g=gravitational acceleration and t=fall time. Therefore, for example, the time T required for free fall of 30 cm is T=SQR(0.6/9.8)≈0.247 seconds from 0.3=1/ ² *g*T2. Here, if TOTAL = 300 [mm] and the movement time of the character AMU is calculated, from the above equation 1, TOTAL / 1450 ≈ 0.207 [seconds], and according to this embodiment, the movement distance is about 30 cm If so, it is confirmed that the accessory AMU can be moved at a speed higher than that of free fall. In free fall, the falling speed when passing 51 cm is 1 m/s.

FIG. 64(b) is a drawing for explaining an example of a motor presentation by motor MO3 and/or motor MO4. showing. This operation consists of (1) return-to-origin operation, (2) standby operation, (3) rapid drop operation, (4) bound-up operation, and (5) bound-down operation.

First, the return-to-origin operation may use the operation mode (MD6) of moving in the CCW direction until sensor detection, but here, the operation mode (MD4) of positioning movement in the CCW direction is used. Next, the rapid drop operation uses the operation mode (MD3) for positioning movement in the CW direction. It goes without saying that an operation mode (MD5) in which movement is performed in the CW direction until sensor detection may be used.

In any case, since the operating speed of the rapid fall motion (3) is set to 2900 pps, the character object AMU moves at a speed faster than that of the free fall. The number of pulses set in the pulse number register RWV is 600 pulses, and the moving distance TOTAL is 600/48*24=300 mm. In addition, trapezoidal driving is employed, and a predetermined acceleration rate and deceleration rate are defined to ensure optimum acceleration and deceleration times. Therefore, troubles such as loss of synchronism do not occur even when moving at high speed.

For the subsequent bound-up operation (4) and bound-down operation (5), an operation mode (MD4) for positioning movement in the CCW direction and an operation mode (MD3) for positioning movement in the CW direction are used. Since the operating speed is low at about 500 pps, rectangular driving is adopted, and the number of steps is 50 pulses, producing a rebound motion of about 25 mm.

As described above, in this embodiment, by utilizing the motor controller 85, the control load of the effect control CPU 63 can be reduced, and complicated and sophisticated motor effects can be realized. In addition, even if the accessory is moved at high speed, it is possible to prevent situations such as step-out by securing acceleration time and deceleration time.

However, the motor drivers DV3 and DV4 used in this embodiment have the circuit configuration shown in FIG. 57 for their VREFA and VREFB terminals. NF cannot be controlled in multiple steps. On the other hand, since the upper limit current setting circuit LMT is provided, the upper limit current NF can be controlled at any timing by ON/OFF-controlling the electronic switch SW by the 1-bit long setting signal SET (FIG. 57). reference).

Therefore, in this embodiment, the upper limit current NF is set to the H level (473 mA) only when the performance of the character by the motor MO3 or MO4 is executed, and in the other standby state, the electronic switch SW is set to OFF to set the upper limit current NF. is maintained at L level (102 mA).

Further, in another embodiment, wasteful power consumption is suppressed by appropriately controlling the upper limit current NF even during the performance of the character. Specifically, the environment setting register RENV of the motor controller 85 is utilized to execute the countdown control shown in FIG. 60(d). As described above, the environment setting register RENV is configured so that the count-up time TCUP and the count-down time TCDW can be set.

Therefore, in this embodiment, when the start command is issued, the setting signal SET is changed to H level, the upper limit current NF is set to H level (473 mA), and the count-up time TCUP is set. to start the TCUP countdown operation. The motor controller 85 is configured so that the start command is not executed until the countdown operation is completed, and starts outputting a series of pulse trains after a predetermined waiting time (countdown time).

On the other hand, since the setting signal SET immediately transitions to H level in response to the issuance of the start command, the corresponding stepping motors MO3/MO4 change from the previous standby mode with the low upper limit current NF to the high upper limit current NF. It will shift to driving mode. However, at this timing, a new stepping clock CLK has not yet been output, so the motors MO3/MO4 remain stopped, but the drive in the stopped state shifts from low-current drive to high-current drive. becomes (see FIG. 58(c)).

After that, at the timing when the new stepping clock CLK is output, the motors MO3/MO4 rotate stepwise in a stable high-current driving state. At the start of rotation, a specified level of output torque is always required, but in this embodiment, since high current drive is started in advance, there is no shortage of output torque, and even objects with large inertia can be smoothly rotated. can be started at

After that, after the motors MO3/MO4 complete a predetermined rotation operation, a stop command is issued. After that, the effect control CPU 63 makes READ access to the environment setting register RENV every 1 ms, and if it is confirmed that the TCDW countdown operation is completed, the setting signal SET is changed to L level and the upper limit current NF is set to L. Drop to level (102mA). It is also preferable to activate interrupt processing in response to the end of the TCDW countdown operation. In this case, it is not necessary to make READ access to the environment setting register RENV every 1 ms.

In any case, the above-described countdown control is for reliably stabilizing the stopped state even when the inertia of the accessory is large. is stabilized. Note that the countdown control is executed mainly for the purpose of absorbing the inertia of the accessory AMU, so the countup time TCUP and the countdown time TCDW set in the environment setting register RENV correspond to the weight of the accessory AMU. Appropriately set. Also, instead of setting the count-up time TCUP in response to the start command, it is also possible to set the count-up time TCUP before issuing the start command. , output of the stepping clock CLK is started.

Although the embodiments of the present invention have been described above, the specific description does not particularly limit the present invention. For example, the CPU circuit 51 may directly control the drivers DV3 and DV4 without going through the motor driver 85 . In addition, in FIG. 63, an example in which the accessory AMU moves linearly corresponding to the rotation of the spiral shaft BAR has been described, but the present invention is not limited in any way, and a rack that is a circular gear and a flat plate material that meshes with the circular gear can be used. A transmission mechanism using a certain pinion may be used. Also, the movement of the accessory is not necessarily limited to linear movement. The character object may be rotated, or non-linear reciprocating movement of the character object, for example, reciprocating movement along an arc track is also suitable.

Also, trapezoidal drive suitable for high-speed operation and constant-speed operation (rectangular drive) with immediate start and stop suitable for low-speed operation, which has an acceleration time and a deceleration time, have been described, but the invention is not particularly limited. For example, a constant speed start operation with zero acceleration time and an immediate stop operation with zero deceleration time are also suitable. Moreover, although the trapezoidal drive which the motor controller 85 interposes was demonstrated, for example, in the structure of FIG.50(b), the production|presentation control CPU63 may perform not only a rectangular drive but a trapezoidal drive. The same applies to constant speed start operation and immediate stop operation.

GM game machine 51 effect control means (CPU circuit)
MO1 to MO4 production motor DV1 to DV4 driving means (motor driver)
OUTx, OUTy /LATCH pulse signal

Claims (10)

Effect control means for controlling a role product effect in which a character object moves in accordance with the rotation of the effect motor, and driving means for generating a drive signal based on the control data output by the effect control means and driving the effect motor. and
Based on a predetermined pulse signal, the effect motor is configured to rotate or stop,
The game machine, wherein the predetermined performance is configured such that the frequency of the pulse signal is maintained at a specified frequency, and then the performance is stopped after a deceleration time that gradually decreases. 2. The gaming machine according to claim 1, wherein the frequency of said pulse signal is provided with acceleration time for gradually increasing toward said specified frequency. 3. The game machine according to claim 2, wherein the increase in frequency during the acceleration time is defined by a predetermined acceleration rate. 4. The gaming machine according to any one of claims 1 to 3, wherein the frequency drop during the deceleration time is defined by a predetermined deceleration rate. The pulse signal is supplied from the production control means toward the driving means,
The game machine according to any one of claims 1 to 4, wherein the performance motor is configured to rotate by one step in response to the supply of one or more of the pulse signals. An intermediate control means for controlling the drive means under the control of the effect control means,
The game machine according to any one of claims 1 to 4, wherein said intermediate control means supplies said drive means with said pulse signal for advancing the rotational position of said performance motor by one step. 7. The gaming machine according to any one of claims 1 to 6, wherein during a predetermined effect, the accessory is linearly moved in correspondence with the rotation of the rotating shaft or the circular gear driven by the effect motor. The gaming machine according to any one of claims 1 to 7, wherein said specified frequency is set to 500 pps [pulse per second] or higher. 9. The game machine according to claim 7, wherein the movement speed of said linear movement is 1000 mm/s or more corresponding to said specified frequency of said pulse signal. The game machine according to any one of claims 1 to 9, wherein the performance motor is a bipolar stepping motor.

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