JP2022121541A5 - - Google Patents

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JP2022121541A5
JP2022121541A5 JP2022103237A JP2022103237A JP2022121541A5 JP 2022121541 A5 JP2022121541 A5 JP 2022121541A5 JP 2022103237 A JP2022103237 A JP 2022103237A JP 2022103237 A JP2022103237 A JP 2022103237A JP 2022121541 A5 JP2022121541 A5 JP 2022121541A5
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display list
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上記の目的を達成するため、本発明に係る遊技機は、表示装置の表示画面を特定するディスプレイリストを発行するCPU回路を有する画像制御手段と、前記CPU回路が設定した各種の内蔵レジスタへの設定値、及び、前記ディスプレイリストに基づく所定の画像データを、所定のRWメモリに生成する描画動作を実行する描画回路を有する画像生成手段と、前記画像データの基礎データを圧縮状態で記憶する所定のCGメモリと、を有する遊技機であって前記内蔵レジスタの何れかに、前記CPU回路が必要な設定値を設定することで、前記RWメモリを特別領域と確保領域とを含む複数の記憶領域に区画し、前記特別領域以外の記憶領域に、所定の二次元空間を確保する確保処理が、前記描画回路の描画動作に先行して実行され、前記ディスプレイリストには、前記描画回路の描画動作に対応して機能する、前記所定の二次元空間内部の矩形空間の基点位置を特定する第1情報と、前記ディスプレイリストに基づく描画内容のうち、前記矩形空間に反映される描画内容を規定する矩形描画範囲について、その対角位置の二端点を特定する第2情報と前記基礎データを取得すべき場合、前記基礎データの記憶位置及びデータサイズを特定する第3情報と、が記載されており、第1情報と第2情報によって、前記矩形描画範囲が、前記RWメモリの前記矩形空間に対応付けられることで前記ディスプレイリストに基づく描画内容が、前記矩形空間に反映されると共に、第3情報に基づいて取得される前記基礎データは、前記特別領域に取得された後、前記確保領域に展開されるよう構成され、前記画像生成手段は、所定の取得ビット単位で前記CPU回路から前記ディスプレイリストの構成データを受ける転送ポートと、前記転送ポートが受けた構成データを蓄積するFIFO構造のFIFOバッファとを有するデータ転送回路を有して構成され、前記画像制御手段は、前記画像生成手段に内蔵された一又は複数のステイタスレジスタに基づいて、前記データ転送回路が正常に機能していることを判定する判定手段と、限界時間又は限界判定回数を経過しても、判定手段による判定が正常とならない場合には、前記画像生成手段に内蔵された一又は複数のレジスタに初期化指示を設定して前記ディスプレイリストの発行を中止する中止手段、とを有して構成されている。 In order to achieve the above object, the gaming machine according to the present invention provides image control means having a CPU circuit for issuing a display list specifying a display screen of a display device ; image generating means having a drawing circuit for executing a drawing operation to generate predetermined image data based on the set values and the display list in a predetermined RW memory; and a CG memory , wherein the RW memory is a plurality of memories including a special area and a reserved area by setting a setting value required by the CPU circuit in any of the built-in registers. Securing processing for partitioning into areas and securing a predetermined two-dimensional space in a storage area other than the special area is executed prior to the drawing operation of the drawing circuit, and the display list includes the drawing of the drawing circuit. First information specifying a base point position of a rectangular space within the predetermined two-dimensional space, which functions in response to an action, and defining the drawing content to be reflected in the rectangular space among the drawing content based on the display list. 2nd information specifying the two corner points of the diagonal position of the rectangular drawing range, and 3rd information specifying the storage position and data size of the basic data when the basic data is to be acquired. By associating the rectangular drawing range with the rectangular space of the RW memory by means of the first information and the second information, the drawing contents based on the display list are reflected in the rectangular space. 3 The basic data acquired based on the information is configured to be acquired in the special area and then developed in the reserved area, and the image generating means extracts the basic data from the CPU circuit in units of predetermined acquired bits. a data transfer circuit having a transfer port for receiving configuration data of a display list and a FIFO buffer having a FIFO structure for accumulating the configuration data received by the transfer port; determination means for determining whether the data transfer circuit is functioning normally based on one or more status registers built in the device; canceling means for setting an initialization instruction in one or a plurality of registers incorporated in the image generating means to stop issuing the display list when the display list is not normalized.

Claims (1)

表示装置の表示画面を特定するディスプレイリストを発行するCPU回路を有する画像制御手段と、前記CPU回路が設定した各種の内蔵レジスタへの設定値、及び、前記ディスプレイリストに基づく所定の画像データを、所定のRWメモリに生成する描画動作を実行する描画回路を有する画像生成手段と、前記画像データの基礎データを圧縮状態で記憶する所定のCGメモリと、を有する遊技機であって
前記内蔵レジスタの何れかに、前記CPU回路が必要な設定値を設定することで、前記RWメモリを特別領域と確保領域とを含む複数の記憶領域に区画し、前記特別領域以外の記憶領域に、所定の二次元空間を確保する確保処理が、前記描画回路の描画動作に先行して実行され、
前記ディスプレイリストには、
前記描画回路の描画動作に対応して機能する、前記所定の二次元空間内部の矩形空間の基点位置を特定する第1情報と、前記ディスプレイリストに基づく描画内容のうち、前記矩形空間に反映される描画内容を規定する矩形描画範囲について、その対角位置の二端点を特定する第2情報と前記基礎データを取得すべき場合、前記基礎データの記憶位置及びデータサイズを特定する第3情報と、が記載されており、
第1情報と第2情報によって、前記矩形描画範囲が、前記RWメモリの前記矩形空間に対応付けられることで前記ディスプレイリストに基づく描画内容が、前記矩形空間に反映されると共に、第3情報に基づいて取得される前記基礎データは、前記特別領域に取得された後、前記確保領域に展開されるよう構成され、
前記画像生成手段は、
所定の取得ビット単位で前記CPU回路から前記ディスプレイリストの構成データを受ける転送ポートと、前記転送ポートが受けた構成データを蓄積するFIFO構造のFIFOバッファとを有するデータ転送回路を有して構成され、
前記画像制御手段は、
前記画像生成手段に内蔵された一又は複数のステイタスレジスタに基づいて、前記データ転送回路が正常に機能していることを判定する判定手段と、
限界時間又は限界判定回数を経過しても、判定手段による判定が正常とならない場合には、前記画像生成手段に内蔵された一又は複数のレジスタに初期化指示を設定して前記ディスプレイリストの発行を中止する中止手段、とを有して構成されていることを特徴とする遊技機。
image control means having a CPU circuit that issues a display list specifying a display screen of a display device ; setting values for various built-in registers set by the CPU circuit; and predetermined image data based on the display list, A gaming machine comprising: image generation means having a drawing circuit for executing a drawing operation to be generated in a predetermined RW memory; and a predetermined CG memory for storing basic data of the image data in a compressed state ,
By setting a setting value required by the CPU circuit in any of the built-in registers, the RW memory is partitioned into a plurality of storage areas including a special area and a reserved area, and storage areas other than the special area are divided. , securing processing for securing a predetermined two-dimensional space is executed prior to the drawing operation of the drawing circuit;
The display list contains
first information specifying a base point position of a rectangular space within the predetermined two-dimensional space, which functions corresponding to the drawing operation of the drawing circuit; second information specifying the two corner points of the diagonal positions of the rectangular drawing range defining the drawing content; and third information specifying the storage location and data size of the basic data when the basic data is to be acquired. and are described,
By associating the rectangular drawing range with the rectangular space of the RW memory by the first information and the second information, the drawing contents based on the display list are reflected in the rectangular space, and the third information. The basic data acquired based on is configured to be expanded in the reserved area after being acquired in the special area,
The image generation means is
comprising a data transfer circuit having a transfer port for receiving the configuration data of the display list from the CPU circuit in units of predetermined acquired bits, and a FIFO buffer having a FIFO structure for storing the configuration data received by the transfer port. ,
The image control means is
determination means for determining whether the data transfer circuit is functioning normally based on one or more status registers incorporated in the image generation means;
When the determination by the determination means is not normal even after the limit time or the number of limit determinations has passed, an initialization instruction is set in one or a plurality of registers built in the image generation means, and the display list is issued. and a stopping means for stopping the gaming machine.
JP2022103237A 2019-09-10 2022-06-28 game machine Active JP7325583B2 (en)

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JP2019164671A JP7097862B2 (en) 2019-09-10 2019-09-10 Pachinko machine
JP2022103237A JP7325583B2 (en) 2019-09-10 2022-06-28 game machine

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JP2022121541A JP2022121541A (en) 2022-08-19
JP2022121541A5 true JP2022121541A5 (en) 2022-10-26
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JP4663660B2 (en) 2007-01-11 2011-04-06 株式会社三共 Game machine
JP6296013B2 (en) * 2015-07-21 2018-03-20 株式会社三洋物産 Game machine
JP6761647B2 (en) 2016-03-04 2020-09-30 株式会社三共 Slot machine
JP6680436B2 (en) 2018-04-17 2020-04-15 株式会社藤商事 Amusement machine
JP6827024B2 (en) 2018-10-24 2021-02-10 株式会社藤商事 Game machine
JP6872521B2 (en) 2018-11-28 2021-05-19 株式会社藤商事 Pachinko machine

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