JP2022119180A - Antenna device and camera system - Google Patents

Abstract

To provide an antenna device that operates satisfactorily with reduced parasitic oscillation.SOLUTION: An antenna device of the present disclosure has: an antenna array in which a plurality of antennas is arranged each consisting of a negative differential resistance element and a resonance circuit; a voltage bias circuit that applies a voltage to the antenna array; a first shunt element that is connected in parallel with the negative differential resistance elements and the voltage bias circuit between the antenna array and the voltage bias circuit and has a first resistance and a first capacity connected in series thereto; and a second shunt element that is connected in parallel with the negative differential resistance elements and the voltage bias circuit between the first shunt element and the voltage bias circuit and has a second resistance and a second capacity connected in series thereto. The first shunt element and the second shunt element have a lower impedance with reference to a value of resistance of the negative differential resistance elements.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to an antenna device and a camera system that transmit or receive electromagnetic waves.

An antenna composed of a negative differential resistance element and a resonance circuit generates electromagnetic waves (hereinafter simply referred to as "terahertz waves") including at least part of the frequency band from millimeter waves to terahertz waves (30 GHz or more and 30 THz or less). can be made As an example, Patent Document 1 discloses an antenna that integrates a negative differential resistance element and a resonance circuit on a semiconductor chip and emits terahertz waves.

In Patent Document 1, a resonant tunneling diode (RTD) is used as a negative differential resistance element, and a power supply for supplying a bias voltage to the negative differential resistance element is provided. A bias voltage from a power supply is supplied to the negative resistance element through a bias supply section including wires and conductors. Parasitic low-frequency oscillation (parasitic oscillation) other than the terahertz wave emitted by the antenna is often caused by the structure associated with the bias supply section. Therefore, Patent Document 1 discloses a technique for suppressing parasitic oscillation by arranging a shunt element in a bias supply section.

JP 2015-180049 A

As a means for increasing the antenna output, a plurality of antennas each having a negative differential resistance element and a resonance circuit are arranged to form an antenna array. When a chip with an integrated antenna array is mounted on another substrate such as a ceramic package or printed circuit board, the chip and substrate are connected with bonding wires, and a shunt element is placed on the substrate to suppress parasitic oscillation.

The bonding wire and the resistance and capacitance forming the shunt element have parasitic inductance. This parasitic inductance cannot be ignored when normally generating a terahertz wave, and causes parasitic oscillation at a frequency lower than that of the terahertz wave (less than 30 GHz). This parasitic inductance is particularly likely to cause parasitic oscillations from 10 MHz to 10 GHz. In order to normally oscillate terahertz waves in such an antenna array, it is necessary to optimize the circuit parameters and arrangement of the shunt elements on the substrate.

Accordingly, an object of the present disclosure is to provide a technology for suppressing parasitic oscillation in an antenna device having an antenna array composed of a negative differential resistance element and a resonance circuit.

In order to achieve the above object, the antenna device according to the present disclosure includes:
An antenna device for transmitting or receiving electromagnetic waves,
An antenna array in which a plurality of antennas each comprising a negative differential resistance element and a resonant circuit are arranged;
a voltage bias circuit that applies a voltage to the antenna array;
A first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, wherein the first resistor and the first shunt element of the first shunt element a first shunt element having one capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second resistance of the second shunt element and a second shunt element in which the second capacitor is connected in series;
has
The antenna device is characterized in that the first shunt element and the second shunt element have a low impedance with respect to the resistance value of the negative differential resistance element.

Further, the antenna device according to the present disclosure is
An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas composed of negative differential resistance elements and resonant circuits are arranged;
a substrate on which the chip is arranged;
a voltage bias circuit that applies a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit and including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitor, disposed on the substrate;
An antenna device is included, wherein the antenna array is positioned between the first pad and the second pad.
Further, the camera system according to the present disclosure is
the above antenna device;
a detection device for detecting electromagnetic waves transmitted from the antenna device;
a camera system having a processor for processing signals from the detector.

According to the technique of the present disclosure, it is possible to provide an antenna device and a camera system that optimize the configuration of the shunt element, suppress parasitic oscillation, and operate satisfactorily.

An example of a plan view of the antenna device according to the first embodiment An example of a cross-sectional view of the antenna device according to the first embodiment An example of a cross-sectional view of the antenna device according to the first embodiment Explanatory drawing showing the antenna array according to the first embodiment Equivalent circuit diagram of the antenna device according to the first embodiment Graphs for explaining the antenna device according to the first embodiment Graphs for explaining the antenna device according to the first embodiment A diagram for explaining an antenna device according to a first embodiment. A diagram for explaining an antenna device according to a first embodiment. An example of a plan view of an antenna device according to a second embodiment An example of a plan view of an antenna device according to a third embodiment An example of a plan view of an antenna device according to a fourth embodiment An example of a plan view of an antenna device according to a fourth embodiment An example of a plan view of an antenna device according to a fourth embodiment An example of a plan view of an antenna device according to a fifth embodiment An example of a plan view of an antenna device according to a fifth embodiment Equivalent circuit diagram of the antenna device according to the sixth embodiment Explanatory diagram showing an antenna array according to the sixth embodiment An example of a cross-sectional view of an antenna device according to a sixth embodiment Explanatory drawing showing an antenna array according to a modified example of the sixth embodiment An example of a cross-sectional view of an antenna device according to a modified example of the sixth embodiment An example of a plan view of an antenna device according to a fourth embodiment FIG. 12 is a schematic diagram for explaining a camera system according to a seventh embodiment; FIG.

Embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to the following embodiments, and can be modified as appropriate without departing from the scope of the present disclosure. In addition, in the drawings described below, the same reference numerals are assigned to elements having the same function, and the description thereof may be omitted or simplified.

(First embodiment)
An antenna device according to a first embodiment will be described with reference to FIGS. 1 to 9. FIG. FIG. 1 is a plan view showing a schematic configuration of an antenna device according to this embodiment. FIG. 2 is a cross-sectional view taken along line AA' of FIG.

As shown in FIGS. 1 and 2, the antenna device 100 according to the present embodiment has a rectangular chip 11 on which an antenna array 12 composed of a plurality of antennas 121 is mounted on a substrate 10 . FIG. 1 shows the configuration on the surface of the chip 11. As shown in FIG. Although details of the antenna 121 will be described later, the antenna 121 includes a negative differential resistance element and a resonance circuit, and transmits or receives electromagnetic waves in the terahertz frequency band. Antenna 121 generates electromagnetic waves (hereinafter simply referred to as “terahertz waves”) including at least part of the frequency band from millimeter waves to terahertz waves (30 GHz to 30 THz). Adjacent antennas 121 are capacitively coupled by a microstrip line (described later with reference to FIG. 4).

Chip 11 includes antenna array 12 , resistor element 131 and capacitor element 132 forming first shunt element 1300 , pad 141 for applying bias voltage to chip 11 , and pad 142 for applying ground voltage to chip 11 . The pads 141 and 142 are for electrical connection with circuits outside the chip 11, for example, for supplying a predetermined voltage from the outside. Pads 141 and 142 are made of a conductor. Hereinafter, pads are for electrical connection with the outside. Specifically, the pad is for receiving a predetermined voltage from the outside, and may be for supplying a predetermined voltage to the outside. In this embodiment, the predetermined voltage can be a ground voltage, a power supply voltage, a voltage from a voltage bias circuit, or the like.

The antenna array 12 is arranged substantially in the center of the chip 11 , and the capacitive element 132 is arranged adjacent to the antenna array 12 . In addition, by arranging the capacitive element 132 so as to surround the antenna array 12, it is possible to expand the arrangement area of the capacitive element on the chip 11 and secure a large capacity. In addition, the capacitive elements 132 are arranged so that the antenna array 12 is sandwiched between the capacitive elements 132 on each side of two opposing sides of the chip 11 (the right side and the left side of the chip 11 in the figure). As a result, the resistor element 131, wiring, pads, and the like can be arranged in a portion where the capacitive element 132 is not arranged (upper side of the chip 11 in the drawing), so that the chip size of the chip 11 can be reduced.

As shown in FIG. 2, one terminal of the resistive element 131 is connected to one terminal of the capacitive element 132 through the wiring 133 and the via 134 . The resistance element 131 and the capacitance element 132 are connected in series, and the resistance element 131 is preferably arranged near the capacitance element 132 in order to easily arrange the connection. Alternatively, the resistive element 131 may be arranged to overlap the capacitive element 132 . The other terminal of resistive element 131 is connected to pad 141 via bias voltage line 130 . The bias voltage line 130 is also arranged between the antennas 121 of the antenna array 12 and commonly connected to each antenna 121 to apply a bias voltage to each antenna 121 . The other terminal of the capacitive element 132 is connected to the pad 142 via wiring and vias (not shown).

As the capacitive element 132, an MIM (Metal-Insulator-Metal) capacitor in which an insulating layer is sandwiched between metal layers can be used. A wiring layer in the chip 11 can be used as the metal layer, and an insulating layer or a dielectric layer forming an antenna can be used as the insulating layer. According to this embodiment, as shown in FIG. 2, a ground metal layer 124 is used as one electrode of the MIM capacitor, and the ground metal layer 124 is connected to a pad 142 that applies a ground voltage. A metal layer 135 is formed via an insulating layer as the other electrode of the MIM capacitor. Metal layer 135 is connected to wiring 133 through via 134 . By configuring the MIM capacitor in this way, the capacitor can be formed in the chip by a simple manufacturing process.

In addition to the above configuration, it is also possible to form a capacitor on a substrate different from the chip 11 and attach it to the front surface or the back surface of the chip 11. According to this configuration, a capacitive element with a larger capacity can be provided. is possible.

In the first shunt element 1300, the resistive element 131 is connected to the pad 141 applying the bias voltage, and the capacitive element 132 is connected to the pad 142 applying the ground voltage. However, the connection relationship may be reversed so that the resistance element 131 is connected to the pad 142 to which the ground voltage is applied and the capacitance element 132 is connected to the pad 141 to which the bias voltage is applied.

Preferably, 20 to 40 antennas are arranged on the chip 11 as the antennas 121 of the antenna array 12 . Also, the number of pads 141 for applying a bias voltage and the number of pads 142 for applying a ground voltage are made smaller than the number of antennas. As a result, the space of the chip 11 can be effectively used and the chip 11 can be made smaller. Furthermore, if the number of sets of resistance elements 131 and capacitive elements 132 is equal to or less than the number of pads 141 for applying a bias voltage or equal to or less than the number of pads 142 to apply a ground voltage, the space of the chip 11 can be effectively used. can be used to make the chip 11 smaller.

The substrate 10 also includes a resistor element 151 and a capacitor element 152 that constitute the second shunt element 1500 , pads 161 for connecting with the pads 141 of the chip 11 , and pads 162 for connecting with the pads 142 of the chip 11 . Pads 161 and 162 are for electrical connection with circuits outside chip 11 . Pads 161 and 162 are made of a conductor. Here, the external circuit is the chip 11 . It also has a connection terminal 181 to which a bias voltage is supplied from the voltage bias circuit 17 and a connection terminal 182 to which a ground voltage is applied. For miniaturization of the substrate 10, it is preferable to use surface mount devices (SMD) as the resistance element 151 and the capacitance element 152. FIG. Since the wiring arranged on the substrate 10 also has a resistance value, the resistance of the wiring on the substrate 10 included in the path connecting the first shunt element 1300 and the second shunt element 1500 may be used as the resistance element 151. . As a result, the number of parts used in the chip 11 can be reduced, and the size of the chip 11 can be reduced. Here, the connection terminals 181 and 182 may be pads.

The voltage bias circuit 17 is connected from the outside of the substrate 10 via connection terminals 181 and 182 . Note that instead of this configuration, the voltage bias circuit 17 may be arranged on the substrate 10 or may be arranged on the chip 11 .

Pads 141 of chip 11 and pads 161 of substrate 10 are connected by bonding wires 191 . Pads 142 of chip 11 and pads 162 of substrate 10 are connected by bonding wires 192 . In order to reduce the inductance of bonding wires 191 and 192, pads 141 and 161 as well as pads 142 and 162 are preferably arranged close to each other to shorten the length of bonding wires 191 and 192. FIG.

In order to shorten the bonding wires 191 and 192 , the pads 141 and 142 should be arranged at the edge of the chip 11 . Also, the pads 141 and 161 are preferably arranged facing each other with the side of the chip 11 interposed therebetween. Also, the pads 142 and the pads 162 are preferably arranged facing each other with the side of the chip 11 interposed therebetween.

One terminal 1512 of the resistance element 151 is connected to one terminal 1521 of the capacitance element 152 through the wiring 157 . That is, the resistive element 151 and the capacitive element 152 are connected in series. Therefore, it is preferable to arrange the resistor element 151 and the capacitor element 152 close to each other. More preferably, one terminal 1512 of the resistive element 151 is arranged adjacent to one terminal 1521 of the capacitive element 152 . Thereby, the length of the wiring 157 can be shortened and the inductance can be reduced.

The other terminal 1511 of the resistance element 151 is connected to the pad 161 via the wiring 153 and connected to the connection terminal 181 via the wiring 154 . Further, the other terminal 1522 of the capacitive element 152 is connected to the pad 162 via the wiring 155 and connected to the connection terminal 182 via the wiring 156 . It is preferable that the direction in which the terminals 1511 and 1512 of the resistance element 151 and the terminals 1521 and 1522 of the capacitance element 152 are aligned is the same as the direction in which the pads 161 and 162 are aligned. With such an arrangement, the wiring for connection can be shortened, and the inductance can be reduced.

In the second shunt element 1500, the resistive element 151 is connected to a connection terminal 181 for applying a bias voltage, and the capacitive element 132 is connected to a connection terminal 182 for applying a ground voltage. However, the connection relationship may be reversed so that the resistive element 131 is connected to the connection terminal 182 to which the ground voltage is applied and the capacitive element 132 is connected to the connection terminal 181 to which the bias voltage is applied.

In this embodiment, an example is assumed in which the first shunt element 1300 and the second shunt element 1500 are composed of resistive elements 131 and 151 and capacitive elements 132 and 152, respectively. However, the first shunt element and the second shunt element may be composed of either a resistive element or a capacitive element. When the shunt element is provided with a capacitive element, it is possible not only to suppress parasitic oscillation but also to suppress power consumption by cutting direct current using the frequency characteristics of impedance.

As for the positional relationship of the components of the antenna device 100 , the first shunt element 1300 is arranged between the antenna array 12 and the voltage bias circuit 17 , and the second shunt element 1300 is arranged between the first shunt element 1300 and the voltage bias circuit 17 . A shunt element 1500 is placed.

FIG. 3 is a partial cross-sectional view of the antenna device 100 for explaining a configuration in which pads are formed on the back surface of the chip 11 and the chip 11 and the substrate 10 are connected without using the bonding wire 19. As shown in FIG. According to FIG. 3, the wiring on the surface of the chip 11 is connected to the pad 141 on the back surface of the chip 11 via the through electrode 135 .

The through electrode 135 is formed by forming a through hole in the chip 11 and then forming an insulating film on the inner wall of the through hole for electrical isolation. is formed by filling the through holes with Also, the through electrode 135 is smoothed using a CMP (Chemical Mechanical Polishing) process or the like. Penetration electrode 135
, a pad 141 is formed on the rear surface of the chip 11 so as to be electrically connected to the through electrode 135 .

The pads 141 on the back surface of the chip 11 and the pads 161 on the substrate 10 are arranged so as to overlap and are connected by soldering or the like. Since no bonding wire is used when the through electrode 135 is used for electrical connection, the inductance is reduced and parasitic oscillation in the antenna device 100 can be easily suppressed.

FIG. 4 is an explanatory diagram showing the antenna array 12 in this embodiment. 4A is a top view of the antenna array 12, and FIG. 4B is a cross-sectional view of the antenna array 12 along line B-B' in FIG. 4A. In the drawing, two antennas 121 and 122 included in the antenna array 12 are shown as an example.

Generally, in an antenna array for the purpose of power combining, the distance between individual antennas is set to be equal to or less than the wavelength of oscillating electromagnetic waves in vacuum, or an integral multiple of the wavelength, more preferably half the wavelength or less. In this embodiment, the antennas 121 and 122 are arranged such that the antenna spacing is equal to or less than half the wavelength of the transmitted electromagnetic waves.

In the antenna array 12, oscillation is performed by a microstrip resonator composed of a metal layer 123, a dielectric layer 128, which is a first conductor forming part of the antenna, and a ground metal layer 124, which is a second conductor forming a part of the antenna. A resonance circuit 1200 is configured to control the frequency. Antennas 121 and 122 are composed of this resonant circuit 1200 and a negative differential resistance element 127 . A bias voltage line 130 is connected to the metal layer 123 via a via 135 to apply a bias voltage to the negative differential resistance element 127 . Negative differential resistance element 127 produces electromagnetic wave gain to sustain oscillation. Since the individual antennas 121 and 122 oscillate synchronously in phase, they are designed to have an oscillation frequency ω ₀ close to that. Therefore, it is preferable that the shapes of the individual antennas including the half-wave resonators are similar to each other. It is preferable to use the same shape and characteristics as the negative differential resistance element 127 . The microstrip line 125 is an inter-element structure for synchronizing and oscillating the individual antennas as described above in phase with each other.

The microstripline 125, which is the transmission line of the metal part forming the link structure, is arranged so that the length along the microstripline 125 from one end to the other end is 2π in electrical length at the oscillation frequency _ω0 after synchronization. preferably selected. The electrical length of 2π is the length corresponding to the effective oscillation wavelength λ ₀ converted by the effective dielectric constant of the surrounding structure. The reason why 2π is selected as the electrical length is to oscillate the antennas 121 and 122 in synchronization with each other in the same phase. When the antennas 121 and 122 are synchronized in antiphase, the electrical length may be π or 3π. Synchronization of the antennas 121, 122 is possible even though the length of the microstrip line 125 is not exactly 2π. Although it depends on the magnitude of the coupling between the elements formed by the microstrip line 125, an electrical length of about 2π±10% is typically an allowable range. This allowable range is wider than when the microstrip line 125 is not used for coupling. The electrical length of the microstrip line can be easily confirmed using an electromagnetic field simulator or the like.

A part of the oscillation output of the antenna 121 is input to the adjacent antenna 122 via the microstrip line 125 in substantially the same phase. On the other hand, part of the oscillation output of the antenna 122 is input to the adjacent antenna 121 via the microstrip line 125 in substantially the same phase. In the antenna array of this embodiment, a microstrip line 125 is introduced in order to realize such a mutual injection locking phenomenon between the antennas 121 and 122 .

The microstrip line 125 of this embodiment is characterized by being capacitively coupled with the metal layer 123 of the resonant structure. They only form capacitance through insulating layer 129 in metal-insulator-metal (MIM) region 126 and are DC open. As a result, in the band of the oscillation frequency _ω0 , the magnitude of the inter-antenna coupling can be secured as large as in the direct coupling. Furthermore, since the magnitude of coupling is small in a low frequency region smaller than ω ₀ , isolation between antennas can be ensured. The microstripline 125 of this embodiment is preferable because it has such properties. Furthermore, the open-ended microstripline 125 becomes a capacitive element in the low frequency region below ω ₀ . As seen from the negative differential resistance element 127 on the antenna 121 side, the microstrip line 125 is a capacitive element, and the metal layer 123 of the resonant structure on the antenna 122 side is also a capacitor. Therefore, the resonance frequency itself, which is a concern in the low frequency region, is not generated. Therefore, it is possible to suppress parasitic oscillation in the low frequency region.

Although two separate antennas 121, 122 are described in FIGS. 4A and 4B, the antenna array 12 can be arrayed by placing each antenna in a configuration similar to antennas 121, 122. FIG. A plurality of metal layers 123 corresponding to the number of arrays are arranged on the ground metal layer 124 via a dielectric layer 128, and negative differential resistance elements 127 corresponding to the metal layers 123 are arranged. be. Adjacent antennas are capacitively coupled by microstripline 125 . Also, the electrical length of each microstrip line 125 is about 2π. Therefore, all the negative differential resistance elements 127 can be synchronized in phase. By forming an antenna array in this way, not only is the combined power increased, but sharp directivity is obtained, which is preferable.

A plurality of metal layers 123 are connected in common via strip conductors (not shown) inside the chip 11 and are connected to pads 141 to which a bias voltage is applied. is connected to the pad 142 at . With this configuration, a bias voltage is applied to the negative differential resistance element 127 when a voltage is applied to the pads 141 and 142 .

A resonant tunneling diode lattice-matched to the InP substrate can be used as the negative differential resistance element 127 . The negative differential resistance element 127 is not limited to the resonant tunneling diode, and may be an Esaki diode or a Gunn diode. Resonant tunneling diodes are constructed, for example, with multiple quantum well structures of InGaAs/InAlAs, InGaAs/AlAs on an InP substrate and electrical contact layers of n-InGaAs. For example, a triple barrier structure is used as the multiple quantum well structure. More specifically, AlAs (1.3
nm)/InGaAs (7.6 nm)/InAlAs (2.6 nm)/InGaAs (5.
6 nm)/AlAs (1.3 nm). Of these, InGa
As is a well layer, and lattice-matched InAlAs or non-matched AlAs is a barrier layer. These layers are intentionally undoped without carrier doping. Such a multiple quantum well structure is sandwiched between electrical contact layers of n-InGaAs with an electron concentration of 2×10 ¹⁸ cm ⁻³ . In the current-voltage (I/V) characteristics of the structure between these electrical contact layers, the peak current density is 280 kA/cm ² and the negative resistance region is from about 0.7V to about 0.9V. As for the configuration of the diode, in the case of a mesa structure with a diameter of 2 μm, a peak current value of 10 mA and a negative resistance value of −20Ω are obtained. Considering the reactance associated with the junction capacitance of the resonant tunneling diode with a diameter of 2 μm connected to the bottom of the metal layer 123, the oscillation frequency is approximately 0.55 THz.

Next, FIG. 5 shows an equivalent circuit diagram of the antenna device according to this embodiment. The equivalent circuit of the chip 11 has a resistance r (r indicates the absolute value of the resistance of the negative differential resistance element) of the negative differential resistance element forming the antenna array 12 . Also, the equivalent circuit of the chip 11 has the impedance Z of the resonance circuit 1200 forming the antenna array 12 and the resistance Rc of the resistive element 131 forming the first shunt element 1300 . Furthermore, the equivalent circuit of chip 11 has capacitance Cc of capacitive element 132 that constitutes first shunt element 1300 .

The first shunt element 1300 is configured by connecting a resistor Rc and a capacitor Cc in series. Furthermore, the resistor r, the impedance Z of the resonance circuit 1200, and the first shunt element 1300 are connected in parallel with each other. More specifically, one terminal of the resistor r, one terminal of the impedance Z of the resonant circuit 1200, and one terminal of the resistor Rc are each connected to the first node n1. Also, the other terminal of the resistor Rc is connected to one terminal of the capacitor Cc. The other terminal of the resistor r, the other terminal of the impedance Z of the resonance circuit 1200, and the other terminal of the capacitor Cc are connected to the ground voltage. The first node n1 is connected to the pad 141 of the chip 11 and the ground voltage is applied through the pad 142 of the chip 11. FIG.

The equivalent circuit of the substrate 10 includes the resistance Rp of the resistance element 151 and the capacitance Cp of the capacitance element 152 that constitute the second shunt element 1500, and the inductance L of the path that connects the first shunt element 1300 and the second shunt element 1500. , consists of The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, and the pad.

The second shunt element 1500 is configured by connecting a resistor Rp and a capacitor Cp in series. Further, chip 11 and second shunt element 1500 are connected via inductance L. FIG. More specifically, one terminal of the inductance L is connected to the first node n1 in the equivalent circuit of the chip 11, and the other terminal of the inductance L and one terminal of the resistor Rp are connected to the second node n2. Also, the other terminal of the resistor Rp is connected to one terminal of the capacitor Cp. A ground voltage is applied to the other terminal of the capacitor Cp. Furthermore, the second node n2 is connected to the terminal 181, and the voltage bias circuit V is connected. Therefore, a bias voltage is applied to the second node n2, and a bias voltage is applied to the resistor r through the inductance L. FIG.

The first shunt element 1300 (resistance Rc and capacitance Cc) is connected in parallel with the negative differential resistance element (resistance r), and is also connected in parallel with the second shunt element 1500 (resistance Rp and capacitance Cp) via the inductance L. It is connected to the. Furthermore, the first shunt element 1300 is also connected in parallel with the voltage bias circuit V. FIG.

In order to suppress parasitic oscillation in such an antenna device, it is preferable that first shunt element 1300 and second shunt element 1500 have low impedance with resistance r of negative differential resistance element 127 as a reference. That is, it is preferable to set the impedance to be low when viewed from the negative differential resistance element 127 in a frequency band smaller than the terahertz frequency band. In this case, the following conditional expressions (1) and (2) hold.
Rp+1/(2π×f×Cp)<r (1)
Rc+1/(2π×f×Cc)<r (2)
Here, r is the absolute value of the resistance value of the negative differential resistance element, Rc is the resistance value of the resistor Rc, which is the first resistor, and Cc is the capacitance value of the capacitor Cc, which is the first capacitor. Rp is the resistance value of the resistor Rp, which is the second resistor, Cp is the capacitance value of the capacitor Cp, which is the second capacitor, and L is the path connecting the first shunt element 1300 and the second shunt element 1500. is the inductance of Also, f is the frequency of the target parasitic oscillation, which is less than the resonant frequency of the resonant circuit forming the antenna array 12 . Further, the frequency f is specifically less than 30 GHz, but is particularly in the range of 10 MHz to 10 GHz when the chip 11 is mounted on the substrate 10 as in this embodiment.

However, even if the formulas (1) and (2) hold, LC resonance may occur in the inductance L and the capacitance Cc. In order to suppress this LC resonance, it is necessary to secure Rc, and it is preferable to reduce L and increase Cc, because the oscillation energy is lost. Therefore, in order to suppress the parasitic oscillation, the following conditional expression (3) also holds.
L/(Cc×r) <Rc (3)

FIG. 6 is a graph showing frequency characteristics of impedance seen from the negative differential resistance element 127 when the value of the inductance L is changed based on the equivalent circuit of FIG. The dashed line shows the characteristics for L=1 nH, the solid line shows the characteristics for 5 nH, and the one-dot chain line shows the characteristics for 10 nH, and the impedance has a peak value at a specific frequency. Specifically, L=1 nH has a peak value of 1.8 Ω at 160 MHz, L=5 nH has a peak value of 16.8 Ω at 50 MHz, and L=10 nH has a peak value of 8.5 Ω at 71 MHz.

FIG. 7 is a graph showing the relationship between the inductance L and the peak value of the impedance viewed from the negative differential resistance element 127, based on the frequency characteristics of FIG. According to FIG. 7, the peak value of impedance increases as the inductance L increases.

At the frequency f of the parasitic oscillation to be suppressed, if the impedance of the line seen from the negative differential resistance element 127 is 10 times or less than the absolute value of the negative differential resistance element 127, the gain of the negative differential resistance element 127 is Therefore, the magnitude of loss due to the line cannot be ignored. Oscillation of LC resonance can be suppressed by this. As an example, in an antenna array with a chip size of 3 mm square to 4 mm square, 20 to 40 antennas can be arranged, and the combined resistance value of the negative differential resistance 127 is at most 1 Ω, that is, 1 Ω or less. Become. Therefore, parasitic oscillation can be suppressed if the resistance is 10Ω or less, which is ten times the resistance value. That is, according to the graph of FIG. 7, it is sufficient if L≦5 nH.

The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, and the pad. These inductances of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated by the following equations (4) and (5), respectively. In the path connecting the first shunt element 1300 and the second shunt element 1500, the portion where the cross section can approximate a circle is calculated by Equation (4), and the portion where the cross section can approximate a square is calculated by Equation (5).
L1=0.2×l1×[ln(4×l1/d)−0.75] [nH] (4)
L2=0.2×l2×[ln{2×l2/(w+h)}+0.2235×(w+h)/l2+0.5] [nH] (5)
Here, l1 is the length (mm) of the portion of the path whose cross section can approximate a circle, and d is its cross-sectional diameter (mm). In addition, l2 is the length (mm) of the portion of the path whose cross section can approximate a square, w is its width (mm), and h is its thickness (mm).

FIG. 8 is a diagram for explaining the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500 in this embodiment. The path connecting the first shunt element 1300 and the second shunt element 1500 includes wiring (first portion P1) connecting the resistance element 131 and the pad 141 constituting the first shunt element 1300, pad 141 (second portion P2). Further, the path includes bonding wire 19 (third portion P3), pad 161 (fourth portion P4), wiring (fifth portion P5).

The length of the path connecting the first shunt element 1300 and the second shunt element 1500 is preferably 4 mm or less, which is suitable for reducing parasitic inductance and suppressing parasitic oscillation. More preferably, it is 2 mm or less.

An example of the dimensions of each part in the path and the inductance calculated by Equation (4) or Equation (5) will be described below.

The first portion P1 has a length of 0.3 mm, a width of 0.2 mm, and a thickness of 0.5 μm, and the inductance L1 of this region is 0.1 nH as calculated by Equation (5).

The inductance L2 of the second portion P2 is calculated as the area from the end of the pad 141 to the substantially central portion of the pad 141 to which the bonding wire 19 is connected. This region has a length of 0.1 mm, a width of 0.2 mm, and a thickness of 0.5 μm.

The third portion P3 is a bonding wire with a length of 1.0 mm and a cross-sectional diameter of 20 μm, and the inductance L3 of this region is 0.91 nH as calculated by Equation (4).

The inductance L4 of the fourth portion P4 is calculated as a region from the end of the pad 161 to the substantially central portion of the pad 161 to which the bonding wire 19 is connected. This region has a length of 0.6 mm, a width of 1.2 mm, and a thickness of 35 μm.

The fifth portion P5 has a length of 0.8 mm, a width of 0.6 mm, and a thickness of 35 μm, and the inductance L5 of this region is 0.26 nH as calculated by equation (5).

Therefore, the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated as the sum of the inductances L1, L2, L3, L4, and L5, and is 1.4 nH.

In the present embodiment, the inductance is calculated using equation (4) assuming that the bonding wire 19 has a circular cross section, but a ribbon-like bonding wire with a square cross section may be used. For ribbon bonding wires, equation (5) can be used to calculate the inductance. A ribbon-shaped bonding wire can have a large cross-sectional area and can reduce the inductance.

9A and 9B are diagrams illustrating calculation of wiring inductance. Here, the wiring 153 that connects the pad 161 and the resistance element 151 that constitutes the second shunt element 1500 will be described. The wiring that connects the resistor element 131 and the pad 141 that constitute the first shunt element 1300 can also be considered in the same way.

FIG. 9A is a diagram showing an example of a configuration in which wiring 153 has a bent portion. In the example shown in FIG. 9A, the wiring 153 is configured by a bent portion having two 90-degree bent portions. The inductance of the wiring 153 in the example shown in FIG. 9A can be calculated by dividing it into three rectangular portions. The three rectangular portions are a first rectangular portion RS1 connected to the pad 161, a second rectangular portion RS2 connected to the first rectangular portion, and a third rectangular portion RS3 connected to the second rectangular portion. is. A third rectangular portion RS3 is connected to the resistive element 151 . The first rectangular portion RS1 has a length l21, width w1 and thickness h1, the second rectangular portion RS2 has a length l22, width w2 and thickness h2, and the third rectangular portion RS3 has a length l22, width w2 and thickness h2. It has a length l23, a width w3, and a thickness h3. The inductance of each rectangular portion is calculated using equation (5), and the total is taken as the inductance of the wiring 153 .

Here, an example of the method of determining the length l21, length l22, and length l23 will be described. Point A is the intersection of a line X passing through the center of the width direction of the first rectangular portion RS1 and extending in the length direction and a line Y passing through the center of the width direction of the second rectangular portion RS2 and extending in the length direction. do. A point B is an intersection point between the line Y and a line Z passing through the center in the width direction of the third rectangular portion RS3 and extending in the length direction. The distance between the end of the pad 161 and the point A is defined as the length l21 of the first rectangular portion, the distance between the point A and the point B is defined as the length l22 of the second rectangular portion RS2, and the point B and the resistor element 151 is the length l23 of the third rectangular portion RS3.

As a method for determining the length l21, the length l22, and the length l23, a determination method other than the above may be adopted as long as the wiring 153 can be divided and rectangular portions can be specified.

Next, FIG. 9B is a diagram showing an example in which the wiring 153 is configured to linearly extend from the resistance element 151 toward the pad 161 with the width gradually increasing. Even with such a wiring 153, the inductance of the wiring 153 can be calculated using Equation (5) by replacing the wiring 153 with a rectangular portion RS4 as shown in the figure. Rectangular portion RS4 has length l24, width w4 and thickness h4.

Next, an example of a method of determining the length l24 and width w4 of the rectangular portion RS4 will be described. A center point C of a portion VV' where the wiring 153 and the pad 161 are in contact is defined, and a point D which is the shortest distance from the point C and contacts the resistance element 151 is defined. Let the distance between point C and point D be length l24. Also, the distance between the ends of the wiring in the direction perpendicular to the line segment CD passing through the center E between the points C and D is defined as a width w4.

Thus, the wiring inductance can be calculated by the determination method described with reference to FIGS. 9A and 9B.

According to the present embodiment, parasitic oscillation can be suppressed by configuring the shunt element so as to satisfy the formulas (1), (2), and (3). Further, when obtaining the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500 used in the equation (3), the equations (4), (5), FIGS. 8 and 9 are used. The calculation method described above can be applied.

(Second embodiment)
An antenna device according to a second embodiment of the present disclosure will be described using FIG. The second embodiment differs from the first embodiment in that pads are connected by a plurality of bonding wires. In addition, in this embodiment, description of the same configuration as in the first embodiment is omitted.

The antenna device 200 shown in FIG. 10 has a chip 21 with a pad 241 for applying a bias voltage and a pad 242 for applying a ground voltage. Further, the substrate 20 is provided with pads 261 for connecting with the pads 241 of the chip 21 and pads 262 for connecting with the pads 242 of the chip 21 . The substrate 20 is also provided with a plurality of bonding wires 291 for connecting the pads 241 and 261 and a plurality of bonding wires 292 for connecting the pads 242 and 262 . Other antenna arrays, first shunt elements, second shunt elements, etc. in the antenna device 200 are the same as those in the antenna device 100 according to the first embodiment.

In order to reduce the inductance of the bonding wires 291 and 292, it is preferable to arrange the pads 241 and 261 and the pads 242 and 262 close to each other so that the bonding wires 291 and 292 are short.

In order to shorten the bonding wires 291 and 292 , it is preferable to arrange the pads 241 and 242 at the ends of the chip 21 . Assuming that one side of the chip 21 crossed by the plurality of bonding wires 291 and 292 is a first side 271, the pads 241 and 261 are arranged to face each other with the first side 271 interposed therebetween. The pads 242 and 262 are also arranged to face each other with the first side 271 interposed therebetween. Furthermore, the plurality of bonding wires 291 and 292 are arranged side by side at intervals in the direction parallel to the first side 271 .

A plurality of bonding wires 291 and 292 are electrically connected in parallel. A combined inductance Lm of the M bonding wires connected in parallel can be calculated by the following equation (6).
1/Lm=Σ(1/Li) (i=1,2,3,...,M)...(6)
Here, Li is the inductance of the i-th bonding wire out of the M wires, and when the cross section of the bonding wire is circular, it is calculated using formula (4), and when the cross section of the bonding wire is square, is calculated using Equation (5). It should be noted that whether the cross section of the bonding wire is circular or rectangular may be determined as appropriate, and the combined inductance Lm of the bonding wire may be calculated by equations (4) and (5).

By electrically connecting the plurality of bonding wires 291 and 292 in parallel in this manner, the combined inductance of the bonding wires 291 and 292 can be reduced, thereby facilitating suppression of parasitic oscillation.

In this embodiment, the area of pads 241 and 242 is made larger than that of pads 141 and 142 in the first embodiment, and the area of pads 261 and 262 is made larger than that of pads 161 and 162 in the first embodiment. As a result, the number of bonding wires connecting pads can be increased, and the combined inductance of a plurality of bonding wires can be reduced.

Also, the pads 241 , 242 , 261 , 262 are configured such that the dimension in the direction parallel to the first side 271 of the chip 21 is larger than the dimension in the direction perpendicular to the first side 271 . As a result, the number of bonding wires that can be arranged can be increased, and the combined inductance of the bonding wires can be reduced.

Also, the pads 241, 242, 261, 262 can be divided for each bonding wire as in the first embodiment. In this case, the connection may be made in a wiring layer below the metal layer forming the pads. However, the configuration of arranging a plurality of bonding wires on one pad as shown in FIG. 10 eliminates the need to secure a space for dividing the pads, thereby facilitating pattern formation. Therefore, by adopting the configuration illustrated in FIG. 10, an inexpensive printed circuit board or ceramic package can be used as the substrate 20, and cost can be reduced.

(Third embodiment)
An antenna device according to a third embodiment of the present disclosure will be described using FIG. The third embodiment differs from the first embodiment in that resistance elements and capacitance elements that constitute the first shunt element and the second shunt element are added and connected in parallel. In this embodiment, descriptions of the same configurations as in the first and second embodiments are omitted.

The antenna device 300 according to this embodiment shown in FIG. Equipped with an element. Further, the antenna device 300 includes pads 341 and 343 for applying a bias voltage and a pad 342 for applying a ground voltage to the chip 31 . Further, the substrate 30 is provided with a second shunt element composed of a resistive element 351 and a capacitive element 352 and another second shunt element composed of a resistive element 353 and a capacitive element 354 .

Further, the substrate 30 is provided with pads 361 for connecting with the pads 341 of the chip 31 , pads 362 for connecting with the pads 342 of the chip 31 , and pads 363 for connecting with the pads 343 of the chip 31 . Pads 341 and 361 are connected by a bonding wire 391 , pads 342 and 362 are connected by a bonding wire 392 , and pads 343 and 363 are connected by a bonding wire 393 . Further, the substrate 30 has connection terminals 381 and 383 to which a bias voltage is supplied from the voltage bias circuit 37, and a connection terminal 182 to which a ground voltage is applied.

In FIG. 11, pads 341, 342 and 343 of chip 31 and pads 361, 362 and 363 of substrate 30 are connected by bonding wires 391, 392 and 393, respectively. However, two pads may be connected by a plurality of bonding wires as in the second embodiment. Alternatively, as shown in FIG. 3, two pads may be connected by through electrodes without using bonding wires 391, 392, and 393. FIG.

The antenna array 32 is arranged substantially in the center of the chip 31 as in the first embodiment, and the capacitive element 332 is arranged adjacent to the antenna array 32 . One terminal of the resistance element 331 is connected to one terminal of the capacitance element 332 through a wiring and a via (not shown). One terminal of the resistance element 333 is connected to one terminal of the capacitance element 332 through a wiring and a via (not shown). The resistance elements 331 and 333 are preferably arranged near the capacitance element 332 . Alternatively, the resistive elements 331 and 333 may be arranged to overlap the capacitive element 332 . The other terminal of resistive element 331 is connected to pad 341 via bias voltage line 330 . A bias voltage line 330 is also arranged between each antenna 321 of the antenna array 32 and connected to each antenna 321 . Thereby, a bias voltage is applied to each antenna 321 . The other terminal of the capacitive element 332 is connected to the pad 342 via wiring and vias (not shown). The other terminal of resistive element 333 is connected to pad 343 via bias voltage line 330 .

One terminal 3512 of the resistor 351 is connected to one terminal 3521 of the capacitor 352 through a wiring. That is, the resistive element 351 and the capacitive element 352 are connected in series. Therefore, it is preferable to arrange the resistance element 351 and the capacitance element 352 adjacent to each other. More preferably, if one terminal 3512 of the resistance element 351 is arranged adjacent to one terminal 3521 of the capacitance element 352, the wiring can be shortened and the inductance can be reduced.

The other terminal 3511 of the resistive element 351 is connected to the pad 361 via wiring, and is also connected to the connection terminal 381 via wiring. Also, the other terminal 3522 of the capacitive element 352 is connected to the pad 362 via wiring, and is also connected to the connection terminal 382 via wiring.

One terminal 3532 of the resistor 353 is connected to one terminal 3541 of the capacitor 354 through a wiring. That is, the resistive element 353 and the capacitive element 354 are connected in series. Therefore, it is preferable to arrange the resistance element 353 and the capacitance element 354 adjacent to each other. More preferably, if one terminal 3532 of the resistance element 353 is arranged adjacent to one terminal 3541 of the capacitance element 354, the wiring can be shortened and the inductance can be reduced.

The other terminal 3531 of the resistive element 353 is connected to the pad 363 via wiring, and is also connected to the connection terminal 383 via wiring. Also, the other terminal 3542 of the capacitive element 354 is connected to the pad 362 via wiring, and is also connected to the connection terminal 382 via wiring.

In FIG. 11, terminals 3511 and 3512 of the resistance element 351, terminals 3521 and 3522 of the capacitance element 352, terminals 3531 and 3532 of the resistance element 353, and terminals 3541 and 3542 of the capacitance element 354 are arranged in one direction on the substrate 30 ( left and right direction). In this embodiment, the pads 361, 362, 363 are also arranged in the same direction as the terminals 3511, 3512, 3521, 3522, 3531, 3532, 3541, 3542 are arranged. By arranging the terminals and pads in this manner, the wiring for connection can be shortened and the inductance can be reduced.

Since a bias voltage is supplied to both connection terminals 381 and 383 from the voltage bias circuit 37, the other terminal 3511 of the resistance element 351 and the other terminal 3531 of the resistance element 353 are electrically connected. Further, the other terminal 3522 of the capacitive element 352 and the other terminal 3542 of the capacitive element 354 are commonly connected by wiring. Therefore, the resistive element 351 and the capacitive element 352 forming the second shunt element and the resistive element 353 and the capacitive element 354 forming another second shunt element are electrically connected in parallel. SMDs (Surface Mount Devices), for example, are employed as the resistance elements 351, 353 and the capacitance elements 352, 354. Such parts have not only resistance and capacitance but also parasitic inductance. Therefore, for two sets of the first shunt element and the second shunt element, the second shunt elements of each set (resistive element 351 and capacitive element 352 and resistive element 353 and capacitive element 354) are connected in parallel. Thereby, parasitic inductance can be reduced and parasitic oscillation can be suppressed.

Moreover, since the bonding wire 391 and the bonding wire 393, which are the paths for supplying the bias voltage, are connected in parallel, the combined inductance of the bonding wires is also reduced.

Moreover, since the wiring arranged on the substrate 30 also has a resistance value, the resistance of the wiring on the substrate 30 connecting the first shunt element and the second shunt element may be used as the resistance elements 351 and 353 . As a result, the number of components arranged on the substrate 30 can be reduced, which is advantageous for miniaturization.

In the chip 31 , the elements and pads arranged on the chip 31 and the elements, pads, wiring, etc. arranged on the substrate 30 are arranged symmetrically with respect to an axis passing through the center of the antenna array 32 . The axis passing through the center of the antenna array 32 includes, for example, an axis AX extending in a direction perpendicular to the surface of the substrate 30 and an axis extending in a direction parallel to the surface of the substrate 30 . Here, symmetry is determined with reference to an axis extending in a direction parallel to the surface of the substrate. The center of the antenna array 32 can be determined based on the planar shape of the conductor of the antenna array 32 . Also, the center of the antenna array 32 may be the center of gravity of the conductors of the antenna array 32 . The center of gravity can be determined based on the cross-sectional shape and planar shape. Therefore, on the substrate 30, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. This improves the directivity of the terahertz waves generated from the antenna array 32 and increases the frontal strength of the terahertz waves.

In this embodiment, a configuration is adopted in which bias voltages are supplied from two paths using connection terminals 381 and 383 and ground voltage is supplied from one path using connection terminal 182 . However, a configuration may be used in which the ground voltage is supplied from two paths using the connection terminals 381 and 383 and the bias voltage is supplied from one path using the connection terminal 182 .

(Fourth embodiment)
An antenna device according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 12 to 14. FIG. The antenna device according to the fourth embodiment is different from the first in that the pads are arranged on both sides of the chip, i.e., the pads and the chip are arranged so that the chip is sandwiched between the pads. It differs from the antenna device according to the embodiment. In this embodiment, the description of the same configuration as in the above embodiment is omitted.

An antenna device 400 according to the present embodiment shown in FIG. 12 includes a pad 441 for applying a bias voltage and a pad 442 for applying a ground voltage in a chip 41, as in the first embodiment. Also, unlike the first embodiment, the antenna device 400 includes a pad 443 for applying a bias voltage and a pad 444 for applying a ground voltage.

Also, in the chip 41 , the pads 441 and 442 are arranged on the side of the chip 41 on which the first side 411 is located when viewed from the antenna array 42 . Also, in the chip 41 , the pads 443 and 444 are arranged on the side of the second side 412 facing the first side 411 of the chip 41 when viewed from the antenna array 42 . As a result, the antenna array 421 is arranged between the pads 441 and 442 and the pads 443 and 444 . In this way, each set of the first shunt element and the second shunt element is arranged such that the antenna array is sandwiched between the two sets of the first shunt element and the second shunt element.

Also, on the chip 41, a resistive element 431, a capacitive element 432, and a resistive element 433, which constitute the first shunt element, are arranged.

One terminal of the resistance element 431 is connected to one terminal of the capacitance element 432 through a wiring and a via (not shown). The resistor element 431 is preferably arranged near the capacitor element 432 . Alternatively, the resistive element 431 may be arranged to overlap the capacitive element 432 . Also, the other terminal of the resistance element 431 is connected to the pad 441 via the bias voltage line 430 . The bias voltage line 430 is also arranged between the antennas 421 of the antenna array 42 and is commonly connected to each antenna 421 to apply a bias voltage to each antenna 421 .

One terminal of the resistance element 433 is connected to one terminal of the capacitance element 432 through a wiring and a via (not shown). The resistor element 433 is preferably arranged near the capacitor element 432 . Alternatively, it may be arranged to overlap on the capacitive element 432 . Also, the other terminal of the resistance element 433 is connected to the pad 443 via the bias voltage line 430 . Also, the other terminal of the capacitive element 432 is connected to pads 442 and 444 via wiring and vias (not shown).

In the chip 41 , resistor elements 431 and 433 are arranged between the pads 441 and 442 and the pads 443 and 444 . An antenna array 42 around which capacitive elements 432 are arranged is arranged between the resistive element 431 and the resistive element 433 . Thus, the pads and the first shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array 42 (in the figure, the axis BX extending to the surface of the substrate 40). Therefore, on the substrate 40, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. This improves the directivity of the terahertz waves generated from the antenna array 42 and increases the frontal intensity of the terahertz waves.

In the substrate 40, a first region 413 (the region surrounded by the dotted line in the figure) on the first side 411 side of the chip 41 has a resistor forming the second shunt element, as in the first embodiment. An element 451 and a capacitive element 452 are arranged. Further, in the first region 413, pads 461 connected to the pads 441 of the chip 41 and bonding wires 491 and pads 462 connected to the pads 442 of the chip 41 and the bonding wires 492 are arranged. Further, in the first region 413, a connection terminal 481 to which a bias voltage is supplied from the voltage bias circuit 471 and a connection terminal 482 to which a ground voltage is applied are arranged.

Also, in the substrate 40, a resistive element 453 and a capacitative element 454 constituting a second shunt element are provided in a second area 414 (an area surrounded by a dotted line in the figure) on the second side 412 side of the chip 41. are placed. Further, in the second region 414, pads 463 connected to the pads 443 of the chip 41 and bonding wires 493 and pads 464 connected to the pads 444 of the chip 41 and the bonding wires 494 are arranged. Further, in the second region 414, a connection terminal 483 to which a bias voltage is supplied from the voltage bias circuit 472 and a connection terminal 484 to which a ground voltage is applied are arranged.

Although the voltage bias circuits 471 and 472 are described above as separate circuits, the substrate 40 may be configured such that a single voltage bias circuit supplies the bias voltage and the ground voltage.

In this way, the substrate 40 has a structure in which the chip 41 is arranged between the first region 413 and the second region 414 . According to this configuration, the antenna array 42 is arranged between the pads 441,442 and the pads 443,443. In other words, the first region 413, the chip 41, and the second region 414 are arranged in this order along the line connecting the sides 411 and 412. FIG. With such a configuration, it is possible to reduce the impedance of the wiring that supplies the bias voltage. Also, the chip 41 is arranged between the resistive element 451 or the capacitive element 452 and the resistive element 453 or the capacitive element 454 . Therefore, similarly to the case of the first shunt element, the pads and the second shunt element are arranged symmetrically with respect to the axis passing through the center of the antenna array 42 . The axis passing through the center of the antenna array 42 includes, for example, an axis BX extending in a direction perpendicular to the surface of the substrate 40 and an axis extending in a direction parallel to the surface of the substrate 40 . Here, symmetry is determined with reference to an axis extending in a direction parallel to the surface of the substrate. Therefore, on the substrate 40, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. This improves the directivity of the terahertz waves generated from the antenna array 42 and increases the frontal intensity of the terahertz waves.

Further, according to this embodiment, the bias voltage to be applied to the antenna array 42 is supplied from the two opposing sides 411 and 412 of the chip 41 . As a result, compared to the case where the bias voltage is supplied from any one side of the chip 41, the impedance of the wiring for supplying the bias voltage becomes smaller, so that the voltage drop is reduced. As a result, variations in the bias voltage applied to the negative differential resistance element of each antenna among the antennas are reduced, and the uniformity of the antenna output is improved.

Furthermore, the resistance element 451 and the capacitance element 452, and the resistance element 453 and the capacitance element 454, which constitute the second shunt element, are connected in parallel. SMDs, for example, are used as the resistance elements 451, 453 and the capacitance elements 452, 454. Such components have parasitic inductance as well as resistance and capacitance components. Therefore, by connecting the resistance element 451 and the capacitance element 452 and the resistance element 453 and the capacitance element 454 in parallel, the parasitic inductance can be reduced and the parasitic oscillation can be suppressed.

In addition, since the wiring arranged on the substrate 40 also has a resistance value, the resistance of the wiring may be used as the resistance elements 451 and 453, thereby reducing the number of parts arranged on the substrate 40 and contributing to miniaturization. Advantageous.

FIG. 13 is a diagram illustrating an antenna device according to a modification of this embodiment. In addition, in this modification, description is abbreviate|omitted about the structure similar to said embodiment. The configuration of the antenna device 500 shown in FIG. 13 is a configuration obtained by applying the characteristics of this embodiment to the configuration described in the third embodiment. In this modified example, the same reference numerals are assigned to the same configurations as in the third embodiment, and the description thereof is omitted.

In the antenna device 500, resistor elements 531, 533 and pads 541, 542, 543 are arranged on the chip 51 on the side where the first side 511 of the chip 51 is located, as in the third embodiment. Further, resistor elements 534 and 535 and pads 544, 545 and 546 are arranged on the side of the second side 512 facing the first side 511 of the chip 51 .

An antenna array 52 in which a plurality of antennas 521 are arranged is arranged between the first side 511 and the second side 512 of the chip 51 . A capacitive element 532 is arranged around the antenna array 52 . The capacitive element 532 is connected to the resistive elements 531, 533, 534 and 535, respectively, and constitutes a first shunt element.

One terminal of each of the resistive elements 531, 533, 534, and 535 is connected to one terminal of the capacitive element 532 via a wiring and a via (not shown). The resistance elements 531 , 533 , 534 and 535 are preferably arranged near the capacitance element 532 . Alternatively, the resistive elements 531 , 533 , 534 , 535 may be placed overlapping the capacitive element 532 . The other terminals of the resistive elements 531 , 533 , 534 and 535 are connected to the pad 541 via the bias voltage line 530 . The bias voltage line 530 is also arranged between the antennas 521 of the antenna array 52 and is commonly connected to each antenna 521 to apply a bias voltage to each antenna 521 . The other terminal of the capacitive element 532 is connected to pads 542 and 545 via wiring and vias (not shown).

In the chip 51 , resistor elements 531 , 533 and resistor elements 534 , 535 are arranged between the pads 541 , 542 , 543 and the pads 544 , 545 , 546 . An antenna array 52 around which capacitive elements 532 are arranged is arranged between the resistive elements 531 and 533 and the resistive elements 534 and 535 . Thus, the pads and first shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array 52 . The axes passing through the center of the antenna array 52 include, for example, an axis CX extending in a direction perpendicular to the surface of the substrate 50 and an axis extending in a direction parallel to the surface of the substrate 50 . Here, symmetry is determined with reference to an axis extending in a direction parallel to the surface of the substrate. Therefore, on the substrate 50, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. This improves the directivity of the terahertz waves generated from the antenna array 52 and increases the frontal strength of the terahertz waves.

In the substrate 50, the pads 541 of the chip 51 and the pads 541 of the chip 51 are provided in the first region 513 (the region surrounded by the dotted line in the figure) on the side of the first side 511 of the chip 51, as in the third embodiment. A pad 561 connected with a bonding wire 591 is arranged. Further, in the first region 513, a pad 562 connected to the pad 542 by a bonding wire 592 and a pad 563 connected to the pad 543 by a bonding wire 593 are arranged. Furthermore, in the first region 513, resistive elements 551 and 553 and capacitive elements 552 and 554 that constitute the second shunt element are arranged. Furthermore, in the first region 513, connection terminals 581 and 583 to which a bias voltage is supplied from the voltage bias circuit 571 and a connection terminal 582 to which a ground voltage is applied are arranged. The mutual connection relationship between each pad, the second shunt element, and the connection terminal is the same as the connection relationship described in the third embodiment.

Although the voltage bias circuits 571 and 572 are described above as separate circuits, the substrate 50 may be configured such that a single voltage bias circuit supplies the bias voltage and the ground voltage.

In the substrate 50, pads 564 connected to the pads 544 of the chip 51 by bonding wires 594 are provided in the second area 514 (the area surrounded by the dotted line in the figure) on the side of the second side 512 of the chip 51. are placed. Further, in the second region 514, a pad 565 connected to the pad 545 by a bonding wire 595 and a pad 566 connected to the pad 546 by a bonding wire 596 are arranged. Further, in the second region 514, resistive elements 555 and 557 and capacitive elements 556 and 558 forming the second shunt element are arranged. Furthermore, in the second region 514, connection terminals 584 and 586 to which a bias voltage is supplied from the voltage bias circuit 572 and a connection terminal 585 to which a ground voltage is applied are arranged. The connection relationship between each pad, the second shunt element, and the connection terminal in the second region 514 is also the same as the connection relationship described in the third embodiment.

In this manner, the chip 51 is arranged between the first region 513 and the second region 514 on the substrate 50 . According to this configuration, the antenna array 52 is arranged between the pads 541 and 544 , between the pads 542 and 545 , or between the pads 543 and 546 . Also, the chip 51 is arranged between the resistance elements 551 and 553 and the capacitance elements 552 and 554 and the resistance elements 555 and 557 and the capacitance elements 556 and 558 . Therefore, the pads and second shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array 52 . The axes passing through the center of the antenna array 52 include, for example, an axis CX extending in a direction perpendicular to the surface of the substrate 50 and an axis extending in a direction parallel to the surface of the substrate 50 . Here, symmetry is determined with reference to an axis extending in a direction parallel to the surface of the substrate. Therefore, on the substrate 50, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. As a result, the directivity of the terahertz waves generated from the antenna array 52 is improved, and the front strength of the terahertz waves is increased.

Also, by supplying the bias voltage from the two opposing sides 511 and 512 of the chip 51, the impedance of the wiring that supplies the bias voltage is reduced, thereby reducing the voltage drop. As a result, variations in the bias voltage applied to the negative differential resistance element of each antenna among the antennas are reduced, and the uniformity of the antenna output is improved.

Further, the resistive element 551 and the capacitive element 552 and the resistive element 553 and the capacitative element 554 forming the second shunt element are connected in parallel. Similarly, resistive element 555 and capacitive element 556 forming the second shunt element, and resistive element 557 and capacitive element 558 are connected in parallel. Accordingly, in antenna device 500 , the number of resistance elements and capacitive elements connected in parallel is greater than that in antenna device 400 . Therefore, the parasitic inductance included in the resistive element and the capacitive element can be further reduced, and parasitic oscillation can be suppressed.

In addition, since the wiring arranged on the substrate 50 also has a resistance value, the resistance of the wiring may be used as the resistance elements 551, 553, 555, and 557, thereby reducing the number of parts arranged on the substrate 50. , which is advantageous for miniaturization.

FIG. 14 is a diagram illustrating an antenna device according to a modification of this embodiment. The configuration of the antenna device 600 shown in FIG. 14 is a configuration obtained by applying the features of the second embodiment to the configuration of the antenna device 500 shown in FIG. Therefore, the antenna device according to this modification is characterized in that the number of bonding wires connecting the pads is different from that of the antenna device described above. In the configuration of the antenna device shown in FIG. 14, the description of the configuration similar to that of the antenna device 500 shown in FIG. 13 will be omitted.

As shown in FIG. 14, in the antenna device 600, pads 641, 642, and 643 are arranged on the chip 61 on the side where the first side 611 of the chip 61 is located. Further, pads 644 , 645 and 646 are arranged on the side of the second side 612 facing the first side 611 of the chip 61 .

Also, on the substrate 60, pads 661, 662, 663 are provided in a first area 613 (an area surrounded by a dotted line in the figure) on the side of the first side 611 of the chip 61, similarly to the configuration shown in FIG. are placed. Pads 664 , 665 , and 666 are arranged in a second area 614 (an area surrounded by a dotted line in the figure) on the second side 612 side of the chip 61 .

Pads 641 and 661 are connected by a plurality of bonding wires 691 , pads 642 and 662 are connected by a plurality of bonding wires 692 , and pads 643 and 663 are connected by a plurality of bonding wires 693 . Pads 644 and 664 are connected by a plurality of bonding wires 694 , pads 645 and 665 are connected by a plurality of bonding wires 695 , and pads 646 and 666 are connected by a plurality of bonding wires 696 .

In this modification, similarly to the second embodiment, by electrically connecting a plurality of bonding wires in parallel, the combined inductance of the bonding wires can be reduced, and parasitic oscillation can be suppressed.

(Fifth embodiment)
Next, an antenna device according to a fifth embodiment of the present disclosure will be described using FIGS. 15 and 16. FIG. The antenna device according to the fifth embodiment is characterized in that pads are arranged near each side of the chip. In this embodiment, descriptions of the same configurations as those of other embodiments are omitted.

An antenna device 700 according to the present embodiment shown in FIG. 15 has pads 741 and 743 for applying a bias voltage and a pad 742 for applying a ground voltage in a chip 71 . Further, the antenna device 700 has a pad 741 for applying a bias voltage and a pad 742 for applying a ground voltage.

In the antenna device 700 according to this embodiment, a pad 741 is arranged near a first side 711 and a pad 742 is arranged near a second side 712 on a chip 71 . Further, in the chip 71, a pad 743 is arranged near a third side 713 opposite to the first side 711, and a pad 744 is arranged near a fourth side 714 opposite to the second side 712. . A bias voltage is applied to pads 741 and 743 , and a ground voltage is applied to pads 742 and 744 . Pads 741 , 742 , 743 and 744 are arranged around the antenna array 72 so as to surround the antenna array 72 .

Also, resistor elements 731 and 733 and a capacitive element 732 that constitute the first shunt element are arranged on the chip 71 . One terminal of the resistor element 731 and one terminal of the resistor element 733 are connected to one terminal of the capacitor element 132 through a wiring and a via (not shown). Resistive element 731 and resistive element 733 are preferably arranged adjacent to capacitive element 732 . Alternatively, the resistive element 731 may be placed over and over the capacitive element 732 . The other terminal of resistive element 731 is connected to pad 741 via bias voltage line 730 , and the other terminal of resistive element 733 is connected to pad 743 via bias voltage line 730 . The bias voltage line 730 is also arranged between the antennas 721 of the antenna array 72 and is commonly connected to the antennas 721 to apply a bias voltage. The other terminal of capacitor 732 is connected to pads 742 and 744 via wiring and vias (not shown).

In the substrate 70 , in the first region 715 on the side of the first side 711 of the chip 71 , the resistance elements 751 and 758 constituting the second shunt elements are connected to the pads 741 of the chip 71 by bonding wires 791 . A pad 761 is arranged. A connection terminal 781 to which a bias voltage is supplied from a voltage bias circuit 771 is arranged in the first region 715 . One terminal of the resistance element 751 and one terminal of the resistance element 758 are connected to the pad 761 , and the pad 761 is connected to the connection terminal 781 .

Similarly, in a second region 716 on the side of the second side 712 of the chip 71 , capacitive elements 752 and 753 forming the second shunt element are connected to pads 742 of the chip 71 by bonding wires 792 . A pad 762 is arranged to A connection terminal 782 to which a ground voltage is supplied from a voltage bias circuit 772 is arranged in the second region 716 . One terminal of the capacitor 752 and one terminal of the capacitor 753 are connected to the pad 762 , and the pad 762 is connected to the connection terminal 782 .

Similarly, in the third region 717 on the third side 713 side of the chip 71 , the resistance elements 754 and 755 constituting the second shunt element are connected to the pads 743 of the chip 71 by bonding wires 793 . A pad 763 is arranged. A connection terminal 783 to which a bias voltage is supplied from a voltage bias circuit 773 is arranged in the third region 717 . One terminal of the resistance element 754 and one terminal of the resistance element 755 are connected to the pad 763 , and the pad 763 is connected to the connection terminal 783 .

Similarly, in a fourth region 718 on the side of the fourth side 714 of the chip 71 , the resistance elements 756 and 757 constituting the second shunt element are connected to the pads 744 of the chip 71 by bonding wires 794 . A pad 764 is arranged to A connection terminal 784 to which a ground voltage is supplied from the voltage bias circuit 774 is arranged in the fourth region 718 . One terminal of the resistance element 756 and one terminal of the resistance element 757 are connected to the pad 764 , and the pad 764 is connected to the connection terminal 784 .

A resistor element 751 and a capacitor element 752 are arranged in the vicinity of a first corner 726 formed by a first side 711 and a second side 712 of the chip 71, and the other terminal of the resistor element 751 and the other terminal of the capacitor element 752 are arranged. is connected. Also, in the vicinity of a second corner 727 formed by the second side 712 and the third side 713 of the chip 71, the resistor element 753 and the capacitor element 754 are arranged, and the other terminal of the resistor element 753 and the capacitor element 754 are connected. Other terminals are connected. Also, in the vicinity of a third corner 728 formed by the third side 713 and the fourth side 714 of the chip 71, the resistor element 755 and the capacitor element 756 are arranged, and the other terminal of the resistor element 755 and the capacitor element 756 are connected. Other terminals are connected. In addition, in the vicinity of a fourth corner 729 formed by the fourth side 714 and the first side 711 of the chip 71, the resistor element 757 and the capacitor element 758 are arranged, and the other terminal of the resistor element 757 and the capacitor element 758 are connected. Other terminals are connected.

Due to this connection relationship between the resistance element and the capacitance element, the resistance element 751 and the capacitance element 752, the resistance element 753 and the capacitance element 754, the resistance element 755 and the capacitance element 756, and the resistance element 757 and the capacitance element 758, which constitute the second shunt element. , are electrically connected in parallel with each other. Therefore, the parasitic inductance included in each element can be further reduced, and parasitic oscillation can be suppressed.

Although the voltage bias circuits 771, 772, 773, and 774 are shown as separate circuits in FIG. 15, the substrate 70 may be configured such that the bias voltage and the ground voltage are supplied by one voltage bias circuit.

In FIG. 15, the resistance element 751 and the capacitance element 752 that constitute the second shunt element are arranged so that the direction in which the two terminals of the resistance element 751 are aligned and the direction in which the two terminals of the capacitance element 752 are aligned are orthogonal to each other. are placed. Also, the resistor element 753 and the capacitor element 754, the resistor element 755 and the capacitor element 756, and the resistor element 757 and the capacitor element 758 are arranged in the same manner.

In addition, since the wiring arranged on the substrate 70 also has a resistance value, the resistance of the wiring may be used as the resistance elements 751, 753, 755, and 757, thereby reducing the number of parts arranged on the substrate 40. , which is advantageous for miniaturization.

As described above, in the present embodiment, pads are arranged on each of the four sides of the chip 71, and the bias voltage or the ground voltage is supplied from each side. In other words, this configuration is as follows. Pads, chips 71, and pads are arranged in this order in the direction along the line segment connecting two opposite sides, and pads, chips 71, and pads are arranged in this order in the direction along the line segment connecting two opposite sides. be done. A direction along a line segment connecting two opposing sides and a direction along another line segment connecting two opposing sides intersect. With the configuration of this embodiment, the impedance of the wiring that supplies the bias voltage is smaller than when the bias voltage or the ground voltage is supplied from the side where any one or two sides of the chip 71 exist, so that the voltage drop is reduced. Reduce. As a result, variations in the bias voltage applied to the negative differential resistance element of each antenna among the antennas are reduced, and the uniformity of the antenna output is improved.

Also, since the pads are arranged on the sides of the chip 71, it is possible to electrically connect a plurality of bonding wires in parallel while increasing the size of the pads. As a result, the combined inductance of the bonding wires can be reduced, and parasitic oscillation can be further suppressed.

In addition, by arranging the resistance element and the capacitance element of the second shunt element in the vicinity of each of the four corners 726 to 729 of the chip 71 on the substrate 70, the substrate space can be effectively used and the substrate size can be reduced. can reduce manufacturing costs.

Also, the pads and the second shunt element are arranged symmetrically with respect to an axis passing through the center of the antenna array 72 . The axis passing through the center of the antenna array 72 includes, for example, an axis DX extending in a direction perpendicular to the surface of the substrate 70 and an axis extending in a direction parallel to the surface of the substrate 70 . Here, symmetry is determined with reference to an axis extending in a direction parallel to the surface of the substrate. Therefore, on the substrate 70, a plurality of sets of first shunt elements and second shunt elements connected to each other are arranged, and at least two sets of the first shunt elements and second shunt elements are arranged along an axis passing through the center of the antenna array. It is arranged in a symmetrical position. This improves the directivity of the terahertz waves generated from the antenna array 72 and increases the frontal intensity of the terahertz waves.

FIG. 16 is a diagram illustrating an antenna device according to a modification of this embodiment. In addition, in this modification, description is abbreviate|omitted about the structure similar to said embodiment. In the antenna device 800 shown in FIG. 16, a resistance element 851 and a capacitance element 852, a resistance element 853 and a capacitance element 854, a resistance element 855 and a capacitance element 856, and a resistance element 857 and a capacitive element 858 are arranged. Resistive elements 851, 853, 855 and 857 and capacitive elements 852, 854, 856 and 858 are arranged obliquely with respect to the extending direction of each side of the chip. The direction in which the two terminals of the resistor 851 are arranged is the same direction as the direction in which the two terminals of the capacitor 852 are arranged. A capacitive element 858 is similarly arranged.

By arranging each element in this way, the wiring that connects the resistance element, the capacitance element, and the pad can be shortened, and the parasitic inductance contained in the wiring can be reduced, thereby suppressing parasitic oscillation. can.

(Sixth embodiment)
Next, the antenna array in the antenna device according to the sixth embodiment of the present disclosure will be explained using FIGS. 17 to 22. FIG. In this embodiment, descriptions of the same configurations as those of other embodiments are omitted.

FIG. 17 shows an equivalent circuit diagram of the antenna device 900 according to this embodiment. The configuration example of the equivalent circuit diagram shown in FIG. 17 corresponds to the configuration in which the antenna array 12 in the equivalent circuit diagram of the antenna device 100 according to the first embodiment shown in FIG. 5 has antennas 121 arranged in a 3×3 matrix. do. The antenna array 912 includes 3×3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, r33 and resistance elements Rai (i=1, 2, 3 . . . , 12) and capacitive elements Cai (i=1, 2, 3, . . . , 12). Antenna array 912 includes negative differential resistance elements and a plurality of third shunt elements in which resistance elements and capacitance elements are connected in series. Also, the 3×3 negative differential resistance elements and the plurality of third shunt elements are connected in parallel with each other. One terminal of each negative differential resistance element, one terminal of the resistance element Rai in the plurality of third shunt elements, and one terminal of the resistance element Rc in the first shunt element are commonly connected. Also, the other terminal of the resistance element Rai is connected to one terminal of the capacitance element Cai. Further, the other terminal of each negative differential resistance element and the other terminal of the capacitive element Cai in the plurality of third shunt elements are connected to the ground potential. The rest of the configuration of the antenna array 912 is the same as in FIG. 5, so the description is omitted here.

In the antenna array 912, the combined resistance of 3×3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, r33 corresponds to the resistance r shown in FIG. Also, the combined impedance of the parasitic impedance of the third shunt element and the wiring corresponds to the impedance Z shown in FIG.

FIG. 18 is an example of a top view of an antenna array 912 arranged in a 3×3 matrix corresponding to the equivalent circuit diagram of FIG. 17 . 19 is a cross-sectional view taken along line CC' in FIG. 18. FIG. Description of the configuration described using FIG. 4 is omitted, and the same reference numerals are used for the same components as in FIG. Adjacent antennas are coupled to each other by microstrip lines 125a to 125h, as described with reference to FIG. 4, and are mutually injection-locked (mutually synchronized) at the terahertz wave oscillation frequency fTHz. FIG. 18 illustrates a configuration in which one antenna is provided with two negative differential resistance elements 127a and 127b. In order to improve the directivity of the terahertz wave, the two negative differential resistance elements 127a and 127b are preferably arranged symmetrically with respect to a line passing through the center of one antenna.

A third shunt element is provided in the bias voltage line 130 to suppress parasitic oscillation in a frequency band lower than the oscillation frequency fTHz. The third shunt element has a structure of suppressing parasitic oscillation by short-circuiting a frequency band lower than fTHz by arranging it in parallel with the negative differential resistance element. The third shunt element has a structure in which a resistive element or an element in which a resistor and a capacitor are connected in series is arranged in parallel with the negative differential resistance element. In the third shunt element, the resistance and capacitance values are equal to or slightly lower than the absolute value of the synthesized negative differential resistance of the plurality of negative differential resistance elements arranged in the vicinity of the element impedance.

In FIG. 18, a conductor layer 137, which is one electrode of a capacitive element forming the third shunt element, is arranged in a region surrounded by a dashed line 137' in plan view. A resistor 138, which is a resistive element, is arranged in a region surrounded by a dashed line 138'. The conductor layer 137 and the resistor 138 are arranged below the wiring layer forming the bias voltage line 130 . A third shunt element is arranged around each antenna. A bias voltage line 130 is connected to the metal layer 123, which is part of each antenna, to supply a bias voltage. should be placed in between. Such an arrangement enables a configuration in which adjacent antennas share one third shunt element. As a result, the layout efficiency is improved and the size of the chip can be reduced, and the degree of freedom in adjusting the size of the capacitance and resistance of the shunt element is increased, thereby facilitating the suppression of parasitic oscillation.

A dielectric layer 136 is disposed over the ground metal layer 124, as shown in the cross-sectional view of FIG. Since the dielectric layer 136 is used as a dielectric of the capacitor of the third shunt element, it is preferable to use silicon nitride (ε=7) having a relatively high dielectric constant in order to miniaturize the MIM capacitor structure.

A conductor layer 137 is laminated on the dielectric layer 136 . Therefore, the antenna array 912 has a metal-insulator-metal (MIM) capacitor structure in which the ground metal layer 124, the dielectric layer 136, and the conductor layer 137 are laminated in this order. It corresponds to an element. This capacitive element is placed under the bias voltage line 130 placed between the antennas. A conductor layer 137 is located in the layer between the bias voltage line 130 and the ground metal layer 124 . A resistor 138 is connected to the conductor layer 137 and the resistor 138 is connected to the bias voltage line 130 . This resistor 138 corresponds to the resistance element of the third shunt element.

Thus, in this embodiment, the ground metal layer 124 and the bias voltage line 130 are electrically connected via the capacitive element and the resistive element that constitute the third shunt element. A plurality of third shunt elements are arranged in the array antenna so as to be connected to the bias voltage line 130 at each point between the antennas. Although the third shunt element is connected to the ground metal layer 124 in this embodiment, it may be connected to a conductive layer with a fixed potential, or may be connected to another conductive layer.

The configuration in which the third shunt element is arranged at the node of the high-frequency electric field of the oscillation frequency fTHz standing in the antenna is a more suitable configuration for selectively oscillating only the high frequency of the frequency fTHz, which has a high impedance at the frequency fTHz. be. However, with an increase in the number of antenna arrays and common use of bias voltage lines, there is a risk of unexpected low-frequency multimode oscillation. For this reason, in this embodiment, the bias voltage line 130 in the array antenna is configured to have a lower impedance than the negative resistance element in a low frequency band lower than the oscillation frequency fTHz. According to this, even if the number of antenna arrays increases, it is possible to suppress other-mode oscillation and obtain stable single-frequency oscillation in the terahertz band. The third shunt element can effectively suppress parasitic oscillation particularly in a frequency band of 10 GHz or more and less than fTHz.

FIG. 20 is a top view of an antenna array 1012 that is a modification of the antenna array 912 shown in FIG. 18, and FIG. 21 is a cross-sectional view taken along line D-D' in FIG. 18 and 19 are denoted by the same reference numerals, and descriptions thereof are omitted. Antenna array 1012 differs from antenna array 912 shown in FIGS. 18 and 19 in that the resistive elements constituting the third shunt element are composed of resistors 138a and 138b.

As shown in FIG. 20 , in antenna array 1012 , resistors 138 a and 138 b are arranged between antennas 1112 and 1113 . These two resistors 138 a and 138 b correspond to resistor elements of the third shunt element, are connected in parallel, and are connected in series with the capacitive element 137 . Resistive elements 138a and 138b are arranged in the vicinity of connecting portions of antennas 1112 and 1113 and bias voltage line 130, and are arranged in a space obtained by patterning and removing a wiring layer forming bias voltage line 130. FIG.

As shown in the cross-sectional view of FIG. 21, resistors 138a and 138b are arranged at the same height as the bias voltage line . One end of resistor 138a and resistor 138b is connected to bias voltage line 130, and the other end is connected to conductor layer 137 using the same wiring layer as bias voltage line 130. FIG.

For the antenna 1111 at the end of the antenna array 1012, the third shunt element arranged in the region 137'' not sandwiched between other antennas is either the resistor 138a or the resistor 138b (138a in the figure) as a resistive element. ) may be arranged.

The configuration of the antenna array 1012 shown in FIGS. 20 and 21 is such that the wiring layer forming the bias voltage line 130 is removed by patterning at the positions where the resistors 138a and 138b are to be arranged, and the space is filled with a material that will become the resistors. should be formed. Therefore, compared to conventional antenna arrays, the fabrication is easier and the occurrence of defects can be suppressed.

Here, descriptions of the first shunt element, the second shunt element, and the third shunt element will be added with reference to FIG. 22 . FIG. 22 illustrates a configuration in which pads are arranged on two opposing sides of the chip described in the fourth embodiment, and the pads are connected to each other by a plurality of bonding wires. In the following description, the same reference numerals are assigned to the same components as those described in the fourth embodiment, and detailed description thereof will be omitted.

The first shunt element consists of a resistive element 531 and a capacitive element 532 and is arranged around the antenna array 52 within the chip 51 . An MIM capacitor is suitable for the capacitive element 532 .

The second shunt element consists of a resistance element 551 and a capacitance element 552 and is arranged on the substrate 50 on which the chip 51 is mounted. A surface mount device (SMD) is preferably used for the resistance element 551 and the capacitance element 552, and a ceramic capacitor is used as the capacitance element 552, for example.

The third shunt element is composed of a resistive element (not shown) and a capacitive element 521, and is arranged within the chip 51 and within the antenna array 52 in the same manner as the first shunt element. An MIM capacitor is suitable for the capacitive element 521 .

It is preferable that the area or capacitance value of the capacitive elements constituting the three shunt elements be increased in the order of the third shunt element, the first shunt element, and the second shunt element (capacitor element 521<capacitor element 532). <capacitor element 552). Capacitor 521 can be suitably arranged if it is 1 pF or more and less than 100 pF, capacitive element 532 is 100 pF or more and less than 10 nF, and capacitive element 552 is 10 nF or more and less than 100 μF. Also, the resistance elements of the first shunt element, the second shunt element, and the third shunt element can be preferably arranged if they have a resistance of 0.01Ω or more and less than 10Ω.

Although the number of third shunt elements is determined according to the number of antennas in the antenna array 2, it is preferable that the number be equal to or greater than the number of the first shunt elements and the number of the second shunt elements or more, thereby suppressing parasitic oscillation and improving output. becomes.

When the number of antennas in the antenna array 2 is small, such as for adjusting the output to be small, the number of the third shunt elements may be smaller than the number of the first shunt elements and the second shunt elements.

If the number of second shunt elements is greater than or equal to the number of first shunt elements, the number of parallel-connected second shunt elements can be increased. As a result, the parasitic inductance of the SMD can be reduced, thereby suppressing parasitic oscillation. In addition, since the number of first shunt elements is reduced, the chip area can be reduced, which contributes to the cost reduction of the antenna array.

If the number of second shunt elements is less than the number of first shunt elements, the number of SMDs constituting the second shunt elements can be reduced. Since the area required to mount the SMDs on the substrate is relatively large, the reduction in the number of SMDs allows the size of the substrate to be reduced, which contributes to the cost reduction of the antenna array.

Ta, Ti, Mo, Mn, Al, Ni, Nb, W, Ru, and the like are preferably used as resistors forming resistor elements of the first shunt element and the third shunt element in the chip. Furthermore, as the resistor, an alloy film, oxide film, nitride film, silicide film, etc. thereof (eg, TiW, TiN, TaN, WN, WSiN, TaSiN, NbN, MoN, MnO, RuO) are preferably used. . Furthermore, polysilicon, a diffused resistance film obtained by doping impurities into Si, or the like is preferably used as the resistor.

Materials with a resistivity of 1×10 −6 Ω·m or less are preferable as materials for wiring and conductive layers used in the chip. Specifically, metals and metal compounds such as Ag, Au, Cu, W, Ni, Cr, Ti, Al, AuIn alloys, and TiN are preferably used as materials.

The dielectric layer that makes up the MIM capacitor has insulating properties (property of acting as an insulator and high resistance that does not conduct electricity against DC voltage), barrier properties (property of preventing diffusion of metal materials used for electrodes), and processing. (property that can be processed with submicron precision) is required. As specific examples of materials satisfying these requirements, inorganic insulating materials such as silicon oxide (ε=4), silicon nitride (ε=7), aluminum oxide, and aluminum nitride are preferably used.

The negative resistance element includes an electrode and a semiconductor layer, and if the electrode is a conductor ohmically connected to the semiconductor layer, it is suitable for reducing ohmic loss and RC delay due to series resistance. When an electrode is used as an ohmic electrode, the material may be Ti/Pd/Au, Ti/Pt/Au,
, AuGe/Ni/Au, TiW, Mo, ErAs and the like are preferably used.

(Seventh embodiment)
A detection system according to this embodiment will be described with reference to FIG. The detection system may be a system capable of taking images, for example a camera system. In this embodiment, a camera system will be described as an example. FIG. 23 is a schematic diagram for explaining the configuration of a camera system 2300 using terahertz waves.

The camera system 2300 has an oscillation device 2301 , a detection device 2302 and a processing section 2303 . The antenna device described in each embodiment can be applied to the oscillation device 2301 . The detection device 2302 can detect electromagnetic waves transmitted from the antenna device, and may be an antenna device using other semiconductor elements such as Schottky barrier diodes, for example. The terahertz wave emitted from the oscillation device 2301 is reflected by the subject 2305 and detected by the detection device 2302 . A processing unit 2303 processes the signal detected by the detection device 2302 . Image data generated by the processing unit 2303 is output from the output unit 2304 . With such a configuration, a terahertz image can be obtained.

The oscillation device 2301 and the detection device 2302 may be provided with an optical section. The optical section includes at least one material transparent to terahertz waves, such as polyethylene, Teflon (registered trademark), high-resistance silicon, and polyolefin resin, and may be composed of multiple layers.

The camera system described in this embodiment is merely an example, and may be in other forms. In particular, the information acquired by the system is not limited to image information, and may be a detection system that detects signals.

Each of the embodiments merely shows specific examples for carrying out the present invention, and the technical scope of the present invention should not be construed to be limited by these. That is, the present invention can be embodied in various forms without departing from its technical concept or main features.

12 antenna array 17 voltage bias circuit 100 antenna device 131, 151 resistive element 132, 152 capacitive element 1200 resonance circuit 1300 first shunt element 1500 second shunt element

Claims (28)

An antenna device for transmitting or receiving electromagnetic waves,
An antenna array in which a plurality of antennas each comprising a negative differential resistance element and a resonant circuit are arranged;
a voltage bias circuit that applies a voltage to the antenna array;
A first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, wherein the first resistor and the first shunt element of the first shunt element a first shunt element having one capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second resistance of the second shunt element and a second shunt element in which the second capacitor is connected in series;
has
The antenna device according to claim 1, wherein the first shunt element and the second shunt element have a low impedance with respect to the resistance value of the negative differential resistance element. The antenna device according to claim 1, wherein the following equations (1) to (3) are satisfied: Rp+1/(2π×f×Cp)<r (1)
Rc+1/(2π×f×Cc)<r (2)
L/(Cc×r)<Rc (3)
Here, r is the absolute value of the resistance value of the negative differential resistance element, Rp is the resistance value of the second resistor, Cp is the capacitance value of the second capacitor, and Rc is the first The resistance value of the resistor, Cc is the capacitance value of the first capacitor, L is the inductance of the path connecting the first shunt element and the second shunt element, and f is the frequency below the resonance frequency of the resonance circuit. is. The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4),
L≤5nH (4)
When the path is divided into a first portion whose cross-section can be approximated as a circle and a second portion whose cross-section can be approximated as a square, the inductance L1 of the first portion is expressed by the following equation: (5), and the inductance L2 of the second portion is calculated by the following equation (6): L1=0.2×l1×[ln (4×l1/d)−0.75] (5)
L2=0.2×l2×[ln{2×l2/(w+h)}+0.2235×(w+h)/l2+0.5] (6)
where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, and w is the length of the second portion. is the width of the second portion and h is the thickness of said second portion. A plurality of sets of the first shunt element and the second shunt element are arranged,
4. Any one of claims 1 to 3, wherein at least two sets of said first shunt element and said second shunt element are arranged at symmetrical positions with respect to an axis passing through the center of said antenna array. 1. An antenna device according to claim 1. Two sets of the first shunt element and the second shunt element are arranged such that the antenna array is sandwiched between the two sets of the first shunt element and the second shunt element. 5. The antenna device according to claim 4. The first shunt element is arranged on a chip on which the antenna array is arranged,
The chip is a square chip,
6. The antenna device according to claim 4, wherein the second shunt element of each set of the first shunt element and the second shunt element is arranged near a corner of the chip. 5. The antenna device according to claim 4, wherein the second shunt elements of each of the two sets of the first shunt element and the second shunt element are connected in parallel. The first shunt element is arranged on a chip on which the antenna array is arranged,
8. The antenna device according to claim 1, wherein said second shunt element is arranged on a substrate on which said chip is arranged. a path connecting the first shunt element and the second shunt element includes a first pad arranged on the chip and a second pad arranged on the substrate;
9. The antenna device according to claim 8, wherein a bias voltage is supplied to said antenna array through said first pad and second pad. The antenna device further has a third pad arranged on the chip and a fourth pad arranged on the substrate,
A ground voltage is supplied to the antenna array through the third pad and the fourth pad,
The chip is a square chip,
A bias voltage is supplied to the antenna array through the first pad and the second pad from the first side of the chip,
10. A ground voltage is supplied to the antenna array via the third pad and the fourth pad from a side of the chip having a second side different from the first side. An antenna device as described. 11. The antenna device according to claim 9, wherein said first pad and said second pad are connected by a plurality of bonding wires connected in parallel. 11. The antenna device according to any one of claims 8 to 10, wherein the second resistor is wiring arranged on the substrate. An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas composed of negative differential resistance elements and resonant circuits are arranged;
a substrate on which the chip is arranged;
a voltage bias circuit that applies a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit and including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitor, disposed on the substrate;
An antenna device, wherein the antenna array is positioned between the first pad and the second pad. 14. The antenna device according to claim 1, wherein a combined resistance value of said negative differential resistance elements of said antenna array is 1[Omega] or less. 15. The antenna device according to claim 1, wherein the length of the path connecting said first shunt element and said second shunt element is 4 mm or less. 16. The antenna device according to claim 15, wherein the length of the path connecting said first shunt element and said second shunt element is 2 mm or less. 17. The antenna device according to any one of claims 1 to 16, wherein the frequency band of the electromagnetic wave includes at least part of a frequency band of 30 GHz or more and 30 THz or less. 18. The antenna device according to claim 1, wherein said negative differential resistance element is a resonant tunneling diode. 19. The antenna device according to claim 1, wherein the first capacity is MIM (Metal-Insulator-Metal) capacity. 20. The antenna array according to any one of claims 1 to 19, further comprising a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance. antenna device. 21. The antenna device according to claim 20, wherein a plurality of said third shunt elements are arranged between antennas. 22. The antenna device according to claim 21, wherein the third shunt element is shared by antennas on both sides of the third shunt element. 21. The antenna device according to claim 20, wherein the third capacitor, the first capacitor, and the second capacitor have larger areas or larger capacitance values in that order. 21. The antenna device according to claim 20, wherein the number of said third shunt elements is greater than or equal to the number of said first shunt elements and greater than or equal to the number of said second shunt elements. 21. The antenna device according to claim 20, wherein the number of said third shunt elements is less than the number of said first shunt elements and less than the number of said second shunt elements. 20. The antenna device according to claim 1, wherein the number of said second shunt elements is greater than or equal to the number of said first shunt elements. 20. The antenna device according to any one of claims 1 to 19, wherein the number of said second shunt elements is smaller than the number of said first shunt elements. An antenna device according to any one of claims 1 to 27;
a detection device for detecting electromagnetic waves transmitted from the antenna device;
a processing unit for processing signals from the detection device.

Images