JP2022115561A - Electronic apparatus and electric power control method - Google Patents

Abstract

To provide an electronic apparatus configured to cool an arithmetic processing device using a heat diffusion device and capable of preventing the occurrence of dry-out of the heat diffusion device when operating the arithmetic processing device with a heavy load.SOLUTION: An electronic apparatus includes an arithmetic processing device, a heat diffusion device that is used for cooling the arithmetic processing device, and diffuses heat generated from the arithmetic processing device, and an electric power control unit that performs upper limit electric power control that an electric power upper limit as an upper limit of consumption power specified for the arithmetic processing device is changed according to a time lapse.SELECTED DRAWING: Figure 5

Description

The present invention relates to electronic equipment and power control methods.

2. Description of the Related Art There is known an electronic device configured to cool a CPU (Central Processing Unit) or the like by utilizing heat diffusion by a heat pipe (see, for example, Japanese Patent Application Laid-Open No. 2002-200011).

Japanese Patent Application Laid-Open No. 2020-42588

When excessive heat flows into a heat diffusion device such as a heat pipe that utilizes the latent heat of an internal working fluid to diffuse heat, a phenomenon called dryout occurs and the heat diffusion function is lost.
For example, when an arithmetic processing unit such as a CPU is shifted from a low-load state to a high-load state, the amount of heat generated from the CPU becomes considerable. At this time, a phenomenon called dryout may occur in the heat diffusion device, depending on the relationship between the performance required of the processor and the cooling power of the cooling device including the heat pipe.
For this reason, in order to operate an arithmetic processing unit in an electronic device under a high load, it is required to prevent dryout from occurring in the heat diffusion device.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances. The purpose is to prevent dryout of the diffusion device.

One aspect of the present invention for solving the above-described problems is an arithmetic processing unit, a heat diffusion device that is used for cooling the arithmetic processing unit and diffuses heat generated from the arithmetic processing unit, and the arithmetic processing unit. An electronic device comprising: a power control unit that performs upper limit power control to change a power upper limit, which is an upper limit of power consumption defined for a device, according to the passage of time.

Another aspect of the present invention is a power control method in an electronic device including an arithmetic processing unit and a heat diffusion device that is used to cool the arithmetic processing unit and diffuses heat emitted from the arithmetic processing unit. a step of performing upper limit power control for changing a power upper limit, which is an upper limit of power consumption defined for the arithmetic processing unit, according to the lapse of time.

According to the present invention, in an electronic device in which a heat diffusion device is used to cool a processing unit, dryout of the heat diffusion device does not occur when the processing device is operated under a high load. The effect that it becomes possible to do is obtained.

It is a figure which shows the example of an external appearance of the electronic device which concerns on 1st Embodiment. It is a figure which shows typically the structure in the housing|casing of the electronic device which concerns on 1st Embodiment. It is a figure which shows the hardware structural example of the electronic device which concerns on 1st Embodiment. FIG. 4 is a diagram illustrating an example of power control that can be executed by the electronic device according to the first embodiment; It is a figure which shows the example of one aspect|mode of the upper limit electric power control by the electronic device which concerns on 1st Embodiment. It is a figure which shows the functional structural example of the electronic device which concerns on 1st Embodiment. It is a figure which shows the structural example of the stage electric power upper limit value table which concerns on 1st Embodiment. 6 is a flowchart showing an example of a processing procedure executed by the electronic device according to the first embodiment regarding upper limit power control; It is a figure which shows the example of one aspect|mode of the upper limit electric power control by the electronic device which concerns on 2nd Embodiment. 10 is a flow chart showing an example of a processing procedure executed by an electronic device relating to upper limit power control according to the second embodiment;

<First embodiment>
FIG. 1 is a perspective view showing an appearance example of an electronic device according to this embodiment. The illustrated electronic device 10 is a clamshell notebook PC (Personal Computer). The electronic device 10 includes a first housing 101 , a second housing 102 and a hinge mechanism 103 . The first housing 101 and the second housing 102 are substantially rectangular plate-shaped (for example, flat plate-shaped) housings. One of the side surfaces of the first housing 101 and one of the side surfaces of the second housing 102 are coupled (connected) via a hinge mechanism 103, and the first housing 101 rotates around the rotation axis formed by the hinge mechanism 103. and the second housing 102 are relatively rotatable. A state in which the opening angle θ about the rotation axis between the first housing 101 and the second housing 102 is approximately 0° corresponds to a state in which the first housing 101 and the second housing 102 are overlapped and closed (“closed state”). state”). The surfaces of the first housing 101 and the second housing 102 that face each other in the closed state are called "inner surfaces", and the surfaces opposite to the inner surfaces are called "outer surfaces". The opening angle θ can also be said to be the angle formed by the inner surface of the first housing 101 and the inner surface of the second housing 102 . A state in which the first housing 101 and the second housing 102 are opened with respect to the closed state is referred to as an “open state”. The open state is a state in which the first housing 101 and the second housing 102 are relatively rotated until the opening angle θ becomes larger than a preset threshold value (for example, 10°).

A display unit 14 is provided on the inner surface of the first housing 101 . An input section 32 is provided on the inner surface of the second housing 102 . In the illustrated example, the input unit 32 is a physical keyboard. Note that the input unit 32 may include a touch pad or a software keyboard. In the case of a software keyboard, a display section is also provided on the inner surface of the second housing 102 .

In the closed state, the display section 14 cannot be visually recognized and the input section 32 cannot be operated. On the other hand, in the open state, the display unit 14 can be viewed and the keyboard can be operated (that is, the electronic device 10 can be used). In a general usage pattern when a user uses the electronic device 10, for example, it is often in an open state within a range of 90°≦opening angle θ≦180°.

FIG. 2 is a plan view schematically showing the inside of the second housing 102 of the electronic device 10. As shown in FIG. In the description below, the second housing 102 is also simply referred to as housing BD.
A motherboard MB, a storage medium 23, an audio system 24, a battery 34, and a cooling unit 35 are arranged inside the housing BD.
The motherboard MB includes, for example, a CPU (Central Processing Unit) 11 (an example of an arithmetic processing unit), a video subsystem 13, a chipset 21, a BIOS (Basic Input Output System) memory 22, an embedded controller 31, and a power supply circuit 33. Implemented.

The cooling part 35 is a part provided to cool the electronic device 10 . The cooling unit 35 includes a heat dissipation fan 351 and a heat pipe 352 (an example of a heat diffusion device).

The heat radiation fan 351 causes air to flow into the housing BD from the intake port 81 by rotating its fins (wings). The air that has flowed in is heat-exchanged with the heat pipe 352 and then exhausted from the housing BD through the exhaust port 83 .
The heat pipe 352 is a heat transfer member having a tube made of metal and a working fluid and a wick sealed inside the tube. Copper, aluminum, or the like can be used as the material of the tube. Water or the like can be used as the working fluid. A porous material or the like can be used as the wick. The wick is formed with pores that generate capillary force in the liquid-phase working fluid.
Heat pipe 352 has an evaporator and a condenser. The evaporating portion of the heat pipe 352 is provided close to or in contact with the CPU 11 so as to take in heat generated by the CPU 11, for example. A condensing portion of the heat pipe 352 is provided in the vicinity of the heat dissipation fan 351 .
The evaporator of the heat pipe 352 evaporates the working fluid by receiving the heat generated by the CPU 11 . In the evaporating section, the vaporization of the working fluid increases the pressure, so that the vapor-phase working fluid moves toward the condensing section. In the condensing section, the heat of the working fluid is taken away by the airflow generated by the heat radiation fan 351 . The airflow that has taken heat from the working fluid is discharged from the exhaust port 83 to the outside of the housing BD.
The working fluid that has lost heat in the condensation section condenses into a liquid phase. The liquid-phase working fluid flows toward the evaporator by capillary force through pores formed in the wick. The liquid-phase differential fluid that has reached the evaporator receives heat from the CPU 11 again and evaporates. After that, the above phenomenon is repeated.
Thus, the CPU 11 can be cooled by the cooling section 35 having the heat pipe 352 .

Note that the temperature sensors 353 (353a, 353b) provided in the heat pipe 352 correspond to the second embodiment, so description thereof will be omitted here.

CPU 11 may be a CPU and/or a GPU. The CPU 11 may be of a type in which the CPU and GPU are formed on the same core. Further, the CPU 11 may be of a type in which the CPU and GPU are formed by separate cores and share the load. Also, the number of CPUs 11 may be plural.

Next, a main hardware configuration example of the electronic device 10 will be described with reference to FIG. FIG. 3 is a block diagram showing an example of the hardware configuration of the electronic device 10. As shown in FIG.

The electronic device 10 includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, a storage medium 23, an audio system 24, a WLAN card 25, a USB It has a connector 26 , an embedded controller 31 , an input section 32 , a power supply circuit 33 , a battery 34 and a cooling section 35 .
In addition, since the temperature sensor 353 (353a, 353b) corresponds to the second embodiment also in FIG.

The CPU 11 executes various arithmetic processes under program control and controls the electronic device 10 as a whole. For example, the CPU 11 executes processing based on OS (Operating System) and BIOS programs.
The main memory 12 is a writable memory used as a read area for the execution program of the CPU 11 or as a work area for writing processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The execution program includes an OS, various drivers for hardware operation of peripheral devices, various services/utilities, application programs, and the like.

The video subsystem 13 is a subsystem for realizing functions related to image display, and includes a video controller. The video controller processes drawing commands from the CPU 11, writes the processed drawing information to the video memory, reads the drawing information from the video memory, and outputs it to the display unit 14 as drawing data (display data).

The display unit 14 is, for example, a liquid crystal display or an organic EL display, and displays a display screen based on drawing data (display data) output from the video subsystem 13 .

The chipset 21 supports USB (Universal Serial Bus), serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count) bus. It has a controller and multiple devices are connected. For example, the multiple devices include a BIOS memory 22, a storage medium 23, an audio system 24, a WLAN card 25, a USB connector 26, and an embedded controller 31, which will be described later.

The BIOS memory 22 is, for example, an electrically rewritable nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM. The BIOS memory 22 stores the BIOS, system firmware for controlling the embedded controller 31 and the like.

The storage medium 23 includes an HDD (Hard Disk Drive), an SSD (Solid State Drive), and the like. For example, the storage medium 23 stores an OS, various drivers, various services/utilities, application programs, and various data.

The audio system 24 is connected to a microphone and a speaker (not shown), and records, reproduces, and outputs sound data. In addition, the microphone and the speaker are built in the electronic device 10 as an example.

A WLAN (Wireless Local Area Network) card 25 connects to a network via a wireless LAN to perform data communication. For example, when receiving data from the network, the WLAN card 25 generates an event trigger indicating that the data has been received.
The USB connector 26 is a connector for connecting peripheral devices using USB.

The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touch pad. For example, the input unit 32 is arranged as a keyboard on the inner surface of the second housing 102, as shown in FIG. The input unit 32 outputs to the embedded controller 31 input information (for example, an operation signal indicating a key operated on a keyboard) input by a user's operation.

The power supply circuit 33 includes, for example, a DC/DC converter, a charging/discharging unit, an AC/DC adapter, and the like. For example, the power supply circuit 33 converts DC voltage supplied from an external power supply such as an AC adapter (not shown) or a battery 34 into a plurality of voltages necessary for operating the electronic device 10 . Also, the power supply circuit 33 supplies power to each part of the electronic device 10 based on the control from the embedded controller 31 .

The battery 34 is, for example, a secondary battery such as a lithium ion battery. The battery 34 is charged through the power supply circuit 33 when the electronic device 10 is supplied with power from the external power supply, and is charged through the power supply circuit 33 when the electronic device 10 is not supplied with power from the external power supply. The accumulated power is output as the operating power of the electronic device 10 .

The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the electronic device 10 . The embedded controller 31 includes a CPU, ROM, RAM, A/D input terminals for multiple channels, D/A output terminals, a timer, and digital input/output terminals (not shown). The digital input/output terminals of the embedded controller 31 are connected to, for example, the input section 32, the power supply circuit 33, the heat dissipation fan 351, etc. The embedded controller 31 can control these operations.
Also, the embedded controller 31 in FIG. 1 can perform control such as changing the clock frequency of the CPU 11 via the chipset 21 .

FIG. 4 shows an example of power control of the CPU 11 that can be executed by the electronic device 10 . In the example of FIG. 1, two power limit values PL (Power Limit) 1 and PL2 are defined corresponding to the CPU 11 .
The power upper limit value PL1 is the upper limit value of power consumption that is defined as being continuously permitted under the operation of the CPU 11 . In operation with power consumption within the power upper limit PL1, the CPU 11 operates at, for example, a rated clock (base clock). The power upper limit value PL2 is an upper limit value of power consumption that is allowed to temporarily exceed the power upper limit value PL1 within a predetermined time limit when operating the CPU 11 under high load. Under the power upper limit PL2, the electronic device 10 can operate the CPU 11 with a clock with a higher frequency than the rated clock.

In the example of FIG. 1, the CPU 11 is in a low load state where the load (which may be the CPU usage rate) is below a certain level after time t0. The CPU 11 generates power consumption Pid corresponding to the low load state. The low load state corresponds to, for example, an idle state or a state in which processing is being executed with a load below a certain level.
At time t1 after a certain amount of time has passed since time t0, the CPU 11 transitioned to a high load state with a load exceeding a certain level. In other words, at time t1, the degree of increase in the load on the CPU 11 has exceeded a certain level.
A high load state occurs, for example, when an application with a heavy processing load is activated, or when an application is caused to perform processing with a heavy load.
In response to such a load state transition, the electronic device 10 operates with the power consumption of the CPU 11 exceeding the power upper limit PL1 but not exceeding the power upper limit PL2 during the period from time t1 to time t2. to control. A maximum time (maximum permissible time) during which power upper limit PL2 is maintained is predetermined, and the period from time t1 to time t2 is within the maximum permissible time.
After the time t2, the electronic device 10 controls the CPU 11 to operate in a state (steady state) with power consumption that does not exceed the power upper limit PL1.
By controlling the clock frequency of the CPU 11 and the voltage supplied to the CPU 11, for example, the electronic device 10 can control the power consumption of the CPU 11 so as not to exceed the power upper limit PL1 or the power upper limit PL2 as described above. .

The power control of the CPU 11 as described above is intended to maximize the performance of the CPU 11 while keeping the temperature rise of the electronic device 10 within an allowable range.

However, depending on conditions such as the power consumption required of the CPU 11 under a high load condition, the structure of the cooling unit 35, etc., the heat pipe 352 may dry out due to the operation of the CPU 11 under the high load condition shown in FIG. have a nature.
Dry-out is a phenomenon in which the heat pipe 352 receives an excessive amount of heat, making it impossible for the working fluid to change from the vapor phase to the liquid phase, and the liquid-phase working fluid does not flow into the evaporator. The heat pipe 352 that has dried out loses its heat diffusion function. Therefore, it becomes difficult to effectively cool the CPU 11 when the heat pipe 352 is in a dry-out state.
At present, there is a tendency that the power consumption required under high load conditions is increasing. On the other hand, the thickness of the heat pipe 352 is also being reduced in response to the demand for miniaturization, weight reduction, and the like of the electronic device 10 . Therefore, the heat pipe 352 tends to dry out due to the operation of the CPU 11 in a high load state.

Therefore, the electronic device 10 of the present embodiment controls the power upper limit value (upper limit power control) as follows when the CPU 11 is in a high load state, thereby preventing the occurrence of dryout in the heat pipe 352. made to avoid.

FIG. 5 shows an example of the upper limit power control performed by the electronic device 10 according to the high load state.
In the figure, after time t0, the CPU 11 is in a low load state where the load is below a certain level, and the power consumption Pid of the CPU 11 corresponding to the low load state is generated.
At time t11 after a certain amount of time has passed since time t0, the CPU 11 transitioned to the high load state.
At time t11, which is the start timing of the transition to the high load state, the electronic device 10 sets the first stage power upper limit value Pm−1 as the power upper limit value instead of setting the power upper limit value PL2. In the example shown in the figure, the first-stage power upper limit value Pm-1 is a power upper limit value higher than the power upper limit value PL1 but lower than the power upper limit value PL2.
At time t12 after a predetermined duration T(1) has elapsed from time t11, the electronic device 10 sets the power upper limit value to a second-stage power value increased by a constant value from the first-stage power upper limit value Pm-1. Set the upper limit value Pm-2.
At time t13 after the duration T(2) has elapsed from time t12, the electronic device 10 sets the power upper limit to the third-step power upper limit value obtained by increasing the second-step power upper limit value Pm−2 by a constant value. Set Pm-3.
At time t14 after the duration T(3) has elapsed from time t13, the electronic device 10 sets the power upper limit to a fourth-stage power upper limit value increased by a constant value from the third-stage power upper limit Pm-3. Set Pm-4. The figure shows an example in which the fourth stage power upper limit value Pm-4 is the same as the power upper limit value PL2.
At time t15 after duration T(4) has elapsed from time t14, electronic device 10 sets power upper limit PL1.

It should be noted that the length of the period from time t11 to t15 in which upper limit power control is performed in FIG. 5 need not be particularly limited by the maximum allowable time defined corresponding to power upper limit PL2. In other words, the period from times t11 to t15 may be shorter or longer than the maximum allowable time corresponding to power upper limit PL2.

In the following description, when the first stage power upper limit value Pm-1, the second power upper limit value Pm-2, the third power upper limit value Pm-3, and the fourth power upper limit value Pm-4 are not particularly distinguished, , the step power upper limit value Pm.

As described above, the electronic device 10 sets the power upper limit value according to the transition from the low load state to the high load state by increasing the stepped power upper limit value Pm step by step every time a predetermined time elapses. to control.
The CPU 11 is controlled to operate with power consumption up to the set stepped power upper limit value Pm in each of durations T1 to T4 that are sequentially determined as time elapses. Since the stepped power upper limit value Pm is increased for each duration T1 to T4, the allowable power consumption limit for the CPU 11 is released so as to be increased step by step for each duration T1 to T4. Become.

In this way, the upper limit of the allowable power consumption of the CPU 11 is increased in stages when the load is high, so that the amount of heat generated by the CPU 11 does not increase sharply, but slows down to a certain extent. It will continue to increase.
As a result, when the CPU 11 is under a high load, the amount of heat received by the heat pipe 352 is suppressed to a certain level or less, and excessive heat is not received in a short period of time. As a result, even when the CPU 11 is in a high-load state, the working fluid changes from the vapor phase to the liquid phase in the condensing portion of the heat pipe 352, and the state in which the liquid-phase working fluid flows into the evaporating portion is maintained. 352 can maintain the function of heat spreading.

Note that the stepped power upper limit values Pm illustrated in FIG. 5 are all set to values greater than the power upper limit value PL1 and equal to or lower than the power upper limit value PL2. However, among the tiered power upper limit values Pm, some may be set to values lower than the power upper limit PL1, and some may be set to values higher than the power upper limit PL2.
As an example, among the tiered power upper limit values Pm, the first tier power upper limit value Pm-1 is set to a lower value than the power upper limit value PL1, and the second tier power upper limit value Pm-2 and the third tier power upper limit value Pm are set. -3 may be set to a value between the power upper limit PL1 and the power upper limit PL2, and the fourth power upper limit Pm-4 may be set to a value higher than the power upper limit PL2.
Also, a value less than the power upper limit value PL2 may be set for the maximum tiered power upper limit value, such as the fourth tier power upper limit value Pm-4 in FIG.
The duration times T(1) to T(4) corresponding to each step power upper limit value Pm may be the same or may be different as appropriate.
Although FIG. 5 shows an example in which the stepped power upper limit value Pm is changed in four steps, the number of steps of the stepped power upper limit value Pm may be changed as appropriate.
Further, FIG. 5 shows an example in which the stepped power upper limit value Pm is changed so as to increase stepwise as time elapses. However, the tiered power upper limit value Pm may be changed so that a value lower than the tiered power upper limit value Pm of the previous stage is set at a certain stage.

A configuration example of the electronic device 10 for realizing the upper limit power control of the present embodiment performed as described above will be described below.
FIG. 6 shows a functional configuration example of the electronic device 10 corresponding to the upper limit power control of this embodiment. The electronic device 10 shown in FIG. In the same figure, the CPU 11 and the power supply circuit 33 to be controlled by the control unit 200 by the upper limit power control are shown together with the above units.

The control unit 200 has a power control unit 201 . The power control unit 201 performs upper limit power control. For upper limit power control, the power control unit 201 can control, for example, the clock frequency of the CPU 11 and the voltage of power supplied to the CPU 11 from the power supply circuit 33 .
A function of the control unit 200 including the power control unit 201 is realized by the embedded controller 31 executing a program, for example.

The stepped power upper limit value table storage unit 301 stores a stepped power upper limit value table. The stepped power upper limit value table is a table showing the stepped power upper limit value set by the power control unit 201 corresponding to upper limit power control.

FIG. 7 shows an example of a tiered power upper limit value table stored in the tiered power upper limit value table storage unit 301 . The stepped power upper limit value table in the figure corresponds to the example in FIG. Duration times T(1) to T(4) associated with each step power upper limit value Pm of each step are shown.

An example of a processing procedure executed by the electronic device 10 according to the present embodiment for upper limit power control will be described with reference to the flowchart of FIG. 8 . The power control unit 201 executes the processing in FIG.
Step S101: The power control unit 201 waits for the CPU 11 to transition from the low load state to the high load state.
Step S102: When the power control unit 201 determines that the CPU 11 has transitioned from the low load state to the high load state, it performs initialization by substituting "1" for the variable n indicating the number of steps of the step power upper limit value. .

Step S103: The power control unit 201 acquires the n-th stage power upper limit value Pm-n from the stage power upper limit value table, and sets the acquired n-th stage power upper limit value Pm-n as the power upper limit value of the CPU 11. FIG. By setting the power upper limit value Pm-n in this manner, the CPU 11 operates so that the power consumption becomes substantially maximum within a range not exceeding the power upper limit value Pm-n. For this reason, the power control unit 201 controls the clock frequency of the CPU 11 and the voltage applied to the CPU 11 from the power supply circuit 33 so that the power consumption of the CPU 11 is maximized within a range not exceeding the power upper limit value Pm-n. You can As a result, the power control unit 201 can operate the CPU 11 with the maximum performance within a range in which the power consumption does not exceed the power upper limit value Pm-n.

Step S104: After setting the n-th stage power upper limit value in step S103, the power control unit 201 waits until the duration T(n) associated with the n-th stage in the stage power upper limit table elapses. As a result, the n-th stage power upper limit value is continued over the duration time T(n).

Step S105: After the duration T(n) has elapsed, the power control unit 201 determines whether the current variable n is equal to or greater than the maximum value.
Step S106: If it is determined in step S105 that the current variable n is less than the maximum value, it means that the power upper limit value to be increased still remains. Therefore, if the current variable n is less than the maximum value, the power control unit 201 increments the variable n and returns the process to step S103. As a result, the state in which the next n-th stage power upper limit value Pm-n is set continues for the duration T(n).
Step S107: When it is determined in step S105 that the current variable n is equal to or greater than the maximum value, the power control unit 201 ends the stepwise upper limit power control and switches to normal power control. . In normal power control, the power control unit 201 operates the CPU 11 under the setting of the power upper limit PL1 corresponding to the steady state.

<Second embodiment>
Next, a second embodiment will be described. In the first embodiment described above, as the upper limit power control, the predetermined stepped power upper limit value Pm is changed for each duration. In contrast, in the present embodiment, the stepped power upper limit value Pm is changed according to the temperature state of the heat pipe 352 .
As for the temperature state of the heat pipe 352, when the difference between the temperature of the evaporator and the temperature of the condenser is equal to or greater than a predetermined value, the heat diffusion function is maintained without causing dryout. If the difference between the temperature and the temperature of the part is reduced to within a predetermined range, it is considered that dryout has occurred.
Therefore, the power control unit 201 of the present embodiment changes the stepped power upper limit value Pm according to the temperature difference (heat pipe temperature difference) between the evaporating portion and the condensing portion in the heat pipe 352 as described above. .

The information processing apparatus 10 of this embodiment includes temperature sensors 353 (353a, 353b) (FIG. 2). The temperature sensor 353a is provided to detect the temperature of the portion of the heat pipe 352 corresponding to the evaporator. A temperature sensor 353b is provided to detect the temperature of the portion corresponding to the condensation section.
Detection outputs of the temperature sensors 353 (353a, 353b) are input to the embedded controller 31 as shown in FIG. Thereby, the power control section 201, which is a functional section of the embedded controller 31, can detect (calculate) the heat pipe temperature difference based on the detection output of the temperature sensors 353 (353a, 353b). That is, the power control unit 201 may detect the heat pipe temperature difference by calculating the difference between the temperature indicated by the detection output of the temperature sensor 353a and the temperature indicated by the detection output of the temperature sensor 353b.
In this embodiment, the power control unit 201, which is a functional unit of the embedded controller 31, can perform upper limit power control according to the calculated heat pipe temperature difference.

FIG. 9 shows an example of one mode of upper limit power control according to the present embodiment. Here, when the tiered power upper limit values (Pm-1 to Pm-4) indicated by the tiered power upper limit value table illustrated in FIG. will be described as an example.

In the figure, after time t0, the CPU 11 is in a low load state where the load is below a certain level, and the power consumption Pid of the CPU 11 corresponding to the low load state is generated.
At time t11 after a certain amount of time has passed since time t0, the CPU 11 transitioned to the high load state.
At time t11, which is the start timing of the transition to the high load state, the power control unit 201 calculates the current heat pipe temperature difference. Based on the calculated heat pipe temperature difference, the power control unit 201 calculates a change amount v(1) for the first step power upper limit value Pm-1 indicated by the step power upper limit value table. The power control unit 201 adds the calculated positive change amount v(1) to the reference value Pm-1 as the first step power upper limit value Pm-1 (v1 ).
In the example shown in the figure, the power control unit 201 calculates the change amount v(1) as a positive value. As a result, a value higher than the reference value Pm-1 is set as the first-stage power upper limit value. When the change amount is calculated as a positive value in this way, it corresponds to, for example, the case where the detected heat pipe temperature difference is larger than a certain value. If the heat pipe temperature difference is large, there is a margin in the amount of heat that the heat pipe 352 can receive. Therefore, when the heat pipe temperature difference is greater than a certain value, the power control unit 201 calculates a change amount as a positive value corresponding to the heat pipe temperature difference. As a result, when the heat pipe 352 has sufficient function, the performance of the CPU 11 can be improved by setting the power upper limit with a value higher than the reference value.

Next, when the duration time T (1) elapses from time t11 to time t12, the power control unit 201 detects the current heat pipe temperature difference, and uses the detected heat pipe temperature difference to determine the amount of change. Also in this case, the heat pipe temperature difference is greater than a certain value, so the power control unit 201 calculates the change amount v(2) as a positive value.The power control unit 201 performs the second step. As the power upper limit value, a value Pm-2(v) obtained by adding the calculated positive change amount v(2) to the reference value Pm-2 is set.

Next, at time t13 when the duration time T (2) has elapsed from time t12, power control unit 201 detects the current heat pipe temperature difference, and uses the detected heat pipe temperature difference to change amount v3. In this case, the power control unit 201 calculates the change amount v(3) by a negative value.The power control unit 201 calculates the third-stage power upper limit value with respect to the reference value Pm-3: A value Pm-3(v) obtained by adding the calculated negative change amount v(3) is set.
When the change amount is calculated as a negative value in this way, it corresponds to the case where the detected heat pipe temperature difference is smaller than the predetermined value. In this case, it is necessary to suppress an increase in heat generation of the CPU 11 . Therefore, in such a case, the amount of change is set as a negative value, and the stepped power upper limit value is set to a value lower than the reference value so as to increase the heat generation of the CPU 11 .

Next, the power control unit 201 detects the current heat pipe temperature difference from time t13 to time t14 when the duration time T(3) has passed, and uses the detected heat pipe temperature difference to change the amount of change v(4). ).In this case, the power control unit 201 calculates the change amount v(4) equal to the reference value Pm-4.In this case, the power control unit 201 calculates the reference value The same value Pm-4(v) as Pm-4 is set.
In this case as well, power control unit 201 sets power upper limit PL1 at time t15 after duration T(4) has elapsed from time t14.

For example, depending on the ambient temperature of the CPU 11 and the load state of the CPU 11, the heat generated by the CPU 11 in a high-load state may increase considerably. Dryout can occur in pipe 352 . On the other hand, when the heat generated by the CPU 11 is low, the performance of the CPU 11 can be further improved by setting a power upper limit value higher than the fixed stepped power upper limit value Pm-n.
Therefore, if the stepped power upper limit value Pm is changed according to the heat pipe temperature difference, as in the upper limit power control shown in FIG. It is possible to perform upper limit power control while maintaining

An example of a processing procedure executed by the electronic device 10 according to the present embodiment for upper limit power control will be described with reference to the flowchart of FIG. 10 .
The processing of steps S201 and S202 is the same as the processing of steps S101 and S102 in FIG.

Step S203: The power control unit 201 detects the heat pipe temperature difference using the temperatures indicated by the detection outputs of the temperature sensors 353a and 353b.
Step S204: The power control unit 201 calculates the change amount v(n) based on the heat pipe temperature difference calculated in step S203.

Step S205: The power control unit 201 adds the change amount v(n) calculated in step S204 to the reference value Pm-n of the n-th stage power upper limit value acquired from the stage power upper limit table. , the n-th stage power upper limit value Pm−n(v) is calculated.
Step S206: The power control unit 201 sets the n-th stage power upper limit value Pm-n(v) calculated in step S205 as the power upper limit value for the CPU 11 .

The processing of steps S207-S209 is the same as that of steps S104-S106 in FIG. After the process of step S209, the process is returned to step S203. Also, the process of step S210 is the same as the process of step S107 in FIG.

In the above example, the temperature state of the heat pipe 352 is determined based on the temperature difference between the evaporating portion and the condensing portion of the heat pipe 352 . However, for example, the power control unit 201 may simply obtain the amount of change based on the temperature of a predetermined portion of the heat pipe 352 . Alternatively, the power control unit 201 may indirectly treat the temperature detected for the CPU 11 as the temperature state of the heat pipe to obtain the amount of change.
In this embodiment, the power control unit 201 changes the step power upper limit value Pm-n(v) and the length of the duration T(n) for each step according to the temperature state of the heat pipe 352. may Alternatively, the power control unit 201 does not change the step power upper limit value Pm-n for each step at the reference value, and then adjusts the length of the duration T(n) according to the temperature state of the heat pipe 352. may be changed.

Note that the electronic device 10 of the above-described embodiment is a portable type such as a clamshell personal computer, a tablet terminal, or a smart phone, and is configured such that a display device is integrally attached to a housing. However, the electronic device according to the present embodiment may be, for example, a desktop personal computer, in which a main body of each individual device and a display device are connected. Furthermore, the electronic device according to the present embodiment can be applied to devices in general that include a CPU.

Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to the above embodiments, and includes designs and the like within the scope of the gist of the present invention. Each configuration described in the above embodiments can be arbitrarily combined as long as there is no contradiction.

10 information processing device 33 power supply circuit 101 first housing 102 second housing 103 hinge mechanism 11 CPU 21 chipset 31 embedded controller 32 input unit 33 power supply circuit 35 cooling unit 200 control unit, 201, power control unit, 301 stage power upper limit value table storage unit

Claims (5)

an arithmetic processing unit;
a heat diffusion device that is used for cooling the arithmetic processing unit and diffuses heat emitted from the arithmetic processing unit;
An electronic device comprising: a power control unit that performs upper limit power control to change a power upper limit, which is an upper limit of power consumption defined for the arithmetic processing unit, according to the passage of time. The electronic device according to claim 1, wherein the power control unit performs the upper limit power control in response to transition to a state in which the load of the arithmetic processing unit becomes a certain level or more. The electronic device according to claim 1 or 2, wherein the power control unit performs control so as to change the power upper limit value for each duration that is sequentially set over time. The electronic device according to any one of claims 1 to 3, wherein the power control unit sets the power upper limit value that changes over time based on the temperature state of the heat diffusion device. A power control method in an electronic device comprising an arithmetic processing unit and a heat diffusion device used for cooling the arithmetic processing unit and diffusing heat emitted from the arithmetic processing unit,
A power control method, comprising: performing upper limit power control for changing, according to the passage of time, a power upper limit, which is an upper limit of power consumption defined for the arithmetic processing unit.

Images