JP2022114026A - Modulator, demodulator, and communication device - Google Patents

Abstract

To suppress an increase in circuit scale necessary to calculate a logarithmic likelihood ratio when Gray mapping is used.SOLUTION: A modulator includes: an upper bit modulation unit 12 that performs mapping according to ideal symbol point arrangement of upper bits and outputs a symbol point corresponding to the upper bits; a lower bit modulation unit 14 that performs mapping according to ideal symbol point arrangement of lower bits and outputs a symbol point corresponding to the lower bits; and a transmission code control unit 16 that controls reversal operation of a code of a coordinate value of the symbol point corresponding to the lower bits based on a sequence of the upper bits. The transmission code control unit 16 controls the reversal operation of the code of the coordinate value of the symbol point corresponding to the lower bits based on the sequence of the upper bits so that in a state assigned to each of hard-decision decision areas corresponding to the ideal symbol point arrangement of the upper bits, the values of the lower bits corresponding to the ideal symbol points adjacent to each other across a boundary of the hard-decision decision areas are the same.SELECTED DRAWING: Figure 1

Description

The present invention relates to a modulation device, a demodulation device, and a communication device, and more particularly to a modulation device that performs Gray mapping processing, a demodulation device that calculates a log-likelihood ratio, and a communication device that includes the modulation device and the demodulation device.

Conventionally, when applying a low-density parity check (LDPC: abbreviation for Low Density Parity Check) to a high multilevel quadrature amplitude modulation (QAM: abbreviation for Quadrature Amplitude Modulation) system, the modulation sequence is divided into upper bits and lower bits. There is a method for improving the coding rate and reducing the circuit scale by separating the data into two and applying a low-density parity check code only to the lower bits. Double gray mapping is known as a mapping method when using this method (Non-Patent Document 1).

However, the double gray mapping has a problem that if a bit error occurs in the upper bit, the error rate of the lower bit also deteriorates.

E. Eleftheriou & S. Olcer, "Low-Density Parity-Check Codes for Digital Subscriber Lines", IEEE International Conference on Communications, Apr. 28, 2002, pp. 1753-1757.

By the way, in order to solve the problem of the above-mentioned double gray mapping, it is conceivable to improve the error rate of the lower bits when the upper bits are erroneous by using rotationally symmetrical gray mapping as the mapping method. However, if the rotationally symmetric double Gray mapping is used as it is, there is a problem that the circuit scale required for calculating the log-likelihood ratio increases.

Accordingly, the present invention provides a modulation device, a demodulation device, and a communication device including the modulation device and the demodulation device, which are capable of suppressing an increase in the circuit scale required to calculate a log-likelihood ratio when using Gray mapping. intended to provide

In order to solve the above problem, the invention according to claim 1 performs mapping according to the ideal symbol point arrangement of the upper bits to the upper bit series of the series of a predetermined number of bits to correspond to the upper bits. a high-order bit modulation unit for outputting symbol points; mapping a sequence of low-order bits in the sequence of the predetermined number of bits according to an ideal symbol point arrangement of the low-order bits, and outputting symbol points corresponding to the low-order bits; a low-order bit modulation unit; and a transmission code control unit for controlling sign inversion of the coordinate values of the symbol points corresponding to the low-order bits based on the sequence of the high-order bits, wherein the transmission code control unit , the values of the lower bits corresponding to the ideal symbol points adjacent to each other across the boundary of the hard-decision determination area are the same in the state assigned to each of the hard-decision determination areas corresponding to the ideal symbol point arrangement of the upper-bit. The modulating device is characterized in that the operation of reversing the sign of the coordinate values of the symbol points corresponding to the lower bits is controlled based on the sequence of the upper bits so that

According to a second aspect of the present invention, in the modulation device according to the first aspect, the gain of the coordinate values of the symbol points corresponding to the lower bits is the predetermined number of bits, and the interval between the ideal symbol points of the lower bits is the predetermined number of bits. It is characterized in that it has a level adjustment section that adjusts it so as to match the interval of the ideal symbol points in the modulation system of the sequence.

The invention according to claim 3 is the modulation device according to claim 1 or 2, further comprising an LDPC coding unit that performs low-density parity check coding processing on a sequence of lower bits in the sequence of the predetermined number of bits. characterized by having

The invention according to claim 4 is the modulation device according to any one of claims 1 to 3, wherein the sequence of the predetermined number of bits is a 6-bit sequence, and the upper bits are a 4-bit sequence. It is characterized in that the lower bits are a series of 2 bits.

In the invention according to claim 5, a hard decision is performed on a received signal according to the ideal symbol point arrangement of the upper bits, and the upper bit series of the series of a predetermined number of bits and the ideal symbol corresponding to the upper bits are determined. a high-order bit determination unit that outputs a point; a subtraction unit that subtracts the ideal symbol point corresponding to the high-order bit from the received signal and outputs a received signal after the high-order bit is subtracted; a reception code control unit for controlling a sign inversion operation of the coordinate values of the received signal after subtraction of the high-order bits, wherein the reception code control unit performs the hard decision corresponding to the ideal symbol point arrangement of the high-order bits. In the state assigned to each of the decision areas of the hard decision, the lower bits are reversed on the transmitting side so that the values of the lower bits corresponding to the ideal symbol points adjacent to each other across the boundary of the hard decision area become the same. Inverting the sign of the coordinate value of the received signal after the subtraction of the high-order bit is controlled based on the sequence of the high-order bit so as to restore the sign of the coordinate value of the symbol point corresponding to the bit. It is a demodulator that

The invention according to claim 6 is characterized in that, in the demodulator according to claim 5, it further comprises a level adjustment section for adjusting the gain of the coordinate value of the received signal after subtraction of the upper bits.

The invention according to claim 7 is the demodulator according to claim 6, based on the coordinate values after the sign inversion operation and the gain adjustment of the coordinate values, out of the series of the predetermined number of bits. It is characterized by having a log-likelihood ratio calculator for calculating a log-likelihood ratio of each bit constituting a series of lower bits.

The invention according to claim 8 is the demodulation device according to claim 7, further comprising an LDPC decoding unit that performs error correction based on the logarithmic likelihood ratio and outputs the sequence of the lower bits. do.

The invention according to claim 9 is the demodulator according to any one of claims 5 to 8, wherein the sequence of the predetermined number of bits is a 6-bit sequence, and the upper bits are a 4-bit sequence. It is characterized in that the lower bits are a series of 2 bits.

The invention according to claim 10 is directed to at least one of the modulation device according to any one of claims 1 to 4 and the demodulation device according to any one of claims 5 to 9. A communication device characterized by comprising:

According to the inventions of claims 1 to 9, on the transmitting side, the code of the coordinate value of the symbol point corresponding to the lower bit obtained by mapping according to the ideal symbol point arrangement of the lower bit is converted to the ideal symbol of the upper bit. In the state assigned to each of the hard-decision determination regions corresponding to the point arrangement, the values of the upper bits corresponding to the ideal symbol points adjacent to each other across the boundaries of the hard-decision determination regions are the same. Since the inversion operation is performed based on the series, it is possible to suppress an increase in the circuit scale required for calculating the logarithmic likelihood ratio when using Gray mapping. In addition, it is possible to reduce the demodulation error rate in calculating the log-likelihood ratio while suppressing an increase in circuit size.

According to the tenth aspect of the invention, it is possible to achieve the above effects in a communication apparatus that performs error correction in low-density parity check decoding using logarithmic likelihood ratios.

1 is a functional block diagram showing a schematic configuration of a modulation device according to an embodiment of the invention; FIG. It is a figure which shows the mapping of a 6-bit series in embodiment. It is a figure which shows the list of the mapping pattern of a low-order bit in embodiment. FIG. 10 is a diagram showing the correspondence between hard decision regions of upper bits and mapping patterns of lower bits in the embodiment; FIG. 10 is a diagram showing an ideal symbol point arrangement of high-order bits in the embodiment; FIG. 10 is a diagram showing an ideal symbol point arrangement of lower bits in the embodiment; FIG. 10 is a diagram showing an ideal symbol point arrangement of lower bits after level adjustment in the embodiment; 1 is a functional block diagram showing a schematic configuration of a demodulator according to an embodiment of the invention; FIG. FIG. 4 is a diagram showing the correspondence between a hard-decision region for upper bits and a sequence of upper bits in the embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments. In the following, the characteristic configuration of the present invention will be explained, and the explanation of the mechanism similar to the conventional one when performing various communications will be omitted. In each figure, a signal line for transmitting a real part (I signal; in other words, in-phase component, I signal component) and an imaginary part (Q signal; in other words, quadrature component, Q signal component) constituting a complex signal ) are collectively shown as one signal line.

In this embodiment, modulation/demodulation of data is performed by a modulation device 1 provided in a communication device on the transmission side and a demodulation device 2 provided in a communication device on the reception side. It should be noted that two-way communication may be performed and both the modulation device 1 and the demodulation device 2 may be provided in the communication device.

In this embodiment, a case where 6-bit series data, which is a signal of the quadrature amplitude modulation method (that is, 64QAM method) with 64 multilevel values, is divided into upper 4 bits and lower 2 bits and transmitted and received will be described as an example. do. FIG. 2 shows an example of mapping used in this embodiment, in which 6-bit series data is divided into 4 high-order bits and 2 low-order bits.

FIG. 2 shows the I value of the in-phase component (that is, the coordinate value of the I-axis, the real part) and the quadrature component on the complex plane, which is an orthogonal coordinate system of the I-axis corresponding to the real part and the Q-axis corresponding to the imaginary part. A region specified as a combination with a Q value (that is, a coordinate value of the Q axis, the imaginary part) and a corresponding relationship between an ideal symbol point and a bit sequence are defined as a mapping pattern. In FIG. 2, the 4-digit series within the rectangular frame represents the upper 4 bits, and the 2-digit series near the circle representing the ideal symbol point position represents the lower 2 bits.

In the example shown in FIG. 2, the upper bits (4 bits) are mapped based on 16QAM Gray mapping, and the lower bits (2 bits) are mapped by quadrature phase shift keying (QPSK: an abbreviation for Quadrature Phase Shift Keying) Gray mapping. It is mapped based on

Here, in the present invention, the lower bits are mapped in four patterns in order to prevent the lower bits from being affected when a bit error occurs in the upper bits. Specifically, by adjusting the arrangement of the four patterns applied to the lower bits (in other words, the mutual positional relationship of the four patterns), Adjacent ideal symbol points are mapped so that the value of the lower bit does not change (in other words, the value of the lower bit is the same).

FIG. 3 shows a list of lower bit mapping patterns for realizing the mapping shown in FIG. 2, and FIG. Correspondence with bit mapping pattern is shown.

The examples shown in FIGS. 2 to 4 will be specifically described below.

A transmission-side communication device generates a modulated wave from a sequence of information bits representing information to be transmitted, and transmits the modulated wave to a reception-side communication device. Note that the modulated wave is transmitted as a radio signal, an electrical signal, an optical signal, or the like.

A communication device on the receiving side receives a signal in which a modulated wave transmitted from a communication device on the transmitting side is transmitted through a predetermined communication path, and corrects an information bit sequence in which an error has occurred in the received signal. , to generate and output a sequence of information bits after error correction.

FIG. 1 is a functional block diagram showing a schematic configuration of a modulation device 1 according to an embodiment of the invention.

The modulation apparatus 1 according to the embodiment performs mapping according to the ideal symbol point arrangement of the upper bits to the upper bit series of the series of a predetermined number of bits (in this embodiment, a 6-bit series), and maps to the upper bits. A high-order bit modulation unit 12 for outputting a corresponding symbol point performs mapping according to the ideal symbol point arrangement of the low-order bits for the low-order bit series of the series of the predetermined number of bits to generate symbol points corresponding to the low-order bits. and a transmission code control unit 16 for controlling the sign inversion operation of the coordinate values of the symbol points corresponding to the low-order bits based on the sequence of the high-order bits, and the transmission code control unit 16 is assigned to each of the hard-decision decision areas corresponding to the ideal symbol point arrangement of the upper bits, the values of the lower bits corresponding to the ideal symbol points adjacent to each other across the boundaries of the hard-decision decision areas are the same. Thus, the operation of inverting the sign of the coordinate value of the symbol point corresponding to the lower bit is controlled based on the series of upper bits.

The sequence separation unit 11 receives an input of a 6-bit information bit sequence representing information to be transmitted, separates the information bits into 4-bit and 2-bit data sequences, and divides the data of the 4-bit data sequence into upper bits. , and the 2-bit data in the data sequence is output to the LDPC encoding unit 13 as lower bits.

The high-order bit modulation unit 12 receives the input of the high-order bit (4-bit) sequence output from the sequence separation unit 11, and converts the high-order bit data to a quadrature phase amplitude modulation method with 16 multilevel values (that is, 16QAM system), and outputs symbol points corresponding to high-order bits after modulation processing. The mapping in the high-order bit modulation unit 12 follows the so-called Gray mapping in which the Hamming distance between each bit string assigned to each adjacent ideal symbol point is 1. FIG. 5 shows the ideal symbol point arrangement for upper bits.

Specifically, according to the ideal symbol point arrangement of the upper bits shown in FIG. A combination of the I value of the in-phase component (that is, the coordinate value of the I axis, the real part) and the Q value of the quadrature component (that is, the coordinate value of the Q axis, the imaginary part) based on the ideal symbol point arrangement of bits is output.

The LDPC encoding unit 13 receives the input of the lower bit (2-bit) sequence output from the sequence separation unit 11, performs low-density parity check (LDPC) encoding processing on the data of the lower bits, and outputs the result. .

The lower bit modulation unit 14 receives the input of the lower bit data after the low-density parity check encoding process output from the LDPC encoding unit 13, and applies the quadrature phase shift keying (QPSK) method to the lower bit data. , and outputs a symbol point corresponding to the lower bit after modulation processing. Mapping in the low-order bit modulation unit 14 follows Gray mapping. FIG. 6 shows the ideal symbol point arrangement for lower bits.

Specifically, the lower bit modulation unit 14 arranges ideal symbol points on the complex plane corresponding to the lower bits after the low-density parity check encoding process according to the ideal symbol point arrangement of the lower bits shown in FIG. As the information to be represented, the I value of the in-phase component based on the ideal symbol point arrangement of the lower bits shown in FIG. part) is output.

The level adjustment unit 15 outputs the I value of the in-phase component (that is, the coordinate value of the I axis, the real part) and the Q value of the quadrature component (that is, the , Q-axis coordinate value, imaginary part), the gain of the symbol point (coordinate value) corresponding to the lower bit, the interval of the ideal symbol point of the lower bit as a whole (that is, the 6-bit sequence ) is adjusted to match the ideal symbol point interval in the modulation method, and output.

In this embodiment, the ideal symbol point interval in the modulation scheme for the entire (that is, 6-bit series) is 2 as shown in FIG. 2, and the ideal symbol point interval ( In other words, the interval between the ideal symbol points of the lower bits is 10 as shown in FIG. Therefore, the combination of the I value and the Q value is multiplied by 1/5 (=2/10) as a level adjustment coefficient to adjust the amplitude of the symbol point to 1/5. FIG. 7 shows the ideal symbol point arrangement of the lower bits after level adjustment. Since the symbol interval can be appropriately adjusted in the level adjustment section 15, the interval between the ideal symbol points is not limited to a specific value.

Here, the level adjustment processing by the level adjustment section 15 is inserted in order to reduce the mapping patterns processed by the low-order bit modulation section 14 . That is, if the level adjustment unit 15 is not incorporated, it is necessary to change the mapping pattern of the lower bit modulation unit 14 for each symbol interval when using a plurality of modulation schemes with different ideal symbol point intervals such as adaptive modulation. There is a problem that the circuit scale increases. On the other hand, by performing the level adjustment processing by the level adjustment section 15, the above problems can be avoided and the increase in circuit size can be suppressed.

The transmission code control unit 16 receives the input of the high-order bit (4 bits) sequence output from the sequence separation unit 11, and the symbol point corresponding to the low-order bit (2 bits) after level adjustment output from the level adjustment unit 15. In response to the input of the I value of the in-phase component (that is, the coordinate value of the I axis, the real part) and the Q value of the quadrature component (that is, the coordinate value of the Q axis, the imaginary part), based on the sequence of the upper bits to control the inversion operation of the sign of the in-phase component and quadrature component (specifically, the coordinate value) of the symbol point corresponding to the lower bit (specifically, by inverting the positive/negative), and FIG. to one of the lower bit mapping patterns 1 to 4 shown in FIG.

The transmission code control unit 16 determines that the value of the lower bit corresponding to (in other words, linked to) the ideal symbol point adjacent via the boundary of the decision area of the hard decision of QAM modulation corresponding to the sequence of the upper bit is The operation of inverting the sign of the in-phase component and quadrature component (specifically, the coordinate values) of the symbol point is controlled so that they do not change (in other words, the values of the lower bits become the same).

Specifically, in this embodiment, the transmission code control unit 16 controls the high-order bit sequence so that the correspondence relationship between the high-order bit hard decision region and the low-order bit mapping pattern as shown in FIG. Based on, using the correspondence between the high-order bit sequence and the code operation pattern as shown in Tables 1 and 2, and the code operation content for each code operation pattern as shown in Table 3, the low-order bit Controls the sign inversion operation of the in-phase and quadrature components of the symbol points corresponding to .

The transmission code control unit 16 adjusts the code based on the sequence of the upper bits so that the corresponding relationship between the upper bit hard decision region and the lower bit mapping pattern after the code operation, that is, as shown in FIG. Outputs the I value of the in-phase component of the manipulated symbol point corresponding to the lower bits (i.e., I-axis coordinate value, real part) and the Q value of the quadrature component (i.e., Q-axis coordinate value, imaginary part). .

Note that the level adjustment processing by the level adjustment unit 15 may be performed after the code manipulation processing by the transmission code control unit 16 is performed.

The addition unit 17 outputs a modulated wave (16QAM system; specifically, the I value of the symbol point corresponding to the high-order bit (i.e., the I-axis ) and a combination of the Q value (that is, the coordinate value of the Q axis)), and a modulated wave corresponding to the lower bits (2 bits) output from the transmission code control unit 16 (QPSK system , after level adjustment and sign operation; specifically, the combination of the I value (that is, the coordinate value of the I axis) and the Q value (that is, the coordinate value of the Q axis) of the symbol point corresponding to the lower bit. Then, the modulated wave corresponding to the upper bit and the modulated wave corresponding to the lower bit are added to calculate and output the modulated wave corresponding to the 6-bit sequence (64QAM system).

The relationship between the modulated wave output from the adder 17 and the information bits is equivalent to the mapping of the 6-bit series (the number of upper bits is 4 and the number of lower bits is 2) shown in FIG.

The modulated wave output from the adder 17 is subjected to, for example, frequency conversion processing, amplification processing, and the like, and then transmitted from the transmission-side communication device via an antenna or the like.

A communication device on the receiving side receives a modulated wave transmitted from a communication device on the transmitting side via an antenna or the like, and performs frequency conversion processing or the like on the modulated wave. Then, the processed signal is input as a received signal to the demodulator 2 of the communication device on the receiving side.

FIG. 8 is a functional block diagram showing a schematic configuration of demodulator 2 according to the embodiment of the present invention.

The demodulator 2 according to the embodiment performs a hard decision on the received signal according to the ideal symbol point arrangement of the upper bits to An upper bit determination unit 21 that outputs an ideal symbol point corresponding to a sequence and an upper bit, a subtraction unit 22 that subtracts an ideal symbol point corresponding to an upper bit from a received signal and outputs a received signal after subtracting the upper bit, A reception code control unit 23 for controlling the operation of inverting the sign of the coordinate value of the received signal after subtraction of the upper bit based on the sequence of the upper bits; A log-likelihood ratio calculation unit 25 for calculating the log-likelihood ratio of each bit constituting the lower-order bit sequence, and an LDPC decoding that performs error correction based on the log-likelihood ratio and outputs the lower-order bit sequence and a receiving code control unit 23 adjacent to each other across the boundary of the hard-decision decision regions in a state in which they are assigned to each of the hard-decision decision regions corresponding to the ideal symbol point arrangement of the upper bits. Based on the series of upper bits, the sign of the coordinate value of the symbol point corresponding to the lower bit, which has been reversed on the transmitting side so that the value of the lower bit corresponding to the ideal symbol point becomes the same, is restored. The operation of inverting the sign of the coordinate value of the received signal after subtraction of the high-order bits is controlled.

The high-order bit determination unit 21 receives the received signal input to the demodulator 2, and performs hard decision processing on the received signal (64QAM system) using the 16QAM system. FIG. 9 shows the correspondence between the hard-decision determination region and the high-order bit series in the hard-decision processing by the high-order bit determination unit 21 .

The high-order bit determination unit 21 outputs 4-bit information bits, which are a sequence of high-order bits obtained as a result of the hard decision processing, and determines symbol points of the 16QAM system (specifically, ideal symbol points) corresponding to the high-order bits. A combination of the I value of the in-phase component (that is, the coordinate value of the I axis) and the Q value of the quadrature component (that is, the coordinate value of the Q axis) is output. The correspondence between the high-order bit sequence and the ideal symbol constellation of the 16QAM system is the same as in FIG.

The subtraction unit 22 receives the input of the received signal input to the demodulation device 2, and also receives the input of the symbol point (specifically, the ideal symbol point) corresponding to the high-order bit output from the high-order bit determination unit 21. Then, the symbol point (specifically, the ideal symbol point) corresponding to the upper bit is subtracted from the received signal and output. A signal output from the subtraction unit 22 is called a "received signal after subtraction of the upper bit".

A soft decision value corresponding to one of the mapping patterns 1 to 4 shown in FIG. 3 is obtained by the processing of the subtractor 22 . Specifically, the received signal after subtraction of the upper bits is orthogonal to the I value (that is, the coordinate value of the I axis) of the in-phase component corresponding to one of the mapping patterns 1 to 4 shown in FIG. It is a combination with the Q value of the component (that is, the coordinate value of the Q axis).

The reception code control unit 23 receives the input of the high-order bit sequence output from the high-order bit determination unit 21, and receives the input of the received signal after the high-order bit subtraction output from the subtraction unit 22, and converts the high-order bit Based on the sequence, using the correspondence between the high-order bit sequence and the code operation pattern as shown in Tables 1 and 2, and the code operation content for each code operation pattern as shown in Table 3, the above It controls the operation of reversing the sign of the in-phase component and the quadrature component of the received signal after the high-order bit subtraction (specifically, the positive/negative is reversed). By the processing of the reception code control unit 23, the signal output from the reception code control unit 23 becomes a soft decision value corresponding to the ideal symbol point arrangement of the lower bits after level adjustment shown in FIG.

The reception code control unit 23 calculates the I value of the in-phase component as a soft decision value corresponding to the ideal symbol point arrangement of the lower bits after the level adjustment shown in FIG. part) and the Q value of the quadrature component (that is, the coordinate value of the Q axis, the imaginary part) is output.

The level adjustment unit 24 outputs the I value of the in-phase component (that is, the coordinate value of the I axis, the real part) and the Q value of the quadrature component (that is, the Q axis of the Q axis) after the code operation. coordinate value, imaginary part), and the reciprocal of the level adjustment coefficient (specifically, 1/5 in this embodiment) in the level adjustment unit 15 of the modulation device 1 is applied to the combination. A multiplication process is performed to adjust the gain of the I value and the Q value and output. By the processing of the level adjustment section 24, the signal output from the level adjustment section 24 becomes a soft decision value corresponding to the ideal symbol point arrangement of the lower bits shown in FIG.

Here, the level adjustment processing by the level adjustment section 24 is inserted in order to reduce the circuit scale of the log-likelihood ratio calculation section 25 in the subsequent stage. That is, if the level adjustment unit 24 is not incorporated, it is necessary to provide the subsequent log-likelihood ratio calculation unit 25 for each symbol interval when using a plurality of modulation schemes with different ideal symbol point intervals such as adaptive modulation. There is a problem that the circuit scale increases. On the other hand, by performing the level adjustment processing by the level adjustment section 24, the above problems can be avoided and the increase in circuit size can be suppressed.

Note that the code manipulation process by the reception code control part 23 may be performed after the level adjustment process by the level adjustment part 24 is performed.

The log-likelihood ratio calculator 25 calculates the I value of the in-phase component (that is, the coordinate value of the I axis) and the Q value of the quadrature component (that is, the Q axis coordinate values), and based on the I value of the in-phase component and the Q value of the quadrature component, the log-likelihood ratio corresponding to each bit constituting the sequence of lower bits is calculated.

At this time, the combination of the I value of the in-phase component and the Q value of the quadrature component input to the log-likelihood ratio calculation unit 25 is the ideal symbol of the lower bits shown in FIG. Follows point placement. That is, the mapping pattern of the lower bits input to the log-likelihood ratio calculator 25 is unified into the ideal symbol point arrangement of the lower bits shown in FIG.

ここに、ＬＬＲm：下位ｂｉｔの系列のｍ ｂｉｔ目の対数尤度比
ｘ：シンボル点の同相成分または直交成分
Ａi：硬判定による理想シンボル点の配置（同相成分または直交成分）
σ²：雑音分散
Ａi(ｍ)＝１：ｍ番目のｂｉｔが１である理想シンボル点の配置
Ａi(ｍ)＝０：ｍ番目のｂｉｔが０である理想シンボル点の配置 Therefore, the log-likelihood ratio is calculated only according to Equation 1 below.

Here, LLRm: log-likelihood ratio of the m-th bit of the sequence of lower bits
x: in-phase or quadrature component of the symbol point
Ai: Arrangement of ideal symbol points by hard decision (in-phase component or quadrature component)
σ ² : noise variance
Ai(m)=1: Arrangement of ideal symbol points where m-th bit is 1
Ai(m)=0: Arrangement of ideal symbol points where m-th bit is 0

The log-likelihood ratio calculation unit 25 outputs the log-likelihood ratio LLRm corresponding to each bit (specifically, the m-th bit) constituting the sequence of lower bits, which is calculated according to Equation 1 above.

The LDPC decoding unit 26 receives the input of the log-likelihood ratio LLRm output from the log-likelihood ratio calculation unit 25, performs error correction based on the log-likelihood ratio LLRm, and converts a 2-bit sequence of lower bits. Output information bits.

The sequence synthesizing unit 27 receives the input of the high-order bit sequence (specifically, 4-bit information bits) output from the high-order bit determination unit 21, and receives the input of the low-order bit sequence (specifically, 4-bit information bits) output from the LDPC decoding unit 26. Specifically, it receives an input of 2-bit information bits), synthesizes the high-order bit series and the low-order bit series, and outputs a 6-bit information bit series.

According to the modulation apparatus 1 and the demodulation apparatus 2 according to the embodiment, on the transmitting side, the code of the coordinate value of the symbol point corresponding to the lower bit obtained by mapping according to the ideal symbol point arrangement of the lower bit is converted to the ideal symbol point arrangement of the upper bit. In the state assigned to each of the hard-decision determination areas corresponding to the symbol point arrangement, the upper bit is adjusted so that the values of the lower bits corresponding to the ideal symbol points adjacent to each other across the boundary of the hard-decision determination area are the same. Since the inversion operation is performed based on the series of , it is possible to suppress an increase in the circuit scale required to calculate the logarithmic likelihood ratio when using Gray mapping. Moreover, it is possible to reduce the error rate of demodulation in calculating the log-likelihood ratio while suppressing an increase in circuit size.

Although the embodiments of the present invention have been described above, the specific configuration is not limited to the above-described embodiments. Included in the invention.

For example, in the above embodiment, the circuit configuration of the modulation device 1 according to the present invention is shown in FIG. 1 and the circuit configuration of the demodulation device 2 is shown in FIG. 1 and demodulator 2 are not limited to the configurations shown in FIGS. 1 and 8, and the circuit configurations of modulator 1 and demodulator 2 may be configured in other modes. That is, the main point of the modulation device 1 and the demodulation device 2 according to the present invention is that, in a state assigned to each of the hard-decision decision regions corresponding to the ideal symbol point arrangement of the upper bits, It is to control the operation of reversing the sign of the coordinate values of the symbol points corresponding to the lower bits based on the sequence of the upper bits so that the values of the lower bits corresponding to the adjacent ideal symbol points are the same. A specific circuit for realizing is not limited to a specific configuration.

Further, in the above embodiment, the case of the 64QAM system using mapping in which a 6-bit sequence is assigned to each of 64 ideal symbol points has been described, but the scope of application of the present invention is the sequence (in other words, bit column) is not limited to 6 bits, and the multilevel number of the quadrature amplitude modulation (QAM) method is not limited to 64. According to the present invention, an original sequence (bit sequence) is separated into an appropriate number of upper bits and lower bits, respectively, and an ideal symbol point arrangement and a hard decision area corresponding to the upper bit sequence are set. Then, an ideal symbol point arrangement corresponding to the series of lower bits is set, and the ideal symbol points adjacent to the series of upper bits through the boundary of the hard-decision determination area (in other words, linked Invert the sign of the in-phase component or quadrature component (specifically, the coordinate value) of the symbol point corresponding to the lower bit so that the value of the lower bit does not change (in other words, the value of the lower bit becomes the same) Since it can be implemented by controlling the operation, it is applicable if the number of bits of the information bit sequence is 4 bits or more.

Further, in the above embodiment, the ideal symbol point arrangement for the upper bits shown in FIG. 5 and the ideal symbol point arrangement for the lower bits shown in FIG. 6 are used, and the mapping of the entire bit series shown in FIG. 2 is used. However, the ideal symbol point arrangement that can be used in the present invention is not limited to the examples shown in FIGS. 5 and 6, and the mapping of the entire bit sequence is not limited to the example shown in FIG.

Further, in the above embodiment, the upper bit sequence is mapped by the quadrature amplitude modulation method and the lower bit sequence is mapped by the quadrature phase shift keying method. For example, when the upper bit sequence is 2 bits, mapping may be performed on the upper bit sequence by the quadrature phase shift keying method, and when the lower bit sequence is 3 bits or more may be mapped to the sequence of lower bits by the quadrature amplitude modulation method.

1 Modulating Device 11 Sequence Separating Section 12 Upper Bit Modulating Section 13 LDPC Encoding Section 14 Lower Bit Modulating Section 15 Level Adjusting Section 16 Transmission Code Control Section 17 Addition Section 2 Demodulator 21 Higher Bit Decision Section 22 Subtraction Section 23 Receiving Code Control Section 24 Level adjustment unit 25 Logarithmic likelihood ratio calculation unit 26 LDPC decoding unit 27 Sequence synthesis unit

Claims (10)

an upper bit modulation unit that performs mapping according to an ideal symbol point arrangement of the upper bits for a series of upper bits in a series of a predetermined number of bits, and outputs symbol points corresponding to the upper bits;
a low-order bit modulation unit that performs mapping according to an ideal symbol point arrangement of low-order bits to a sequence of low-order bits in the sequence of the predetermined number of bits, and outputs symbol points corresponding to the low-order bits;
a transmission code control unit for controlling a sign inversion operation of the coordinate values of the symbol points corresponding to the low-order bits based on the sequence of the high-order bits;
The transmission code control unit corresponds to the ideal symbol points adjacent to each other across the boundary of the hard-decision region in a state where each of the hard-decision decision regions corresponding to the ideal symbol point arrangement of the high-order bits is assigned. controlling a sign inversion operation of the coordinate values of the symbol points corresponding to the low-order bits based on the series of the high-order bits so that the values of the low-order bits are the same;
A modulation device characterized by: A level adjustment unit that adjusts the gain of the coordinate values of the symbol points corresponding to the lower bits so that the interval between the ideal symbol points of the lower bits matches the interval between the ideal symbol points in the modulation system of the sequence of the predetermined number of bits. has a
2. The modulation device according to claim 1, wherein: An LDPC coding unit that performs low-density parity check coding processing on a sequence of lower bits of the sequence of the predetermined number of bits,
3. The modulation device according to claim 1, wherein: The series of the predetermined number of bits is a 6-bit series,
The upper bit is a 4-bit series and the lower bit is a 2-bit series,
4. The modulation device according to any one of claims 1 to 3, characterized in that: an upper bit determination unit that performs a hard decision on a received signal according to an ideal symbol point arrangement of upper bits and outputs a sequence of upper bits among a sequence of a predetermined number of bits and an ideal symbol point corresponding to the upper bits;
a subtraction unit that subtracts the ideal symbol point corresponding to the high-order bit from the received signal and outputs a received signal after subtraction of the high-order bit;
a reception code control unit that controls a sign inversion operation of the coordinate value of the received signal after the subtraction of the high-order bits based on the sequence of the high-order bits;
The reception code control unit corresponds to the ideal symbol points adjacent via the boundary of the hard-decision region in a state of being assigned to each of the hard-decision decision regions corresponding to the ideal symbol point arrangement of the upper bits. In order to restore the sign of the coordinate value of the symbol point corresponding to the lower bit, which has been inverted on the transmitting side so that the values of the lower bits to be the same are the same, the upper bit is restored based on the series of the upper bits controlling the operation of reversing the sign of the coordinate value of the received signal after subtraction;
A demodulator characterized by: Having a level adjustment unit that adjusts the gain of the coordinate value of the received signal after the high-order bit subtraction,
6. The demodulator according to claim 5, wherein: a log-likelihood ratio for calculating a log-likelihood ratio of each bit constituting a lower-order bit sequence in the sequence of the predetermined number of bits based on the coordinate values after the sign inversion operation and the gain adjustment of the coordinate values; Having a degree ratio calculation unit,
7. The demodulator according to claim 6, wherein: An LDPC decoding unit that performs error correction based on the logarithmic likelihood ratio and outputs the sequence of the lower bits,
8. The demodulator according to claim 7, characterized by: The series of the predetermined number of bits is a 6-bit series,
The upper bit is a 4-bit series and the lower bit is a 2-bit series,
9. The demodulator according to any one of claims 5 to 8, characterized in that: at least one of the modulation device according to any one of claims 1 to 4 and the demodulation device according to any one of claims 5 to 9,
A communication device characterized by:

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