JP2022109079A - Wiring board and manufacturing method thereof - Google Patents

Abstract

To provide a wiring board and a manufacturing method of the wiring board with high connection reliability of a wiring portion against warping of the board during heating and stress inside a rewiring layer in a method of forming a fine rewiring layer on a support board and mounting a semiconductor element.SOLUTION: In a wiring board that includes a semiconductor element, and a second wiring board on which a wiring pattern thicker than the semiconductor element, which is bonded to the semiconductor element is formed, and in which a first wiring board is bonded to the surface opposite to the mounting surface of the semiconductor element of the second wiring board, a dummy pattern consisting of a plurality of islands 3A made of photosensitive resin is arranged at intervals of 1.5 mm or less in a large area pattern portion of 1.5 mm or more on a side of a wiring portion made of a conductive material on the second wiring board, and a flat rewiring layer is formed by suppressing surface waviness due to polishing of each rewiring layer composed of the wiring portion and a photosensitive resin layer.SELECTED DRAWING: Figure 7

Description

The present invention relates to a wiring board and its manufacturing method.

In recent years, as semiconductor devices have become faster and more highly integrated, the wiring substrate for FC-BGA (Flip Chip Bal-l Grid Array) has been required to have narrower pitches of connection terminals with semiconductor elements and miniaturization of substrate wiring. It has been demanded. On the other hand, connection between the FC-BGA wiring board and the mother board is required to be made using connection terminals with substantially the same pitch as in the past.

In order to narrow the pitch of the connection terminals with the semiconductor element in this wiring board for FC-BGA and to miniaturize the board wiring, wiring is formed on the silicon substrate and used as a substrate (silicon interposer) for connecting the semiconductor element. - A method of connecting to a BGA board is known. In addition, the surface of the wiring board for FC-BGA is subjected to CMP (Chemical Mechanical
Japanese Patent Application Laid-Open No. 2002-300000 discloses a method of forming fine wiring after planarization by polishing (chemical-mechanical polishing) or the like. Further, Patent Document 2 discloses a method of forming a fine wiring layer on a supporting substrate, mounting it on an FC-BGA wiring substrate, and then peeling off the supporting substrate to form a narrow-pitch wiring substrate. .

JP 2014-225671 A WO2018/047861 Japanese Patent No. 6247032

A silicon interposer is manufactured using a silicon wafer using facilities for semiconductor front-end processes. Silicon wafers are limited in shape and size. Therefore, the number of interposers that can be manufactured from one wafer is small, and the equipment cost is high, so the interposers are also expensive.
Moreover, since the silicon wafer is a semiconductor, there is a problem that the transmission characteristics are also degraded.
In addition, in the method of flattening the wiring board for FC-BGA and forming fine wiring on it, the deterioration of transmission characteristics seen in silicon interposers is small, but the manufacturing defects and difficulty of the wiring board for FC-BGA Combined with defects during the formation of fine wiring with a high density, there is a problem that the yield within the same substrate plane is reduced, and a problem in mounting semiconductor elements due to warpage and distortion of the FC-BGA wiring substrate.

On the other hand, when fine wiring is formed on a supporting substrate and a semiconductor element is mounted thereon, the supporting substrate is peeled off and the semiconductor element is mounted on the FC-BGA wiring board via the fine wiring. , had the following problem:
For example, a fine wiring pattern is formed by a semi-additive method, the fine wiring is covered with a photosensitive insulating resin layer, and a via part that becomes a connection part with the wiring pattern to be laminated is opened to form a necessary layer. There are several methods of stacking.

In this case, the height of the insulating resin layer at the portion without the wiring pattern is lowered depending on the presence or absence of the wiring pattern and the sparseness of the wiring pattern. As a result, there have been problems such as variations in the dimensions of the wiring patterns to be formed in layers, and problems such as causing electrical connection failures due to variations in height between connection terminals when mounting a semiconductor element. .
This problem is the same in the process of forming fine wiring on a support substrate, mounting it on a wiring substrate for FC-BGA, and mounting it on a semiconductor element.

Further, a fine wiring pattern may be produced by a damascene method using CMP by forming a trench pattern in a photosensitive insulating resin layer and filling it with a conductive material. In this case, the wiring part consisting of the wiring pattern, connection via part, land part, etc., the ground pattern part, the dummy pattern part, and the accessory pattern part consisting of the alignment marks and auxiliary patterns used to fabricate the wiring board, When formed by CMP, a large area pattern portion made of a single material made of a conductive material or a photosensitive resin with a narrowest width of 1.5 mm or more may be excessively polished, resulting in a recessed cross-sectional shape. The depth of the concave shape tends to be deeper as the linear dimension of the wiring portion is longer, and depending on the linear dimension of the wiring portion, the depth of the concave shape varies from several tenths μm to several μm. .

For this reason, the surface of the substrate on which the wiring portion is formed by using CMP has undulations that are recessed by several μm to several μm with respect to the surface of the photosensitive insulating resin layer. ), the photosensitive insulating resin layer is coated along the undulations of the lower layer, and undulations also occur in the trench pattern.
The trench pattern laminated on the top is covered with a conductor layer, and the covered conductor layer is polished by CMP to form the wiring part and the accessory pattern part. However, there is a problem that the pattern cannot be formed because the surface of the trench pattern is not polished.
In addition, the height of the connection terminals formed on the undulations of each layer also varies, which may cause an electrical connection failure due to the height variation between the connection terminals when the semiconductor element is mounted. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wiring board with high connection reliability of wiring portions and a manufacturing method thereof.

As a means for solving the above-mentioned problems, the invention according to claim 1 of the present invention provides a second wiring board bonded to a semiconductor element, and a mounting surface of the second wiring board opposite to the mounting surface of the semiconductor element. Width of wiring constituting each of the first wiring board, the second wiring board, and the semiconductor element is the thinnest in the wiring board provided with the first wiring board mounted on the opposite surface of the side, and the width of the wiring constituting each of the first wiring board, the second wiring board, and the semiconductor element is narrowed in that order. The second wiring board has two or more rewiring layers laminated to form a multilayer wiring, and each wiring layer includes a photosensitive resin layer made of a photosensitive resin, and an opening is provided in the photosensitive resin layer. a wiring pattern portion in which the formed opening forms a resin trench portion and is filled with a conductive material as a part of the resin trench portion; and a photosensitive resin solid pattern portion arranged to surround the wiring pattern; Further, a ground pattern consisting of a large-area pattern having a narrowest width of 1.5 mm or more is provided so as to surround the photosensitive resin solid pattern portion, and a seed adhesion layer is provided on the bottom surface of the resin trench portion. A seed layer and a seed layer are formed in this order, and a wiring portion made of a conductor layer formed by filling the inside of the resin trench portion with a conductive material is formed, and two or more layers of conductor layers to be the wiring portion are laminated. In each rewiring layer composed of the wiring part and the photosensitive resin layer, a plurality of island-shaped photosensitive islands made of photosensitive resin are arranged at intervals of 1.5 mm or less in the ground pattern. It has a dummy pattern in which a flexible resin pattern is arranged.

When the photosensitive resin solid pattern portion is composed of a large-area pattern having a width of 1.5 mm or more at the narrowest portion, a plurality of conductive islands made of a conductive material are formed in the resin solid pattern portion at intervals of 1.5 mm or less. It has dummy patterns in which physical patterns are arranged.

Further, according to an aspect of the present invention, there is provided a wiring board including a second wiring board bonded to a semiconductor element, wherein the second wiring board comprises multilayer wiring by laminating two or more rewiring layers, and Each wiring layer includes a photosensitive resin layer made of a photosensitive resin, and an opening formed in the photosensitive resin layer forms a resin trench portion, and a part of the resin trench portion is filled with a conductive material. A wiring pattern portion is formed, and a seed adhesion layer and a seed layer are formed in this order on the bottom surface of the resin trench portion. A method for manufacturing a wiring board in which a portion is formed, wherein the method for forming the rewiring layer includes the steps of: forming a resin trench portion in the photosensitive resin layer; A step of providing a seed adhesion layer and a seed layer, a step of laminating a conductive material with a solid film on the seed layer, and polishing the conductive material formed with the solid film from the laminated surface of the substrate. A step of polishing and removing the unnecessary conductive material laminated on the surface of the photosensitive resin layer while leaving the conductive material in the resin trench portion by polishing; a step of removing the surfaces of the layer, the seed layer, the conductor layer and the photosensitive resin layer composed of a conductive material by a second polishing, and forming a rewiring layer having a structure in which the resin trench portion is filled with the conductive material; , and the step of forming the rewiring layers is repeated by the required number of layers to form two layers of rewiring layers.

According to the aspect of the present invention, in the second wiring board on which a fine wiring layer is formed and a semiconductor element is mounted, it is possible to improve the electrical connection reliability of the via connection portion between the wiring layers and the insulation reliability between the wirings. Therefore, according to the aspect of the present invention, it is possible to improve the reliability of the wiring board without disconnection or short circuit.

FIG. 4 is a cross-sectional view showing a state in which a release layer is formed on a support substrate; It is sectional drawing which shows the state which formed the photosensitive resin layer. FIG. 4 is a cross-sectional view showing a state in which a seed adhesion layer is formed; FIG. 4 is a cross-sectional view showing a state in which a seed layer is formed; FIG. 4 is a cross-sectional view showing a state in which a conductor layer is formed; FIG. 4 is a cross-sectional view showing a state in which a conductor layer and a seed layer are polished by surface polishing; FIG. 4 is a cross-sectional view showing a state in which the conductor layer, the seed adhesion layer, and the photosensitive resin layer are polished by surface polishing to form connection terminals for bonding to the first wiring board; FIG. 4 is a cross-sectional view showing a state in which a photosensitive resin layer is formed in a connection via portion; FIG. 4 is a cross-sectional view showing a state in which a photosensitive resin layer is formed on a connection via portion and a wiring portion; FIG. 4 is a cross-sectional view showing a state in which a seed adhesion layer is formed; FIG. 4 is a cross-sectional view showing a state in which a seed layer is formed; FIG. 4 is a cross-sectional view showing a state in which a conductor layer is formed; FIG. 4 is a cross-sectional view showing a state in which connection via portions and wiring portions are formed by surface polishing; 3F is a cross-sectional view showing a state in which multilayer wiring is formed by repeating FIGS. 3A to 3F; FIG. It is sectional drawing which shows the state which formed the photosensitive resin layer. FIG. 4 is a cross-sectional view showing a state in which a seed adhesion layer is formed; FIG. 4 is a cross-sectional view showing a state in which a seed layer is formed; FIG. 4 is a cross-sectional view showing a state in which a resist pattern is formed; FIG. 4 is a cross-sectional view showing a state in which a conductor layer is formed; FIG. 4 is a cross-sectional view showing a state in which a resist pattern is removed; FIG. 4 is a cross-sectional view showing a state in which unnecessary seed adhesion layers and seed layers are removed by etching; FIG. 4 is a diagram showing an island-like dummy pattern arranged in a large-area pattern portion composed of a conductive material pattern or a photosensitive insulating resin pattern; FIG. 4 is a cross-sectional view showing a state in which a wiring substrate on a supporting substrate is completed after surface treatment and solder joint formation; FIG. 4 is a cross-sectional view showing a state in which a semiconductor element is bonded to a second wiring board; FIG. 4 is a cross-sectional view showing a state in which a space between the second wiring board and the semiconductor element is filled with underfill; FIG. 4 is a cross-sectional view showing a state in which the semiconductor element on the second wiring board is molded with a sealing resin; FIG. 4 is a cross-sectional view showing a state in which a peeling layer is irradiated with laser light; It is sectional drawing which shows the state which removed the support substrate. FIG. 4 is a cross-sectional view showing a state in which a semiconductor element is mounted; It is sectional drawing which shows the state which joined the semiconductor element, the 2nd wiring board, and the 1st wiring board. An image diagram of one piece and an enlarged view of the part ab in the image diagram are shown in the lower part. The wiring part is an aggregate of patterns of several μm, and is indicated by filling in the one-piece drawing.

An embodiment of the present invention will be described below with reference to the drawings.
In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and that the relationship between thickness and planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it is a matter of course that there are portions with different dimensional relationships and ratios between the drawings.
Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not limited to the following. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

An example of a manufacturing process of a wiring board using a support substrate according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 8. FIG.
First, as shown in FIG. 1, a peeling layer 2 is formed on one surface of a support substrate 1 . The release layer 2 is formed to release the support substrate 1 in a later step.
The peeling layer 2 may be, for example, a resin that can be peeled off by absorbing light such as UV light to generate heat or change properties, or a resin that can be peeled off by foaming with heat. When a resin that can be peeled off by light such as UV light, for example, laser light, is used as the peeling layer 2, the support substrate 1 is irradiated with light from the side opposite to the side on which the peeling layer 2 is provided. The support substrate 1 can be removed from the assembly of the upper wiring substrate 11 and the semiconductor element 15 .

Examples of materials for the release layer 2 include organic resins such as epoxy resins, polyimide resins, polyurethane resins, silicone resins, polyester resins, oxetane resins, maleimide resins, and acrylic resins, amorphous silicon, gallium nitride, and metal oxide films. It can be selected from inorganic layers such as Further, the release layer 2 may contain additives such as photodegradation accelerators, light absorbers, sensitizers, fillers, and the like. Furthermore, the release layer 2 may be composed of a plurality of layers. For example, for the purpose of protecting the multilayer rewiring layer (second wiring board) formed on the support substrate 1, a protective layer is further formed on the release layer 2. Alternatively, a layer for improving adhesion to the support substrate 1 may be provided under the release layer 2 .
Furthermore, a laser reflection layer or a metal layer may be provided between the release layer 2 and the multilayer rewiring layer, and the configuration thereof is not limited by this embodiment.

Since the support substrate 1 may irradiate the peeling layer 2 with light through the support substrate 1, it is preferable that the support substrate 1 has transparency. For example, glass can be used as the support substrate 1. FIG. Since the glass substrate has excellent flatness and high rigidity, it is suitable for fine pattern formation of the wiring substrate 11 on the support substrate 1 . In addition, since glass has a small CTE (coefficient of thermal expansion) and is resistant to distortion, it excels in ensuring pattern arrangement accuracy and flatness. When glass is used as the support substrate 1, the thickness of the glass is desirably thick from the viewpoint of suppressing the occurrence of warpage in the manufacturing process. be. The CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and from the viewpoint of the CTE of the semiconductor element 15 and FC-GBA wiring board 12, the CTE of the glass is more preferably about 9 ppm.

Examples of glass include quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, and the like. On the other hand, if the support substrate 1 does not need to have light transmittance when the support substrate 1 is peeled off, such as by using a resin that foams with heat for the release layer 2, the support substrate 1 may be made of a material with little distortion, such as metal. A substrate made of ceramics or the like can be used.
In one embodiment of the present invention, a resin that can be peeled off by absorbing UV light is used as the peeling layer 2 , and glass is used as the support substrate 1 .

Next, as shown in FIG. 2A, a photosensitive resin layer 3 is formed on the release layer 2 .
In this embodiment, the photosensitive resin layer 3 is formed by spin coating a photosensitive epoxy resin, for example. A photosensitive epoxy resin can be cured at a relatively low temperature, and shrinkage due to curing after formation is small, so that it is excellent for subsequent fine pattern formation. The method for forming the photosensitive resin layer 3 is slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, or gravure offset printing when a liquid photosensitive resin is used for its formation. , spin coating, and doctor coating. The method of forming the photosensitive resin layer 3 can be lamination, vacuum lamination, vacuum pressing, or the like when a film-like photosensitive resin is used.
For the photosensitive resin layer 3, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, and modified products thereof can be used as an insulating resin.

Next, by photolithography, the photosensitive resin layer 3 is provided with a resin trench portion 21 consisting of an opening (see FIG. 2A). The opening forming the resin trench portion 21 is filled with a conductive material, and is used to form a wiring portion including wiring patterns, lands, and connection vias, a ground pattern portion, a dummy pattern portion, and an alignment portion used for manufacturing a wiring board. This is the portion that will be the accessory pattern portion consisting of marks and auxiliary patterns.
The land portion is formed in an opening with a diameter of 100 μm or less. Alignment marks are formed as a cross having a linear dimension of about several hundred micrometers to 2 mm, a circular pattern, or an opening of an assembly thereof.

The minimum line width of the wiring pattern may be selected according to the form of the product. As an example, a semiconductor element having a wiring width of 14 nm is electrically connected to a second wiring substrate having a wiring width of 2 μm and a bump pitch of 50 μm. By electrically connecting to the first wiring board having a wiring width of 10 μm and a bump pitch of 160 μm, it becomes easy to use as a semiconductor device.
In the second wiring substrate, when the wiring width is 3 μm or less, the semi-additive method that has been used for wiring formation becomes difficult, and the damascene method using CMP is effective.
The ground pattern is composed of a large-area opening having an irregular shape and a width of 1.5 mm or more at the narrowest part so as to surround the wiring pattern through the photosensitive resin solid pattern.

In one embodiment of the present invention, as shown in FIG. 8, a wiring board is formed on which a wiring portion, an accessory pattern 27, a ground pattern 30A, a photosensitive resin solid pattern 30B, and a dummy pattern 28 are arranged.
As shown in FIG. 5H, a ground pattern 30A made of a conductive material is formed in a large-area opening surrounded by the photosensitive resin layer 3. As shown in FIG. A dummy pattern 28 composed of a plurality of photosensitive resin layers 3 is arranged in the opening of the ground pattern 30A. The opening of the ground pattern is filled with a conductive material. Also, the wiring pattern is omitted in FIG. 5H. The outline of the ground pattern 21A is arranged to surround the wiring pattern portion as shown in FIG. 5H and has an irregular shape.
Further, it is also possible to reverse the positional relationship between the conductive material portion and the photosensitive resin portion and arrange the dummy pattern 28 made of the conductive material on the photosensitive resin solid pattern 30B surrounded by the conductive material.

The dummy patterns 21 shown in FIG. 5H are arranged in a predetermined arrangement pattern. The interval between the adjacent dummy pattern 28 and ground pattern 30A to the outer periphery is set to 1.5 mm or less. Since one or more dummy patterns 28 are arranged in a square of 3 mm on a side, the number of dummy patterns 28 to be arranged per unit area should be 0.11 (=1/9)/mm 2 square or more.
Although the size and shape of the dummy pattern 28 are not particularly specified, the size of the dummy pattern 28 may be 50 μm or more and 500 μm or less, and the pattern shape may be a circle, an octagon, an ellipse, a square, or the like. The arrangement interval of the dummy patterns 28 is 1.5 mm or less, preferably 1 mm or less, and the lower limit is 500 μm or more.

If the arrangement interval of the islands 3A constituting the dummy patterns is wider than 1.5 mm, when the conductor layer 6 deposited on the photosensitive resin layer 3 is polished and removed by polishing, the conductive material between the arranged dummy patterns will be dislodged. Since the amount of depression is larger than 0.1 μm, the rewiring layer swells more than −0.1 μm, which hinders lamination of the next rewiring layer.
The upper end surface of the dummy pattern 28 thus formed is level with the other photosensitive resin layer 3 .
A plasma treatment may be performed on the resin trench portion 21 for the purpose of removing resin residue during development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer formed in the opening, and is formed to a thickness of 8 μm, for example, in one embodiment of the present invention.

In one embodiment of the invention, the rewiring layer formed on the peeling layer 2 serves as the mounting surface of the semiconductor element 15, and the surface facing the laminated peeling layer 2 is the mounting surface of the first wiring board 12. In the planar structure, dummy patterns 28 of φ200 μm are arranged at intervals of 1 mm for accessory patterns 27 such as alignment marks, ground patterns 30A, and photosensitive resin solid patterns 30B.
A structure in which the rewiring layer formed on the peeling layer 2 becomes the mounting surface of the first wiring board 12 and the surface facing the peeling layer 2 formed by stacking becomes the mounting surface of the semiconductor element 15 is also the present invention. The structure of the wiring substrate 11 on the support substrate 1 obtained in 1 is the same, and is included in the scope of the present claims.

Next, as shown in FIGS. 2B and 2C, a seed adhesion layer 4 and a seed layer 5 are formed in this order in a vacuum.
The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents the seed layer 5 from peeling off. The seed layer 5 acts as a power supply layer for electroplating in the shape of the wiring portion.
The seed adhesion layer 4 and the seed layer 5 are formed by, for example, a sputtering method or a vapor deposition method. Ru, Pd, Pt, AlSi, AlSiCu, AiCu, NIFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu ₃ N ₄ , Cu alloys, and combinations of these can be used. In this embodiment, a titanium layer as the seed adhesion layer 4 and a copper layer as the seed layer 5 are successively formed by sputtering in consideration of electrical properties, ease of manufacture, and cost. The total thickness of the titanium layer and the copper layer is preferably 1 μm or less as a power supply layer for electroplating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

Next, as shown in FIG. 2D, a conductor layer 6 is formed by electrolytic plating.
The conductor layer 6 serves as an electrode for bonding with the FC-BGA substrate 12 . Electrolytic plating includes electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic iridium plating, and the like. Electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity.
The thickness of the electrolytic copper plating is desirably 1 μm or more from the viewpoint of soldering, and 30 μm or less from the viewpoint of productivity.
In one embodiment of the present invention, Cu: 9 μm is formed to fill the trench portion 21 of the photosensitive resin layer 3 , and the upper portion of the photosensitive resin layer 3 is also formed with Cu: 9 μm.

Next, as shown in FIG. 2E, the copper layer on the surface of the photosensitive resin layer is polished and removed by CMP (Chemical Mechanical Polishing) having chemical polishing properties for the conductive material of the conductor layer 6 . That is, the first polishing is performed so that the seed adhesion layer 4 covering the top portion of the resin trench portion 21 and the conductor layer 6 filling the opening portion of the resin trench portion 21 are on the surface. Abrasives used in chemical mechanical polishing contain a chemical polishing component and a physical polishing component, and a formulation dominated by the chemical polishing component is desirable. It is also possible to use a prescription in which the effect of the physical polishing component is highly adjusted. , it becomes difficult to control the height of the wiring and the unevenness of the surface.
In one embodiment of the present invention, the Cu of the upper conductor layer 6 of the photosensitive resin layer 3: 9 μm and the Cu of the seed layer 5: 300 nm are first polished using an abrasive predominantly having a chemical abrasive component. 1 is removed by polishing.

Next, as shown in FIG. 2F, the second polishing for physically polishing and removing the photosensitive resin layer 3, the conductor layer 6, and the seed layer 5 removes the seed adhesion layer 4 and the photosensitive resin layer 3. Remove the superficial layer. The second polishing is polishing different materials of the seed adhesion layer 4 and the photosensitive resin layer 3 . Since the photosensitive resin layer 3 cannot be polished by chemical polishing, physical polishing using an abrasive such as filler is effective. The second polishing is effective in reducing the surface unevenness caused by the first polishing, because the portion with high surface unevenness is polished first in the physical polishing.
As for the abrasive, it is desirable to use an abrasive that is predominantly used for physical polishing and to which a small amount of a chemical abrasive component for the conductive material is added to give the surface of the conductor layer 6 a smooth surface.
By adjusting the polishing speed of the conductor layer 6 and the photosensitive resin layer 3 and increasing the polishing speed of the photosensitive resin layer 3, a shape in which the wiring part is higher than the photosensitive resin layer 3 is realized.

Moreover, in the portion where the opening width of the resin trench portion 21 is wide and the conductor layer 6 is processed into a concave shape by the first polishing, the photosensitive resin layer 3 and the seed adhesion layer 4 located at the end of the concave shape have priority. It is possible to reduce the depth of the concave shape by polishing the surface.
In this manner, the first polishing reduces the depth of the concave shape from a few tenths of a micrometer to a little less than 1 micrometer for the resin trench section 21 having patterns having various opening widths such as the bump section 17, the land section 27, and the accessory pattern 27. By polishing the surface layer of the rewiring layer by a few tenths of a μm by the second polishing, the variation in the height of the wiring portion, the ground pattern portion, and the photosensitive resin solid pattern portion from the virtual plane is reduced from −0.1 to +0. It can be controlled in the range of 0.1 μm.

Here, the film thickness was measured using a stylus-type film thickness meter, a laser microscope, or the like, and the height variation at each measurement point was calculated based on the height of the photosensitive resin layer 3 .
The formula of the virtual plane is shown in 1 below. The unit of measurement in which the three-dimensional measurement value in the entire area is (x _i , y _{i ,} z _i ) is expressed in μm.

The constants (a, b, c) should be determined so that the distance between each measurement point (x _i , y _i, z _i ) and the least-squares plane is minimized. Assuming that the height between each measurement point (x _i , y _{i ,} z _i ) and the least squares plane is E _i and the sum of squares of all points is F, F is expressed by the following formula.

Then, the constants (a, b, c) are determined so as to minimize the F value. In other words, a ternary simultaneous equation (see the following equations) in which the value obtained by partially differentiating the above equation with respect to the constants (a, b, c) becomes =0 is solved.

In practice, the constants (a, b, c) can be obtained by matrix calculation using a computer. Furthermore, the triple value of the mean square distance from the virtual plane can be obtained from the following equation. The following formula indicates that the following value indicating the flatness of the rewiring layer is ±0.1*3 μm or less.

This formula indicates that the value of three times the standard deviation of the distance between the plane obtained from each measurement point and each measurement point is 0.3 μm or less. n is the number of measurement points on the first main surface, and n is desirably at least 5×5=25 or more grid points. More preferably, n is 10×10=100 or more. If the number of measurement points n is less than 25, the number of samples is small and it is difficult to measure the true value.
In this way, the bumps obtained by polishing become connection terminals for the FC-BGA substrate 12 and the semiconductor element 15 .

Next, as shown in FIG. 3A, similarly to FIG. 2A, a photosensitive resin layer 3 is formed on the upper surface.
The thickness of the photosensitive resin layer 3 to be formed is set according to the thickness of the conductor layer to be formed in the opening. In one embodiment of the present invention, the photosensitive resin layer 3 is formed with a thickness of 2 μm, for example. The opening shape of the via portion in plan view is set from the viewpoint of connection with the conductor layer 6, and in one embodiment of the present invention, for example, an opening shape of φ10 μm is formed. This opening has the shape of the connection via portion 19 that connects the upper and lower rewiring layers of the multi-layer rewiring layer.

Further, as shown in FIG. 3B, a photosensitive resin layer 3 is formed on the upper surface in the same manner as in FIG. 2A.
The thickness of the photosensitive resin layer 3 to be formed is set according to the thickness of the conductor layer to be formed in the opening. In one embodiment of the present invention, the photosensitive resin layer 3 is formed with a thickness of 2.5 μm, for example. The resin trench portion 21 includes a wiring portion including a land portion 26 and a wiring pattern portion 25, an accessory pattern portion 27 including alignment marks and the like, and a ground pattern 30A.

The opening shape of the land portion 26 in a plan view is set from the viewpoint of the connectivity of the laminate, and is formed so as to surround the outer side of the opening shape of the lower connection via portion 31 . In one embodiment of the present invention, for example, an aperture shape of φ25 μm is formed. The wiring pattern portion is formed with an opening shape of L/S=2/2 μm, for example.
Alignment marks are composed of cross-shaped or circular patterns of several hundred μm to 2 mm, and openings of aggregates thereof. The width of the narrowest portion surrounding the solid resin pattern portion 30B is 1 mm or more, and is a large-area recessed pattern.

In one embodiment of the present invention, dummy patterns 28 with a diameter of 200 μm are formed at intervals of 1 mm in the openings of a large-area ground pattern.
In one embodiment of the present invention, the photosensitive resin layer 3 was coated in two layers, and each layer, the connection via portion 31, the land portion 27 and the wiring pattern portion 25, was formed separately. It is also possible to form by one photolithography process.

Next, as shown in FIGS. 3C and 3D, a seed adhesion layer 4 and a seed layer 5 are formed in vacuum in the same manner as in FIGS. 2B and 2C. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.
Next, as shown in FIG. 3E, a conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes a wiring portion and an accessory pattern portion. Examples of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. Electrolytic copper plating is simple, inexpensive, and It is desirable because of its good electrical conductivity.
The thickness of the electrolytic copper plating is desirably 0.5 μm or more from the viewpoint of the electrical resistance of the wiring portion, and 10 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 5 μm is formed in the double opening of the photosensitive resin layer 3 , and Cu is also formed in the single opening of the photosensitive resin layer 3 and the upper portion of the photosensitive resin layer 3 . : forming 5 μm.

Next, as shown in FIG. 3F, similarly to FIGS. 2E and 2F, the copper layer on the surface of the photosensitive resin layer is polished and removed by CMP (Chemical Mechanical Polishing) having chemical polishing properties for the conductive material of the conductor layer. do. That is, the first polishing is performed so that the seed adhesion layer 4 covering the top portion of the resin trench portion 21 and the conductor layer 6 filling the opening portion of the resin trench portion 21 are on the surface.
Further, the seed adhesion layer 4 and the surface layer of the photosensitive resin layer 3 are removed by the second polishing for physically polishing and removing the photosensitive resin layer 3 , the conductor layer 6 and the seed layer 5 .
The conductor layer 6 remaining after polishing is the connection via portion 31, the land portion 26, the conductor portion of the wiring pattern portion 25 (wiring portion), the accessory pattern portion 27, and the ground pattern 30A or the photosensitive resin solid pattern 30B. dummy pattern 28.

In one embodiment of the present invention, the resin trench portion 21 formed of patterns having various opening widths such as the wiring portion, the ground pattern 30A, and the accessory pattern portion 27 is subjected to the first polishing so that the depth of the concave shape is reduced by a few tenths. A rewiring layer having a thickness of .mu.m to less than 1 .mu.m is formed. Further, by the second polishing, the variation in height from the imaginary plane of the wiring part, the accessory pattern part and the photosensitive resin layer can be controlled within the range of -0.1 to +0.1 μm.
Then, as shown in FIG. 4, by repeating the steps of FIGS. 3A to 3F, rewiring layers are successively stacked to form multi-layer wiring.
In one embodiment of the present invention, two layers of rewiring layers having fine wiring portions of L/S=2/2 μm are formed.

Next, the process of forming a junction electrode with the semiconductor element 15 will be described.
As shown in FIG. 5A, similarly to FIG. 2A, a photosensitive resin layer 3 is formed on the upper surface of the multilayer wiring. The thickness of the photosensitive resin layer 3 to be formed is set according to the thickness with which the upper and lower layers can be electrically insulated by covering the thickness of the lower conductor layer. In one embodiment of the present invention, for example, a photosensitive resin layer 3 having a thickness of 4 μm is formed.
Next, as shown in FIGS. 5B and 5C, the seed adhesion layer 4 and the seed layer 5 are sequentially formed in vacuum in the same manner as in FIGS. 2B and 2C.

Next, as shown in FIG. 5D, a resist pattern 7 is formed. After that, a conductor layer 6 is formed by electroplating as shown in FIG. 5E. The formed conductor layer 6 becomes an electrode for bonding with the semiconductor element 15 . The thickness of the electrolytic plating is desirably 1 μm or more from the viewpoint of solder joint and 30 μm or less from the viewpoint of productivity.
In one embodiment of the present invention, for example, the resist pattern 7 has an opening shape of φ25 μm, and the interval is 55 μm. Cu: 7 μm is formed on the upper surface of the resin layer 3 .

After that, the resist pattern is removed as shown in FIG. 5F. Thereafter, the unnecessary seed adhesion layer 4 and seed layer 5 are removed by etching as shown in FIG. 5G. The conductor layer 6 consisting of the bump portions 17 remaining on the surface in this state becomes an electrode for bonding with the semiconductor element 15 .
The conductor layer 6 composed of the bumps 17 may be used as it is in a convex shape, or may be covered with a photosensitive resin containing a filler.
Alternatively, after FIG. 5C, a conductor layer is formed as a solid film, and a shape in which the resin trench is filled with the conductor layer by polishing as shown in FIG. 5F may be selected.
The shape of the bump portion 17 may be selected according to the bonding method with the semiconductor element 15 .
Then, in order to prevent oxidation of the surface of the conductor layer 6 consisting of the bumps 17 and improve the wettability of the solder bumps 10, a surface treatment layer 9 is provided on the surface of the conductor layer 6 consisting of the bumps 17 (see FIG. 5I). .

In one embodiment of the present invention, electroless Ni/Pd/Au plating is formed as surface treatment layer 9 . The surface treatment layer 9 may be formed with an OSP (Organic Soiderability Preservative: surface treatment with water-soluble flux) film.
Next, after mounting a solder material on the surface treatment layer 9, the solder material is once melted and cooled to be fixed, thereby obtaining a joint portion of the solder bump 10 (see FIG. 5I). Thus, the wiring substrate 11 formed on the support substrate 1 is completed.

Next, as shown in FIG. 6A, the wiring substrate 11 on the support substrate 1 and the semiconductor element 15 are bonded by the bonding portions of the solder bumps 10 .
The joint is then sealed with an underfill 22, as shown in FIG. 6B.
As the resin material constituting the underfill, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or two of these resins. A material in which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler to a resin in which more than one species is mixed is used. The underfill 22 is formed by filling liquid resin.

Next, as shown in FIG. 6C, a sealing resin 23 for sealing the semiconductor element 15 is formed.
The sealing resin 23 is a material different from that of the underfill 22, and may be one of epoxy resin, silicone resin, acrylic resin, urethane resin, polyester resin, and oxetane resin, or a mixture of two or more of these resins. In addition, a material to which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler is used, and is formed by compression molding, transfer molding, or the like.

Next, as shown in FIG. 6E, the support substrate 1 is peeled off. For example, as shown in FIG. 6D, the peeling is performed by irradiating the peeling layer 2 with a UV laser beam 13 . The release layer 2 formed at the interface with the support substrate 1 is irradiated with a laser beam 13 from the back surface of the support substrate 1, that is, from the surface of the support substrate 1 opposite to the semiconductor element 15, so that the release layer 2 can be peeled off. Then, the support substrate 1 can be removed as shown in FIG. 6E.
Next, the seed adhesion layer 4 and the seed layer 5 formed on the surface of the surface conductor layer 6 are removed to obtain a substrate as shown in FIG. 6F. In the embodiment of the present invention, titanium is used for the seed adhesion layer 4 and copper is used for the seed layer 5, which can be dissolved and removed with an alkaline etchant and an acid etchant, respectively.

In this manner, a semiconductor device as shown in FIG. 6F is obtained in which the second wiring board 14 consisting of two or more rewiring layers (multilayer wiring) and the semiconductor element 15 are joined.
Thereafter, in order to prevent oxidation of the conductor layer 6 exposed on the surface of the second wiring board 14 and to improve the wettability of the solder bump portions 17, the conductor layer 6 exposed on the surface is coated with electroless Ni/Pd/ Surface treatments such as Au plating, OSP, electroless tin plating, and electroless Ni/Au plating may be applied.

After that, as shown in FIG. 7, the semiconductor device (see FIG. 6F) obtained by the above processing is bonded to the FC-BGA substrate (first wiring substrate) 12, and the bonding portion is filled with an underfill 22. The semiconductor device 24 is completed by fixing the semiconductor device and the FC-BGA substrate 12 and sealing the junction.

Tables 1 and 2 show results of dummy pattern dimensions (arrangement intervals between islands (numbers in the horizontal columns in the table)) of the conductor layer and the amount of dents due to polishing as an effect confirmation in this embodiment.
When copper is used as the conductive material (conductive layer), the table shows the amount of dents after the first polishing with high chemical polishing, the second polishing with high physical polishing, and the amount of copper with respect to the photosensitive resin. It shows which of the convex shape/concave shape was finished.
For the first polishing, a slurry intended for chemical polishing of copper is used, and a copper oxidizing agent, an organic reducing agent, a rust preventive, a complexing agent, etc. are dispersed.
For the second polishing, a slurry for the purpose of physically polishing the copper, the seed layer, the inorganic adhesion layer, and the photosensitive resin is used, and a filler made of colloidal silica with a diameter of several tens of nanometers and a dispersion of the filler are used. Stabilizers, additives, etc. are dispersed.

Table 1 shows the case where slurry A is used for the first polishing. Table 2 shows the case where slurry B is used for the first polishing.
Slurry A is a slurry having a strong etching property for copper, and copper is etched even in a narrow pattern area of 20 μm opening width of the photosensitive resin, and the amount of recess of the copper with respect to the photosensitive resin is large.
Slurry B is a slurry that suppresses the etchability of copper. In the narrow pattern area of the opening width of the photosensitive resin, 20 μm, the copper is difficult to be etched. The volume is starting to grow.
The etchability of copper can be adjusted by adjusting the balance of the constituents of the slurry.

The wiring portion of the second wiring board is a region of 200 μm or less, and the unevenness in the wiring board can be controlled within the range of −0.1 to +0.1 μm.
The accessory pattern portion consists of large-area patterns such as alignment marks, ground patterns, and dummy patterns, and there is also a solid pattern portion made of a conductive material larger than 2 mm shown in Tables 1 and 2 above. When forming a solid pattern of a large area pattern by the damascene method of the present invention, the interval is narrower than 1.5 mm, preferably narrower than 1 mm, from Tables 1 and 2, and the material different from the conductive material, such as a photosensitive resin It is effective to place dummy patterns at

In this embodiment, in forming the conductor layer 6 of FIGS. 2F, 3F, and 4, dummy patterns of 200 μm in diameter are arranged in the form of islands at intervals of 1 mm in the body area pattern portion having a linear dimension of the accessory pattern portion larger than 1 mm. placed in
Dummy patterns made of a conductive material and having a diameter of 200 μm were arranged like islands at intervals of 1 mm in the large area pattern portion of the photosensitive insulating resin having a linear dimension of 1 mm.
With this pattern arrangement, it was possible to control the variation in the height of each rewiring layer from the imaginary plane within the range of -0.1 μm to +0.1 μm.

In addition, by controlling the variation in the height of each rewiring layer from the imaginary plane within the range of −0.1 μm to +0.1 μm, undulations during coating of the photosensitive insulating resin laminated on the upper layer are reduced. At the same time, variations in the height of the resin trench portion 21 and variations in dimensional resolution can be suppressed.
In addition, it is possible to control variations in the height of the bumps connected to the semiconductor element, which is effective in improving electrical connection reliability.

Comparative example

The materials used, construction method, and configuration are the same as in the example, and a configuration in which island-shaped dummy patterns are not arranged in the accessory pattern portion or the large area portion of the photosensitive insulating resin with a linear dimension of 1.5 mm or more will be described as a comparative example. do.
In the comparative example, a solid pattern made of an amorphous conductive material surrounding the wiring pattern was arranged as the ground pattern. In forming the conductor layer 6 in FIGS. 3F and 4, the first polishing with a high chemical polishing property causes the ground pattern portion to be recessed by a little over 2 μm, the conductive material near the center of the pattern disappears, and the underlying layer is exposed to light. There was a portion where the flexible resin layer was exposed.
The wiring part could be formed with the same quality as the comparative example.
In the rewiring layer thus obtained, the height variation from the imaginary plane of the surface was in the range of -2 μm to +0.1 μm.

In addition, since the variation in the height of each rewiring layer from the imaginary plane is in the range of -2 μm to +0.1 μm, the resin trench is affected by undulations during coating of the photosensitive insulating resin laminated on the upper layer. Variation in the height of the portion 21 and variation in the dimensional resolution occurred, and the trough portion of the undulation was not well polished, and the pattern resolution was lowered, such as the occurrence of portions where the copper remained as a solid film.
The above-described embodiment is an example, and it goes without saying that other specific details such as the structure can be changed as appropriate.

INDUSTRIAL APPLICABILITY The present invention can be applied to a semiconductor device having a wiring substrate provided with an interposer or the like interposed between a main substrate and a semiconductor element.

Reference Signs List 1 support substrate 2 release layer 3 photosensitive resin layer 4 seed adhesion layer 5 seed layer 6 conductor layer 7 resist pattern 9 surface treatment layer 10 solder bump 11 wiring substrate 12 semiconductor element (first wiring substrate)
14 wiring board (second wiring board)
15 Semiconductor element 17 Bump part 21 Resin trench part 22 Underfill 23 Sealing resin 24 Semiconductor device 25 Wiring pattern 26 Land 27 Accessory pattern 28 Dummy pattern 29 Wiring part 30A Ground pattern 30B Photosensitive resin solid pattern 31 Via

Claims (7)

a second wiring board bonded to the semiconductor element;
A wiring board comprising: a first wiring board mounted on a surface of the second wiring board opposite to a surface on which the semiconductor element is mounted,
Widths of wirings constituting each of the first wiring board, the second wiring board, and the semiconductor element are narrowed in this order in comparison at the narrowest position,
wherein the second wiring board comprises a multi-layer wiring by laminating two or more rewiring layers;
each of the wiring layers includes a photosensitive resin layer made of a photosensitive resin, and an opening formed in the photosensitive resin layer forms a resin trench;
a wiring pattern portion filled with a conductive material as a part of the resin trench portion; a photosensitive resin solid pattern portion disposed so as to surround the wiring pattern portion; a ground pattern consisting of a large-area pattern having a width of 1.5 mm or more at the narrowest part arranged in the
A seed adhesion layer and a seed layer are formed in this order on the bottom surface of the resin trench portion, and a wiring portion made of a conductor layer formed by filling the inside of the resin trench portion with a conductive material is provided. ,
The multilayer wiring is configured by laminating two or more conductor layers serving as the wiring portion,
A dummy in which a plurality of island-shaped photosensitive resin patterns made of a photosensitive resin are arranged at intervals of 1.5 mm or less in the ground pattern in each rewiring layer composed of the wiring portion and the photosensitive resin layer. having a pattern,
A wiring board characterized by: When the photosensitive resin solid pattern portion is composed of a large area pattern having a width of 1.5 mm or more at the narrowest portion, a plurality of islands made of a conductive material are formed in the photosensitive resin solid pattern portion at intervals of 1.5 mm or less. 2. The wiring board according to claim 1, further comprising a dummy pattern in which a plurality of conductive patterns are arranged. A connection via portion connecting between adjacent layers of the rewiring layer has a seed adhesion layer on one side of the side on which the first wiring board or the second wiring board is mounted and on the side surface. The wiring board according to claim 1 or 2. 4. The wiring board according to claim 1, wherein the conductive material contains copper. 5. The wiring board according to claim 1, wherein the seed layer of the second wiring board is a layer containing copper. 6. The wiring board according to claim 1, wherein the seed adhesion layer of the second wiring board is a layer containing titanium. A wiring board provided with a second wiring board bonded to a semiconductor element, wherein the second wiring board is laminated with two or more rewiring layers to form a multilayer wiring, and each wiring layer is made of a photosensitive resin. comprising a photosensitive resin layer consisting of, the opening opening in the photosensitive resin layer forming a resin trench portion,
A wiring pattern portion filled with a conductive material is formed in a part of the resin trench portion, and a seed adhesion layer and a seed layer are formed in this order on the bottom surface of the resin trench portion. A method for manufacturing a wiring board, in which a wiring portion made of a conductor layer is formed by filling a conductive material inside the
The method for forming the rewiring layer is
forming a resin trench portion in the photosensitive resin layer;
providing a seed adhesion layer and a seed layer on the resin trench portion and the photosensitive resin layer;
a step of laminating a conductive material as a solid film on the seed layer;
The conductive material formed by the solid film is polished from the laminated surface of the substrate by the first polishing, leaving the conductive material in the resin trench portion and removing the unnecessary conductive material laminated on the surface of the photosensitive resin layer. polishing away;
The surfaces of the seed adhesion layer, the seed layer, the conductor layer composed of the conductive material, and the photosensitive resin layer on the surface of the substrate exposed by the first polishing are removed by the second polishing, and the inside of the resin trench is made conductive. forming a redistribution layer comprising a material-filled structure;
with
A method for manufacturing a wiring substrate, wherein the step of forming the rewiring layers is repeated for the required number of layers to form two layers of the rewiring layers.

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