JP2022108040A - Method for manufacturing silicon carbide semiconductor wafer and silicon carbide semiconductor device - Google Patents

Abstract

To make it possible to recognize an alignment key more highly accurately.SOLUTION: A forming process of an alignment key KY is commonly used with a forming process of an ion implantation layer 14. Specifically, when forming the ion implantation layer 14 in a device formation region, an opening 13a wider than a width of an opening 13b for forming the ion implantation layer 14 is formed in a mask 13 in an alignment key formation region R1. Thus, because a recess part 12a is formed in the opening 13a on the basis of a micro-loading phenomenon, the part is used as the alignment key KY. The alignment key KY is formed with no positional deviation for the ion implantation layer 14. Therefore, when the alignment key KY is used as a reference, positional deviation of the other ion implantation layer or trench can be minimized.SELECTED DRAWING: Figure 2C

Description

The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor wafer provided with an alignment key used for mask alignment and a method for manufacturing a SiC semiconductor device.

2. Description of the Related Art Conventionally, there has been proposed a technique for recognizing an alignment key used when manufacturing a semiconductor device with high accuracy (see, for example, Japanese Unexamined Patent Application Publication No. 2002-100003).

When a SiC semiconductor device is manufactured using a SiC semiconductor substrate, a high-quality epitaxial layer can be grown. It is used as a semiconductor substrate. Then, after forming an alignment key on such a SiC semiconductor substrate, a predetermined manufacturing process such as formation of an impurity layer by epitaxial growth or ion implantation is performed to manufacture a SiC semiconductor device. Mask alignment during the manufacturing process is performed by specifying the position of an alignment key with a reading device, and a mask of a desired shape is formed by patterning a mask material using the alignment key as a reference.

At this time, as the alignment key, for example, a rectangular trench having two opposite sides parallel to the OFF direction and other two opposite sides perpendicular to the OFF direction can be used. A plurality of rectangular trenches are formed side by side in the off-direction and read by a reading device called a stepper to recognize the alignment key and use it for mask alignment during the manufacturing process.

The off-direction means "a direction parallel to a vector obtained by projecting the normal vector of the growth plane onto the (0001) plane". Further, in the following description, the downstream side in the off direction is defined as one of them, and is "the side to which the tip of the vector obtained by projecting the normal vector of the growth plane onto the (0001) plane faces". means

Japanese Patent Application Laid-Open No. 2003-234272

However, when epitaxial growth is performed after the formation of the alignment key, the epitaxial growth forms a facet surface on the downstream side of the trench in which the alignment key is rectangular in the off direction. I can't do it. As a result, mask misalignment or the like occurs in all photo processes after the epitaxial growth, making it impossible to manufacture SiC semiconductor devices with high precision.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a SiC semiconductor wafer and a SiC semiconductor device that can recognize an alignment key with higher accuracy.

In order to achieve the above object, the invention according to claim 1 provides a SiC semiconductor wafer, which is a wafer-like SiC semiconductor substrate (11, 101) having an alignment key forming region (R1) and a device forming region (R2). ), silicon carbide epitaxial layers (12, 103) formed on the SiC semiconductor substrate and having recesses (12a, 103a) formed in the alignment key forming region, and formed on the epitaxial layers in the device forming region. a first ion-implanted layer (14, 104) having a predetermined width narrower than the recess; and a second ion-implanted layer (15, 104a) formed on the bottom surface of the recess in the epitaxial layer in the alignment key forming region. ), and an alignment key (KY) is formed based on the step between the recess and the epitaxial layer.

If an opening wider than the first ion-implanted layer is formed also in the alignment key forming region with respect to the mask for forming the first ion-implanted layer in the device forming region, the microloading phenomenon can be prevented. A concave portion is formed based on. This recess can be used as an alignment key. By using a SiC semiconductor wafer having an alignment key formed at the same time as the first ion-implanted layer in this way, it is possible to minimize misalignment when other ion-implanted layers and trenches are subsequently formed. Therefore, it is possible to obtain a SiC semiconductor wafer in which the alignment key can be recognized with higher accuracy. When forming such a concave portion for forming an alignment key, the second ion-implanted layer is formed on the bottom surface of the concave portion at the same time as the first ion-implanted layer.

According to a third aspect of the invention, there is provided a method for manufacturing a SiC semiconductor device having a semiconductor element, wherein a wafer-like semiconductor device having an alignment key forming region (R1) and a device forming region (R2) in which the semiconductor element is formed is provided. preparing SiC substrates (11, 101); forming epitaxial layers (12, 103) made of SiC on the SiC substrate; By patterning the mask material, first openings (13b, 117b) are formed in the device formation region and second openings (13a, 117a) wider than the first openings are formed in the alignment key formation region. is formed, and the mask is used to implant impurity ions into the epitaxial layer, thereby forming the first ion-implanted layers (14, 104) through the first openings. forming and forming a second ion-implanted layer (15, 104a) through the second opening. By forming the mask, recesses (12a, 103a) are formed in the epitaxial layer located at the bottom of the second opening based on the microloading phenomenon in the photo process, and the surfaces of the recesses and the epitaxial layer are formed. Then, an alignment key (KY) is formed based on the steps of .

As described above, in the photo process for forming the mask for forming the first ion-implanted layer, recesses are formed in the epitaxial layer located at the bottom of the second opening based on the microloading phenomenon. As a result, the alignment key can be formed based on the step between the recess and the surface of the epitaxial layer, and the alignment key and the first ion-implanted layer can be formed without misalignment. Therefore, if the alignment key is used as a reference, misalignment of other ion-implanted layers and trenches can be minimized. Therefore, it is possible to recognize the alignment key with higher accuracy.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

It is the figure which showed the manufacturing flow of the SiC semiconductor device concerning 1st Embodiment. 2 is a cross-sectional view of a SiC semiconductor wafer in a pre-process of the manufacturing flow shown in FIG. 1; FIG. 2B is a cross-sectional view of the SiC semiconductor wafer in one step in the manufacturing flow shown in FIG. 1 following FIG. 2A; FIG. 2B is a cross-sectional view of the SiC semiconductor wafer in one step in the manufacturing flow shown in FIG. 1; FIG. It is the figure which looked at FIG. 2B from the paper surface upper direction. 4 is an enlarged cross-sectional view of the vicinity of an opening formed in an alignment key forming area; FIG. 4 is an enlarged cross-sectional view of the vicinity of an opening formed in a device formation region; FIG. It is a figure showing a manufacturing flow of a conventional SiC semiconductor device. FIG. 4 is a cross-sectional view of a SiC semiconductor device described in a second embodiment; FIG. 7 is a perspective cross-sectional view of the SiC semiconductor device shown in FIG. 6; 7 is a cross-sectional perspective view showing a manufacturing process of the SiC semiconductor device shown in FIG. 6; FIG. 8B is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device following FIG. 8A; FIG. 8C is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device continued from FIG. 8B; FIG. 8D is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device following FIG. 8C; FIG. 8C is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device following FIG. 8D; FIG. 8F is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device following FIG. 8E; FIG. 8F is a cross-sectional perspective view showing the manufacturing process of the SiC semiconductor device following FIG. 8F; FIG. FIG. 10 is a diagram showing a change in shape of an alignment key when epitaxial growth is performed on the alignment key;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. In this embodiment, a case where alignment using an alignment key is performed as part of the manufacturing process when manufacturing a SiC semiconductor device will be taken as an example. The manufacturing process according to the present embodiment will be described below with reference to the manufacturing flow shown in FIG. 1 and cross-sectional views corresponding to the manufacturing flow of FIG. 1 shown in FIGS. 2A to 2C.

First, as a pre-process for each process shown in FIG. 1, an n-type or p-type wafer-shaped SiC semiconductor substrate 11 is prepared as shown in FIG. 2A. For example, a SiC semiconductor substrate 11 made of a 4H-type SiC single crystal having an off-angle of 4° and an off-direction of <11-20> is prepared. A region of the SiC semiconductor substrate 11 where an alignment key is formed is defined as an alignment key forming region R1, and a region where a device such as a semiconductor element is formed is defined as a device forming region R2. Alignment key forming region R1 is arranged, for example, in a dicing region of wafer-shaped SiC semiconductor substrate 11 . For this reason, it is removed when singulated into individual chips after going through various manufacturing processes, but the alignment key formed in this region is used for alignment of the mask during various manufacturing processes. Therefore, accurate positioning becomes possible.

Next, a SiC epitaxial layer 12 is formed on this SiC semiconductor substrate 11 by epitaxial (hereinafter referred to as epitaxial) growth. Here, for example, an n-type SiC epitaxial layer 12 is formed. At this time, since epitaxial growth is performed based on step flow growth, the SiC epitaxial layer 12 inherits the crystallinity of the SiC semiconductor substrate 11 and has an off angle.

Subsequently, as shown in FIG. 2B, a mask 13 for alignment key formation and ion implantation is formed on the surface of the SiC epitaxial layer 12 . For example, first, as the mask material deposition step shown in FIG. 1, an oxide film that is the material of the mask 13 is deposited by CVD (chemical vapor deposition) or the like. Next, as the photo process shown in FIG. 1, a photo mask is formed by applying a photoresist (not shown), and performing patterning by exposure and development. Then, as the mask etching process shown in FIG. 1, the mask 13 is formed into a desired pattern by dry etching the oxide film covered with a photomask. Specifically, openings 13 a corresponding to the second openings are formed in the alignment key formation planned positions in the alignment key formation region R<b>1 of the mask 13 . Also, an opening 13b corresponding to the first opening is formed in the mask 13 at the position where the ion-implanted layer is to be formed in the device formation region R2. Then, as the ashing step shown in FIG. 1, the photomask is removed by ashing.

At this time, the opening width of the opening 13a at the position where the alignment key is to be formed is made wider than the opening width of the opening 13b at the position where the ion-implanted layer is to be formed. For example, the openings 13a and 13b are shaped as shown in FIG. Although FIG. 3 is not a cross-sectional view, the openings 13a and 13b are indicated by hatching.

As shown in FIG. 3, the opening 13a has a rectangular outer shape when viewed from above. A key mask portion 13c that is not the opening 13a is provided inside the opening 13a so as to be surrounded by the opening 13a. The key mask portion 13c has a striped shape in which a plurality of rectangular lines are arranged at regular intervals, and the mask 13 is left in this portion. The outer shape of the opening 13a is, for example, 150 μm in length of two sides extending in one direction, here, the OFF direction, and 80 μm in length of two sides extending in a direction perpendicular to the OFF direction. Each key mask portion 13c arranged in a plurality of lines has a length of two sides extending in the off direction of 5 μm and a length of two sides extending in a direction perpendicular to the off direction of 40 μm.

On the other hand, when the opening 13b is viewed from above, it has a rectangular shape. The length of the side is set to 1 μm. In this case, the direction in which the shortest side of the two openings 13a and 13b extends, here, the direction in which the side of the opening 13b extends perpendicular to the off direction, is the width direction of the openings 13a and 13b. .

Due to such dimensions, the opening 13a is wider than the opening 13b, and the region where the opening 13a is formed is a sparse pattern in which the oxide film is sparse, and the opening 13b is formed. The region becomes a dense pattern in which the oxide film is dense. Therefore, during patterning for forming the openings 13a and 13b, the etching rate of the wide opening 13a is higher than that of the narrow opening 13b due to the microloading phenomenon. Then, when the etching of the oxide film to be removed to form the opening 13b is completed, the etching of the oxide film to be removed to form the opening 13a has already been completed, and the underlying SiC epitaxial layer is already etched. You can dig up to 12.

Therefore, as can be seen from the enlarged cross-sectional view of the vicinity of the opening 13a shown in FIG. 4A and the enlarged cross-sectional view of the vicinity of the opening 13b shown in FIG. , the SiC epitaxial layer 12 is etched to a deep position. In the experiment, for example, the depth of the recess 12a formed in the SiC epitaxial layer 12 in the opening 13a, that is, the amount of scraping of the SiC epitaxial layer 12 was 60 nm. Further, the depth of the recess 12b formed in the SiC epitaxial layer 12 in the opening 14b, that is, the amount of scraping of the SiC epitaxial layer 12 was 10 nm. From this, it can be seen that there is a step of about 50 nm between the bottom surface of the recess 12a and the bottom surface of the recess 12b.

Thus, the recess 12a formed in the alignment key forming region R1 can be made deeper than the recess 12b formed in the device forming region R2. Therefore, if the alignment key KY is configured based on the step between the concave portion 12a and the surface of the SiC epitaxial layer 12, it can be used for subsequent mask alignment. When the key mask portion 13c is shaped as described above, the alignment key KY can also be formed of a stripe-shaped convex portion in which a plurality of rectangular lines are arranged at equal intervals. Since the alignment key KY may be formed based on the steps, it may be formed only by the concave portion 12a, or may be formed by a convex portion left in the concave portion 12a.

Furthermore, as the ion implantation step shown in FIG. 1, impurity ions are implanted while being covered with a mask 13 as shown in FIG. An injection layer 14 is formed. Here, the p-type ion-implanted layer 14 is formed by implanting Al or the like as the p-type impurity. Since the opening 13a is also formed in the alignment key forming region R1, the ion-implanted layer 15 is also formed on the bottom surface of the recess 12a. Since the ion-implanted layer 15 is removed when singulated into individual chips after going through various manufacturing processes, it does not affect the device characteristics of the SiC semiconductor device. The ion-implanted layer 14 formed here corresponds to the first ion-implanted layer, and the ion-implanted layer 15 corresponds to the second ion-implanted layer.

After that, the mask 13 is peeled and washed as the peeling and washing step shown in FIG. As a result, a SiC semiconductor wafer is formed in which the alignment key KY is formed in the alignment key formation region R1 by the concave portion 12a, and the ion-implanted layer 14 is formed in the device formation region R2 so as not to be misaligned with the alignment key KY.

In this way, when forming the ion-implanted layer 14 of a different conductivity type on the SiC epitaxial layer 12, the alignment key KY is formed in the alignment key forming region R1 using the microloading phenomenon. Therefore, it is possible to share the process of forming the alignment key KY with the process of forming the ion-implanted layer 14 .

Further, when forming other ion-implanted layers or forming trenches in the SiC epitaxial layer 12 on the same layer, for example, at a position other than the ion-implanted layer 14 in the device formation region R2, alignment Alignment can be performed using the key KY as a reference. At this time, the same mask 13 is used to form the ion-implanted layer 14 and the alignment key KY, and since there is no positional deviation between these, if the alignment key KY is used as a reference, positional deviation of other ion-implanted layers and trenches can be minimized. In other words, if the alignment key KY and the ion-implanted layer 14 are formed in separate processes and the ion-implanted layer 14 is formed with the alignment key KY as a reference, there is a positional deviation between the alignment key KY and the ion-implanted layer 14 . can occur. Therefore, the maximum possible positional deviation is the sum of the positional deviation generated when forming the ion-implanted layer 14 and the positional deviation generated when forming the other ion-implanted layers and trenches. On the other hand, since the alignment key KY and the ion-implanted layer 14 are formed by the same mask 13 without positional deviation, even if other ion-implanted layers or trenches are formed, only the positional deviation occurs. Therefore, it is possible to reduce the maximum possible amount of positional deviation.

Here, the reason why such effects are obtained will be described by comparing the conventional manufacturing flow and the manufacturing flow of the present embodiment.

Conventionally, the process of forming an alignment key and the process of forming an ion-implanted layer are performed as separate processes. Specifically, conventionally, when manufacturing a SiC semiconductor device, a manufacturing process such as the manufacturing flow shown in FIG. 5 is executed.

First, an alignment key forming process is performed. For example, after forming an oxide film as a material for an alignment key forming mask on an n-type SiC epitaxial layer, a photo resist is applied and patterned by exposure as a photo process to form a photo mask. Next, the oxide film is etched while covered with a photomask to form an alignment key forming mask having a desired pattern, and then the photomask is removed by ashing. Then, dry etching is performed using an alignment key forming mask to form recesses that serve as alignment keys in the SiC epitaxial layer. Thereafter, the alignment key forming mask is removed by peeling and cleaning.

Subsequently, a step of forming an ion implantation mask is performed. That is, after removing the alignment key forming mask, an oxide film is formed again as a material for the ion implantation mask. Then, as a photo process, a photo resist is applied and patterning is performed by exposure to form a photo mask. At this time, the alignment key formed in the previous step is used as a reference for mask alignment when exposing the photoresist. Further, the oxide film is etched while covered with a photomask to form an ion implantation mask having a desired pattern, and then the photomask is removed by ashing. Then, for example, an ion-implanted layer is formed by ion-implanting an impurity of a conductivity type different from that of the SiC epitaxial layer, such as a p-type impurity, from above the ion-implantation mask. After that, the ion implantation mask is removed by peeling and cleaning.

As described above, in the conventional manufacturing flow, the process of forming the alignment key and the process of forming the ion-implanted layer are performed as separate processes. For this reason, in addition to the possibility of misalignment occurring between the alignment key and the ion-implanted layer, there is the possibility that processes such as the formation of a mask material, such as oxide film deposition, photolithography, and mask patterning, must be performed separately. Therefore, the number of manufacturing steps increases.

On the other hand, in the present embodiment, as described above, by adopting a manufacturing process similar to the manufacturing flow shown in FIG. It is possible to reduce the number of processes. Specifically, a mask material film forming process, a photo process, a mask etching process, an ashing process, and a peeling/cleaning process can be shared.

In addition, the alignment key KY and the ion-implanted layer 14 can be formed without misalignment. Therefore, if the alignment key KY is used as a reference, misalignment of other ion-implanted layers and trenches can be minimized.

Further, by using the SiC semiconductor wafer having the alignment key KY formed at the same time as the ion-implanted layer 14 in this way, it is possible to minimize misalignment when other ion-implanted layers and trenches are subsequently formed.

(Second embodiment)
A second embodiment will be described. In this embodiment, a case where the manufacturing process described in the first embodiment is applied to a SiC semiconductor device provided with an inverted vertical MOSFET having a trench gate structure shown in FIGS. 6 and 7 as a semiconductor element will be described. do. The vertical MOSFETs shown in FIGS. 6 and 7 are formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure so as to surround the cell region. However, only vertical MOSFETs are shown here. 6 and 7, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET crossing the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET The horizontal direction, that is, the direction normal to the XY plane will be described as the Z direction.

As shown in FIGS. 6 and 7, the SiC semiconductor device uses an n ⁺ -type substrate 101 made of SiC as a semiconductor substrate. An n ⁻ -type layer 102 made of SiC is formed on the main surface of an n ⁺ -type substrate 101 . The n ⁺ -type substrate 101 is an off-cut substrate having a (0001) Si surface and an off-angle of 4°.

A JFET portion 103 made of SiC and an electric field blocking layer 104 are formed on the n ⁻ -type layer 102 , and the n ⁻ -type layer 102 is connected to the JFET portion 103 at a position away from the n ⁺ -type substrate 101 . ing.

The JFET portion 103 and the electric field blocking layer 104 constitute a saturation current suppressing layer, both extend in the X direction, and are alternately and repeatedly arranged in the Y direction. That is, when viewed from the direction normal to the main surface of n ⁺ -type substrate 101, at least a portion of JFET portion 103 and electric field blocking layer 104 are formed in a plurality of strips, that is, in stripes, and are arranged alternately. layout.

In this embodiment, the JFET portion 103 is formed below the electric field blocking layer 104 . For this reason, the striped portions of the JFET portion 103 are connected below the electric field blocking layers 104 , but each striped portion is between the electric field blocking layers 104 . It is placed.

The JFET portion 103 is composed of an n-type impurity layer, and each portion of the stripe-shaped portion, that is, each strip-shaped portion has the same width. The electric field blocking layer 104 is composed of a p-type impurity layer. As described above, the electric field blocking layer 104 is striped, and each strip-shaped portion of the striped electric field blocking layer 104 has the same width. In the case of this embodiment, the electric field blocking layer 104 has a constant p-type impurity concentration in the depth direction. The surface of the electric field blocking layer 104 opposite to the n ⁻ -type layer 102 is flush with the surface of the JFET section 103 .

Furthermore, an n-type current spreading layer 105 made of SiC is formed on the JFET portion 103 and the electric field blocking layer 104 . The n ^- type current spreading layer 105 is a layer that allows the current flowing through the channel to diffuse in the X direction, as will be described later. In this embodiment, the n-type current spreading layer 105 extends in the Y direction and has an n-type impurity concentration equal to or higher than that of the JFET section 103 .

Here, for convenience, the drift layer is divided into the n ⁻ -type layer 102, the JFET portion 103, and the n-type current spreading layer 105 for explanation. Concatenated.

A p-type base region 106 made of SiC is formed on the n-type current spreading layer 105 . An n-type source region 108 is formed on the p-type base region 106 . The n-type source region 108 is formed on a portion of the p-type base region 106 corresponding to the n-type current spreading layer 105 .

The p-type base region 106 has a lower p-type impurity concentration than the electric field blocking layer 104 . The n-type source region 108 is in contact with the p-type base region 106 and has a high concentration of n-type impurities for contact with a source electrode 115 which will be described later.

Further, from the p-type base region 106 downward, specifically, between the surfaces of the JFET portion 103 and the electric field blocking layer 104 and the p-type base region 106, the n-type current spreading layer 105 is not formed. A p-type deep layer 109 forming a connecting layer is formed in the portion. In the present embodiment, the p-type deep layer 109 has a strip-like shape whose longitudinal direction is the direction intersecting the longitudinal direction of the striped portion of the JFET portion 103 and the electric field blocking layer 104, here the Y direction. , and are laid out in a stripe shape by arranging a plurality of them in the X direction. Through this p-type deep layer 109, the p-type base region 106 and the electric field blocking layer 104 are electrically connected. The formation pitch of the p-type deep layers 109 is matched with the cell pitch, which is the formation interval of trench gate structures to be described later, so that the p-type deep layers 109 are arranged between adjacent trench gate structures.

Furthermore, a position on the p-type base region 106 corresponding to the p-type deep layer 109, in other words, a position different from the n-type source region 108 and opposite to the trench gate structure with the n-type source region 108 interposed therebetween. , a p-type coupling layer 110 is formed. The p-type coupling layer 110 is a layer for electrical connection by coupling the p-type base region 106 and a source electrode 115 to be described later. In this embodiment, the p-type coupling layer 110 is arranged on the opposite side of the trench gate structure with the n-type source region 108 interposed therebetween. A structure in which the connection layers 110 are alternately and repeatedly arranged may be used.

Furthermore, the total thickness of the p-type base region 106 and the n-type source region 108 with a predetermined width and depth is formed so as to penetrate through the n-type source region 108 and the p-type base region 106 and reach the n-type current spreading layer 105 . A deeper gate trench 111 is formed. The p-type base region 106 and the n-type source region 108 are arranged so as to be in contact with the side surfaces of the gate trench 111 . The gate trench 111 has a strip-shaped layout in which the X direction in FIG. 7 is the width direction, the direction intersecting with the longitudinal direction of the JFET portion 103 and the electric field blocking layer 104, here the Y direction is the longitudinal direction, and the Z direction is the depth direction. is formed by Although not shown in FIGS. 6 and 7, the gate trenches 111 are formed in a striped shape in which a plurality of trenches are arranged at equal intervals in the X direction. A source region 108 is located. A p-type deep layer 109 and a p-type coupling layer 110 are arranged at intermediate positions of each gate trench 111 .

At the side of this gate trench 111, the p-type base region 106 forms a channel region connecting between the n-type source region 108 and the n-type current spreading layer 105 during operation of the vertical MOSFET. The inner wall surface of the gate trench 111 including this channel region is covered with a gate insulating film 112 . A gate electrode 113 made of doped Poly-Si is formed on the surface of the gate insulating film 112, and the inside of the gate trench 111 is filled with the gate insulating film 112 and the gate electrode 113 to form a trench gate structure. It is

In this trench gate structure, the sidewalls of the gate trench 111 are substantially parallel to the Z direction, and are rounded and inclined on the entrance side of the opening so that the width of the opening is slightly wider than the bottom. . More specifically, the portion of the side wall of gate trench 111 contacting p-type base region 106 and n-type current spreading layer 105 is substantially parallel to the Z direction, and the portion contacting n-type source region 108 is rounded. It is in a slanted state.

A source electrode 115 and a gate wiring layer (not shown) are formed on the surface of the n-type source region 108 and the surface of the gate electrode 113 with an interlayer insulating film 114 interposed therebetween. The source electrode 115 and gate wiring layer are composed of a plurality of metals such as Ni/Al. Of the plurality of metals, at least n-type SiC, more specifically, the portion in contact with n-type source region 108 is made of a metal capable of ohmic contact with n-type SiC. At least the portion of the plurality of metals that contacts p-type SiC, specifically the p-type coupling layer 110, is made of a metal capable of making ohmic contact with p-type SiC. Source electrode 115 is electrically insulated from the SiC portion by being formed on interlayer insulating film 114 . It is in electrical contact with deep layer 109 .

On the other hand, a drain electrode 116 electrically connected to the n ⁺ -type substrate 101 is formed on the back side of the n ⁺ -type substrate 101 . With such a structure, a vertical MOSFET having an n-channel type inverted trench gate structure is formed. A cell region is configured by arranging a plurality of cells of such vertical MOSFETs. A SiC semiconductor device is constructed by constructing a peripheral breakdown voltage structure, such as a guard ring (not shown), so as to surround the cell region in which such a vertical MOSFET is formed.

In a SiC semiconductor device having a vertical MOSFET configured in this manner, for example, a gate voltage Vg of 20 V is applied to the gate electrode 113 with a source voltage Vs of 0 V and a drain voltage Vd of 1 to 1.5 V. It is operated by applying voltage. That is, the vertical MOSFET forms a channel region in the p-type base region 106 in contact with the gate trench 111 by applying the gate voltage Vg. This allows conduction between the n-type source region 108 and the n-type current spreading layer 105 . Therefore, the vertical MOSFET passes from the n ⁺ -type substrate 101 through the n ⁻ -type layer 102, the JFET portion 103 and the n-type current spreading layer 105 through the drift layer, and further from the channel region through the n-type source region 108. It performs the operation of passing a current between the drain and the source.

Further, the SiC semiconductor device of this embodiment includes a JFET section 103 and an electric field blocking layer 104 . Therefore, during the operation of the vertical MOSFET, the JFET portion 103 and the electric field blocking layer 104 function as a saturation current suppressing layer, exhibiting a saturation current suppressing effect, thereby achieving a low on-resistance and maintaining a low saturation current. It becomes possible to Specifically, since the JFET portion 103 has a structure in which the striped portion and the electric field blocking layer 104 are alternately and repeatedly formed, the following operation is performed.

First, when the drain voltage Vd is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the electric field blocking layer 104 side to the JFET section 103 is formed in a stripe shape in the JFET section 103. It stretches only to a width smaller than the width of the part that has been made. Therefore, even if the depletion layer extends into the JFET portion 103, a current path is secured. In addition, since the n-type impurity concentration of the JFET portion 103 is higher than that of the n ⁻ -type layer 102, the current path can be configured to have a low resistance, so that a low on-resistance can be achieved.

Further, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short circuit or the like, the depletion layer extending from the electric field blocking layer 104 side to the JFET portion 103 extends beyond the width of the striped portion of the JFET portion 103 . . Then, the JFET portion 103 is immediately pinched off before the n-type current spreading layer 105 is. At this time, the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the width of the striped portion of the JFET portion 103 and the n-type impurity concentration. Therefore, the width and n-type impurity concentration of the striped portion of the JFET portion 103 are set so that the JFET portion 103 is pinched off when the voltage becomes slightly higher than the drain voltage Vd during normal operation. do. This makes it possible to pinch off the JFET section 103 even with a low drain voltage Vd. In this way, by immediately pinching off the JFET unit 103 when the drain voltage Vd becomes higher than the voltage during normal operation, it is possible to maintain a low saturation current, and furthermore, it is possible to maintain a low saturation current. It is possible to improve the resistance of the SiC semiconductor device.

In this way, the JFET portion 103 and the electric field blocking layer 104 function as a saturation current suppressing layer, exhibiting a saturation current suppressing effect, thereby providing a SiC semiconductor device capable of achieving both a low on-resistance and a low saturation current. becomes possible.

Furthermore, by providing the electric field blocking layers 104 so as to sandwich the JFET section 103, a structure is formed in which the striped portions of the JFET section 103 and the electric field blocking layers 104 are alternately and repeatedly formed. Therefore, even if the drain voltage Vd becomes a high voltage, the extension of the depletion layer extending from below to the n ⁻ -type layer 102 is suppressed by the electric field blocking layer 104, and extension to the trench gate structure can be prevented. can. Therefore, the electric field suppressing effect of reducing the electric field applied to the gate insulating film 112 can be exerted, and the breakdown of the gate insulating film 112 can be suppressed. Since the depletion layer can be prevented from extending to the trench gate structure in this way, the n ⁻ -type layer 102 and the JFET portion 103, which form part of the drift layer, can have a relatively high n-type impurity concentration. On-resistance can be achieved.

Next, a method for manufacturing a SiC semiconductor device including a vertical MOSFET having an n-channel type inverted trench gate structure according to the present embodiment will be described with reference to cross-sectional views during manufacturing steps shown in FIGS. 8A to 8H. explain.

[Steps shown in FIG. 8A]
First, as a SiC semiconductor substrate, an n ⁺ -type substrate 101 composed of an off-cut substrate having an off-angle of, for example, 4° is prepared. Then, an n ⁻ -type layer 102 made of SiC is formed on the main surface of the n ⁺ -type substrate 101 by epitaxial growth using a CVD apparatus (not shown). At this time, a so-called epi-substrate having an n ⁻ -type layer 102 grown in advance on the main surface of the n ⁺ -type substrate 101 may be used. Then, a JFET portion 103 made of SiC is epitaxially grown on the n ⁻ -type layer 102 .

The epitaxial growth is performed by introducing a gas, such as a nitrogen gas, as an n-type dopant, in addition to silane and propane, which are raw material gases of SiC.

[Steps shown in FIG. 8B]
A mask 117 corresponding to a first mask is formed on the surface of the JFET portion 103, and p-type impurity ions are implanted into the JFET portion 103 using this mask 117 to form the electric field blocking layer 104. FIG. Either one or both of boron (B) and aluminum (Al) can be used as the p-type impurity.

The manufacturing process shown in the manufacturing flow of FIG. 1 described in the first embodiment is applied to the ion implantation for forming the mask 117 and forming the electric field blocking layer 104 at this time. Specifically, first, a mask material for forming the mask 117 is arranged. Next, through a photo process or the like, an opening 117b corresponding to the first opening is formed in the mask 117 at a position where the electric field blocking layer 4 is to be formed, using the cell region shown in FIG. 8B as the device forming region R2. do. At the same time, an alignment key formation region R1 is provided in a region different from the device formation region R2, and an opening 117a corresponding to the second opening is formed in the mask 117 at the position where the alignment key KY is to be formed. By ion-implanting a p-type impurity, an electric field blocking layer 104 is formed as an ion-implanted layer, and then the mask 117 is removed. At the time of patterning the mask 117 used for forming the electric field blocking layer 104, a concave portion 103a is formed in the alignment key forming region R1 at the same time. As a result, the electric field blocking layer 104 is formed in the same process, and the first alignment key KY1 composed of the concave portion 103a can be formed, and the electric field blocking layer 104 and the first alignment key KY1 can be formed without misalignment. can do.

[Steps shown in FIG. 8C]
Subsequently, an n-type current spreading layer 105 is formed by epitaxially growing n-type SiC on the JFET portion 103 and the electric field blocking layer 104 . Then, a mask (not shown) is placed on the n-type current spreading layer 105 so as to open a region where the p-type deep layer 109 is to be formed. Thereafter, a p-type deep layer 109 is formed by ion-implanting p-type impurities from above the mask.

When the n-type current spreading layer 105 is epitaxially grown, the first alignment key KY1 formed on the base is inherited, and the second alignment key KY2 is newly formed in the alignment key forming region R1. Therefore, the ion implantation for forming the p-type deep layer 109 is performed by alignment with the new second alignment key KY2 as a reference. However, at this time, the second alignment key KY2 is formed by forming the n-type current spreading layer 105 corresponding to the SiC epitaxial layer on the JFET portion 103 serving as the base. Therefore, a facet surface is formed on the second alignment key KY2 on the downstream side in the OFF direction. Therefore, when the p-type deep layer 109 is formed, the facet surface may cause positional deviation during alignment with the second alignment key KY2 as a reference.

Specifically, as shown in FIG. 9A, the n-type current spreading layer 105 is formed by further epitaxially growing on each layer epitaxially grown on the n ⁺ -type substrate 101. It has a crystal structure inheriting the off-angle of the n ⁺ -type substrate 101 . Then, when the n-type current spreading layer 105 is formed so as to cover the first alignment key KY1 constituted by the concave portion 103a, as shown in FIGS. A (0001) facet is formed on the downstream side. Therefore, an error may occur in recognition of the second alignment key KY2 by a reading device called a stepper.

However, since the simultaneously formed first alignment key KY1 and the electric field blocking layer 104 are not misaligned, only the second alignment key KY2 newly formed thereon and the p-type deep layer 109 are misaligned. Therefore, it is possible to reduce the maximum possible amount of positional deviation.

[Steps shown in FIG. 8D]
A CVD apparatus (not shown) is used to epitaxially grow the p-type base region 106 on the n-type current spreading layer 105 and the p-type deep layer 109 . Then, an n-type source region 108 is formed by ion-implanting n-type impurities into the surface layer portion of the p-type base region 106 using an ion implantation apparatus.

When the p-type base region 106 is epitaxially grown, the second alignment key KY2 formed in the underlying layer is inherited, and a new third alignment key KY3 is formed again in the alignment key forming region R1.

[Steps shown in FIG. 8E]
A mask material is placed over the n-type source region 108 . Then, a mask 118 corresponding to a second mask is formed by patterning the mask material by a photo process. Using this mask 118 as an ion implantation mask, p-type impurity ions are implanted from above the mask 118, and then heat treatment for activation is performed. As a result, the p-type coupling layer 110 can be formed by implanting the p-type impurity ions into the n-type source region 108 .

The manufacturing process shown in the manufacturing flow of FIG. 1 described in the first embodiment is also applied to the ion implantation for forming the mask 118 and forming the p-type coupling layer 110 at this time. Specifically, first, a mask material for forming the mask 118 is arranged. Next, the mask 118 is patterned using the alignment key KY3 as a reference. 8E is used as a device forming region R2, an opening 118b corresponding to the third opening is formed in the mask 118 at the position where the p-type coupling layer 110 is to be formed. At the same time, an alignment key forming region R1 is provided in a region different from the device forming region R2, and an opening 118a corresponding to the fourth opening is formed in the mask 118 at a position different from the alignment key KY3. By ion-implanting a p-type impurity, a p-type coupling layer 110 is formed as an ion-implanted layer, and then the mask 118 is removed. At the time of patterning the mask 118 used for forming the p-type coupling layer 110, the concave portion 108a is simultaneously formed in the alignment key forming region R1. As a result, in the same process, while forming the p-type coupling layer 110, the fourth alignment key KY4 can be formed based on the step between the recess 108a and the n-type source region 108, and the p-type coupling layer 110 and the fourth alignment key KY4 can be formed. Alignment key KY4 can be formed without positional deviation.

When forming the p-type coupling layer 110, ions are also implanted through the opening 118a, so that the p-type ion-implanted layer 110a is formed at the bottom of the recess 108a. A third alignment key KY3 used for patterning the mask 18 used for forming the p-type coupling layer 110 is formed in a portion of the p-type base region 106 located in the alignment key formation region R1. is. Since the p-type base region 106 is formed by epitaxial growth, a facet surface is formed in the third alignment key KY3 on the downstream side in the off direction. Therefore, when the p-type coupling layer 110 is formed, positional deviation may occur during alignment with the third alignment key KY3 as a reference due to the influence of the facet surface. However, since the first alignment key KY1 and the electric field blocking layer 104 formed at the same time in the lower layer are not misaligned, only the third alignment key KY3 newly formed thereon and the p-type coupling layer 110 are misaligned. , the maximum amount of possible misalignment can be reduced.

[Steps shown in FIG. 8F]
After forming a mask (not shown) on the n-type source region 108 and the like, a region of the mask where the gate trench 111 is to be formed is opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using a mask to form the gate trench 111 .

At this time, the patterning of the etching mask used to form the gate trench 111 can be aligned using the fourth alignment key KY4 formed simultaneously with the formation of the p-type coupling layer 110 as a reference. That is, for the gate trench 111 formed on the same layer as the p-type coupling layer 110, it is possible to form an etching mask based on accurate alignment. Therefore, the gate trench 111 can be formed without being misaligned with respect to the p-type coupling layer 110 .

[Steps shown in FIG. 8G]
Thereafter, the gate insulating film 112 is formed by, for example, thermal oxidation after removing the mask, and covers the inner wall surface of the gate trench 111 and the surface of the n-type source region 108 with the gate insulating film 112 . Then, after depositing Poly-Si doped with p-type impurities or n-type impurities, this is etched back to leave Poly-Si at least in the gate trench 111, thereby forming the gate electrode 113. FIG. This completes the trench gate structure.

Although not shown, the following steps are performed. That is, an interlayer insulating film 114 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 113 and the gate insulating film 112 . Further, contact holes are formed in the interlayer insulating film 114 using a mask (not shown) to expose the n-type source region 108 and the p-type deep layer 109 . Then, after forming an electrode material composed of, for example, a laminated structure of a plurality of metals on the surface of the interlayer insulating film 114, the electrode material is patterned to form the source electrode 115 and the gate wiring layer. Furthermore, a drain electrode 116 is formed on the back side of the n ⁺ -type substrate 101 . Thus, the SiC semiconductor device according to this embodiment is completed.

As described above, in the present embodiment, in the method of manufacturing a SiC semiconductor device having a vertical MOSFET, the process of forming the alignment key and the process of forming the ion-implanted layer are made common, and the alignment key and the ion-implanted layer are formed in common. It is formed without positional deviation. For example, the first alignment key KY1 and the electric field blocking layer 104 are formed without positional deviation, and the fourth alignment key KY4 and the p-type coupling layer 110 are formed without positional deviation.

Therefore, when forming other ion-implanted layers and trenches in the same layer as the ion-implanted layer, it is possible to form a mask based on accurate alignment with the alignment key KY as a reference. Further, it is possible to minimize misalignment of other ion-implanted layers and trenches with respect to the ion-implanted layer formed at the same time as the alignment key KY.

Furthermore, according to the manufacturing method of this embodiment, the following effects can also be obtained.

(1) In this embodiment, the process of forming the alignment key KY and the process of forming the ion-implanted layer are made common. are formed, and ion-implanted layers and trenches are formed in the SiC epitaxial layer thereabove. An alignment key KY is formed at the same time as the ion-implanted layer of the upper SiC epitaxial layer is formed. Specifically, after forming the first alignment key KY1 and the electric field blocking layer 104 at the same time, the n-type current spreading layer 105 and the p-type base region 106 are formed as SiC epilayers thereon. A p-type coupling layer 110 is formed as an ion-implanted layer. Then, the fourth alignment key KY4 is formed at the same time when the p-type coupling layer 110 is formed.

At this time, the electric field blocking layer 104 that becomes the lower ion-implanted layer 14 and the first alignment key KY1 are formed without positional deviation. For this reason, even if the p-type base region 106 and the like serving as the SiC epitaxial layer are formed thereon and the p-type coupling layer 110 is formed thereon, the third alignment key KY3 inherited by the p-type base region 106 and the p-type base region 106 are formed. Only the positional deviation from the coupling layer 110 is caused. Therefore, the maximum amount of deviation that can occur between the electric field blocking layer 104 and the p-type coupling layer 110 can be reduced.

(2) In addition, other ion-implanted layers and trenches can be formed in the upper SiC epilayer. In this case, the alignment key formed simultaneously with the ion-implanted layer in the upper SiC epitaxial layer can be used to align other ion-implanted layers and trenches in the same upper SiC epitaxial layer. Therefore, the maximum amount of misalignment that can occur between the ion-implanted layer first formed in the upper SiC epitaxial layer and other ion-implanted layers or trenches can be reduced.

For example, the gate trench 111 can be formed for the p-type base region 106 corresponding to the upper SiC epi layer. In this case, the gate trench 111 can be formed by alignment based on the fourth alignment key KY4 formed at the same time as the p-type connection layer 110 . Therefore, the gate trench 111 can be formed without being misaligned with respect to the p-type coupling layer 110 .

(Other embodiments)
Although the present disclosure has been described based on the above embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including single, more, or less elements thereof, are within the scope and spirit of this disclosure.

For example, the above-described first and second embodiments are merely examples of SiC semiconductor devices to which the present invention is applied, and the present invention can also be applied to SiC semiconductor devices having other element structures.

For example, the n-type source region 108 may be formed not only by ion implantation but also by epitaxial growth. Even in this case, since the n-type source region 108 takes over the third alignment key KY3, the p-type coupling layer 110 can be formed with high precision without misalignment by ion implantation based on mask alignment with the third alignment key KY3 as a reference. Further, if the patterning of the etching mask is performed by mask alignment using the fourth alignment key KY4 as a reference, the gate trench 111 can be formed with high accuracy without misalignment.

When indicating crystal orientation, etc., a bar (-) should be attached to the desired number, but since there are restrictions on expression based on electronic filing, in this specification, the desired number shall be preceded by a bar.

REFERENCE SIGNS LIST 11 SiC semiconductor substrate 12 SiC epitaxial layer 13 mask 13a, 13b opening 14, 15 ion-implanted layer

Claims (7)

A silicon carbide semiconductor wafer,
a wafer-shaped silicon carbide semiconductor substrate (11, 101) having an alignment key formation region (R1) and a device formation region (R2);
silicon carbide epitaxial layers (12, 103) formed on the silicon carbide semiconductor substrate and having recesses (12a, 103a) formed in the alignment key forming region;
a first ion-implanted layer (14, 104) formed with respect to the epitaxial layer in the device formation region and having a predetermined width narrower than the recess;
a second ion-implanted layer (15, 104a) formed on the bottom surface of the recess in the epitaxial layer in the alignment key forming region;
A silicon carbide semiconductor wafer having The recess has a rectangular shape with two sides extending in one direction and two sides extending in a direction perpendicular to the two sides,
2. The silicon carbide semiconductor wafer according to claim 1, wherein an alignment key (KY) composed of a stripe-shaped convex portion in which a plurality of rectangular lines are arranged is formed inside said rectangular shape. A method for manufacturing a silicon carbide semiconductor device including a semiconductor element,
preparing a wafer-shaped silicon carbide semiconductor substrate (11, 101) having an alignment key forming region (R1) and a device forming region (R2) in which the semiconductor elements are formed;
forming an epitaxial layer (12, 103) made of silicon carbide on the silicon carbide semiconductor substrate;
After disposing a mask material on the epitaxial layer, the mask material is patterned by a photo process to form the first openings (13b, 117b) in the device forming region and the alignment key forming region. forming a mask (13, 117) in which a second opening (13a, 117a) wider than the first opening is formed;
Impurity ions are implanted into the epitaxial layer using the mask to form a first ion-implanted layer (14, 104) through the first opening, and second ions are implanted through the second opening. forming an injection layer (15, 104a);
In the formation of the mask, recesses (12a, 103a) are formed in the epitaxial layer located at the bottom of the second opening based on the microloading phenomenon in the photo process. A method for manufacturing a silicon carbide semiconductor device, wherein an alignment key (KY) is formed based on a level difference with the surface of a layer. A method for manufacturing a silicon carbide semiconductor device including a semiconductor element,
Preparing a wafer-shaped silicon carbide semiconductor substrate (101) having an alignment key forming region (R1) and a device forming region (R2) in which the semiconductor elements are formed, and having a first or second conductivity type. When,
forming a first conductivity type layer (102) made of silicon carbide having an impurity concentration lower than that of the silicon carbide semiconductor substrate on the silicon carbide semiconductor substrate;
an electric field blocking layer (104) made of silicon carbide of the second conductivity type, in which a plurality of layers are arranged in stripes with one direction as the longitudinal direction, on the first conductivity type layer; and forming saturation current suppression layers (103, 104) having a JFET portion (103) made of silicon carbide of the first conductivity type and having a portion in which a plurality of lines are alternately arranged in stripes with the electric field blocking layer;
forming a current spreading layer (105) made of silicon carbide of a first conductivity type having a first conductivity type impurity concentration higher than that of the first conductivity type layer on the saturation current suppression layer by epitaxial growth; ,
By ion-implanting impurities of the second conductivity type into the current spreading layer, a connection layer (109) of the second conductivity type reaching the electric field blocking layer and having a longitudinal direction intersecting with the one direction is formed. forming;
forming a base region (106) made of silicon carbide of the second conductivity type on the current spreading layer and the tie layer by epitaxial growth;
forming a source region (108) made of silicon carbide of a first conductivity type having a first conductivity type impurity concentration higher than that of the first conductivity type layer on the base region;
After forming a plurality of gate trenches (111) deeper than the base region from the surface of the source region in a stripe shape with one direction as a longitudinal direction, a gate insulating film (112) is formed on the inner wall surface of the gate trench. forming a trench gate structure by forming a gate electrode (113) on the gate insulating film;
forming a source electrode (115) electrically connected to the source region;
forming a drain electrode (116) on the back surface side of the silicon carbide semiconductor substrate;
Forming the saturation current suppression layer includes:
One of the JFET portion and the electric field blocking layer is composed of an epitaxial layer, and the other is formed by ion-implanting an impurity into the epitaxial layer, and a mask material is placed on the epitaxial layer. After that, by patterning the mask material in a photo process, a first opening (117b) is formed in the device forming region and a first opening (117b) wider than the first opening is formed in the alignment key forming region. forming a first mask (117) having two openings (117a);
By ion-implanting the impurity into the epitaxial layer using the first mask, a first ion-implanted layer (104) is formed through the first opening, and a second ion-implanted layer (104) is formed through the second opening. forming an ion-implanted layer (104a);
By forming the first mask, a recess (103a) is formed in the epitaxial layer located at the bottom of the second opening based on the micro-loading phenomenon in the photo process, so that the recess and the epitaxial layer are formed. A method for manufacturing a silicon carbide semiconductor device, wherein first alignment keys (KY, KY1) are formed based on a step with the surface of a layer. In forming the current spreading layer, second alignment keys (KY, KY2) inheriting the first alignment key are formed in the current spreading layer located in the alignment key forming region,
5 . The method of manufacturing the silicon carbide semiconductor device according to claim 4 , wherein forming said connecting layer includes performing ion implantation based on mask alignment with reference to said second alignment key to form said connecting layer. forming the base region and forming the source region forming a third alignment key (KY, KY3) inherited from the second alignment key;
forming an interconnecting layer (110) of a second conductivity type by implanting a second conductivity type impurity into the source region after forming the source region;
6. The method of manufacturing a silicon carbide semiconductor device according to claim 5, wherein forming said coupling layer includes performing ion implantation based on mask alignment with said third alignment key as a reference to form said coupling layer. By forming the connection layer,
After disposing a mask material on the source region, the mask material is patterned by a photo process, thereby forming a third opening (118b) in the device formation region and in the alignment key formation region. forming a second mask (118) having a fourth opening (118a) wider than the third opening at a position different from the third alignment key;
Impurity ions are implanted into the source region using the second mask to form the connection layer through the third opening and to form an ion-implanted layer (110a) through the fourth opening. including and
In forming the second mask, a recess (108a) is formed in the source region located at the bottom of the fourth opening based on the micro-loading phenomenon in the photo process, so that the recess and the source are formed. forming a fourth alignment key (KY, KY4) based on a step difference with the surface of the region;
In forming the trench gate structure, when forming the gate trench by etching from the surface of the source region, etching is performed using an etching mask formed based on mask alignment with the fourth alignment key as a reference. 7. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein said gate trench is formed by performing a

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