JP2022097258A - Code generating circuit - Google Patents

Abstract

To generate a random data signal composed of data with a bit width of 2 bits or more while suppressing the circuit scale.SOLUTION: A code generating circuit 100 includes a PN code generating circuit 11 that outputs pseudo random noise (PN) code data bit by bit in synchronization with the clock, a count circuit 12 that counts the number of clocks and outputs a count value of 2 or more, and a conversion circuit 13 that converts PN code data to parallel data in synchronization with the clock and outputs parallel data at the timing when the count value reaches a predetermined value.SELECTED DRAWING: Figure 1

Description

The present invention relates to a code generation circuit.

Conventionally, a circuit for generating a PN (Pseudo Random Noise) code, which is a data string having a bit width of 1 bit, is known. Patent Document 1 discloses a frequency signal generator that generates a signal in which the noise level of each of a plurality of frequency domains is controlled based on a PN code.

Japanese Patent No. 6433336

For example, in a communication device using an analog modulation method such as AM modulation, FM modulation or PM modulation, when it is necessary to generate highly random data such as test transmission data or interference wave data, the PN code generation circuit is used. It is required to generate random data with a bit width larger than a bit. When a random data signal composed of data with a bit width of 2 bits or more is generated using conventional techniques, a filter aimed at controlling the frequency domain of the generated signal is placed after the circuit that generates the PN code. Need to be connected. As a result, there has been a problem that the circuit scale becomes large.

Therefore, the present invention has been made in view of these points, and provides a code generation circuit capable of generating a random data signal composed of data having a bit width of 2 bits or more while suppressing the circuit scale. The purpose.

The code generation circuit according to the aspect of the present invention is a PN code generation circuit that outputs PN (Pseudo Random Noise) code data bit by bit in synchronization with a clock, counts the number of the clocks, and counts two or more count values. It has a count circuit for outputting and a conversion circuit for converting the PN code data into parallel data in synchronization with the clock and outputting the parallel data at a timing when the count value becomes a predetermined value.

The conversion circuit may output the parallel data at the timing when the count value reaches the maximum value.

The conversion circuit may convert the PN code data into parallel data having a bit width corresponding to the maximum value of the count value.

The conversion circuit may have a latch that stores the PN code data of the number of bits corresponding to the maximum value of the count value.

Further having a setting circuit for setting the maximum value of the count value, the count circuit may output a count value equal to or less than the maximum value of the count value set by the setting circuit.

According to the present invention, there is an effect that a random data signal composed of data having a bit width of 2 bits or more can be generated while suppressing the circuit scale.

It is a figure which shows the structure of the code generation circuit 100 which concerns on this embodiment. It is a figure which shows the value and the frequency characteristic of the parallel data output by a conversion circuit 13. It is a figure which shows the structure of the code generation circuit 100 which concerns on a modification.

[Structure of Code Generation Circuit 100]
FIG. 1 is a diagram showing a configuration of a code generation circuit 100 according to the present embodiment. The code generation circuit 100 includes a PN (Pseudo Random Noise) code generation circuit 11, a count circuit 12, and a conversion circuit 13. The code generation circuit 100 generates a random data signal composed of data having a bit width of 2 bits or more in synchronization with the input clock signal.

The PN code generation circuit 11 is a circuit for generating PN code data which is a data string having a bit width of 1 bit. The PN code generation circuit 11 has, for example, a linear feedback shift register, and generates PN code data by inputting a clock to the linear feedback shift register. The PN code generation circuit 11 outputs PN code data bit by bit in synchronization with the clock.

FIG. 1 shows a Fibonacci LFSR (Linear Feedback Shift Register) as an example of a linear feedback shift register included in the PN code generation circuit 11. The PN code generation circuit 11 may generate a PN code using a linear feedback shift register different from the Fibonacci LFSR shown in FIG.

The counting circuit 12 counts the number of clocks and outputs a count value of 2 or more. The counting circuit 12 counts, for example, the number of clocks in ascending order. When the count value is the maximum value, the count circuit 12 further counts the clock to make the count value the minimum value. For example, when the count circuit 12 outputs a count value having a bit width of 4 bits as shown in FIG. 1, the count circuit 12 outputs 15 which is the maximum value of the count value, and then further counts the clock to minimize the count value. Outputs the value 0.

The conversion circuit 13 is, for example, a circuit having a serial-parallel conversion circuit. The conversion circuit 13 converts the PN code data into parallel data in synchronization with the clock, and outputs the parallel data at the timing when the count value becomes a predetermined value. The predetermined value is, for example, a predetermined value, which is a value stored in a storage unit (not shown) of the code generation circuit 100. The conversion circuit 13 outputs parallel data, for example, at the timing when the count value reaches the maximum value.

The conversion circuit 13 may convert the PN code data into parallel data having a bit width corresponding to the maximum value of the count value. When the maximum value of the count value is 15, the conversion circuit 13 converts the PN code data into parallel data having a bit width of 16 bits corresponding to the count circuit 12 counting 16 clocks. In this case, the conversion circuit 13 outputs parallel data obtained by converting PN code data 16 bits at a time.

FIG. 2 is a diagram showing the values and frequency characteristics of the parallel data output by the conversion circuit 13. FIG. 2 illustrates a case where the conversion circuit 13 outputs parallel data having a bit width of 16 bits as shown in FIG. FIG. 2A shows the value of the parallel data output by the conversion circuit 13. FIG. 2B shows the frequency characteristics of the parallel data output by the conversion circuit 13.

In FIG. 2A, the horizontal axis shows the order of the parallel data output by the conversion circuit 13, and the vertical axis shows the value of the parallel data. As shown in FIG. 2A, the conversion circuit 13 randomly outputs values from the minimum value of parallel data "-32768" to the maximum value of parallel data "32767".

In FIG. 2B, the horizontal axis shows the frequency, and the vertical axis shows the value obtained by logarithmically transforming the magnitude of each frequency component included in the parallel data. As shown in FIG. 2B, the conversion circuit 13 outputs parallel data in which the logarithmically converted values at each of the plurality of frequencies are within a certain range. Therefore, the conversion circuit 13 outputs parallel data with no bias in frequency characteristics.

As described above, the conversion circuit 13 converts the PN code data into parallel data and outputs the parallel data at the timing when the count value becomes a predetermined value, whereby the code generation circuit 100 is as shown in FIG. Random data with no bias in frequency characteristics can be output. Further, the code generation circuit 100 can suppress the circuit scale by outputting random data by using, for example, the count circuit 12 and the conversion circuit 13 whose circuit scale is smaller than that of the filter circuit.

The conversion circuit 13 may have a latch for storing PN code data having a number of bits corresponding to the maximum value of the count value. For example, the conversion circuit 13 stores the acquired PN code in the latch in synchronization with the clock, and outputs a plurality of PN codes stored in the latch at the timing when the count value becomes a predetermined value. As described above, when the conversion circuit 13 uses the latch for generating the PN code data, the conversion circuit 13 can facilitate the circuit configuration and reduce the circuit scale as compared with the serial-parallel conversion circuit.

[Modification example]
In the above description, the predetermined value used by the conversion circuit 13 is stored in the storage unit of the code generation circuit 100, but the present invention is not limited to this. The predetermined value used by the conversion circuit 13 may be set from outside the code generation circuit 100, for example. FIG. 3 is a diagram showing a configuration of a code generation circuit 100 according to a modification. The code generation circuit 100 shown in FIG. 3 is different from the code generation circuit 100 shown in FIG. 1 in that it has a setting circuit 14, and is the same in other respects.

The setting circuit 14 accepts a setting from the outside of the code generation circuit 100. The setting is, for example, the maximum value of the count value. The setting circuit 14 accepts the setting by receiving data via the I2C (Inter-Integrated Circuit) interface or acquiring the switching value of the DIP switch, for example. When the setting circuit 14 receives the maximum value of the count value, the setting circuit 14 sets the maximum value of the count value in the count circuit 12 and the conversion circuit 13.

When the setting circuit 14 sets the maximum value of the count value, the count circuit 12 outputs a count value equal to or less than the maximum value of the count value set by the setting circuit 14. For example, when the setting circuit 14 sets the maximum value of the count value to 7, the count circuit 12 outputs a count value of 7 or less.

For example, when the setting circuit 14 sets the maximum value of the count value to 7, the conversion circuit 13 outputs parallel data at the timing when the count value becomes 7. In this case, the conversion circuit 13 converts the PN code into parallel data having a bit width of 8 bits corresponding to 7, which is the maximum value of the count value. In this way, the conversion circuit 13 outputs parallel data based on the maximum value of the count value set by the setting circuit 14, and the conversion circuit 13 outputs parallel data having a bit width according to, for example, a user's request. can do.

[Effect of code generation circuit 100]
As described above, the code generation circuit 100 includes a PN code generation circuit 11 that generates PN code data bit by bit in synchronization with a clock, and a count circuit that counts the number of clocks and outputs a count value of 2 or more. Has 12 and. Then, the conversion circuit 13 converts the PN code data into parallel data in synchronization with the clock, and outputs the parallel data at the timing when the count value becomes a predetermined value, whereby the conversion circuit 13 has two or more bits or more. Outputs random data composed of bit width data.

By using the count circuit 12 and the conversion circuit 13 in this way, the code generation circuit 100 can output random data composed of data having a bit width of 2 bits or more while suppressing the circuit scale.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes can be made within the scope of the gist thereof. be. For example, all or part of the device can be functionally or physically distributed / integrated in any unit. Also included in the embodiments of the present invention are new embodiments resulting from any combination of the plurality of embodiments. The effect of the new embodiment produced by the combination has the effect of the original embodiment together.

11 PN code generation circuit 12 Count circuit 13 Conversion circuit 14 Setting circuit 100 Code generation circuit

Claims (5)

A PN code generation circuit that outputs PN (Pseudo Random Noise) code data bit by bit in synchronization with the clock, and
A count circuit that counts the number of clocks and outputs a count value of 2 or more,
A conversion circuit that converts the PN code data into parallel data in synchronization with the clock and outputs the parallel data at the timing when the count value reaches a predetermined value.
A code generation circuit having. The conversion circuit outputs the parallel data at the timing when the count value reaches the maximum value.
The code generation circuit according to claim 1. The conversion circuit converts the PN code data into parallel data having a bit width corresponding to the maximum value of the count value.
The code generation circuit according to claim 1 or 2. The conversion circuit has a latch that stores the PN code data of the number of bits corresponding to the maximum value of the count value.
The code generation circuit according to any one of claims 1 to 3. Further having a setting circuit for setting the maximum value of the count value,
The count circuit outputs a count value equal to or less than the maximum value of the count value set by the setting circuit.
The code generation circuit according to any one of claims 1 to 4.

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