JP2022095431A - Memory cell array unit - Google Patents

Abstract

To provide a memory cell array unit capable of suppressing malfunction caused by an internal voltage.SOLUTION: A memory cell array unit according to the first aspect of the present disclosure includes an internal power supply unit, a memory cell array, and a micro controller. The memory cell array includes a plurality of non-volatile memory cells that share the internal power supply unit and into which writing can be performed. The micro controller simultaneously executes a set operation for a plurality of first non-volatile memory cells that are one part of the plurality of non-volatile memory cells, and together, executes a reset operation for a plurality of second non-volatile memory cells different from the plurality of first non-volatile memory cells of the plurality of non-volatile memory cells, sequentially for each set in predetermined units within a period when the set operation is executed.SELECTED DRAWING: Figure 9

Description

The present disclosure relates to a memory cell array unit.

Conventionally, a memory cell array unit including a plurality of rewritable memory cells having non-volatility is known (see, for example, Patent Documents 1 and 2).

Japanese Unexamined Patent Publication No. 2013-12786 International Publication 2013/08511

By the way, in the above-mentioned memory cell array unit, a high-precision internal voltage is generated by a regulator based on a low-precision power supply voltage supplied from an external power source and applied to the memory cell. A voltage drop occurs in this internal voltage due to the wiring resistance and the current flowing through the memory cell. Therefore, it is difficult to keep the voltage applied to the memory cell constant regardless of the position of the memory cell, which may cause a malfunction. Therefore, it is desirable to provide a memory cell array unit capable of suppressing malfunction caused by an internal voltage.

The memory cell array unit according to the first aspect of the present disclosure includes an internal power supply unit, a memory cell array, and a microcontroller. The memory cell array includes a plurality of writable non-volatile memory cells that share an internal power supply. The microcontroller simultaneously performs a set operation on a plurality of first non-volatile memory cells that are a part of the plurality of non-volatile memory cells, and at the same time, a plurality of first non-volatile memory cells among the plurality of non-volatile memory cells. A plurality of second non-volatile memory cells different from the non-volatile memory cells are sequentially reset for each predetermined unit within the period during which the set operation is performed.

In the memory cell array unit according to the first aspect of the present disclosure, a set operation is simultaneously performed on a plurality of first non-volatile memory cells, and a set operation is performed on a plurality of second non-volatile memory cells. The reset operation is sequentially performed for each predetermined unit within the performing period. As a result, the maximum load current of the internal power supply unit is suppressed to be low as compared with the case where the reset operation is simultaneously performed on the plurality of second non-volatile memory cells.

The memory cell array unit according to the second aspect of the present disclosure includes a memory cell array, an internal power supply unit, and a microcontroller. The memory cell array includes a plurality of writable non-volatile memory cells and a drive unit for driving the plurality of non-volatile memory cells. The internal power supply unit supplies current to the memory cell array. The microcontroller controls the drive unit in response to the input of write commands, write data, and address data. The drive unit has a variable resistance circuit provided in the path of the current supplied from the internal power supply unit to the non-volatile memory cell, and a current limiting circuit that limits the overcurrent in the above path.

In the memory cell array unit according to the second aspect of the present disclosure, a variable resistance circuit provided in the path of the current supplied from the internal power supply unit to the non-volatile memory cell is used to input write commands, write data, and address data. It is controlled according to. Thereby, for example, it is possible to adjust the resistance value of the variable resistance circuit according to the positional relationship of the non-volatile memory cell to be written with the internal power supply unit. As a result, the current flowing through each non-volatile memory cell to be written becomes more uniform than in the case where the variable resistance circuit is not provided.

It is a figure which shows an example of the schematic structure of the information processing system which concerns on one Embodiment. It is a figure which shows an example of the schematic structure of the memory cell array unit of FIG. It is a figure which shows an example of the schematic structure of each die of FIG. It is a figure which shows an example of the schematic structure of each bank of FIG. It is a figure which shows an example of the schematic structure of each tile of FIG. It is a figure which shows an example of the schematic structure of the bl decoder and wl decoder in the tile of FIG. It is a figure which shows an example of the schematic structure of the memory cell array of FIG. It is a figure which shows an example of the value of the voltage applied to the memory cell of FIG. It is a figure which shows an example of the waveform of the current flowing through the memory cell of FIG. It is a figure which shows an example of the read operation in the memory cell of FIG. It is a figure which shows an example of the writing operation in the memory cell of FIG. It is a figure which shows an example of the electric current flowing through the tile which concerns on a comparative example. It is a figure which shows an example of the schematic structure of the bl decoder and wl decoder in the tile of FIG. It is a figure which shows one modification of the writing operation in the memory cell of FIG.

Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention of excluding various modifications and applications of techniques not specified below. This technique can be implemented with various modifications (for example, combining each embodiment) within a range that does not deviate from the purpose. Further, in the description of the following drawings, the same or similar parts are represented by the same or similar reference numerals. The drawings are schematic and do not necessarily match the actual dimensions and ratios. Even between drawings, there may be parts where the relationship and ratio of dimensions differ from each other.

<1. Embodiment>
[Constitution]
FIG. 1 shows an example of a functional block of an information processing system according to an embodiment. This information processing system includes a host computer 100 and a memory unit 200. The memory unit 200 includes a memory controller 300, one or more memory cell array units 400, and a power supply unit 500. FIG. 1 illustrates a state in which one memory cell array unit 400 is provided. The memory cell array unit 400 corresponds to a specific example of the "memory cell array unit" of the present disclosure.

(Host computer 100)
The host computer 100 controls the memory unit 200. Specifically, the host computer 100 issues a command for designating the logical address of the access destination, and supplies the command and data to the memory unit 200. The host computer 100 receives the data output from the memory unit 200. Here, the command is for controlling the memory unit 200, and includes, for example, a write command instructing a data write process or a read command instructing a data read process. Further, the logical address is an address assigned to each area of the access unit when the host computer 100 accesses the memory unit 200 in the address space defined by the host computer 100.

(Memory controller 300)
The memory controller 300 controls one or more memory cell array units 400. The memory controller 300 receives a write command from the host computer 100 that specifies a logical address. Further, the memory controller 300 executes the data writing process according to the writing command. In this write process, the logical address is converted into a physical address, and data is written to the physical address. Here, the physical address is an address assigned in one or a plurality of memory cell array units 400 for each access unit when the memory controller 300 accesses one or a plurality of memory cell array units 400. When the memory controller 300 receives the read command for specifying the logical address, the memory controller 300 converts the logical address into a physical address and reads data from the physical address. Then, the memory controller 300 outputs the read data as read data to the host computer 100.

(Power supply unit 500)
The power supply unit 500 supplies a desired voltage to one or a plurality of memory cell array units 400. The power supply unit 500 supplies, for example, a voltage to be used at the time of writing (at the time of setting, resetting) or at the time of reading (at the time of sense) to the wl decoder 112 described later. The power supply unit 500 supplies, for example, a voltage to be used at the time of writing (at the time of setting, resetting) or at the time of reading (at the time of sense) to the bl decoder 113 described later.

(Memory cell array unit 400)
Next, the memory cell array unit 400 will be described. FIG. 2 shows an example of a functional block of the memory cell array unit 400. The memory cell array unit 400 is composed of, for example, a semiconductor chip. The memory cell array unit 400 has, for example, m dies 400-j (1 ≦ j ≦ m) as shown in FIG. For example, as shown in FIG. 3, each die 400-j has z banks 410-k (1 ≦ k ≦ z), a Periphery circuit 420 that controls access to each bank 410-k, and a memory controller. It has an interface circuit 430 that communicates with the 300.

Each bank 410-k has, for example, a memory cell array 10, a microcontroller 20, and an internal power supply unit 30, as shown in FIG. The memory cell array 10 corresponds to a specific example of the "memory cell array" of the present disclosure. The microcontroller 20 corresponds to a specific example of the "microcontroller" of the present disclosure. The internal power supply unit 30 corresponds to a specific example of the “internal power supply unit” of the present disclosure.

The memory cell array 10 has n tiles 10a each having a 1-bit access unit. Note that FIG. 4 illustrates a case where 12 tiles 10a are arranged in 3 rows and 4 columns. The microcontroller 20 controls access to each tile 10a and communicates with the memory controller 300. In each bank 410-k, the microcontroller 20 cooperates with a plurality of tiles 10a to realize access to a data block having a predetermined bit size as a whole. In each bank 410-k, the microcontroller 20 allocates n bits to each bank 410-k from the memory controller 300 for data writing and data reading based on, for example, read / write control from the memory controller 300. Is used to read and write n-bit data to and from the memory cell array 10. In each bank 410-k, the microcontroller 20 accesses an n-bit data block based on, for example, read / write control from the memory controller 300.

The microcontroller 20 realizes a write operation (set operation, reset operation) and a read operation (sense operation) for the memory cell array 10 by inputting various signals to each tile 10a. The set operation refers to passing a set current Issue, which will be described later, to the tile 10a. The reset operation means that a reset current Irst, which will be described later, is passed through the tile 10a.

When a plurality of tiles 10a are arranged in a matrix in relation to the microcontroller 20, the microcontroller 20 sequentially resets the plurality of tiles 10a row by row. At this time, the memory cell array 10 is provided with a reset signal line for each row, and the microcontroller 20 is provided with a reset signal rst (reset signal rst) for a plurality of tiles 10a via the reset signal line provided for each row. For example, it has a level shifter 21 that performs a reset operation by sequentially applying rst1, rst2, and rst3) row by row. For example, the level shifter 21 generates a plurality of reset signals rst (for example, three reset signals rst1, rst2, rst3) that do not overlap each other on the time axis based on the input reset signal, and the set operation is performed. In the meantime, it is applied to the memory cell array 10. The microcontroller 20 performs a write operation (set operation, reset operation) and a read operation (sense operation) by simultaneously applying various control signals (control signal ctl) other than the reset signal rst to each tile 10a. conduct.

The internal power supply unit 30 generates a high-precision internal voltage based on the low-precision power supply voltage supplied from the power supply unit 500, and supplies it to the memory cell array 10. When the plurality of tiles 10a are arranged in a matrix in relation to the microcontroller 20, the internal power supply unit 30 has a plurality of regulators 30a assigned to each predetermined unit row. Note that FIG. 4 illustrates a case where a plurality of regulators 30a are assigned to each of two rows in a plurality of tiles 10a arranged in a matrix. Each regulator 30a is shared by a plurality of tiles 10a provided in the corresponding rows. That is, the memory cell array 10 includes a plurality of tiles 10a that share the regulator 30a.

The regulator 30a has a voltage (first voltage) required to pass a set current Iset to the memory cell MC to be set during the set operation, and a set current Iset to the memory cell MC to be reset during the reset operation. A voltage (second voltage) required to pass a reset current Irst having a peak value larger than the peak value of is generated. The memory cell array 10 is provided with a set of wiring La for connecting the regulator 30a and the plurality of tiles 10a corresponding to the regulator 30a. The set of wiring La includes, for example, a wiring that supplies a voltage (first voltage) to the tile 10a during a write operation (during a set operation and a reset operation), and a tile 10a during a read operation (during a sense operation). Includes wiring and the like to supply a voltage (second voltage). The microcontroller 20 supplies a voltage (first voltage) to each memory cell MC to be set during the set operation, and also supplies a voltage (a voltage (first voltage) to each memory cell MC of the reset elephant during the reset operation. The memory cell array 10 is controlled so that the second voltage) is supplied. The writing operation (set operation, reset operation) will be described in detail later.

In each bank 410-k, the microcontroller 20 allocates n bits to each bank 410-k from the memory controller 300 for data writing and data reading based on, for example, read / write control from the memory controller 300. Is used to read and write n-bit data to and from the memory cell array 10. In each bank 410-k, the microcontroller 20 accesses an n-bit data block based on, for example, read / write control from the memory controller 300.

Each tile 10a has, for example, a memory cell array 111, as shown in FIG. The memory cell array 111 has, for example, a 1-bit memory cell MC at each intersection of the word line wl and the bit line bl. The memory cell MC corresponds to a specific example of the "nonvolatile memory cell" of the present disclosure. The memory cell MC is a writable non-volatile memory. The memory cell MC has a series structure of a resistance changing element VR (Variable Resistor) that records 1-bit information depending on the state of high and low resistance values and a selection element SE (Selector Element) having bidirectional diode characteristics. .. The resistance change element VR is, for example, a phase change memory (PCM).

As shown in FIG. 7, the memory cell array 111 may be composed of two layers of memory cell array 111a and 111b, for example. The memory cells 111a and 111b each have one bit at each intersection of the upper word line uwl and the bit line bl and each intersection of the lower word line lwl and the bit line bl, as shown in FIG. 7, for example. It has a memory cell MC. In the present specification, the word line wl is appropriately used as a general term for the upper word line uwl and the lower word line lwl.

Each tile 11 has, for example, a wl decoder 112, a bl decoder 113, a voltage switch 114, a latch 115 and a sense amplifier (SA) 116, as shown in FIG.

The wl decoder 112 applies a predetermined voltage to each word line wl based on a control signal (word line address) by the microcontroller 20. The wl decoder 112 has, for example, as shown in FIG. 6, a gwl decoder 112a commonly provided for each memory cell MC and an lwl decoder 112b provided one for each memory cell MC. .. In the lwl decoder 112b, the selection element SE2 having a current limiting function and the potential on the word line wl side of the memory cell MC at the time of non-selection are set to a predetermined voltage (for example, the reference potential of the substrate on which the memory cell MC is formed). It is configured to include a transistor TR2 for the purpose. The selection element SE2 is provided in the path through which the current Ic flowing through the memory cell MC flows.

The bl decoder 113 selects one or a plurality of bit line bls from the plurality of bit line bls based on the control signal (bit line address) by the microcontroller 20. As shown in FIG. 6, the bl decoder 113 has, for example, a gbl decoder 113a commonly provided for each memory cell MC and an bl decoder 113b provided one for each memory cell MC. .. The lbl decoder 113b includes a selection element SE1 and a transistor TR1 for setting the potential on the bit line bl side of the memory cell MC to a predetermined voltage (for example, the reference potential of the substrate on which the memory cell MC is formed). Is configured to include.

The voltage switch 114 sets the voltage of the node gwl, gbl to which the selected word line wl and bit line bl are connected based on the control signal Ctl by the microcontroller 20 and the data of the set latch and the reset latch of the latch 115. Switch. The voltage from the regulator 30a is supplied to the voltage switch 114.

The latch 115 has, for example, a write latch that latches the write data WDATA and a sense latch that latches the read data RDATA. The write data WDATA corresponds to one bit of data in the write data input to the bank 410-k. The read data RDATA corresponds to the data for one bit of the read data read from the bank 410-k. The latch 115 further has, for example, a set latch that latches the set data generated by the logical operation by the microcontroller 20 and a reset latch that latches the reset data generated by the logical operation by the microcontroller 20. ..

The microcontroller 20 determines the value of the set latch and the value of the reset latch based on the value of the write latch and the value of the sense latch. For example, when the value of the write latch = the value of the sense latch, the microcontroller 20 does not need a write operation on the tile 10a, so the set latch value and the reset latch value are set to 0. For example, when the value of the light latch = 1 and the value of the sense latch = 0, the microcontroller 20 needs to perform the set operation on the tile 10a. Therefore, the value of the set latch is set to 1 and the value of the reset latch is set to 0. And. For example, when the value of the write latch is 0 and the value of the sense latch is 1, the microcontroller 20 needs to perform a reset operation on the tile 10a. Therefore, the value of the set latch is set to 0 and the value of the reset latch is set to 1. And.

The latch 115 latches the write data WDATA input from the microcontroller 20 to the write latch. The latch 115 latches the read data RDATA input from the sense amplifier 116 to the sense latch, and outputs the value of the sense latch to the microcontroller 20 under the control of the microcontroller 20. The latch 115 latches the set data input from the microcontroller 20 to the set latch, and outputs the set latch value to the voltage switch 114 according to the control by the microcontroller 20. The latch 115 latches the reset data input from the microcontroller 20 to the set latch, and outputs the reset latch value to the voltage switch 114 according to the control by the microcontroller 20.

The sense amplifier 116 compares the voltage of the node gwl obtained from the wl decoder 112 with the reference voltage based on the control signal Ctl by the microcontroller 20, and the resistance changing element VR is in a low resistance state (LRS) or has a high resistance. Determine if it is a state (HRS). The sense amplifier 116 generates logic 0 when the resistance changing element VR is in the low resistance state (LRS), and generates logic 1 when the resistance changing element VR is in the high resistance state (HRS). Generates read data RDATA. The sense amplifier 116 outputs the generated read data RDATA to the latch 115.

[motion]
Next, the operation of the information processing system according to the present embodiment will be described.

The data unit for writing and reading in each bank 410-k is very small with respect to the data unit for the host computer 100 to access the memory cell array unit 400, and is n bits (for example, 12 bits). In order to respond to the request of the host computer 100 (particularly the read request) with the minimum delay, the memory controller 300 distributes the access granularity of the host computer 100 to a plurality of banks 410-k and performs read / write control.

(set)
For the tile 10a, for example, when the set latch is 1 and the reset latch is 0, + 4.5 V is applied to the bit line bl and -3.7 V is applied to the lower word line lwl (see FIG. 8). As a result, the resistance changing element VR of the memory cell MC at the intersection of the lower word line lwl and the bit line bl changes from the high resistance state (HRS) to the low resistance state (LRS). In this way, the memory cell MC is set. For the tile 10a, for example, when the set latch is 0 and the reset latch is 0, 0V is applied to the bit line bl and 0V to 0.8V is applied to the lower word line lwl (see FIG. 8). As a result, the state change does not occur in the memory cell MC at the intersection of the lower word line lwl and the bit line bl.

(reset)
For the tile 10a, for example, when the set latch is 0 and the reset latch is 1, + 4.5 V is applied to the bit line bl and -3.7 V is applied to the lower word line lwl. As a result, the resistance changing element VR of the memory cell MC at the intersection of the lower word line lwl and the bit line bl changes from the low resistance state (LRS) to the high resistance state (HRS). In this way, the memory cell MC is reset.

FIG. 9 shows an example of the waveform of the current flowing through the memory cell MC. Generally, the pattern of write data is arbitrary. Therefore, among the plurality of tiles 10a in the bank 410-k, all of them may be set operation or reset operation, and in the plurality of tiles 10a in bank 410-k, set operation and reset operation are mixed. In some cases. In the present embodiment, in order to shorten the writing time, the controller 20 simultaneously performs a setting operation and a reset operation for each tile 10a based on the writing data input to the bank 410-k.

Specifically, the controller 20 performs a set operation and a reset operation according to the write data and the address data (physical address) input to the bank 410-k. The controller 20 compares, for example, the write data input to the bank 410-k with the state of each tile 10a based on the address data (physical address) input to the bank 410-k. Based on the comparison result, the controller 20 simultaneously performs the set operation (control to flow the set current Iset) for each tile 10a requiring the set operation at the same time in the period Δt1, as shown in FIG. 9, for example. For each tile 10a that requires a reset operation, a reset operation (control to flow a reset current Irst) is sequentially performed for each predetermined unit (for example, a row) within the period Δt1 during which the set operation is performed.

The period Δt1 for performing the set operation is determined by the pulse width of the set current Iset. The period Δt2 for performing the reset operation is determined by the pulse width of the reset current Irst, and is narrower than the pulse width of the set current Iset. For example, in the bank 410-k, when 12 tiles 10a are arranged in 3 rows and 4 columns, the reset operation period Δt2 is less than 1/3 of the set operation period Δt1. Further, the peak value of the reset current Irst is about 2 to 3 times the peak value of the set current Issue. At this time, the maximum load current of the regulator 30a is reduced to 1 / d times when the number of divisions of the reset operation is d, as compared with the case where the reset operation is performed simultaneously for each tile 10a requiring the reset operation. Will be.

(Read (sense) operation)
FIG. 10 shows an example of a read (sense) operation in the memory unit 200. Upon receiving the read command and the logical address, the memory controller 300 converts the logical address into a physical address (bank address, in-bank address), and then transmits the read command and the physical address to the interface circuit 430 (step S11). When the interface circuit 430 receives the read command and the physical address from the memory controller 300, the interface circuit 430 transmits a sense command together with the in-bank address to the microcontroller 20 of the bank 410-k corresponding to the received bank address (step S12).

The microcontroller 20 converts the designated in-bank address into a word line address and a bit line address in the tile 10a, and sets the word line address and the bit line address for each tile 10a (step S13). The microcontroller 20 applies various control signals (control signal ctl) to the memory cell array 10. As a result, the tile 10a applies a read voltage (and current Isns) to each memory cell MC to be read via the word line WL and the bit line BL (step S14, FIG. 9). The microcontroller 20 reads data from each memory cell MC to be read and takes it into the sense latch (step S15).

The interface circuit 430 commands the microcontroller 20 of each bank 410-k to read data at the timing when a predetermined period Δx has elapsed after receiving the read command from the memory controller 300. The predetermined period Δx corresponds to the period from the reception of the read command from the memory controller 300 to the acquisition of data into the sense latch.

In each bank 410-k, the microcontroller 20 reads 1-bit data from the sense latch of each tile 10a according to a command from the interface circuit 430, and transmits the n-bit data obtained thereby to the interface circuit 430. (Step S16). The interface circuit 430 transmits n × k-bit read data consisting of n-bit data obtained from each bank 410-k to the memory controller 300 (step S17). In this way, the read operation is performed.

(Write (set, reset) operation)
FIG. 11 shows an example of a write (set, reset) operation in the memory unit 200. When the memory controller 300 receives the write command, the logical address, and the write data, the memory controller 300 converts the logical address into a physical address (bank address, in-bank address), and then transfers the write command and the physical address to the interface via the command address bus. It is transmitted to the circuit 430 (step S21). At this time, the memory controller 300 transmits the write data to the interface circuit 430 via the data bus (step S22).

When the interface circuit 430 receives a write command, a physical address, and write data from the memory controller 300, the interface circuit 430 sends a write command and an in-bank address to the microcontroller 20 of the bank 410-k corresponding to the received bank address via the command address bus. Is transmitted (step S23). At this time, the interface circuit 430 transmits the write data to the microcontroller 20 of the bank 410-k corresponding to the received bank address via the data bus (step S24). The microcontroller 20 causes the write latch of each tile 10a to hold one bit of the received write data. Subsequently, the microcontroller 20 reads data from each memory cell MC to be written by performing the same operation as in steps S13, S14, and S15 in the read (sense) operation, and captures the data into the sense latch (step S25). ..

Next, the microcontroller 20 performs the following logical operations based on the values held in the write latch and the sense latch in each tile 10a, and determines the values of the set latch and the reset latch (step S26).
1. 1. When the value of the write latch = the value of the sense latch, it is not necessary to perform the writing operation on the tile 10a, so that the microcontroller 20 sets the values of the set latch and the reset latch to 0.
2. 2. When the value of the light latch = 1 and the value of the sense latch = 0, it is necessary to perform the set operation on the tile 10a. Therefore, the microcontroller 20 sets the value of the set latch to 1 and sets the value of the reset latch to 1. Set to 0.
3. 3. When the light latch value = 0 and the sense latch value = 1, it is necessary to perform a reset operation on the tile 10a. Therefore, the microcontroller 20 sets the set latch value to 0 and sets the reset latch value to 0. Set to 1.

Subsequently, the microcontroller 20 applies various control signals (control signal ctl) to the memory cell array 10. As a result, the tile 10a applies a voltage (and current Iset) for setting to the memory cell MC of each tile 10a to be set via the word line WL and the bit line BL (step S27, FIG. 9). ). The microcontroller 20 writes data to each memory cell MC to be set. At this time, the microcontroller 20 has a word line WL and a bit line with respect to the memory cell MC of each tile 10a to be reset while the setting operation is being performed for each memory cell MC to be set. The reset voltage (and current Irst) is sequentially applied in predetermined units (for example, rows) via the BL (step S28, FIG. 9). As a result, the maximum load current of the regulator 30a is reduced to 1 / d times when the number of divisions of the reset operation is d, as compared with the case where the reset operation is performed simultaneously for each tile 10a requiring the reset operation. can do.

[effect]
Next, the effect of the information processing system according to the present embodiment will be described.

In the present embodiment, the set operation is simultaneously performed on the plurality of memory cell MCs to be set, and every predetermined unit within the period during which the set operation is performed on the plurality of memory cell MCs to be reset. The reset operation is sequentially performed. As a result, the maximum load current of the internal power supply unit 30 can be suppressed to a low level as compared with the case where the reset operation is simultaneously performed on the plurality of memory cells MC to be reset. As a result, the voltage drop due to the wiring resistance and the current flowing through the memory cell MC can be suppressed to a low level, so that the malfunction caused by the internal voltage can be suppressed.

In this embodiment, the set operation and the reset operation are performed in response to the input of the write command, the write data, and the address data (logical address). As a result, when writing data to a plurality of memory cell MCs corresponding to the address data in response to the input of one write command, the set operation is simultaneously performed for the plurality of memory cell MCs to be set. At the same time, the reset operation is sequentially performed for each predetermined unit within the period during which the set operation is performed for the plurality of memory cells MC to be reset. As a result, the maximum load current of the internal power supply unit 30 can be suppressed to a low level as compared with the case where the reset operation is simultaneously performed on the plurality of memory cells MC to be reset. As a result, the voltage drop due to the wiring resistance and the current flowing through the memory cell MC can be suppressed to a low level, so that the malfunction caused by the internal voltage can be suppressed.

In the present embodiment, the plurality of memory cell MCs are arranged in a matrix in relation to the microcontroller 20, and the microcontroller 20 sequentially performs a reset operation for each of the plurality of memory cell MCs row by row. Will be. As a result, the maximum load current of the internal power supply unit 30 can be suppressed to a low level as compared with the case where the reset operation is simultaneously performed on the plurality of memory cells MC to be reset. As a result, the voltage drop due to the wiring resistance and the current flowing through the memory cell MC can be suppressed to a low level, so that the malfunction caused by the internal voltage can be suppressed.

In the present embodiment, the voltage required to pass the set current Iset to the memory cell MC during the set operation and the reset of the peak value larger than the peak value of the set current Issue to the memory cell MC during the reset operation. A regulator 30a is provided in the bank 410-k to generate the voltage required to pass the current Irst. Then, the microcontroller 20 supplies the voltage required to flow the set current Iset to each memory cell MC during the set operation, and resets each memory cell MC during the reset operation. The memory cell array 10 is controlled so that the voltage required for passing the current Irst is supplied. As a result, the maximum load current of the internal power supply unit 30 can be kept low by sequentially resetting the plurality of memory cells MC row by row by the microcontroller 20. As a result, the voltage drop due to the wiring resistance and the current flowing through the memory cell MC can be suppressed to a low level, so that the malfunction caused by the internal voltage can be suppressed.

In the present embodiment, each memory cell MC has a series structure of a resistance changing element VR that records 1-bit information depending on the state of high and low resistance values and a selection element SE having bidirectional diode characteristics. .. Thereby, the rewritable memory cell array unit 400 can be realized by controlling the high and low resistance values of the resistance changing element VR by the microcontroller 20.

<2. Modification example>
Next, a modified example of the information processing system according to the above embodiment will be described.

FIG. 12 shows a schematic configuration of a part of the tiles according to the comparative example. For example, as shown in FIG. 12, when + 4.5V is applied to the bit line bl and -3.7V is applied to the word line wl in the memory cell MC in the tile 10a located near the internal power supply unit 30. The memory cell MC is turned on and the cell current Ic reaches 50 μA. Then, the voltage Vwl on the word line wl side of the memory cell MC rises from -3.7V to 1.3V due to the current limiting function of the selection element SE2. When the voltage Vwl on the word line wl side reaches 1.3 V, the parasitic diode in the transistor TR2 is turned on and the current Ia flows to the substrate. Since this current Ia bypasses the selection element SE2, an overcurrent flows in the memory cell MC by that amount, and the voltage drop due to the wiring resistance and the current Ic flowing in the memory cell MC increases. As a result, the load of the regulator 30a increases, which may lead to write failure.

On the other hand, in the above embodiment, for example, as shown in FIG. 13, the path of the current Ic supplied from the internal power supply unit 30a to the memory cell MC in the gbl decoder 113a (hereinafter, “current path α””. A variable resistance circuit Rv may be provided in). In this case, the microcontroller 20 controls the resistance value of the variable resistance circuit Rv by applying the control signal r_b to the variable resistance circuit Rv. The microcontroller 20 is variable, for example, by generating a control signal r_b based on the address data (logical address) input from the memory controller 300 together with the write command, and inputting the generated control signal r_b to the variable resistance circuit Rv. The resistance value of the resistance circuit Rv is controlled. The variable resistance circuit Rv is arranged in the current path α.

The lwl decoder 112b is provided with a selection element SE2 as a specific example of a current limiting circuit that limits an overcurrent in the current path α. The selection element SE2 is arranged in the current path α.

For example, when the memory cell MC corresponding to the address data is provided at a position close to the internal power supply unit 30a, the microcontroller 20 sets the resistance value of the variable resistance circuit Rv in the memory cell MC corresponding to the address data. , It is made larger than the resistance value of the variable resistance circuit Rv in the memory cell MC located at a position away from the internal power supply unit 30a. As a result, in the memory cell MC provided at a position close to the internal power supply unit 30a, the current Ia flowing to the substrate can be reduced. As a result, the load of the regulator 30a is reduced, and the occurrence of write defects can be reduced.

(Write (set, reset) operation)
FIG. 14 shows an example of a write (set, reset) operation in the memory unit 200 according to this modification. Upon receiving the write command, the logical address, and the write data, the memory controller 300 executes steps S21 to 26 in the above embodiment (FIG. 14).

Subsequently, the microcontroller 20 generates a control signal r_b based on the address data (logical address), and inputs the generated control signal r_b to the variable resistance circuit Rv to set the resistance value of the variable resistance circuit Rv to a predetermined value. Set to a value (step S29, FIG. 14). For example, when the memory cell MC corresponding to the address data is provided at a position close to the internal power supply unit 30a, the microcontroller 20 sets the resistance value of the variable resistance circuit Rv in the memory cell MC corresponding to the address data. , It is made larger than the resistance value of the variable resistance circuit Rv in the memory cell MC located at a position away from the internal power supply unit 30a. As a result, in the memory cell MC provided at a position close to the internal power supply unit 30a, the current Ia flowing to the substrate can be reduced. As a result, the load of the regulator 30a is reduced, and the occurrence of write defects can be reduced.

Subsequently, the microcontroller 20 applies various control signals (control signal ctl) to the memory cell array 10. As a result, the tile 10a applies a voltage (and current Iset) for setting to the memory cell MC of each tile 10a to be set via the word line WL and the bit line BL (step S27, FIG. 14). ). The microcontroller 20 writes data to each memory cell MC to be set. At this time, the microcontroller 20 has a word line WL and a bit line with respect to the memory cell MC of each tile 10a to be reset while the setting operation is being performed for each memory cell MC to be set. The reset voltage (and current Irst) is sequentially applied in predetermined units (for example, rows) via the BL (step S28, FIG. 14). As a result, the maximum load current of the regulator 30a is reduced to 1 / d times when the number of divisions of the reset operation is d, as compared with the case where the reset operation is performed simultaneously for each tile 10a requiring the reset operation. can do.

Although the present technique has been described above with reference to the embodiments and examples thereof, the present disclosure is not limited to the above embodiments and the like, and various modifications are possible. The effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than those described herein.

Further, for example, the present disclosure may have the following structure.
(1)
Internal power supply and
A memory cell array including a plurality of writable non-volatile memory cells sharing the internal power supply unit,
A set operation is simultaneously performed on a plurality of first non-volatile memory cells that are a part of the plurality of non-volatile memory cells, and the plurality of first non-volatile memory cells among the plurality of non-volatile memory cells are simultaneously performed. A memory cell array unit including a microcontroller that sequentially resets a plurality of second non-volatile memory cells different from the sex memory cells in predetermined units within the period during which the set operation is performed.
(2)
The memory cell array unit according to (1), which performs the set operation and the reset operation in response to input of a write command, write data, and address data.
(3)
The plurality of non-volatile memory cells are arranged in a matrix in relation to the microcontroller.
The memory cell array unit according to (1) or (2), wherein the microcontroller sequentially performs the reset operation for each of the plurality of second non-volatile memory cells row by row.
(4)
The internal power supply unit uses the first voltage required to pass a set current through the first non-volatile memory cell during the set operation and the second non-volatile memory cell during the reset operation. It has a regulator that produces a second voltage required to carry a reset current with a peak value greater than the peak value of the set current.
The microcontroller supplies the first voltage to each of the first non-volatile memory cells during the set operation, and supplies the first voltage to each of the second non-volatile memory cells during the reset operation. The memory cell array unit according to any one of (1) to (3), which controls the memory cell array so that the third voltage is supplied to the memory cell array.
(5)
Each of the non-volatile memory cells has a series structure of a resistance changing element that records 1-bit information depending on the state of high and low resistance values and a selection element having bidirectional diode characteristics (1) to (4). The memory cell array unit described in one.
(6)
A memory cell array including a plurality of writable non-volatile memory cells and a drive unit for driving the plurality of non-volatile memory cells.
An internal power supply unit that supplies current to the memory cell array,
It is equipped with a microcontroller that controls the drive unit in response to the input of write commands, write data, and address data.
The drive unit
A variable resistance circuit provided in the path of the current supplied from the internal power supply unit to the non-volatile memory cell, and
A memory cell array unit having a current limiting circuit that limits overcurrent in the path.
(7)
The memory cell array unit according to (6), wherein the microcontroller controls the resistance value of the variable resistance circuit based on the address data.
(8)
The memory cell array unit according to (6) or (7), wherein the variable resistance circuit and the current limiting circuit are arranged in the path.
(9)
Each of the non-volatile memory cells has a series structure of a resistance changing element that records 1-bit information depending on the state of high and low resistance values and a selection element having bidirectional diode characteristics (6) to (8). The memory cell array unit described in one.

In the memory cell array unit according to the first aspect of the present disclosure, a set operation is simultaneously performed on a plurality of first non-volatile memory cells, and a set operation is performed on a plurality of second non-volatile memory cells. The reset operation is sequentially performed for each predetermined unit within the performing period. As a result, the maximum load current of the internal power supply unit can be suppressed to a low level as compared with the case where the reset operation is simultaneously performed on the plurality of second non-volatile memory cells. As a result, the voltage drop due to the wiring resistance and the current flowing through the non-volatile memory cell can be suppressed to a low level, so that the malfunction caused by the internal voltage can be suppressed. The effects of the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described herein.

In the memory cell array unit according to the second aspect of the present disclosure, a variable resistance circuit provided in the path of the current supplied from the internal power supply unit to the non-volatile memory cell is used to input write commands, write data, and address data. It is controlled according to. Thereby, for example, it is possible to adjust the resistance value of the variable resistance circuit according to the positional relationship of the non-volatile memory cell to be written with the internal power supply unit. As a result, the current flowing through each non-volatile memory cell to be written becomes more uniform as compared with the case where the variable resistance circuit is not provided, so that the malfunction caused by the internal voltage can be suppressed. The effects of the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described herein.

10 ... Memory cell array, 10a ... Tile, 20 ... Microcontroller, 21 ... Level shifter, 30 ... Internal power supply unit, 30a ... Regulator, 100 ... Host computer, 111, 111a, 111b ... Memory cell array, 112 ... wl decoder, 112a ... gwl Decoder, 112b ... lwl decoder, 113 ... bl decoder, 113a ... gbl decoder, 113b ... lbl decoder, 114 ... voltage switch, 115 ... latch, 116 ... sense amplifier, 200 ... memory unit, 300 ... memory controller, 400 ... memory cell array Unit, 400-1,400-2,400-j, 400-m ... Die, 410-1,410-2, 410-k, 410-z ... Bank, 420 ... Periphery circuit, 430 ... Interface circuit, 500 ... Power supply unit, ctl ... control signal, Ic ... cell current, lbl ... lower bit line, Irst, Irst1, Irst2, Irst3 ... reset current, Iset ... set current, Isns ... sense current, lwl ... lower word line, MC ... memory cell , Rv ... variable resistance circuit, r_b ... control signal, SE, SE1, SE2 ... selection element, TR1, Tr2 ... transistor, ubl ... upper bit line, uwl ... upper word line, Vwl ... word line voltage, Vbl ... bit line voltage , VR ... Resistance changing element.

Claims (9)

Internal power supply and
A memory cell array including a plurality of writable non-volatile memory cells sharing the internal power supply unit,
A set operation is simultaneously performed on a plurality of first non-volatile memory cells that are a part of the plurality of non-volatile memory cells, and the plurality of first non-volatile memory cells among the plurality of non-volatile memory cells are simultaneously performed. A memory cell array unit including a microcontroller that sequentially resets a plurality of second non-volatile memory cells different from the sex memory cells in predetermined units within the period during which the set operation is performed. The memory cell array unit according to claim 1, wherein the set operation and the reset operation are performed in response to input of a write command, write data, and address data. The plurality of non-volatile memory cells are arranged in a matrix in relation to the microcontroller.
The memory cell array unit according to claim 1, wherein the microcontroller sequentially performs the reset operation for each of the plurality of second non-volatile memory cells row by row. The internal power supply unit uses the first voltage required to pass a set current through the first non-volatile memory cell during the set operation and the second non-volatile memory cell during the reset operation. It has a regulator that produces a second voltage required to carry a reset current with a peak value greater than the peak value of the set current.
The microcontroller supplies the first voltage to each of the first non-volatile memory cells during the set operation, and supplies the first voltage to each of the second non-volatile memory cells during the reset operation. The memory cell array unit according to claim 1, wherein the memory cell array is controlled so that the third voltage is supplied to the memory cell array. The memory cell array unit according to claim 1, wherein each of the non-volatile memory cells has a series structure of a resistance changing element that records 1-bit information depending on the state of high and low resistance values and a selection element having bidirectional diode characteristics. .. A memory cell array including a plurality of writable non-volatile memory cells and a drive unit for driving the plurality of non-volatile memory cells.
An internal power supply unit that supplies current to the memory cell array,
It is equipped with a microcontroller that controls the drive unit in response to the input of write commands, write data, and address data.
The drive unit
A variable resistance circuit provided in the path of the current supplied from the internal power supply unit to the non-volatile memory cell, and
A memory cell array unit having a current limiting circuit that limits overcurrent in the path. The memory cell array unit according to claim 6, wherein the microcontroller controls a resistance value of the variable resistance circuit based on the address data. The memory cell array unit according to claim 6, wherein the variable resistance circuit and the current limiting circuit are arranged in the path. The memory cell array unit according to claim 6, wherein each non-volatile memory cell has a series structure of a resistance changing element that records 1-bit information depending on the state of high and low resistance values and a selection element having bidirectional diode characteristics. ..

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