JP2022089289A - Optical node device - Google Patents

Abstract

To provide an optical node device that can prevent burn-in to increase reliability.SOLUTION: A plurality of pixels Pix3 of a spatial light modulator of an optical node device each comprises: a first switching circuit SW13 and a first signal holding circuit SM13 that sample and hold forward rotation gradation data or reverse rotation gradation data; a second switching circuit SW21 and a second signal holding circuit DM21 that sample the forward rotation gradation data or the reverse rotation gradation data held by the first signal holding circuit at timing common to all of the plurality of pixels and hold the data for one sub-frame period and apply the data to a reflecting electrode PE. The first switching circuit and the first signal holding circuit constitute a first static random access memory 111. The second switching circuit and the second signal holding circuit constitute a first dynamic random access memory 121. The second signal holding circuit is constituted by a capacity C1.SELECTED DRAWING: Figure 12

Description

The present invention relates to an optical node device.

Optical networks are used to support modern demand for high-speed, high-capacity telecommunications. These networks utilize as much optical spectrum as possible, commonly using a technique known as wavelength division multiplexing (WDM).

In many optical networks, optical node devices corresponding to the branch points of the optical network are used. It is often desirable to use reconfigurable optical add-drop multiplexer (ROADM) devices with reconfigurable add / drop capabilities in optical node appliances.

To implement a ROADM system, a wavelength selection switch (WSS) may be used for routing any wavelength channel. In WSS, a light beam deflection device such as a spatial light modulator may be used to select the wavelength for deflection to the desired output port. WSS, which uses a reflective spatial light modulator, is currently in use.

Japanese Patent No. 5733154

In the above-mentioned reflection type spatial light modulator, it is desirable that seizure can be suppressed in order to improve reliability.

In view of the above problems, it is an object of the present invention to provide an optical node device capable of increasing reliability.

The optical node device according to one aspect of the present invention has an input / output unit having an input port for incident light and an output port for emitting emitted light corresponding to each wavelength included in the incident light, and the input / output unit. A wavelength disperser that spatially disperses the light of each wavelength contained in the emitted light according to each wavelength and emits the emitted light to the input / output unit side, and the light of each wavelength dispersed by the wavelength disperser. Is focused on a two-dimensional plane for each wavelength and emits the reflected light of each wavelength to the side of the wavelength disperser, and is arranged at the position of the two-dimensional plane and has a plurality of pixels. A spatial optical modulator that reflects the light of each wavelength focused by the optical coupler in a direction determined by routing for each wavelength by expressing the gradation by the plurality of pixels, and the space. It includes a spatial optical modulator driving unit that drives the plurality of pixels of the optical modulator. For the gradation, forward rotation gradation data is input to each of the plurality of pixels by the spatial light modulator drive unit in one subframe period of the plurality of subframe periods in which one frame period is divided. , Is formed by inputting inverted gradation data in the other one subframe period of the plurality of subframe periods. Each of the plurality of pixels has a first switching circuit that samples the normal rotation gradation data or the inversion gradation data from a data line, and the forward rotation gradation data or the inversion sampled by the first switching circuit. The first signal holding circuit for holding the gradation data and the normal rotation gradation data or the inverted gradation data held in the first signal holding circuit are sampled at a timing common to all of the plurality of pixels. The second switching circuit and the forward rotation gradation data or the inversion gradation data sampled by the second switching circuit are held for one subframe period, and are applied to the reflection electrode of the liquid crystal display element and the second signal. It is equipped with a holding circuit. The spatial light modulator drive unit applies a positive / negative AC voltage to the liquid crystal of the liquid crystal display element by inverting the voltage of the common electrode of the liquid crystal display element at the timing, and the forward rotation gradation data and the said. A voltage having an amplitude different from that of the inverted gradation data is supplied to the common electrode. The first switching circuit and the first signal holding circuit constitute a first static random access memory. The second switching circuit and the second signal holding circuit constitute a first dynamic random access memory. The second signal holding circuit is composed of a capacitance.

According to the present invention, it is possible to increase the reliability.

FIG. 1 is a diagram showing a configuration of a wavelength selection switch array according to the first embodiment. FIG. 2 is a diagram showing a configuration of a wavelength selection switch array according to the first embodiment. FIG. 3 is a diagram showing a reflective liquid crystal display device of the wavelength selection array of the first embodiment. FIG. 4 is a diagram showing a configuration of a reflective liquid crystal display device according to a second embodiment. FIG. 5 is a diagram showing a pixel configuration of the reflective liquid crystal display device according to the second embodiment. FIG. 6 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the third embodiment. FIG. 7 is a diagram showing a circuit configuration of a CMOS inverter. FIG. 8 is a diagram illustrating the magnitude relationship of the driving force between the inverters. FIG. 9 is a timing diagram showing the operation of the reflective liquid crystal display device according to the third embodiment. FIG. 10 is a diagram showing the relationship between the applied voltage of the liquid crystal display and the gray scale value. FIG. 11 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the fourth embodiment. FIG. 12 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the fifth embodiment. FIG. 13 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the fifth embodiment. FIG. 14 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the sixth embodiment. FIG. 15 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the sixth embodiment. FIG. 16 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the seventh embodiment. FIG. 17 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the seventh embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below. In addition, the components in the following embodiments include those that can be easily replaced by those skilled in the art, or those that are substantially the same.

<First Embodiment>
1 and 2 are diagrams showing the configuration of a wavelength selection switch (WSS) array according to the first embodiment. FIG. 1 is a view of the WSS array 10 in a direction opposite to the x-axis direction. FIG. 2 is a view of the WSS array 10 in the direction opposite to the y-axis direction.

The WSS array 10 corresponds to an example of the "optical node device" of the present disclosure.

The WSS array 10 of the present disclosure uses at least two WSSs in a single package. The WSS array 10 of the present disclosure enables independent operation of each WSS within the WSS array 10 without the need for a dedicated optical element. On the contrary, many of the optics can be shared between individual WSS devices, thus reducing costs and miniaturization. Such devices are ideally suitable for use in modern communication networks, for example as reconfigurable optical add-drop multiplexers (ROADMs). In addition, an array with two combined WSSs, one or more, may ideally be suitable as a component within a branch node using the root and select (RS) architecture.

Referring to FIG. 1, the WSS array 10 includes two independent WSS devices WSS1 and WSS2, each of which can operate as an independent WSS device. In the present disclosure, the term "independent" refers to the function of the WSS device WSS1 to independently process one or more WDM signals independently of the WSS device WSS2 and vice versa. In the present disclosure, the term "processing" is used broadly, for example, to modulate, attenuate, block, redirect, and / or redirect the individual wavelength channels that make up each WDM signal. Including switching.

The WSS array 10 includes an input / output unit 11 and an optical system 12. The optical system 12 is configured to beam-shape each WDM signal beam. Further, the optical system 12 is configured to spectrally disperse (multiplex) the respective WDM signals into the wavelength channels (or groups of wavelength channels) constituting them. Further, the optical system 12 is configured to spectrally couple (multiplex) the dispersed wavelength channels (or groups of wavelength channels) to one or more WDM signals. Further, the WSS array 10 includes a reflective liquid crystal display device 13. The reflective liquid crystal display device 13 is configured to optically process the dispersed wavelength channels, for example, to redirect individual wavelength channels along a predetermined path within the WSS array 10.

The reflective liquid crystal display device 13 corresponds to an example of the "spatial light modulator" of the present disclosure. The reflective liquid crystal display device 13 will be described in detail in the second and subsequent embodiments.

The WSS array 10 uses a symmetric architecture with respect to the axis of symmetry 14, so that the single optical system 12 and the reflective liquid crystal display device 13 can be combined with several WSS devices of the WSS array 10, in this example the WSS device WSS1 and. Make it sharable between WSS2. However, while the WSS devices WSS1 and WSS2 can share many of the same optics, the architecture of the first embodiment is that the WSS devices WSS1 and WSS2 of the WSS array 10 are independently controllable devices. Enables. Therefore, the WSS array 10 of the first embodiment is miniaturized and the optical complexity is reduced. In addition, the WSS array 10 provides a multi-WSS device that retains the independent processing power inherent in larger and more costly devices.

In the present disclosure, the input / output unit 11 may include several input ports and output ports for transmitting one or more optical WDM signals. For example, the device may include several optical fibers, planar waveguides, etc., all of which may be assigned as input or output ports. In the first embodiment described below, the input port or output port is implemented as an optical fiber 15. However, any other type of port can be used without departing from the scope of the invention.

The input / output unit 11 includes an input / output unit 11-1 for the WSS device WSS1. The input / output unit 11-1 includes an input fiber 1 and some output fibers 1a, 1b, ..., 1n. Here, n is a natural number. The input / output unit 11 further includes an input / output unit 11-2 for the WSS device WSS2. The input / output unit 11-2 includes an input fiber 2 and some output fibers 2a, 2b, ..., 2n. Here, n is a natural number. Therefore, FIG. 1 shows an array of two 1 × N WSS devices including WSS devices WSS1 and WSS2 as an example. In other words, the input / output unit 11 of the WSS array 10 has input fibers 1, output fibers 1a, 1b, ..., 1n, input fibers 2, and output fibers 2a forming an optical fiber stack arranged along the y-axis direction. 2b, ..., Including an array of 2n.

The input / output unit 11 further includes an array of collimating lenses 16 in the form of a microlens array. The array of collimating lenses 16 is arranged in front (z direction) of an array of corresponding optical power elements, for example, each of which is an output portion and / or an input portion of an optical fiber. In the present disclosure, the collimating lens 16 includes any optical element capable of guiding and / or reorienting the light beam and / or condensing a set of rays. The first group including the input fiber 1, the output fibers 1a, 1b, ..., 1n is combined with the first group of the paired collimating lenses 16 to form the input / output unit 11-1 of the WSS device WSS1. Form. The second group including the input fiber 2, the output fibers 2a, 2b, ..., 2n is combined with the second group of the paired collimating lens 16 to form the input / output unit 11-2 of the WSS device WSS2. Form. Although FIG. 1 shows a WSS array 10 mounted as a microlens array, other types of WSS arrays can also be used without departing from the scope of the invention.

In the present disclosure, for example, the optical axis of the optical fiber of the first group is displaced with respect to the optical axis of the collimating lens 16 of the first group. Due to this relative positional deviation between the array of input and output ports and the array of collimating lenses 16, the input and output beams of the first group are optical at an angle θ1 with respect to the axis of symmetry 14. It is sent so as to enter (or exit from) the system 12. As a result, the group of the input beam and the output beam from the WSS device WSS1 is transmitted along the angle θ1 in the descending direction (opposite to the y-axis direction) as a whole.

Similarly, the optical axis of the second group of fibers is displaced with respect to the optical axis of the second group of collimating lenses 16. The input beam and the output beam of the second group are sent so as to enter the optical system 12 (or exit the optical system 12) at an angle θ2 with respect to the axis of symmetry 14. As a result, the group of the input beam and the output beam from the WSS device WSS2 is transmitted along the angle θ2 in the ascending direction (y-axis direction) as a whole.

As mentioned earlier, an exemplary example shown in FIG. 1 is a WSS array 10 using two 1 × N WSSs, namely WSS devices WSS1 and WSS2. Therefore, in the example shown in FIG. 1, the WSS device WSS 1 includes one input fiber 1 that causes the WDM signal beam 31 to be incident on the device, and also includes one input fiber 2 that causes the WDM signal beam 32 to be incident on the device. The input fiber / output fiber configuration shown herein is provided for purposes of illustration only and is not intended to limit the scope of the present invention. Rather, any useful input / output port combination can be used without departing from the scope of the invention.

The WDM signal beam 31 is sent from the input fiber 1 to the device, passes through the collimating lens 16, and then travels through the optical system 12 in the yz plane at an angle θ1. The WDM signal beam 31 is then incident on the lens 21 for shaping the WDM signal beam 31 in the x direction. In one example, the lens 21 may be a cylindrical lens in which the cylindrical axis extends along the y direction. Therefore, the lens 21 does not affect the WDM signal beam 31 when viewed from the viewpoint as shown in FIG.

The WDM signal beam 31 passes through the lens 21 and then enters the lens 22. In the example shown in FIG. 1, the lens 22 may be a cylindrical lens in which the cylindrical axis extends along the x direction. The action of the lens 22 depends on the reflective liquid crystal display device 13 positioned on the focal plane of the lens 22. Further, the center (cylindrical axis) of the lens 22 is on the axis of symmetry 14. Since the reflective liquid crystal display device 13 is positioned on the focal plane of the lens 22, any set of parallel rays entering the lens 22 will be focused at the same height on the reflective liquid crystal display device 13. Conversely, any set of rays starting at the same height on the reflective liquid crystal display device 13 will exit the lens 22 as a set of parallel rays.

For example, as shown in FIG. 1, any incident beam (for example, WDM signal beam 31) traveling along the angle θ1 is directed by the lens 22 toward the position LC1 in the y-axis direction on the reflective liquid crystal display device 13. Directed to. On the contrary, the group of light rays 41 starting from the position LC1 on the reflective liquid crystal display device 13 exits the lens 22 as parallel rays traveling at the same angle θ1 as shown in FIG. Similarly, any incident beam traveling along the angle θ2 (eg, the WDM signal beam 32) is directed by the lens 22 toward position LC2 in the y-axis direction on the reflective liquid crystal display device 13. On the contrary, the group of light rays 42 starting from the position LC2 on the reflective liquid crystal display device 13 exits the lens 22 as parallel light rays traveling at the same angle θ2 as shown in FIG.

Returning to the propagation of the WDM signal beam 31 through the optical system 12, after passing through the lens 22, the WDM signal beam 31 angularly disperses the wavelength channel of the WDM signal beam 31 as shown in FIGS. 1 and 2. It passes through the dispersion element 24 to be made to pass. In the present disclosure, the dispersion element 24 may be a transmission type optical component such as a diffraction grating or a prism.

The dispersion element 24 corresponds to an example of the "wavelength disperser" of the present disclosure.

The dispersed wavelength channels pass through the dispersion element 24, and then, as shown in FIGS. 1 and 2, the lens 23 condenses the dispersed wavelength channels on the surface of the reflective liquid crystal display device 13 for each wavelength channel. Pass through. In the present disclosure, the lens 23 may be a cylindrical lens.

The lens 23 corresponds to an example of the "optical coupler" of the present disclosure.

The reflective liquid crystal display device 13 is a two-dimensional pixelated optical element, for example, a pixelated spatial light modulator. A two-dimensional pixelated optic is one of the dispersed wavelength channels such that one or more of the dispersed wavelength channels are routed to any one of the output fibers, as described in more detail below. Or it can reflect more than one, or it can be redirected.

Regarding the WSS device WSS1, according to the present disclosure, since there is a lens 22, all the light rays starting from the position LC1 on the reflective liquid crystal display device 13 are output from the lens 22 along the angle θ1 as shown in FIG. Will be done. However, all the light rays starting from the position LC1 on the reflective liquid crystal display device 13 are displaced with respect to each other by an amount corresponding to the deflection angle from the reflective liquid crystal display device 13. Therefore, if the deflection angle is set appropriately, the reflected output light beam can be routed to any output fiber among the output fibers 1a, 1b, ..., 1n. Here, the reflected output ray is, for example, a reflected output ray corresponding to a group of rays 41, each of which may contain one or more of the wavelength channels of the WDM signal beam 31. Further, in the present disclosure, each of the collimating lenses 16 is displaced by the same amount with respect to its corresponding output fiber, so that the individual output beams are relocated to their respective output fibers with improved efficiency. It is possible to be combined.

Similarly, with respect to the WSS device WSS2, according to the present disclosure, since there is a lens 22, all the light rays starting from the position LC2 on the reflective liquid crystal display device 13 are all along the angle θ2 as shown in FIG. Is output from. However, all the light rays starting from the position LC2 on the reflective liquid crystal display device 13 are displaced with respect to each other by an amount corresponding to the deflection angle from the reflective liquid crystal display device 13. Therefore, if the deflection angle is set appropriately, the reflected output rays can be routed to any of the output fibers 2a, 2b, ..., 2n. Here, the reflected output ray is, for example, a reflected output ray corresponding to a group of rays 42, each of which may contain one or more of the wavelength channels of the WDM signal beam 32. Further, in the present disclosure, each of the collimating lenses 16 is displaced by the same amount with respect to its corresponding output fiber, so that the individual output beams are relocated to their respective output fibers with improved efficiency. It is possible to be combined.

Therefore, the combination of the input / output unit 11 and the lens 22 emits a given set of beams along a given angle (for example, the angle θ1 in the case of the WSS device WSS1 and the angle θ2 in the case of the WSS device WSS2). .. The combination of the input / output unit 11 and the lens 22 then directs these beams toward positions (position LC1 and position LC2) on the reflective liquid crystal display device 13 that depends only on the input angle, the WSS array device. Bring. Therefore, the WSS array 10 is an optical system 12 and a reflective liquid crystal display device having the same two sets of WDM signal beams 31 and 32 from WSS devices WSS1 and WSS2, or rays 41 and 42 to WSS devices WSS1 and WSS2. Allows 13 to be shared. On the other hand, the WSS array 10 at the same time retains the ability of the WSS array to process the individual wavelength channels separately.

Referring to FIG. 2, the stack of fibers and microlenses constituting the input / output section 11 is observed from above the fiber stack, so that only the input fiber 1 is visible with its corresponding collimating lens 16. The following description focuses on the WSS device WSS1, but due to the symmetry of the system, the exact same description applies to the WSS device WSS2.

As mentioned above, in the case of the WSS device WSS1, the WDM signal beam 31 is incident on the system via the input fiber 1. In FIG. 2, the angle θ1 is invisible because it is in the direction of entering the inner side of the paper surface. In the present disclosure, the WDM signal beam 31 includes several wavelength channels, which have a wavelength range from the longest wavelength λ1 to the shortest wavelength λn. In some examples, the number of wavelength channels may be large, for example 96 wavelength channels with intervals of 50 GHz or 100 GHz on a fixed grid. In another example, the device can use frequency intervals of, for example, 12.5 GHz and can be used in adaptive grid systems with 97 or more wavelength channels, such as 130 or more wavelength channels.

The WDM signal beam 31 first incidents on the lens 21. The lens 21 functions to extend the beam on the dispersion element 24 to a diameter suitable for achieving the desired beam size. For example, the collimating lens 16 and the lens 21 may function as a beam expansion telescope. In the present disclosure, the dispersion element 24 functions to angularly disperse the wavelength channel of the WDM signal beam 31 in the x-axis direction, as shown in FIG. Each of the wavelength channels 51 to 5n is angularly dispersed in the x-axis direction by the dispersion element 24, and then condensed on the surface of the reflective liquid crystal display device 13 by the lens 23. As a result, the wavelength channels 51 to 5n are spatially dispersed in the wavelength dispersion direction (x-axis direction) on the reflective liquid crystal display device 13 according to the wavelength.

FIG. 3 is a diagram showing a reflective liquid crystal display device of the WSS array according to the first embodiment. FIG. 3 is a view of the reflective liquid crystal display device 13 as viewed from the z-axis direction.

An example of the distribution of wavelength channels on the surface of the reflective liquid crystal display device 13 is shown more clearly in FIG. More generally, the wavelength channels may be arranged on the two-dimensional surface of the reflective liquid crystal display 13 as long strips or elliptical spots. Briefly, the wavelength channel is treated as a discrete wavelength signal that can be acted upon independently by the reflective liquid crystal display device 13. However, in the present disclosure, the reflective liquid crystal display device 13 is not limited to acting on an individual wavelength channel, and may act on a group of wavelength channels. Moreover, as shown in FIG. 3, the wavelength channel or group of wavelength channels does not have to have a fixed bandwidth in itself. This is because the reflective liquid crystal display device 13 can be implemented as a dynamically and fully reconfigurable spatial light modulator. Accordingly, the present disclosure may be implemented in the current fixed grid architecture and / or in the current or future developed highly adaptable grid architecture.

Referring to FIG. 2 again, the reflective liquid crystal display device 13 selectively redirects one or more of the wavelength channels 51 to 5n in a certain direction. Then, the reflective liquid crystal display device 13 has one or a plurality of output ports (for example, one or a plurality of outputs on the back side of the paper in FIG. 2) for the selected one or a plurality of wavelength channels 51 to 5n. It can be redirected towards the fiber (see Figure 1)). In the case shown in FIG. 2, the direction change achieved by the reflective liquid crystal display device 13 is performed along an angle located in a plane (yz plane) orthogonal to the paper surface. Wavelength channels 51 to 5n are redirected, for example, as shown and described in more detail above with reference to FIG. The redirected wavelength channels 51 to 5n are reflected by the reflective liquid crystal display device 13, then incident again on the lens 23, further redirected to reach the dispersion element 24, and recombined in the dispersion element 24. To. For example, those wavelength channels 51 to 5n that are redirected along the same angle are recombinated into a single beam that can then output the processed signal at one of the output ports. Turns along the possible directions.

For example, consider a WDM signal beam 31 containing three WDM channels having wavelengths λ1, λ2 and λ3 and channel bandwidths δλ1, δλ2 and δλ3, respectively. In the example shown in FIG. 1, the WDM signal beam 31 enters the system at an angle θ1. Further, the WDM signal beam 31 traveling at the angle θ1 passes through the center of the lens 22 and is not deflected from the angle θ1 and is not deflected. After passing through the dispersion element 24, the three wavelength channels of the WDM signal beam 31 are angularly dispersed in an orthogonal plane (x-z plane), while all of the angularly dispersed channels are at an angle θ1. Still going on. These three dispersed wavelength channels are then focused by the lens 23 at different locations on the reflective liquid crystal display device 13, as shown in FIG.

With respect to the routing capabilities of the device, several different routing combinations are possible here. For example, consider the case where all three wavelength channels are desired to be routed to the output fiber 1n shown in FIG. The corresponding portion of the reflective liquid crystal display device 13 is a wavelength channel of wavelengths λ1, λ2 and λ3 so that the wavelength channels of wavelengths λ1, λ2 and λ3 each return along one of the rays 41 shown in FIG. Bias each one. The action of the dispersion element 24 on the return path for these wavelength channels is to recombine (multiplex) each of the wavelength channels so that they are the same beam that is currently propagating. The coupled beam is then redirected by the lens 22 to have an angle θ1 and propagates along the now displaced output beam 31c from the WDM signal beam 31. The action of the collimating lens 16 is to couple the recombined and redirected output beam 31c to the output fiber 1n. Thus, in this mode of operation, the action of the WSS device WSS1 is to pass all three wavelength channels of the WDM signal beam 31 from the input fiber 1 to the output fiber 1n.

In another example, it may be desirable to route some of the wavelength channels separately to different output fibers. For example, in some cases, the reflective liquid crystal display device 13 deflects the wavelength channel of wavelength λ1 along the output beam 31a, deflects the wavelength channel of wavelength λ2 along the output beam 31b, and deflects the wavelength channel of wavelength λ2 along the output beam 31c. It deflects the wavelength channel of wavelength λ3. Again, the action of the dispersion element 24 is to turn each of these output beams. However, in this case, the dispersion element 24 does not recombin the output beams into a single beam, but generates three output beams that spread and travel in a fan shape. Further, since each of these output beams starts at the same y-axis position LC1 on the reflective liquid crystal display 13, these output beams propagate along the same angle θ1 as the original WDM signal beam 31. It is emitted from the lens 22 as a set of parallel rays. However, since each output beam is incident on the lens 22 at a different height (different position in the y-axis direction), the output beams are displaced from each other. Thereby, for example, the wavelength channel of wavelength λ1 propagates along the output beam 31a, the wavelength channel of wavelength λ2 propagates along the output beam 31b, and the wavelength channel of wavelength λ3 propagates along the output beam 31c. It will propagate. Therefore, in this configuration, the action of the WSS device WSS1 is to route the wavelength channel of wavelength λ1 from the input fiber 1 to the output fiber 1a. The action of the WSS device WSS1 is to route the wavelength channel of wavelength λ2 from the input fiber 1 to the output fiber 1b. The action of the WSS device WSS1 is to route the wavelength channel of wavelength λ3 from the input fiber 1 to the output fiber 1n.

Considering the above, it is clear that the WSS array 10 of the present disclosure allows any wavelength channel of the WDM signal beam to be routed to any output fiber of the output fibers as needed. Further, due to the symmetry of the system shown in FIG. 1, the above description also applies to routing the WDM signal beam 32 using the WSS device WSS2. This is because, as shown in FIG. 3, the dispersed wavelength channels of the WSS devices WSS1 and WSS2 are finally focused on different parts of the reflective liquid crystal display device 13, respectively. Further, in the examples shown in FIGS. 1 to 3, one input port and n output ports are used, but the output ports can be reconfigured as input ports, and vice versa. Will be understood. Furthermore, any number of input and output ports can be used without departing from the scope of the invention. Similarly, an example explicitly shown in FIGS. 1 to 3 is a WSS array 10 using two WSS devices WSS1 and WSS2, but without departing from the scope of the invention, any number of WSS devices. Can be used. For example, if the I / O unit 11 is designed to use four separate delivery angles, the WSS array 10 may provide four independent WSS devices.

<Second embodiment>
FIG. 4 is a diagram showing a configuration of a reflective liquid crystal display device according to a second embodiment.

The reflective liquid crystal display device 13 uses a subframe drive system as the halftone display system. In the subframe drive method, which is a type of time axis modulation method, a predetermined period (for example, in the case of a moving image, one frame period, which is a display unit of one image) is divided into a plurality of subframe periods, and the floor to be displayed is displayed. Pixels are driven by a combination of subframes according to the key. The displayed gradation is determined by the ratio of the driving period of the pixel to the predetermined period, and this ratio is determined by the combination of subframes.

The reflective liquid crystal display device 13 includes an image display unit 61 in which a plurality of pixels Pix are regularly arranged, a timing generator 62, a vertical shift register 63, a data latch circuit 64, and a horizontal driver 65. The horizontal driver 65 includes a horizontal shift register 65a, a latch circuit 65b, and a level shifter / pixel driver 65c.

The timing generator 62, the vertical shift register 63, the data latch circuit 64, and the horizontal driver 65 correspond to an example of the “spatial light modulator drive unit” of the present disclosure.

The row scanning lines g1 to gm of m lines (m is a natural number of 2 or more) extend in the row direction (x direction), and one end of each is connected to the vertical shift register 63. In addition to the row scanning lines g1 to gm, the inverted row scanning lines gb1 to gbm may be provided. n (n is a natural number of 2 or more) column data lines d1 to dn extend in the column direction (y direction), and one end of each is connected to the level shifter / pixel driver 65c. In addition to the column data lines d1 to dn, the inverted column data lines db1 to dbn may be provided.

The image display unit 61 has a plurality of pixels Pix provided at each intersection where the row scanning lines g1 to gm and the column data lines d1 to dn intersect. That is, the plurality of pixels Pix are arranged in a two-dimensional matrix.

All the pixels Pix in the image display unit 61 are commonly connected to the trigger line trig whose one end is connected to the timing generator 62. In addition to the trigger line trig, an inversion trigger line trigb may be provided.

The forward (non-inverting) row scanning pulse transmitted from the row scanning lines g1 to gm and the inverted row scanning pulse transmitted from the inverted row scanning lines gb1 to gbm always have an inverse logic value relationship (complementary relationship). )It is in.

Further, the forward rotation (non-inverted) data transmitted from the column data lines d1 to dn and the inverted data transmitted from the inverted column data lines db1 to dbn always have an inverse logic value relationship (complementary relationship). be.

Further, the forward rotation trigger pulse TRIG transmitted by the trigger line trig and the reverse rotation trigger pulse TRIGB transmitted by the reverse trigger line trigb are always in an inverse logic value relationship (complementary relationship).

The timing generator 62 receives an external signal such as a vertical synchronization signal Vst, a horizontal synchronization signal Hst, and a basic clock signal CLK from the host device 71 as an input signal. The timing generator 62 is an internal signal such as an AC signal FR, a vertical start pulse VST, a horizontal start pulse HST, a clock signal VCK and HCK, a latch pulse LT, a forward rotation trigger pulse TRIG, and an inverting trigger pulse TRIGB based on an external signal. To generate.

The AC signal FR is a signal whose polarity is inverted for each subframe, and is supplied to the common electrode of the liquid crystal element in the pixel Pix constituting the image display unit 61 as a common electrode voltage Vcom described later. The vertical start pulse VST is a pulse signal output at the start timing of each subframe described later, and the switching of subframes is controlled by the vertical start pulse VST. The horizontal start pulse HST is a pulse signal output at the start timing input to the horizontal shift register 65a. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 63, and the vertical shift register 63 performs a shift operation at the timing of the clock signal VCK. The clock signal HCK is a shift clock in the horizontal shift register 65a, and is a signal for shifting data with a width of 32 bits.

The latch pulse LT is a pulse signal output at the timing when the horizontal shift register 65a finishes shifting the data corresponding to the number of pixels in one row in the horizontal direction. The timing generator 62 supplies the forward rotation trigger pulse TRIG through the trigger line trig and the reverse rotation trigger pulse TRIGB through the reverse rotation trigger line trigb to all the pixels Pix in the image display unit 61. The forward rotation trigger pulse TRIG and the reverse rotation trigger pulse TRIGB are output immediately after writing data to the first signal holding circuit (described later) in each pixel Pix in the image display unit 61 within the subframe period. The forward rotation trigger pulse TRIG and the reverse rotation trigger pulse TRIGB use the data of the first signal holding circuit (described later) of all the pixel Pix in the image display unit 61 within the output subframe period as the second signal in the same pixel Pix. It is a signal to be transferred to the holding circuit (described later) at once.

The vertical shift register 63 transfers the vertical start pulse VST supplied at the beginning of each subframe according to the clock signal VCK. Further, the vertical shift register 63 sequentially and exclusively supplies a normal rotation scanning pulse for the row scanning lines g1 to gm and an inverted row scanning pulse for the inverted row scanning lines gb1 to gbm in 1H units. do. The vertical shift register 63 supplies a forward scan pulse from all the row scan lines g1 to gm and supplies a reverse row scan pulse from all the reverse row scan lines gb1 to gbm in one frame period. As a result, in one frame period, the row scanning line g and the inverted row scanning line g and the inverted row scanning line g and the inverted row scanning line g and the inverted row scanning line gb1 from the top row scanning line g1 and the inverted row scanning line gb1 to the bottom row scanning line gm and the inverted row scanning line gbm in the image display unit 61. One row scanning line gb is sequentially selected in 1H units.

The data latch circuit 64 latches data having a width of 32 bits divided for each subframe supplied from an external circuit (not shown) based on the basic clock signal CLK from the host device 71. After that, the data latch circuit 64 outputs the latched data to the horizontal shift register 65a in synchronization with the basic clock signal CLK. Here, in the second embodiment, the reflective liquid crystal display device 13 divides one frame of the video signal into a plurality of subframes having a display period shorter than one frame period of the video signal, and subframes. Gradation is displayed by the combination of. Therefore, the above-mentioned external circuit is a 1-bit sub of each subframe unit for displaying the gradation data indicating the gradation of each pixel of the video signal in the entire plurality of the plurality of subframes. Convert to frame data. Then, the external circuit further collects the subframe data for 32 pixels in the same subframe and supplies the data in the 32-bit width to the data latch circuit 64.

When viewed in a 1-bit serial data processing system, the horizontal shift register 65a starts a shift by the horizontal start pulse HST first supplied from the timing generator 62 in 1H. Then, the horizontal shift register 65a shifts the 32-bit width data supplied from the data latch circuit 64 in synchronization with the clock signal HCK. The latch pulse LT is supplied from the timing generator 62 when the horizontal shift register 65a has finished shifting data for n bits, which is the same as the number of pixels n for one line of the image display unit 61. The latch circuit 65b latches n bits of data (that is, subframe data of n pixels in the same row) supplied in parallel from the horizontal shift register 65a according to the latch pulse LT, and the level shifter / pixel driver 65c level shifter. Output to. When the data transfer to the latch circuit 65b is completed, the horizontal start pulse HST is output again from the timing generator 62, and the horizontal shift register 65a resumes the shift of 32-bit width data from the data latch circuit 64 according to the clock signal HCK.

The level shifter in the level shifter / pixel driver 65c shifts the signal level of n subframe data corresponding to one row of n pixels latched and supplied by the latch circuit 65b to the liquid crystal drive voltage amplitude. The pixel driver in the level shifter / pixel driver 65c outputs n subframe data corresponding to n pixels in one row after level shift in parallel from n column data lines d1 to dn.

The horizontal driver 65 performs the output of data for the pixel row in which the data is written this time and the shift of the data regarding the pixel row in which the data is written in the next 1H in parallel in 1H. In a certain horizontal scanning period, n subframe data for one latched row are output in parallel and all at once from n column data lines d1 to dn as data signals.

The n pixel Pix in one row selected by the normal rotation scan pulse from the vertical shift register 63 can generate n subframe data for one row simultaneously output from the level shifter / pixel driver 65c. Sampling is performed through the column data lines d1 to dn of the book. Then, the n pixel Pix in one row writes the sampled n subframe data for one row to the first signal holding circuit (described later) in each pixel Pix.

FIG. 5 is a diagram showing a pixel configuration of the reflective liquid crystal display device according to the second embodiment.

The pixel Pix is arranged at the intersection of the row scanning line g and the column data line d. The pixel Pix includes a first memory 81 and a second memory 82 that store 1-bit gradation data (pixel data), respectively. The first memory 81 includes a switch 81a and a first signal holding circuit 81b. The second memory 82 includes a switch 82a and a second signal holding circuit 82b.

The pixel Pix includes a liquid crystal display element LC. In the liquid crystal display element LC, a liquid crystal LCM is sandwiched between the reflective electrodes PE and the common electrode CE arranged so as to face each other. It is exemplified that the common electrode CE is formed on the facing substrate of the reflective liquid crystal display device 13, but the present disclosure is not limited to this.

The column data line d is connected to the horizontal driver 65 (see FIG. 4). The horizontal driver 65 drives a specific column data line d by changing the drive timing. The row scan line g is connected to the vertical shift register 63 (see FIG. 4). The vertical shift register 63 drives a specific row scan line g by changing the drive timing.

The switch 81a is turned on when a forward-rotating scan pulse is supplied to the row scan line g. At this time, the gradation data supplied from the column data line d is written to the first signal holding circuit 81b via the switch 81a. The switch 82a is turned on when the forward rotation trigger pulse TRIG is supplied to the trigger line trig. At this time, the gradation data held in the first signal holding circuit 81b is transferred to the second signal holding circuit 82b via the switch 82a. The gradation data transferred to the second signal holding circuit 82b is supplied to the reflective electrode PE of the liquid crystal display element LC.

When the pixel Pix at a specific intersection is selected by the column data line d and the row scanning line g, 1-bit gradation data is written in the first memory 81 in the pixel Pix. By repeating this at different timings with respect to all the pixel Pix, 1-bit gradation data is written to all the pixel Pix. After that, the forward rotation trigger pulse TRIG is supplied to the trigger line trig commonly connected to all the pixel Pix, so that the gradation data held in the first memory 81 in all the pixel Pix is the second memory. Transferred to 82. A reflection electrode PE is connected to the second memory 82, and the gradation data held in the second memory 82 is applied to the liquid crystal display element LC.

When the transfer of the gradation data from the first memory 81 to the second memory 82 is completed, the supply of the forward rotation trigger pulse TRIG ends, so that the first memory 81 and the second memory 82 become non-conducting. .. Then, once again, 1-bit gradation data is written in the first memory 81 of all the pixels Pix. While the gradation data is being written to the first memory 81, the gradation data held in the second memory 82 continues to be applied to the liquid crystal display element LC.

The gradation data will be described. First, the normal rotation subframe gradation data is written in all the pixels Pix, and the liquid crystal display element LC displays the normal rotation subframe gradation data based on the normal rotation subframe gradation data. Next, the inverted gradation data is written to the first memory 81 of all the pixels Pix. When the writing of the inverted gradation data to the first memory 81 is completed, the forward rotation trigger pulse TRIG is supplied, and the inverted gradation data is transferred to the second memory 82 of all the pixels Pix at once. Then, the liquid crystal display element LC displays based on the inverted gradation data. At this timing, the common electrode voltage Vcom supplied to the common electrode CE of the liquid crystal display element LC is inverted. The relationship between the inverting gradation data and the common electrode voltage Vcom is a voltage on the opposite side as compared with the case where the normal rotation subframe gradation data is applied to the liquid crystal display element LC. That is, the liquid crystal display element LC can perform positive / negative AC drive by sequentially inputting the forward rotation subframe gradation data and the reverse rotation gradation data to the pixel Pix. As a result, a highly reliable reflective liquid crystal display device 13 can be realized without burning the liquid crystal display element LC.

According to the configuration of the pixel Pix, the time for writing the gradation data to the first memory 81 of the pixel Pix and the time for applying the gradation data to the reflection electrode PE of the liquid crystal display element LC can be separated. That is, the gradation data written in the first memory 81 during the gradation data writing time is not applied to the liquid crystal display element LC at the time of being written in the first memory 81. Therefore, the voltage relationship between the voltage of the reflecting electrode PE and the common electrode voltage Vcom is not broken during the writing of the gradation data to the first memory 81. Therefore, unlike the conventional case, it is not necessary to turn off the liquid crystal display element LC by setting the reflective electrode PE and the common electrode CE to the same potential during the gradation data writing time. As described above, since the display loss time of the liquid crystal display element LC in the gradation data writing time can be eliminated, it is possible to provide a high-performance reflective liquid crystal display device 13 having good gradation. Further, there is no restriction that the liquid crystal display element LC cannot display during the gradation data writing time. Therefore, it is possible to realize a high-performance reflective liquid crystal display device 13 without sacrificing gradation even for a device having a large number of pixels such as FHD (1920 × 1080) and 4K2K.

<Third embodiment>
FIG. 6 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the third embodiment.

One end of each of the column data line d and the inverted column data line db is connected to the level shifter / pixel driver 65c (see FIG. 4) and extends in the column direction (y direction). The column data line d and the inverted column data line db are a total of n pairs of columns in which the column data line dj for normal rotation subframe gradation data and the inverted column data line dbj for inverted gradation data are paired. Any pair of data lines. Pixel Pix1 is provided at the intersection of an arbitrary pair of column data lines d and inverted column data lines db and an arbitrary one row scanning line g.

Pixel Pix1 includes a first memory 91 and a second memory 92, and a liquid crystal display element LC. The first memory 91 includes switches SW11a and SW11b, and a first signal holding circuit SM11. The second memory 92 includes switches SW12a and SW12b, and a second signal holding circuit SM12.

In the pixel Pix 1, each of the first memory 91 and the second memory 92 is composed of a static random access memory (Static Random Access Memory: SRAM).

The switches SW11a and SW11b correspond to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit SM11 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 91 corresponds to an example of the "first static random access memory" of the present disclosure. The switches SW12a and SW12b correspond to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit SM12 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 92 corresponds to an example of the "second static random access memory" of the present disclosure.

The switch SW11a is an N-channel type MOS (Metal) in which the gate is connected to the row scanning line g, the drain is connected to the column data line d, and the source is connected to one input terminal of the first signal holding circuit SM11. Oxide Semiconductor: It is composed of (NMOS) transistors. The switch SW11b is composed of an NaCl transistor in which the gate is connected to the row scan line g, the drain is connected to the inverted column data line db, and the source is connected to the other input terminal of the first signal holding circuit SM11. There is.

The first signal holding circuit SM11 is a self-holding memory composed of two inverters INV1 and INV2 in which one output terminal is connected to the other input terminal. The input terminal of the inverter INV1 is connected to the output terminal of the inverter INV2, the source of the MIMO transistor constituting the switch SW11a, and the switch SW12a. The input terminal of the inverter INV2 is connected to the output terminal of the inverter INV1, the source of the nanotube transistor constituting the switch SW11b, and the switch SW12b.

In the switch SW12a, the gate is connected to the trigger line transistor, the drain is connected to the connection point between the first signal holding circuit SM11 and the switch SW11a, and the source is connected to one input terminal of the second signal holding circuit SM12. , NMOS is composed of transistors. The switch SW12b has a gate connected to the trigger line transistor, a drain connected to the connection point between the first signal holding circuit SM11 and the switch SW11b, and a source connected to the other input terminal of the second signal holding circuit SM12. , NMOS is composed of transistors.

The second signal holding circuit SM12 is a self-holding memory composed of two inverters INV3 and INV4 in which one output terminal is connected to the other input terminal. The input terminal of the inverter INV3 is connected to the output terminal of the inverter INV4, the source of the NOTE transistor constituting the switch SW12a, and the reflection electrode PE. The input terminal of the inverter INV4 is connected to the output terminal of the inverter INV3 and the source of the NOTE transistor constituting the switch SW12b.

Each of the inverters INV1, INV2, INV3 and INV4 is exemplified by the configuration of a CMOS (Complementary Metal Oxide Semiconductor) inverter.

FIG. 7 is a diagram showing a circuit configuration of a CMOS inverter. The source of the polyclonal transistor Ptr is connected to the power supply voltage VDD. The drain of the polyclonal transistor Ptr is connected to the drain of the nanotube transistor Ntr. The source of the IGMP transistor Ntr is connected to the reference voltage GND. The gate of the ProLiant transistor Ptr and the gate of the MIMO transistor Ntr are connected to each other and are input terminals IN of the CMOS inverter. The drain of the FIGURE transistor Ptr and the drain of the Now's transistor Ntr are connected to each other and are the output terminals OUT of the CMOS inverter.

Referring to FIG. 6 again, the gradation data is written to the first memory 91 via the two switches SW11a and SW11b operated by the normal rotation scanning pulse. Gradation data having opposite polarities is supplied to the column data line d and the inverted column data line db. The two switches SW11a and SW11b are composed of an HCl transistor. Of the switches SW11a and SW11b, the power supply voltage VDD is supplied to the drain of the IGMP transistor of one switch, and the reference voltage GND is supplied to the drain of the IGMP transistor of the other switch. When the power supply voltage VDD is supplied to the drain of one of the Now's transistors, only the voltage lower by the threshold voltage Vth of the Now's transistor is output from the power supply voltage VDD from the source of the NOTE transistor. Moreover, at this voltage, the µtransistor is driven in the vicinity of the threshold voltage Vth, so that almost no current flows. Therefore, the gradation data is written in the first memory 91 by the µ transistor to which the other reference voltage GND is supplied.

The gradation data is written to the second memory 92 via two switches SW12a and SW12b operated by the forward rotation trigger pulse TRIG. Gradation data having opposite polarities is supplied to the wiring m between the output terminal of the inverter INV2 and the switch SW12a and the wiring mb between the output terminal of the inverter INV1 and the switch SW12b. The two switches SW12a and SW12b are composed of an nanotube transistor. Of the switches SW12a and SW12b, the power supply voltage VDD is supplied to the drain of the IGMP transistor of one switch, and the reference voltage GND is supplied to the drain of the IGMP transistor of the other switch. When the power supply voltage VDD is supplied to the drain of one of the Now's transistors, only the voltage lower by the threshold voltage Vth of the Now's transistor is output from the power supply voltage VDD from the source of the NOTE transistor. Moreover, at this voltage, the µtransistor is driven in the vicinity of the threshold voltage Vth, so that almost no current flows. Therefore, the gradation data is written in the second memory 92 by the IGMP transistor to which the other reference voltage GND is supplied.

When the forward rotation trigger pulse TRIG is supplied, it is necessary to rewrite the gradation data of the second memory 92 with the gradation data of the first memory 91. That is, the gradation data of the first memory 91 must not be rewritten by the gradation data of the second memory 92. Therefore, the driving force of the inverters INV3 and INV4 constituting the second memory 92 needs to be smaller than the driving force of the inverters INV1 and INV2 constituting the first memory 91. That is, when the gradation data of the first memory 91 and the second memory 92 are different, the output of the inverter INV1 and the output of the inverter INV3 compete with each other when the forward rotation trigger pulse TRIG is supplied. The driving force of the inverter INV1 needs to be larger than the driving force of the inverter INV3 so that the gradation data of the inverter INV4 can be reliably rewritten by the gradation data of the inverter INV1.

Similarly, in the competition between the inverter INV2 and the inverter INV4, it is necessary that the gradation data of the inverter INV3 can be reliably rewritten by the gradation data of the inverter INV2. Therefore, the driving force of the inverter INV2 needs to be larger than the driving force of the inverter INV4.

FIG. 8 is a diagram illustrating the magnitude relationship of the driving force between the inverters.

Briefly explaining the relationship between the inverter INV1 and the inverter INV3, when the gradation data of the first memory 91 in the wiring mb is “H” level, the polyclonal transistor PT1 of the inverter INV1 is on. On the other hand, when the gradation data on the mb side of the second memory 92 is already at the “L” level, the IGMP transistor NT2 of the inverter INV3 is on.

Consider the case where the nanotube transistor constituting the switch SW12b is turned on by the “H” level of the forward rotation trigger pulse TRIG, and the outputs of the inverter INV1 and the inverter INV3 are electrically connected to each other. The current flows from the power supply voltage VDD to the reference voltage GND via the polyclonal transistor PT1 of the inverter INV1 and the nanotube transistor NT2 of the inverter INV3. At this time, the voltage of the wiring mb is determined by the ratio of the on-resistance of the polyclonal transistor PT1 of the inverter INV1 and the nanotube transistor NT2 of the inverter INV3.

On the contrary, when the gradation data of the first memory 91 in the wiring mb is at the “L” level, it is in a state where the nanotube transistor NT1 of the inverter INV1 is on. On the other hand, when the gradation data on the mb side of the second memory 92 is already at the “H” level, the polyclonal transistor PT2 of the inverter INV3 is on.

Consider the case where the nanotube transistor constituting the switch SW12b is turned on by the “H” level of the forward rotation trigger pulse TRIG, and the outputs of the inverter INV1 and the inverter INV3 are electrically connected to each other. The current flows from the power supply voltage VDD to the reference voltage GND via the polyclonal transistor PT2 of the inverter INV3 and the nanotube transistor NT1 of the inverter INV1. At this time, the voltage of the wiring mb is determined by the ratio of the on-resistance of the polyclonal transistor PT2 of the inverter INV3 and the IGMP transistor NT1 of the inverter INV1.

Further, an input gate of the inverter INV4 (see FIG. 6) is connected to the wiring mb. In the inverter INV4, the output data is fixed to the "L" level or the "H" level by the input of the voltage level of the wiring mb. That is, the output data of the second memory 92 is determined by the voltage level of the wiring mb. Therefore, in order to rewrite the gradation data of the second memory 92 by the gradation data of the first memory 91, the on-resistance of the transistors of the inverters INV1 and INV2 needs to be lower than the on-resistance of the transistors of the inverters INV3 and INV4. be. Since the on-resistance of the transistors of the inverters INV1 and INV2 is lower than the on-resistance of the transistors of the inverters INV3 and INV4, the gradation data of the first memory 91 is the second gradation data level of the second memory 92. It is surely written to the memory 92.

The use of a transistor with a low on-resistance can be realized by using a transistor with a high driving force, and can be realized by reducing the gate length or increasing the gate width.

Referring to FIG. 6 again, when the gradation data stored in the first memory 91 is transferred to the second memory 92 of all the pixels Pix1 all at once, the forward rotation trigger pulse TRIG becomes “L” level and the switch is switched. SW12a and SW12b are turned off. Therefore, the second memory 92 holds the transferred gradation data, and fixes the potential of the reflective electrode PE to the potential corresponding to the gradation data for an arbitrary time (here, one subframe period). Can be done.

The switches SW11a, SW11b, SW12a and SW12b may be configured by a polyclonal transistor. In that case, since it may be considered as having the opposite polarity to the above description, the illustration and description will be omitted.

Further, the switches SW11a, SW11b, SW12a and SW12b may be a transmission gate composed of a polyclonal transistor and an IGMP transistor.

FIG. 9 is a timing diagram showing the operation of the reflective liquid crystal display device according to the third embodiment.

As described above, in the reflective liquid crystal display device 13 (see FIG. 4), the row scan line g is directed from the row scan line g1 to the row scan line gm by the normal rotation scan pulse output from the vertical shift register 63. Are sequentially selected one by one in 1H units. As a result, the plurality of pixels Pix1 constituting the image display unit 61 are written with gradation data in units of n pixels Pix1 in one row commonly connected to the selected row scanning line g. Then, after writing to all of the plurality of pixels Pix1 constituting the image display unit 61 is completed, the forward rotation trigger pulse TRIG transfers all the pixels Pix1 from the first memory 91 to the second memory 92 all at once. Will be done.

FIG. 9A schematically shows a write period and a read period of one pixel of 1-bit subframe gradation data output from the horizontal driver 65 from the column data lines d1 to dn. The downward slash indicates the writing period. In FIG. 9A, the bits B0b, B1b and B2b are inverted data of the gradation data of the bits B0, B1 and B2.

FIG. 9B shows a forward rotation trigger pulse TRIG output from the timing generator 62 to the trigger line trig. The forward rotation trigger pulse TRIG is output for each subframe.

FIG. 9C schematically shows the bits of the subframe gradation data applied to the reflective electrode PE. FIG. 9D shows a common electrode voltage Vcom. FIG. 9E shows the voltage applied to the liquid crystal LCM.

First, the switches SW11a and SW11b of the plurality of pixels Pix1 in one row selected by the forward rotation scan pulse output from the timing generator 62 are turned on by the forward rotation scan pulse. At that time, the normal rotation subframe gradation data of the bit B0 (FIG. 9A) output to the column data line d is sampled by the switch SW11a and written to the first signal holding circuit SM11. Hereinafter, in the same manner, the forward rotation subframe gradation data of the bit B0 is written to the first signal holding circuit SM11 of all the pixels Pix1 constituting the image display unit 61. At the timing T1 after the writing operation is completed, the “H” level forward rotation trigger pulse TRIG (FIG. 9B) is simultaneously supplied to all the pixels Pix1 constituting the image display unit 61.

As a result, the switches SW12a and SW12b of all the pixels Pix1 are turned on. Therefore, the normal rotation subframe gradation data of the bit B0 stored in the first signal holding circuit SM11 is collectively transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the normal rotation subframe gradation data of the bit B0 is applied to the reflection electrode PE. The retention period of the normal rotation subframe gradation data of the bit B0 by the second signal holding circuit SM12 is one subframe from the timing T1 to the timing T2 at which the next “H” level forward rotation trigger pulse TRIG is input. It is a period.

Here, when the bit value of the subframe gradation data is “1”, that is, “H” level, the power supply voltage VDD (for example, 3.3 V) is applied to the reflective electrode PE. When the bit value of the subframe gradation data is “0”, that is, “L” level, a reference voltage GND (for example, 0V) is applied to the reflective electrode PE. On the other hand, a free voltage can be applied to the common electrode CE as the common electrode voltage Vcom without being limited by the reference voltage GND and the power supply voltage VDD. The common electrode voltage Vcom is set to switch to a specified voltage at the same timing as when the "H" level normal rotation trigger pulse TRIG is supplied. Here, the common electrode voltage Vcom is 0 V for the subframe period (for example, from timing T1 to timing T2) in which the normal rotation subframe gradation data is applied to the reflective electrode PE, as shown in FIG. 9 (D). The voltage is set to be lower than the threshold voltage Vtt of the liquid crystal display.

The liquid crystal display element LC performs gradation display according to the applied voltage of the liquid crystal LCM, which is an absolute value of the difference voltage between the applied voltage of the reflecting electrode PE and the common electrode voltage Vcom. In one subframe period from the timing T1 to the timing T2, the normal rotation subframe gradation data of the bit B0 is applied to the reflection electrode PE. Therefore, as shown in FIG. 9E, the applied voltage of the liquid crystal LCM is 3.3V + Vtt (= 3.3V− (−Vtt)) when the bit value of the subframe gradation data is “1”. .. On the other hand, the applied voltage of the liquid crystal LCM is + Vtt (= 0V− (−Vtt)) when the bit value of the subframe gradation data is “0”.

FIG. 10 is a diagram showing the relationship between the applied voltage (RMS (effective) voltage) of the liquid crystal display and the gray scale value.

As shown in FIG. 10, the grayscale value curve 101 is shifted to the high voltage side. Specifically, the black gray scale value corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal LCM, and the white gray scale value corresponds to the RMS voltage of the saturation voltage Vsat (= 3.3 V + Vtt) of the liquid crystal LCM. It is possible to match the grayscale value with the effective portion of the grayscale value curve 101. Therefore, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3 V + Vtt) as described above, and displays black when the applied voltage is + Vtt.

Referring to FIG. 9 again, within the subframe period displaying the normal rotation subframe gradation data of bit B0, the inverted subframe gradation data of bit B0b (see FIG. 9A) of the pixel Pix1. Writing to the first signal holding circuit SM11 is started in order. Then, the inverted subframe gradation data of the bit B0b is written in the first signal holding circuit SM11 of all the pixels Pix1 of the image display unit 61. At the timing T2 after the writing is completed, the “H” level forward rotation trigger pulse TRIG is simultaneously supplied to all the pixels Pix1 constituting the image display unit 61.

As a result, the switches SW12a and SW12b of all the pixels Pix1 are turned on. Therefore, the inverted subframe gradation data of the bit B0b stored in the first signal holding circuit SM11 passes through the switches SW12a and SW21b, and the second signal holding circuit SM.
Transferred to 12 and retained. At the same time, the inverted subframe gradation data of the bit B0b is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data of the bit B0b by the second signal retention circuit SM12 is one subframe period from the timing T2 to the timing T3 when the next “H” level forward rotation trigger pulse TRIG is supplied. Is. Here, the inverted subframe gradation data of the bit B0b always has an inverse logic value relationship with the normal rotation subframe gradation data of the bit B0. Therefore, the inverted subframe gradation data of the bit B0b is "0" when the normal rotation subframe gradation data of the bit B0 is "1", and the normal rotation subframe gradation data of the bit B0 is "0". In the case of, it is "1".

On the other hand, the common electrode voltage Vcom has a one subframe period from the timing T2 to the timing T3 when the inverted subframe gradation data is applied to the reflective electrode PE, as shown in FIG. 9D, more than 3.3V. The voltage is set higher by the threshold voltage Vtt of the liquid crystal LCM. Therefore, in one subframe period from timing T2 to timing T3, the applied voltage of the liquid crystal LCM is −Vtt (as shown in FIG. 9E) when the bit value of the subframe gradation data is “1”. = 3.3V- (3.3V + Vtt)). On the other hand, the applied voltage of the liquid crystal LCM is -3.3V-Vtt (= 0V- (3.3V + Vtt)) when the bit value of the subframe gradation data is "0".

When the bit value of the forward rotation subframe gradation data of the bit B0 is "1", the bit value of the inverted subframe gradation data of the bit B0b subsequently input is "0". Therefore, the applied voltage of the liquid crystal LCM becomes − (3.3V + Vtt), and the direction of the potential applied to the liquid crystal LCM is opposite to that of the normal rotation subframe gradation data of bit B0, but the absolute value is the same. Is. Therefore, the pixel Pix1 displays white as in the case of displaying the normal rotation subframe gradation data of the bit B0. Similarly, when the bit value of the forward rotation subframe gradation data of the bit B0 is "0", the bit value of the inverted subframe gradation data of the bit B0b subsequently input is "1". Therefore, the applied voltage of the liquid crystal LCM is −Vtt, and the direction of the potential applied to the liquid crystal LCM is opposite to that of the normal rotation subframe gradation data of the bit B0, but the absolute value is the same. Therefore, the pixel Pix1 displays black as in the case of displaying the normal rotation subframe gradation data of the bit B0.

Therefore, as shown in FIG. 9E, the pixel Pix1 displays the same gradation in the bit B0 and the bit B0b which is a complementary bit of the bit B0 during the two subframe periods from the timing T1 to the T3. .. At the same time, the pixel Pix1 performs an AC drive in which the potential direction of the liquid crystal LCM is inverted for each subframe. Thereby, the pixel Pix1 can prevent the burn-in of the liquid crystal LCM.

Subsequently, within the subframe period displaying the inverted subframe gradation data of the bit B0b, the first signal holding circuit of the pixel Pix1 of the normal rotation subframe gradation data of the bit B1 (see FIG. 9A). Writing to SM11 is started in order. Then, the forward rotation subframe gradation data of the bit B1 is written to the first signal holding circuit SM11 of all the pixels Pix1 of the image display unit 61. At the timing T3 after the writing is completed, the “H” level forward rotation trigger pulse TRIG is simultaneously supplied to all the pixels Pix1 constituting the image display unit 61.

As a result, the switches SW12a and SW12b of all the pixels Pix1 are turned on. Therefore, the forward rotation subframe gradation data of the bit B1 stored in the first signal holding circuit SM11 is transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the normal rotation subframe gradation data of the bit B1 is applied to the reflection electrode PE. The retention period of the normal rotation subframe gradation data of the bit B1 by the second memory 92 is one subframe period from the timing T3 to the timing T4 in which the next “H” level forward rotation trigger pulse TRIG is supplied. be.

On the other hand, the common electrode voltage Vcom is a voltage in which the subframe period in which the normal rotation subframe gradation data is applied to the reflective electrode PE is lower than 0V by the threshold voltage Vtt of the liquid crystal LCM, as shown in FIG. 9D. Is set to. In one subframe period from the timing T3 to the timing T4, the normal rotation subframe gradation data of the bit B1 is applied to the reflection electrode PE. Therefore, as shown in FIG. 9E, the applied voltage of the liquid crystal LCM is 3.3V + Vtt (= 3.3V− (−Vtt)) when the bit value of the subframe gradation data is “1”. .. On the other hand, the applied voltage of the liquid crystal LCM is + Vtt (= 0V− (−Vtt)) when the bit value of the subframe gradation data is “0”.

Subsequently, within the subframe period displaying the normal rotation subframe gradation data of the bit B1, the first signal holding circuit of the pixel Pix1 of the inverted subframe gradation data of the bit B1b (see FIG. 9A). Writing to SM11 is started in order. Then, the inverted subframe gradation data of the bit B1b is written in the first signal holding circuit SM11 of all the pixels Pix1 of the image display unit 61. At the timing T4 after the writing is completed, the “H” level forward rotation trigger pulse TRIG is simultaneously supplied to all the pixels Pix1 constituting the image display unit 61.

As a result, the switches SW12a and SW12b of all the pixels Pix1 are turned on. Therefore, the inverted subframe gradation data of the bit B1b stored in the first signal holding circuit SM11 is transferred to and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the inverted subframe gradation data of the bit B1b is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data of the bit B1b by the second signal retention circuit SM12 is one subframe period from the timing T4 to the timing T5 when the next “H” level forward rotation trigger pulse TRIG is supplied. Is. Here, the inverted subframe gradation data of the bit B1b always has an inverse logic value relationship with the normal rotation subframe gradation data of the bit B1.

On the other hand, in the common electrode voltage Vcom, the subframe period in which the inverted subframe gradation data is applied to the reflective electrode PE is higher than 3.3V by the threshold voltage Vtt of the liquid crystal LCM as shown in FIG. 9 (D). Set to voltage. In the one subframe period from the timing T4 to the timing T5, the inverted subframe gradation data of the bit B1b is applied to the reflection electrode PE. Therefore, as shown in FIG. 9E, the applied voltage of the liquid crystal LCM is −Vtt (= 3.3V- (3.3V + Vtt)) when the bit value of the subframe gradation data is “1”. Become. On the other hand, the applied voltage of the liquid crystal LCM is -3.3V-Vtt (= 0V- (3.3V + Vtt)) when the bit value of the subframe gradation data is "0".

Therefore, as shown in FIG. 9E, the pixel Pix1 displays the same gradation in the bit B1 and the bit B1b which is a complementary bit of the bit B1 during the two subframe periods from the timing T3 to the T5. .. At the same time, the pixel Pix1 performs an AC drive in which the potential direction of the liquid crystal LCM is inverted for each subframe. Thereby, the pixel Pix1 can prevent the burn-in of the liquid crystal LCM.

After that, the same operation as described above is repeated, and according to the reflective liquid crystal display device 13 including the pixel Pix1, gradation display can be performed by combining a plurality of subframes.

The display period length of bit B0 and the display period length of bit B0b, which is a complementary bit, are the same first subframe period length. Further, the display period length of the bit B1 and the display period length of the complementary bit B1b are the same second subframe period length. However, the first subframe period length and the second subframe period length are not always the same. Here, as an example, the second subframe period length is set to twice the first subframe period length. Further, the display period length of the bit B2, the display period length of the complementary bit B2b, and the third subframe period length are set to be twice the second subframe period length. The same applies to the other subframe periods, each subframe period length is determined to be a predetermined length according to the system, and the number of subframes is also determined to be an arbitrary number.

(summary)
The gradation data written in the second memory 92 is normal rotation subframe gradation data and reverse rotation subframe gradation data that are switched for each subframe. On the other hand, the common electrode voltage Vcom alternately switches to a predetermined potential for each subframe in synchronization with writing. As a result, the pixel Pix1 can drive the liquid crystal display element LC with positive and negative alternating current. Therefore, the reflective liquid crystal display device 13 can suppress the burning of the liquid crystal display element LC, so that the reliability can be improved.

Further, the pixel Pix1 does not need to turn off the liquid crystal display element LC by setting the reflective electrode PE and the common electrode CE to the same potential during the gradation data writing time. Therefore, the reflective liquid crystal display device 13 can eliminate the display loss time of the liquid crystal display element LC in the gradation data writing time, so that the gradation can be improved. Further, since the reflective liquid crystal display device 13 does not have the restriction that the liquid crystal display element LC cannot display during the gradation data writing time, the gradation can be obtained even for a device having a large number of pixels such as FHD and 4K2K. There is no sacrifice.

Further, since the pixel Pix1 sets the driving force of the inverters INV1 and INV2 to be larger than the driving force of the inverters INV3 and INV4, stable and accurate gradation display can be performed.

Further, the pixel Pix1 can set a high voltage applied to the liquid crystal display element LC, and can widen the dynamic range. As a result, the reflective liquid crystal display device 13 can suppress the decrease in contrast and the decrease in brightness. Further, the reflective liquid crystal display device 13 can increase the reflection angle of the reflected light.

When the reflective liquid crystal display device 13 of the third embodiment, which can suppress the decrease in contrast and can suppress the decrease in brightness, is applied to the WSS array 10, the decrease in contrast from the output beams 31a to 31c (see FIG. 1) is applied. Can be suppressed, and the decrease in brightness can be suppressed. Thereby, the WSS array 10 can improve the S / N (signal / noise) ratio of the wavelength channel.

Further, when the reflective liquid crystal display device of the third embodiment capable of increasing the reflection angle of the reflected light is applied to the WSS array 10 of the first embodiment, the output beams 31a to 31c (see FIG. 1). ) Can be widened. Thereby, the WSS array 10 can improve the S / N ratio of the wavelength channel. Alternatively, the WSS array 10 can output a new output beam while maintaining the spatial spacing from the output beams 31a to 31c. This allows the WSS array 10 to increase the wavelength channel.

Further, in the pixel Pix1, the first signal holding circuit SM11 and the second signal holding circuit SM12 are static random access memories. Therefore, the pixel Pix1 can increase the noise immunity.

<Fourth Embodiment>
FIG. 11 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the fourth embodiment.

Among the components of the pixel Pix2 of the reflective liquid crystal display device of the fourth embodiment, the same components as the pixel Pix1 of the third embodiment are designated by the same reference numerals and the description thereof is omitted. do.

The pixel Pix2 is provided at the intersection of an arbitrary one column data line d and an arbitrary one row scanning line g.

The pixel Pix2 includes a first memory 111 and a second memory 112, and a liquid crystal display element LC. The first memory 111 includes a switch SW13 and a first signal holding circuit SM13. The second memory 112 includes a switch SW14 and a second signal holding circuit SM14.

In the pixel Pix2, each of the first memory 111 and the second memory 112 is composed of SRAM.

The switch SW13 corresponds to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit SM13 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 111 corresponds to an example of the "first static random access memory" of the present disclosure. The switch SW14 corresponds to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit SM14 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 112 corresponds to an example of the "second static random access memory" of the present disclosure.

Pixel Pix2 is composed of two SRAM stages as in pixel Pix1 (see FIG. 6), but writing to the first signal holding circuit SM13 and the second signal holding circuit SM14 is performed via switches SW13 and SW14. It is characteristic in that it is done.

The switch SW13 is composed of an NaCl transistor in which the gate is connected to the row scan line g, the drain is connected to the column data line d, and the source is connected to one input terminal of the first signal holding circuit SM13. ..

The first signal holding circuit SM13 is a self-holding memory composed of two inverters INV11 and INV12 in which one output terminal is connected to the other input terminal. The input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NOTE transistor constituting the switch SW13. The input terminal of the inverter INV12 is connected to the output terminal of the inverter INV11 and the drain of the NOTE transistor constituting the switch SW14.

The switch SW14 is composed of an NaCl transistor in which the gate is connected to the trigger line rig, the drain is connected to the output terminal of the first signal holding circuit SM13, and the source is connected to the input terminal of the second signal holding circuit SM14. ing.

The second signal holding circuit SM14 is a self-holding memory composed of two inverters INV13 and INV14 in which one output terminal is connected to the other input terminal. The input terminal of the inverter INV13 is connected to the output terminal of the inverter INV14 and the reflection electrode PE. The input terminal of the inverter INV14 is connected to the output terminal of the inverter INV13 and the source of the NOTE transistor constituting the switch SW14.

Each of the inverters INV11, INV12, INV13 and INV14 is exemplified by the configuration of a CMOS inverter (see FIG. 7).

The pixel Pix2 performs the same operation as described with the timing diagram of FIG. 9 in the third embodiment.

First, the switch SW13 of the plurality of pixels Pix2 in one row selected by the normal rotation scanning pulse output from the timing generator 62 is turned on by the normal rotation scanning pulse. At that time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW13 and written to the first signal holding circuit SM13. Hereinafter, in the same manner, the forward rotation subframe gradation data is written to the first signal holding circuit SM13 of all the pixels Pix2 constituting the image display unit 61. At the timing after the writing operation is completed, the “H” level forward rotation trigger pulse TRIG is simultaneously supplied to all the pixels Pix2 constituting the image display unit 61.

As a result, the switches SW14 of all the pixels Pix2 are turned on. Therefore, the forward rotation subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred to and held in the second signal holding circuit SM14 via the switch SW14. At the same time, the normal rotation subframe gradation data is applied to the reflection electrode PE. The holding period of the normal rotation subframe gradation data by the second signal holding circuit SM14 is one subframe period until the next “H” level normal rotation trigger pulse TRIG is input.

Subsequently, each pixel Pix2 in the image display unit 61 is selected in line units by the normal rotation scanning pulse in the same manner as described above, and each pixel Pix2 has the inverse logic value of the immediately preceding normal rotation subframe gradation data. Inverted subframe gradation data is written to the first signal holding circuit SM13. When the writing of the inverted subframe gradation data to the first signal holding circuit SM13 of all the pixels Pix2 constituting the image display unit 61 is completed, the “H” level forward rotation trigger pulse TRIG constitutes the image display unit 61. It is supplied to all pixels Pix2 at the same time.

As a result, the switches SW14 of all the pixels Pix2 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred to and held in the second signal holding circuit SM14 via the switch SW14. At the same time, the inverted subframe gradation data is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data by the second signal retention circuit SM14 is one subframe period until the next “H” level forward rotation trigger pulse TRIG is supplied.

Data writing to the first signal holding circuit SM13 is performed via one switch SW13 as described above. In this case, the transistor in the inverter INV11 on the input side when viewed from the switch SW13 uses a transistor having a larger driving force than the transistor in the inverter INV12 on the output side when viewed from the switch SW13. Further, as the µtransistor constituting the switch SW13, a transistor having a larger driving force than the transistor constituting the inverter INV12 is used.

This is related to the case of rewriting the gradation data of the first signal holding circuit SM13. In particular, when the voltage a on the switch SW13 side of the first signal holding circuit SM13 is at the “L” level and the data on the column data line d is at the “H” level, the input voltage (threshold voltage) that the inverter INV 11 inverts is This is because it is necessary to raise the voltage a higher than the voltage).

That is, the voltage a in the case of the “H” level is determined by the ratio of the current of the NOTE transistor constituting the inverter INV12 to the current of the Now NO transistor constituting the switch SW13. The switch SW13 is an µtransistor. Therefore, when the switch SW13 is in the ON state, even if the “H” level power supply voltage VDD is input to the drain from the column data line d, the voltage output from the source is the threshold voltage of the MIMO transistor rather than the power supply voltage VDD. It is lowered by Vth. That is, the “H” level voltage of the voltage a becomes a voltage lower than the power supply voltage VDD by the threshold voltage Vth. Moreover, at this voltage, the NOTE transistor of the switch SW13 operates in the vicinity of the threshold voltage Vth, so that almost no current flows. That is, the higher the voltage a that conducts the switch SW13, the smaller the current that flows through the switch SW13.

That is, when the voltage a is at the “H” level, in order for the voltage a to reach a voltage equal to or higher than the voltage at which the IGMP transistor of the inverter INV11 is inverted, the current flowing through the switch SW13 is larger than the current flowing through the IGMP transistor of the inverter INV12. It needs to be big. Therefore, as the HCl transistor constituting the switch SW13, a transistor having a driving force larger than that of the IGMP transistor constituting the inverter INV12 is used. In consideration of the magnitude relationship of the driving force, it is necessary to determine the transistor size of the IGMP transistor constituting the switch SW13 and the transistor size of the nanotube transistor constituting the inverter INV12.

Further, data writing to the second signal holding circuit SM14 is performed via one switch SW14. In this case, the transistor in the inverter INV14 on the input side when viewed from the switch SW14 uses a transistor having a larger driving force than the transistor in the inverter INV13 on the output side when viewed from the switch SW14.

The case where the forward rotation trigger pulse TRIG becomes “H” level and the switch SW14 is turned on will be examined. When the gradation data held by the first signal holding circuit SM13 and the gradation data held by the second signal holding circuit SM14 are different, the output of the inverter INV11 and the output of the inverter INV13 compete with each other. .. However, the driving force of the inverter INV11 is larger than the driving force of the inverter INV13. Therefore, the gradation data of the first signal holding circuit SM13 is not rewritten by the gradation data of the second signal holding circuit SM14, and the gradation data of the second signal holding circuit SM14 is the gradation data of the first signal holding circuit SM13. Rewritten by.

Further, as the µtransistor constituting the switch SW14, a transistor having a larger driving force as compared with the µtransistor constituting the inverter INV13 is used.

This is related to the case of rewriting the gradation data of the second signal holding circuit SM14. In particular, when the voltage b on the switch SW14 side of the second signal holding circuit SM14 is at the “L” level and the gradation data of the first signal holding circuit SM13 is at the “H” level, the inverter INV14 is inverted. This is because the voltage b needs to be higher than the threshold voltage.

That is, the voltage b in the case of the "H" level is determined by the ratio of the current of the nanotube transistor constituting the inverter INV13 and the current of the Now NO transistor constituting the switch SW14. The switch SW14 is an IGMP transistor. Therefore, when the switch SW14 is in the ON state, even if the “H” level power supply voltage VDD is input to the drain from the first signal holding circuit SM13, the voltage output from the source is the DCM transistor rather than the power supply voltage VDD. The voltage becomes lower by the threshold voltage Vth. That is, the “H” level voltage of the voltage b becomes a voltage lower than the power supply voltage VDD by the threshold voltage Vth. Moreover, at this voltage, the NOTE transistor of the switch SW14 operates in the vicinity of the threshold voltage Vth, so that almost no current flows. That is, the higher the voltage b that conducts the switch SW14, the smaller the current that flows through the switch SW14.

That is, when the voltage b is at the “H” level, in order for the voltage b to reach a voltage equal to or higher than the voltage at which the IGMP transistor of the inverter INV14 is inverted, the current flowing through the switch SW14 is larger than the current flowing through the IGMP transistor of the inverter INV13. It needs to be big. Therefore, as the HCl transistor constituting the switch SW14, a transistor having a driving force larger than that of the IGMP transistor constituting the inverter INV13 is used. In consideration of the magnitude relationship of the driving force, it is necessary to determine the transistor size of the IGMP transistor constituting the switch SW14 and the transistor size of the nanotube transistor constituting the inverter INV13.

When the gradation data held in the first memory 111 is simultaneously transferred to the second memory 112 of all the pixels Pix2, the forward rotation trigger pulse TRIG becomes the “L” level and the switch SW14 is turned off. Therefore, the second memory 112 holds the transferred gradation data, and fixes the potential of the reflective electrode PE to the potential corresponding to the gradation data for an arbitrary time (here, one subframe period). Can be done.

The switches SW13 and SW14 may be configured by a polyclonal transistor. In that case, since it may be considered as having the opposite polarity to the above description, the illustration and description will be omitted.

Further, the switches SW13 and SW14 may be transmission gates composed of a polyclonal transistor and an NaCl transistor.

(summary)
The pixel Pix2 has the same effect as the pixel Pix1 of the third embodiment.

In addition, the pixel Pix2 has the effect of being able to be miniaturized. The reason is as follows. Each of the inverter INV11 to the inverter INV14 is composed of two transistors. Therefore, the pixel Pix2 is composed of a total of 10 transistors, and can be composed of a smaller number of elements than the pixel Pix1 (a total of 12 transistors).

<Fifth Embodiment>
The pixel Pix1 of the third embodiment requires a total of 12 transistors. The pixel Pix2 of the fourth embodiment requires a total of 10 transistors.

Further, the liquid crystal display element LC is required to be driven by 3V to 5V, and the transistor needs to be driven by 3.3V or 5V. Therefore, it is necessary to use a transistor having a high withstand voltage and a large size.

Further, in the pixels Pix1 and Pix2 using two SRAMs, it is necessary to design in consideration of the transistor size of each switch and the SRAM in order to surely rewrite the data. Transistors that need to have a large driving force need to have a large size.

On the other hand, the number of pixels of the reflective liquid crystal display device is increasing year by year, and there is a strong demand for pixel miniaturization. Therefore, it is necessary to configure a two-stage memory as shown in FIG. 5 with a small number of transistors in a small pixel pitch. ..

The pixel Pix3 of the fifth embodiment can meet the above-mentioned request.

FIG. 12 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the fifth embodiment.

Among the components of the pixel Pix3 of the reflective liquid crystal display device of the fifth embodiment, the same components as the pixel Pix1 of the third embodiment or the pixel Pix2 of the fourth embodiment are the same. Reference numerals are added, and the description thereof will be omitted.

The pixel Pix3 is provided at the intersection of an arbitrary one column data line d and an arbitrary one row scanning line g.

The pixel Pix3 includes a first memory 111 and a second memory 121, and a liquid crystal display element LC. The second memory 121 includes a switch SW21 and a second signal holding circuit DM21.

In the pixel Pix3, the first memory 111 is composed of a SRAM, and the second memory 121 is composed of a dynamic random access memory (DRAM).

The switch SW13 corresponds to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit SM13 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 111 corresponds to an example of the "first static random access memory" of the present disclosure. The switch SW21 corresponds to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit DM21 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 121 corresponds to an example of the "first dynamic random access memory" of the present disclosure.

The switch SW21 is a known transmission gate composed of an IMS transistor Tr1 and a polyclonal transistor Tr2 in which drains of each other are connected to each other and sources of each other are connected to each other. The gate of the IGMP transistor Tr1 is connected to the trigger line trig, and the gate of the polyclonal transistor Tr2 is connected to the inverting trigger line trigb.

Further, in the switch SW21, one terminal is connected to the first signal holding circuit SM13, and the other terminal is connected to the second signal holding circuit DM21 and the reflection electrode PE. Therefore, the switch SW21 is turned on when the forward rotation trigger pulse TRIG is at the “H” level (in this case, the reverse rotation trigger pulse TRIGB is at the “L” level). Therefore, the switch SW21 reads out the gradation data of the first signal holding circuit SM13 and transfers it to the second signal holding circuit DM21 and the reflection electrode PE. Further, the switch SW21 is turned off when the forward rotation trigger pulse TRIG is at the “L” level (in this case, the reverse rotation trigger pulse TRIGB is at the “H” level), and the gradation data of the first signal holding circuit SM13 is turned off. Is not read.

Since the switch SW21 is a known transmission gate composed of the MIMO transistor Tr1 and the polyclonal transistor Tr2, it is possible to turn on / off a voltage in the range from the reference voltage GND to the power supply voltage VDD. That is, when the signal applied to the gates of the nanotube transistor Tr1 and the polyclonal transistor Tr2 is the voltage (“L” level) on the reference voltage GND side, the polyclonal transistor Tr2 cannot be conducted. Instead, the IGMP transistor Tr1 can conduct with low resistance. On the other hand, when the signal applied to the gates of the nanotube transistor Tr1 and the polyclonal transistor Tr2 is the voltage on the power supply voltage VDD side (“H” level), the norx transistor Tr1 cannot be conducted. Instead, the polyclonal transistor Tr2 can conduct with low resistance. Therefore, the transmission gate constituting the switch SW21 is controlled to be turned on / off by the forward rotation trigger pulse TRIG and the reverse rotation trigger pulse TRIGB. By this control, the switch SW21 can switch the voltage range from the reference voltage GND to the power supply voltage VDD with low resistance and high resistance.

The second signal holding circuit DM21 is composed of the capacitance C1. Here, a case where the gradation data of the first signal holding circuit SM13 and the gradation data of the second signal holding circuit DM21 are different will be examined. When the switch SW21 is turned on and the gradation data of the first signal holding circuit SM13 is transferred to the second signal holding circuit DM21, the gradation data of the second signal holding circuit DM21 is transferred to the first signal holding circuit SM13. It is necessary to rewrite with gradation data.

When the gradation data of the capacitance C1 constituting the second signal holding circuit DM21 is rewritten, the gradation data changes by charging or discharging. The charge / discharge of the capacitance C1 is driven by the output signal of the inverter INV11.

When the gradation data of the capacitance C1 is rewritten from the "L" level to the "H" level by charging, the output signal of the inverter INV11 is "H". At this time, the polyclonal transistor (see the polyclonal transistor Ptr in FIG. 7) constituting the inverter INV11 is in the on state, and the nanotube transistor (see the HCl transistor Ntr in FIG. 7) is in the off state. Therefore, the capacitance C1 is charged by the power supply voltage VDD connected to the source of the polyclonal transistor of the inverter INV11.

On the other hand, when the gradation data of the capacitance C1 is rewritten from the "H" level to the "L" level by discharging, the output signal of the inverter INV11 is the "L" level. At this time, the MIMO transistor constituting the inverter INV11 (see the NaCl transistor Ntr in FIG. 7) is in the ON state, and the polyclonal transistor (see the polyclonal transistor Ptr in FIG. 7) is in the off state. Therefore, the charge of the capacitance C1 is discharged to the reference voltage GND via the nanotube transistor of the inverter INV11. Since the switch SW21 is configured as an analog switch using a transmission gate, high-speed charging / discharging of the capacitance C1 becomes possible.

Further, the driving force of the inverter INV 11 is set to be larger than the driving force of the inverter INV 12. Therefore, the inverter INV11 can charge and discharge the capacitance C1 constituting the second signal holding circuit DM21 at high speed.

When the switch SW21 is turned on, the electric charge stored in the capacitance C1 may also affect the input gate of the inverter INV12. However, since the driving force of the inverter INV11 is set to be larger than that of the inverter INV12, the charging / discharging of the capacitance C1 by the inverter INV11 is prioritized over the data inversion of the inverter INV12. Therefore, the gradation data of the first signal holding circuit SM13 is not rewritten by the gradation data of the second signal holding circuit DM21.

The pixel Pix3 can transfer 1-bit gradation data from the first signal holding circuit SM13 to the second signal holding circuit DM21 with the amplitude of the reference voltage GND and the power supply voltage VDD. Therefore, when the pixel Pix3 is driven by the same power supply voltage VDD, the applied voltage of the liquid crystal display element LC can be set high, and the dynamic range can be widened.

In addition, the pixel Pix3 has the effect of being able to be miniaturized. The first reason is as follows. Each of the inverters INV11 and INV12 is composed of two transistors. Therefore, the pixel Pix3 is composed of a total of seven transistors and one capacitance C1, and can be composed of a smaller number of elements than the pixel Pix1 (a total of 12 transistors) and the pixel Pix2 (a total of 10 transistors). .. The second reason is that, as described below, the first signal holding circuit SM13, the second signal holding circuit DM21, and the reflective electrode PE can be effectively arranged in the height direction of the element.

FIG. 13 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the fifth embodiment.

The capacity C1 includes a MIM (Metal-Insulator-Metal) capacity that forms a capacity between wirings, a Diffusion capacity that forms a capacity between a substrate and polysilicon, and a PIP (Poly-Insulator) that forms a capacity between two layers of polysilicon. -Poly) Capacity, etc. can be used. FIG. 13 shows a cross-sectional configuration of a reflective liquid crystal display device in the case where the capacitance C1 is configured by MIM.

In FIG. 13, on the N-well 201 formed on the silicon substrate 200, a polyclonal transistor PTr11 of an inverter INV11 in which drains are connected to each other by sharing a diffusion layer, and a polyclonal transistor Tr2 of a switch SW21 are formed. ing. Further, on the P-well 202 formed on the silicon substrate 200, an IMS transistor NTr11 of an inverter INV11 in which drains are connected to each other by sharing a diffusion layer as a drain, and an nanotube transistor Tr1 of a switch SW21 are formed. It has been. Note that FIG. 13 does not show the NaCl transistor and the polyclonal transistor constituting the inverter INV12.

Further, an interlayer insulating film 205 is interposed between the metals above the polyclonal transistors PTr11 and Tr2, and above the nanotube transistors Tr1 and NTr12, so that the first metal 206, the second metal 208, the third metal 210, and the electrode 212 are interposed. The fourth metal 214 and the fifth metal 216 are laminated. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel. The two diffusion layers, each of which constitutes the source of the nanotube transistor Tr1 and the polyclonal transistor Tr2 constituting the switch SW21, are electrically connected to the first metal 206 by two contacts 218, respectively. Further, the two diffusion layers are electrically connected to the second metal 208, the third metal 210, the fourth metal 214 and the fifth metal 216 via through holes 219a, 219b, 219c and 219e. That is, each source of the MIMO transistor Tr1 and the polyclonal transistor Tr2 constituting the switch SW21 is electrically connected to the reflection electrode PE.

Further, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216), and is arranged so as to be separated from the common electrode CE which is a transparent electrode. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form a liquid crystal display element LC.

Here, the electrode 212 is formed on the third metal 210 via the interlayer insulating film 205. The electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute the capacitance C1.

When the capacitance C1 is configured by MIM, the first signal holding circuit SM13, the switch SW13 and the switch SW12 are composed of a transistor on the silicon substrate 200 and a first and second layer wiring of the first metal 206 and the second metal 208. be able to. Further, the second signal holding circuit DM21 can be configured by MIM wiring using the third metal 210 on the upper part of the transistor.

The electrode 212 is electrically connected to the fourth metal 214 via a through hole 219d. Further, the fourth metal 214 is electrically connected to the reflective electrode PE via the through hole 219e. Therefore, the capacitance C1 is electrically connected to the reflective electrode PE.

Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels backward in the original incident path, and passes through the common electrode CE. It is emitted.

As shown in FIG. 13, the pixel Pix3 allocates the fifth metal 216 to the reflection electrode PE, so that the first signal holding circuit SM13, the second signal holding circuit DM21, and the reflecting electrode PE are arranged in the height direction. It becomes possible to arrange it effectively. Therefore, the pixel Pix3 can realize the pixel miniaturization. As a result, the pixel Pix3 can be composed of pixels having a pitch of, for example, 3 μm or less, with a transistor having a power supply voltage of 3.3 V. The pixels having a pitch of 3 μm can realize a liquid crystal display panel having a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

The pixel Pix3 performs the same operation as described with the timing diagram of FIG. 9 in the third embodiment.

First, the switch SW13 of the plurality of pixels Pix3 in one row selected by the normal rotation scanning pulse output from the timing generator 62 is turned on by the normal rotation scanning pulse. At that time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW13 and written to the first signal holding circuit SM13. Hereinafter, in the same manner, the forward rotation subframe gradation data is written to the first signal holding circuit SM13 of all the pixels Pix3 constituting the image display unit 61. At the timing after the writing operation is completed, the “H” level forward rotation trigger pulse TRIG and the “L” level reverse rotation trigger pulse TRIGB are simultaneously supplied to all the pixels Pix3 constituting the image display unit 61.

As a result, the switches SW21 of all the pixels Pix3 are turned on. Therefore, the forward rotation subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred to and held in the second signal holding circuit DM21 via the switch SW21. At the same time, the normal rotation subframe gradation data is applied to the reflection electrode PE. The retention period of the normal rotation subframe gradation data by the second signal holding circuit DM21 is one subframe until the next "H" level forward rotation trigger pulse TRIG and "L" level reverse rotation trigger pulse TRIGB are input. It is a period.

Subsequently, each pixel Pix3 in the image display unit 61 is selected in row units by the normal rotation scanning pulse in the same manner as described above, and each pixel Pix3 has the inverse logic value of the immediately preceding normal rotation subframe gradation data. Inverted subframe gradation data is written to the first signal holding circuit SM13. When the writing of the inverted subframe gradation data to the first signal holding circuit SM13 of all the pixels Pix3 of the image display unit 61 is completed, the “H” level forward rotation trigger pulse TRIG and the “L” level inverted trigger pulse TRIGB Is supplied to all pixels Pix3 at the same time.

As a result, the switches SW21 of all the pixels Pix3 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred to and held in the second signal holding circuit DM21 via the switch SW21. At the same time, the inverted subframe gradation data is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data by the second signal holding circuit DM21 is one subframe period until the next “H” level forward rotation trigger pulse TRIG and “L” level inverted trigger pulse TRIGB are supplied. Is.

The switch SW13 may be composed of a polyclonal transistor. In that case, since it may be considered as having the opposite polarity to the above description, the illustration and description will be omitted.

Further, the switch SW13 may be a transmission gate composed of a polyclonal transistor and an nanotube transistor.

Further, the switch SW21 may be composed of a polyclonal transistor or an nanotube transistor.

(summary)
The pixel Pix3 has the same effect as the pixels Pix1 and Pix2 of the third and fourth embodiments.

In addition, the pixel Pix3 has the effect of being able to be miniaturized.

<Sixth Embodiment>
FIG. 14 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the sixth embodiment.

Among the components of the pixel Pix4 of the reflective liquid crystal display device of the sixth embodiment, the same components as the pixels Pix1 to Pix3 of the third to fifth embodiments are designated by the same reference numerals. Therefore, the description is omitted.

The pixel Pix4 is provided at the intersection of an arbitrary single column data line d, and an arbitrary pair of row scanning lines g and an inverted row scanning line gb.

The pixel Pix4 includes a first memory 131 and a second memory 132, and a liquid crystal display element LC. The first memory 131 includes a switch SW31 and a first signal holding circuit DM31. The second memory 132 includes a switch SW32 and a second signal holding circuit SM32.

In the pixel Pix4, the first memory 131 is composed of DRAM, and the second memory 132 is composed of SRAM.

The switch SW31 corresponds to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit DM31 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 131 corresponds to an example of the "first dynamic random access memory" of the present disclosure. The switch SW32 corresponds to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit SM32 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 132 corresponds to an example of the "first static random access memory" of the present disclosure.

The switch SW31 is a known transmission gate composed of an IGMP transistor Tr31 and a polyclonal transistor Tr32 in which drains of each other are connected to each other and sources of each other are connected to each other. The gate of the MIMO transistor Tr31 is connected to the row scan line g, and the gate of the polyclonal transistor Tr32 is connected to the inverted row scan line gb.

Further, in the switch SW31, one terminal is connected to the column data line d, and the other terminal is connected to the first signal holding circuit DM31. Therefore, the switch SW31 is turned on when the forward scan pulse is at the “H” level (in this case, the reverse scan pulse is at the “L” level), and reads out the gradation data of the column data line d. Is transferred to the first signal holding circuit DM31. Further, the switch SW31 is turned off when the forward scan pulse is at the “L” level (in this case, the reverse scan pulse is at the “H” level), and the gradation data of the column data line d is read out. Do not do.

Since the switch SW31 is a known transmission gate composed of the IGMP transistor Tr31 and the polyclonal transistor Tr32, it is possible to turn on / off a voltage in the range from the reference voltage GND to the power supply voltage VDD. That is, when the signal applied to the gates of the MIMO transistor Tr31 and the polyclonal transistor Tr32 is the voltage (“L” level) on the reference voltage GND side, the polyclonal transistor Tr32 cannot conduct. Instead, the IGMP transistor Tr31 can conduct with low resistance. On the other hand, when the signal applied to the gates of the nanotube transistor Tr31 and the polyclonal transistor Tr32 is the voltage on the power supply voltage VDD side (“H” level), the norx transistor Tr31 cannot conduct. Instead, the polyclonal transistor Tr32 can conduct with low resistance. Therefore, the voltage range from the reference voltage GND to the power supply voltage VDD is set to low resistance and high resistance by controlling the transmission gate constituting the switch SW31 on / off by the forward rotation scan pulse and the reverse rotation scan pulse. Can be switched with.

The first signal holding circuit DM31 is composed of the capacitance C2. Here, a case where the gradation data of the column data line d and the gradation data of the first signal holding circuit DM31 are different will be examined. When the switch SW31 is turned on and the gradation data of the column data line d is transferred to the first signal holding circuit DM31, the gradation data of the first signal holding circuit DM31 is the gradation data of the column data line d. Needs to be rewritten.

When the gradation data of the capacitance C2 constituting the first signal holding circuit DM31 is rewritten, the gradation data changes by charging or discharging. When the gradation data of the column data line d is transferred to the capacitance C2, the gradation data is written by the charge transfer between the data line capacitance of the column data line d and the capacitance C2. Usually, the capacity ratio of the data line capacity of the column data line d and the capacity C2 is as large as about 1000: 1. Therefore, the pixel Pix4 can surely rewrite the gradation data of the capacitance C2.

The switch SW32 is a known transmission gate composed of an IGMP transistor Tr33 and a polyclonal transistor Tr34 in which drains of each other are connected to each other and sources of each other are connected to each other. The gate of the IGMP transistor Tr33 is connected to the trigger line trig, and the gate of the polyclonal transistor Tr34 is connected to the inverting trigger line trigb.

Further, in the switch SW32, one terminal is connected to the first signal holding circuit DM31 and the other terminal is connected to the second signal holding circuit SM32. Therefore, the switch SW32 is turned on when the forward rotation trigger pulse TRIG is at the “H” level (in this case, the reverse rotation trigger pulse TRIGB is at the “L” level), and the gradation data of the first signal holding circuit DM31 is turned on. Is read and transferred to the second signal holding circuit SM32. Further, the switch SW32 is turned off when the forward rotation trigger pulse TRIG is at the “L” level (in this case, the reverse rotation trigger pulse TRIGB is at the “H” level), and the gradation data of the first signal holding circuit DM31 is turned on. Is not read.

The second signal holding circuit SM32 is a self-holding memory composed of two inverters INV33 and INV34 in which one output terminal is connected to the other input terminal. The input terminal of the inverter INV33 is connected to the output terminal of the inverter INV34 and the reflection electrode PE. The input terminal of the inverter INV34 is connected to the output terminal of the inverter INV33 and the switch SW32.

For each of the inverters INV33 and INV34, the configuration of a CMOS inverter (see FIG. 7) is exemplified.

Data writing to the second signal holding circuit SM32 is performed via one switch SW32 as described above. In this case, the transistor in the inverter INV34 on the input side when viewed from the switch SW32 uses a transistor having a larger driving force than the transistor in the inverter INV33 on the output side when viewed from the switch SW32. Further, as the transistor constituting the switch SW32, a transistor having a larger driving force than the transistor constituting the inverter INV33 is used. As a result, in the second signal holding circuit SM32, data is easily input from the capacitance C2, and data is difficult to be input from the liquid crystal display element LC.

When the switch SW32 is turned on, the electric charge stored in the capacitance C2 drives the input gate of the inverter INV34 and rewrites the gradation data of the second signal holding circuit SM32. When the switch SW32 is turned on, the output of the inverter INV33 may affect the capacitance C2. However, the capacity on the input side of the inverter INV33 is only the gate capacity constituting the inverter INV33 and the liquid crystal capacity of the liquid crystal display element LC, and the capacity is significantly larger than the gate capacity and capacity C2 constituting the input of the inverter INV34. Few. Further, the driving force of the inverter INV34 is set to be larger than that of the inverter INV33. Therefore, the drive of the inverter INV34 by the capacitance C2 is prioritized over the output of the inverter INV33, and the gradation data of the capacitance C2 is not rewritten by the gradation data of the second signal holding circuit SM33.

Further, the gradation data of the capacitance C2 is a charge transfer from the column data line d. In addition, the influence of gate feedthrough and the like that occur at the timing when the IGMP transistor and the polyclonal transistor constituting the switch SW31 are turned off occurs. Therefore, the potential of the capacitance C2 is fixed with the potential fluctuation, and the voltage deviates from the reference voltage GND and the power supply voltage VDD in the direction of reducing the dynamic range. However, the voltage finally applied to the reflective electrode PE is shaped by the second signal holding circuit SM33, and an accurate reference voltage GND or a power supply voltage VDD is applied. Therefore, the pixel Pix4 can widen the dynamic range.

Further, when light hits the diffusion electrode portion of the transistor constituting the switch SW31 and SW32 connected to the capacitance C2, a leak current is generated, the charge held in the capacitance C2 is reduced, and the potential fluctuation may occur.

However, the voltage held in the capacitance C2 is for driving the second signal holding circuit SM33. Therefore, even if the voltage held in the capacitance C2 fluctuates to some extent, it is reflected unless the second signal holding circuit SM33 fluctuates beyond the threshold value at which the gradation data can be held at the “L” level or the “H” level. It does not affect the voltage of the electrode PE. At this time, the voltage of the reflective electrode PE applied to the liquid crystal display LCM is supplied from the second signal holding circuit SM33. When the voltage of the reflective electrode PE is “H” level, the polyclonal transistor in the inverter INV34 constituting the second signal holding circuit SM33 is turned on, and the power supply voltage VDD is applied to the reflective electrode PE. When the voltage of the reflective electrode PE is at the “L” level, the IGMP transistor in the inverter INV34 constituting the second signal holding circuit SM33 is turned on, and the reference voltage GND is applied. Therefore, the voltage of the reflective electrode PE is not affected by the leakage current due to light, and the reflective electrode PE can apply a stable voltage to the liquid crystal LCM.

As described above, even if the voltage of the capacitance C2 fluctuates slightly due to charge transfer, gate feedthrough, optical leakage, etc., there is a problem if the gradation data of the second signal holding circuit SM33 can be rewritten. do not have.

Therefore, the switch SW31 that constitutes the first memory 131 and the switch SW32 that constitutes the second memory 132 do not have to be complementary switches that use an IGMP transistor and a polyclonal transistor.

For example, consider the case where the switch SW31 and the switch SW32 are composed of only an HCl transistor. In this case, the switch SW31 and the switch SW32 can pass the "H" level voltage of the input signal only up to VDD-Vth including the substrate effect. That is, when the switch SW31 is composed of only an NaCl transistor, the voltage a at the connection point between the switch SW31 and the capacitance C2 is equal to or less than VDD-Vth even if a voltage of 3.3 V is supplied to the column data line d. For example, it becomes 2.5V. Therefore, a voltage of 2.5V is stored in the capacitance C2. Next, the switch SW32 is turned on to rewrite the gradation data of the second signal holding circuit SM33. When the switch SW32 is also composed of only an NaCl transistor, the voltage b at the connection point between the switch SW32 and the second signal holding circuit SM33 is 2.5V, similarly to the voltage a. However, if the voltage b is 1.65 V or more of VDD / 2, it is possible to input an “H” level to the second signal holding circuit SM33 (apply an “L” level to the output reflecting electrode PE). can. Therefore, the second signal holding circuit SM33 can write both "H" level gradation data and "L" level gradation data.

When the switch SW31 and the switch SW32 are composed of only a polyclonal transistor, the voltage range not input is the reverse of the above.

As described above, the switch SW31 and the switch SW32 may be a switch using one MOS transistor instead of the complementary switch. In this case, since the number of transistors constituting one pixel is reduced, the pixel Pix4 has an effect that it can be further miniaturized.

A voltage that is logically inverted from the voltage of the capacitance C2 is applied to the reflective electrode PE. Therefore, as the gradation data to be written to the pixel Pix4, it is necessary to input the inverted data of the data (voltage) to be applied to the reflective electrode PE.

The pixel Pix4 has the effect that the pixel can be miniaturized. The first reason is as follows. Each of the inverters INV33 and INV34 is composed of two transistors. Therefore, the pixel Pix4 is composed of a total of eight transistors and one capacitance C1, and can be composed of a smaller number of elements than the pixel Pix1 (a total of 12 transistors) and the pixel Pix2 (a total of 10 transistors). Because. Further, in addition to the first reason, the second reason is that the first signal holding circuit DM31, the second signal holding circuit SM32, and the reflective electrode PE are effective in the height direction of the element, as described below. This is because it can be placed in.

FIG. 15 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the sixth embodiment.

As the capacity C2, a MIM capacity, a diffusion capacity, a PIP capacity, or the like can be used. FIG. 15 shows a cross-sectional configuration of a reflective liquid crystal display device in the case where the capacitance C2 is configured by MIM.

In FIG. 15, on the N-well 201 formed on the silicon substrate 200, the polyclonal transistor PTr11 of the inverter INV33 to which the drains are connected by making the diffusion layer common, and the polyclonal transistor Tr2 of the switch SW32 are formed. ing. Further, on the P-well 202 formed on the silicon substrate 200, an IMS transistor NTr11 of an inverter INV33 to which drains are connected by sharing a diffusion layer as a drain and an nanotube transistor Tr1 of a switch SW32 are formed. It has been. Note that FIG. 15 does not show the nanotube transistor and the polyclonal transistor constituting the inverter INV34.

Further, an interlayer insulating film 205 is interposed between the metals above the polyclonal transistors Tr2 and PTr11, and above the nanotube transistors NTr11 and Tr1, and the first metal 206, the second metal 208, the third metal 210, and the electrode 212 are provided. The fourth metal 214 and the fifth metal 216 are laminated. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel. Each diffusion layer constituting each drain of the IGMP transistor and the polyclonal transistor (not shown), the gate electrode of the nanotube transistor NTr11, and the gate electrode of the polyclonal transistor PTr11 are connected to each other via a contact (not shown). Each of the 1 metal 206 is electrically connected. Further, the diffusion layer and the gate electrode are electrically connected to the second metal 208, the third metal 210, the fourth metal 214 and the fifth metal 216 via through holes 219a, 219b, 219c and 219e. Has been done. That is, each drain of the MIMO transistor and the polyclonal transistor constituting the inverter INV34 (not shown) is electrically connected to the reflection electrode PE.

Further, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216), and is arranged so as to be separated from the common electrode CE which is a transparent electrode. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form a liquid crystal display element LC.

Here, the electrode 212 is formed on the third metal 210 via the interlayer insulating film 205. The electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute the capacitance C2.

When the capacitance C2 is configured by MIM, the second signal holding circuit SM32, the switch SW31 and the switch SW32 are composed of a transistor on the silicon substrate 200 and a first and second layer wiring of the first metal 206 and the second metal 208. be able to. Further, the first signal holding circuit DM31 can be configured by MIM wiring using the third metal 210 on the upper part of the transistor.

The electrode 212 is electrically connected to the fourth metal 214 via the through hole 219d. Further, the fourth metal 214 is electrically connected to the switches SW31 and SW32 at a place (not shown).

Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels backward in the original incident path, and passes through the common electrode CE. It is emitted.

As shown in FIG. 15, the pixel Pix4 allocates the fifth metal 216 to the reflection electrode PE, so that the first signal holding circuit DM31, the second signal holding circuit SM32, and the reflecting electrode PE are arranged in the height direction. It becomes possible to arrange it effectively. Therefore, the pixel Pix4 can realize the pixel miniaturization. As a result, the pixel Pix4 can be composed of pixels having a pitch of, for example, 3 μm or less, with a transistor having a power supply voltage of 3.3 V. The pixels having a pitch of 3 μm can realize a liquid crystal display panel having a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

The pixel Pix4 performs the same operation as described with the timing diagram of FIG. 9 in the third embodiment.

First, in the plurality of pixels Pix4 in one row selected by the forward-transit scan pulse and the reverse-transit scan pulse output from the timing generator 62, the switch SW31 is turned on by the forward-transit scan pulse and the reverse-transit scan pulse. Become. At that time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW31 and written to the first signal holding circuit DM31. Hereinafter, in the same manner, the forward rotation subframe gradation data is written to the first signal holding circuit DM31 of all the pixels Pix4 constituting the image display unit 61. At the timing after the writing operation is completed, the “H” level forward rotation trigger pulse TRIG and the “L” level reverse rotation trigger pulse TRIGB are simultaneously supplied to all the pixels Pix 4 constituting the image display unit 61.

As a result, the switches SW32 of all the pixels Pix4 are turned on. Therefore, the forward rotation subframe gradation data stored in the first signal holding circuit DM31 is collectively transferred to and held in the second signal holding circuit SM32 via the switch SW32. At the same time, the normal rotation subframe gradation data is applied to the reflection electrode PE. The retention period of the normal rotation subframe gradation data by the second signal holding circuit SM32 is one subframe until the next "H" level forward rotation trigger pulse TRIG and "L" level reverse rotation trigger pulse TRIGB are input. It is a period.

Subsequently, each pixel Pix4 in the image display unit 61 is selected row by row by the forward rotation scan pulse and the reverse rotation scan pulse in the same manner as described above. Then, the immediately preceding normal rotation subframe gradation data and the reverse logic value inversion subframe gradation data are written in the first signal holding circuit DM31. When the writing of the inverted subframe gradation data to the first signal holding circuit DM31 of all the pixels Pix4 of the image display unit 61 is completed, the “H” level forward rotation trigger pulse TRIG and the “L” level inverted trigger pulse TRIGB Is supplied to all pixels Pix4 at the same time.

As a result, the switches SW32 of all the pixels Pix4 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit DM31 is collectively transferred to and held in the second signal holding circuit SM32 via the switch SW32. At the same time, the inverted subframe gradation data is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data by the second signal holding circuit SM32 is one subframe period until the next “H” level forward rotation trigger pulse TRIG and “L” level inverted trigger pulse TRIGB are supplied. Is.

(summary)
The pixel Pix4 has the same effect as the pixels Pix1 to Pix3 of the third to fifth embodiments.

In addition, the pixel Pix4 has the effect of being able to be miniaturized.

<7th embodiment>
FIG. 16 is a diagram showing a circuit configuration of pixels of the reflective liquid crystal display device according to the seventh embodiment.

Among the components of the pixel Pix 5 of the reflective liquid crystal display device of the seventh embodiment, the same components as the pixels Pix 1 to Pix 4 of the third to sixth embodiments are designated by the same reference numerals. Therefore, the description is omitted.

The pixel Pix5 is provided at the intersection of an arbitrary one column data line d and an arbitrary one row scanning line g.

The pixel Pix 5 includes a first memory 141 and a second memory 142, and a liquid crystal display element LC. The first memory 141 includes a switch SW41 and a first signal holding circuit DM41. The second memory 142 includes a switch SW42 and a second signal holding circuit DM42.

In the pixel Pix5, the first memory 141 and the second memory 142 are composed of DRAM.

The switch SW41 corresponds to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit DM41 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 141 corresponds to an example of the "first dynamic random access memory" of the present disclosure. The switch SW42 corresponds to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit DM42 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 142 corresponds to an example of the "second dynamic random access memory" of the present disclosure.

The switch SW41 is composed of an NaCl transistor in which the gate is connected to the row scan line g, the drain is connected to the column data line d, and the source is connected to the first signal holding circuit DM11.

The first signal holding circuit DM41 is composed of the capacitance C3. Here, a case where the gradation data of the column data line d and the gradation data of the first signal holding circuit DM41 are different will be examined. When the switch SW41 is turned on and the gradation data of the column data line d is transferred to the first signal holding circuit DM41, the gradation data of the first signal holding circuit DM41 is used as the gradation data of the column data line d. Needs to be rewritten.

When the gradation data of the capacitance C3 constituting the first signal holding circuit DM41 is rewritten, the gradation data changes by charging or discharging. When the gradation data of the column data line d is transferred to the capacity C3, the gradation data is written by charge transfer between the data line capacity of the column data line d and the capacity C3. Usually, the capacity ratio of the data line capacity of the column data line d and the capacity C3 is as large as about 1000: 1. Therefore, the pixel Pix5 can surely rewrite the gradation data of the capacitance C3.

The switch SW42 is composed of an NaCl transistor in which the gate is connected to the trigger line trig, the drain is connected to the first signal holding circuit DM41, and the source is connected to the second signal holding circuit DM42 and the reflecting electrode PE. ..

The second signal holding circuit DM42 is composed of the capacitance C4. Here, a case where the gradation data of the first signal holding circuit DM41 and the gradation data of the second signal holding circuit DM42 are different will be examined. When the switch SW42 is turned on and the capacitance C3 and the capacitance C4 are electrically connected, it is necessary to rewrite the gradation data of the second signal holding circuit DM42 with the gradation data of the first signal holding circuit DM41.

When the charge level of the capacitance C3 (gradation data of the first signal holding circuit DM41) and the charge level of the capacitance C4 (gradation data of the second signal holding circuit DM42) are different, the charge is neutralized. Therefore, in the present disclosure, the capacity C3 is made larger than the capacity C4. That is, C3> C4. For example, when the capacity C3 holds the “H” level gradation data and the capacity C4 holds the “L” level gradation data, charge neutralization occurs. However, by setting C3> C4, even if the charge is neutralized, the neutralized voltage can be made higher than the threshold voltage. That is, "H" level gradation data can be written in the capacitance C4. As a result, the pixel Pix5 can reliably rewrite the gradation data of the capacity C4 with the gradation data of the capacity C3.

The switches SW41 and SW42 may be composed of a polyclonal transistor. In that case, since it may be considered as having the opposite polarity to the above description, the illustration and description will be omitted.

Further, the switches SW41 and SW42 may be transmission gates composed of a polyclonal transistor and an NaCl transistor.

The pixel Pix5 has the effect of being able to be miniaturized. The first reason is as follows. The pixel Pix5 is composed of a total of two transistors and two capacitances C3 and C4. That is, the pixel Pix5 includes pixelPix1 (12 transistors in total), Pix2 (10 transistors in total), Pix3 (7 transistors in total and 1 capacitance), and Pix4 (8 transistors in total). It can be composed of a smaller number of elements (capacity of one). The second reason is that, as described below, the first signal holding circuit DM41, the second signal holding circuit DM42, and the reflection electrode PE can be effectively arranged in the height direction of the element.

FIG. 17 is a diagram showing a cross-sectional configuration of pixels of the reflective liquid crystal display device according to the seventh embodiment.

As the capacities C3 and C4, MIM capacities, Diffusion capacities, PIP capacities and the like can be used. FIG. 17 shows a cross-sectional configuration of a reflective liquid crystal display device in the case where the capacitances C3 and C4 are configured by MIM.

In FIG. 17, the µtransistor of the switch SW41 is formed on the P well 202 formed on the silicon substrate 200. The drain of the nanotube transistor of the switch SW41 is electrically connected to the column data line d (not shown) via the contact 218a and the first metal 206.

Further, an µtransistor of the switch SW42 is formed on the P well 203 formed on the silicon substrate 200. The drain of the IGMP transistor of the switch SW42 is electrically connected to the source of the IGMP transistor of the switch SW41 via the contact 218b and the first metal 206.

Further, an interlayer insulating film 205 is interposed between the metals above the MIMO transistor of the switch SW41 and the HCl transistor of the switch SW42, and the first metal 206, the second metal 208, the third metal 210, the electrode 212, and the fourth metal are interposed. Metal 214 and fifth metal 216 are laminated. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel.

Further, a passivation film (PSV) 217 is formed as a protective film on the reflective electrode PE (fifth metal 216), and is arranged so as to be separated from the common electrode CE which is a transparent electrode. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE to form a liquid crystal display element LC.

Here, the electrodes 212a and 212b are formed on the third metal 210 via the interlayer insulating film 205. The electrode 212a, the third metal 210, and the interlayer insulating film 205 between the electrodes 212a and the third metal 210 constitute the capacitance C3. The electrode 212b, the third metal 210, and the interlayer insulating film 205 between the electrode 212b and the third metal 210 constitute the capacitance C4.

Here, the electrode 212a is larger than the electrode 212b. As a result, the capacity C3 becomes larger than the capacity C4. That is, C3> C4.

When the capacitances C3 and C4 are configured by MIM, the switch SW41 and the switch SW42 can be configured by the transistor on the silicon substrate 200 and the 1st and 2nd layer wirings of the 1st metal 206 and the 2nd metal 208. Further, the first signal holding circuit DM41 and the second signal holding circuit DM42 can be configured by MIM wiring using the third metal 210 on the upper part of the transistor.

The source of the nanotube transistor of the switch SW41 is electrically connected to the electrode 212a via the contacts 218c, through holes 219d, 219e, 219f and 219g. The third metal 210 facing the electrode 212a is electrically connected to the reference potential (ground potential) via the through hole 219h.

The source of the IGMP transistor of the switch SW42 is electrically connected to the electrode 212b via the contacts 218d, through holes 219j, 219k, 219l and 219m. The third metal 210 facing the electrode 212b is electrically connected to the reference potential (ground potential) via the through hole 219n. The electrode 212b is electrically connected to the reflective electrode PE via through holes 219m and 219o.

Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216), is reflected, travels backward in the original incident path, and passes through the common electrode CE. It is emitted.

As shown in FIG. 17, the pixel Pix5 enables the first signal holding circuit DM41, the second signal holding circuit DM42, and the reflecting electrode PE to be effective in the height direction by allocating the fifth metal 216 to the reflecting electrode PE. It will be possible to place it in. Therefore, the pixel Pix5 can realize the pixel miniaturization. As a result, the pixel Pix5 can be composed of pixels having a pitch of, for example, 3 μm or less, with a transistor having a power supply voltage of 3.3 V. The pixels having a pitch of 3 μm can realize a liquid crystal display panel having a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

The pixel Pix5 performs the same operation as described with the timing diagram of FIG. 9 in the third embodiment.

First, the switch SW41 of the plurality of pixels Pix5 in one row selected by the normal rotation scanning pulse output from the timing generator 62 is turned on by the normal rotation scanning pulse. At that time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW41 and written to the first signal holding circuit DM41. Hereinafter, in the same manner, the forward rotation subframe gradation data is written to the first signal holding circuit DM41 of all the pixels Pix5 constituting the image display unit 61. At the timing after the writing operation is completed, the “H” level forward rotation trigger pulse TRIG is simultaneously supplied to all the pixels Pix 5 constituting the image display unit 61.

As a result, the switches SW42 of all the pixels Pix5 are turned on. Therefore, the forward rotation subframe gradation data stored in the first signal holding circuit DM41 is the switch SW4.
It is transferred and held all at once to the second signal holding circuit DM42 via 2. At the same time, the normal rotation subframe gradation data is applied to the reflection electrode PE. The retention period of the forward rotation subframe gradation data by the second signal retention circuit DM42 is one subframe period until the next “H” level forward rotation trigger pulse TRIG is input.

Subsequently, each pixel Pix5 in the image display unit 61 is selected in line units by the normal rotation scanning pulse in the same manner as described above, and each pixel Pix5 has the inverse logic value of the immediately preceding forward rotation subframe gradation data. Inverted subframe gradation data is written to the first signal holding circuit DM41. When the writing of the inverted subframe gradation data to the first signal holding circuit DM41 of all the pixels Pix5 constituting the image display unit 61 is completed, the “H” level forward rotation trigger pulse TRIG constitutes the image display unit 61. It is supplied to all pixels Pix5 at the same time.

As a result, the switches SW42 of all the pixels Pix5 are turned on. Therefore, the inverted subframe gradation data stored in the first signal holding circuit DM41 is the switch SW4.
It is transferred and held all at once to the second signal holding circuit DM42 via 2. At the same time, the inverted subframe gradation data is applied to the reflection electrode PE. The retention period of the inverted subframe gradation data by the second signal retention circuit DM42 is one subframe period until the next “H” level forward rotation trigger pulse TRIG is supplied.

(summary)
The pixel Pix5 has the same effect as the pixels Pix1 to Pix4 of the third to sixth embodiments.

In addition, the pixel Pix5 has the effect of being able to be miniaturized. Although the pixel Pix5 may have the above-mentioned charge neutralization and has lower noise immunity than the SRAM, it can be further miniaturized as compared with the pixels Pix1 to Pix4. Therefore, it may be determined which of the pixels Pix1 to Pix5 is adopted according to the specifications required for the reflective liquid crystal display device 13 (for example, miniaturization priority, noise immunity priority, etc.).

<Additional Notes>
In the reflective liquid crystal display device 13 shown in FIG. 3, the pixels of the portion 13a to which the plurality of diffused wavelength channels are incident are inverted every subframe period. However, the pixels of the portion (frame portion) 13b where the diffused plurality of wavelength channels are not incident need not be inverted for each subframe. From the viewpoint of power consumption, it is better to reduce the number of inversions.

Therefore, the common electrode CE may be divided into a portion 13a and a portion 13b and driven separately to reduce the number of inversions in the portion 13b. In this case, it is preferable that the portion 13a is inverted for each subframe, but the portion 13b is not inverted by a predetermined number of frames (in other words, the inversion is performed for each predetermined number of frames).

In this case, when the pixel of the portion 13b has a configuration like the pixel Pix3 (see FIG. 12), the potential of the reflective electrode PE drops when there is a charge leak in the capacitance C1. Therefore, it is preferable to turn on the forward rotation trigger pulse TRIG and the reverse rotation trigger pulse TRIGB at regular time intervals to perform the rewriting operation to the capacitance C1. Alternatively, it is preferable to reduce the number of predetermined frames until inversion as compared with other pixel circuit configurations.

Further, it is better to write the portion 13b to the first memory immediately before the inversion as much as possible. This is because when the contents of the first memory 111 and the second memory 121 are inverted, a leak current is generated through the switch SW21 and the power consumption increases.

In the configuration of pixel Pix1 (see FIG. 6), writing to the first memory 91 can be performed earliest, so it is better to rewrite the contents of the first memory 91 immediately before.

The technical scope of the present invention is not limited to the above-described embodiment, and changes can be made as appropriate without departing from the spirit of the present invention.

10 WSS array 11 Input / output unit 12 Optical system 13 Reflective liquid crystal display device 16 Collimated lens 21, 22, 23 Lens 24 Dispersion element 61 Image display unit 62 Timing generator 63 Vertical shift register 64 Data latch circuit 65 Horizontal driver 65a Horizontal shift register 65b Latch circuit 65c Level shifter / pixel driver 81, 91, 111, 131, 141 First memory 81a, 82a, SW11a, SW11b, SW12a, SW12b, SW13, SW14, SW21, SW31, SW32, SW41, SW42 Switch 81b, SM11, SM13, DM31, DM41 1st signal holding circuit 82, 92, 112, 121, 132, 142 2nd memory 82b, SM12, SM14, DM21, SM32, DM42 2nd signal holding circuit INV1, INV2, INV3, INV4, INV11, INV12, INV13, INV14, INV33, INV34 Inverter Pix, Pix1, Pix2, Pix3, Pix4, Pix5 Pixel PT1, PT2 FIGURE Transistor NT1, NT2 NOTE Transistor C1, C2, C3, C4 Capacitive LC LCD Display Element LC Common electrode

Claims (5)

An input / output unit having an input port for incident light and an output port for emitting emitted light corresponding to each wavelength included in the incident light.
A wavelength disperser that spatially disperses the light of each wavelength included in the incident light according to each wavelength and emits the emitted light to the input / output unit side.
An optical coupler that collects the light of each wavelength dispersed by the wavelength disperser into a two-dimensional plane for each wavelength and emits the reflected light of each wavelength to the side of the wavelength disperser.
By arranging at the position of the two-dimensional plane, having a plurality of pixels, and expressing the gradation by the plurality of pixels, the light of each wavelength collected by the optical coupler is routed for each wavelength. A spatial light modulator that reflects in a fixed direction,
A spatial light modulator driving unit that drives the plurality of pixels of the spatial light modulator,
Equipped with
For the gradation, forward rotation gradation data is input to each of the plurality of pixels by the spatial light modulator drive unit in one subframe period of the plurality of subframe periods in which one frame period is divided. , Formed by inputting inverted gradation data in the other one subframe period of the plurality of subframe periods.
Each of the plurality of pixels
A first switching circuit that samples the forward gradation data or the reverse gradation data from the data line,
A first signal holding circuit that holds the forward gradation data or the reverse gradation data sampled by the first switching circuit.
A second switching circuit that samples the forward gradation data or the reverse gradation data held in the first signal holding circuit at a timing common to all of the plurality of pixels.
The forward rotation gradation data or the inversion gradation data sampled by the second switching circuit is held for one subframe period, and is applied to the reflection electrode of the liquid crystal display element, and the second signal holding circuit and the second signal holding circuit.
Equipped with
The spatial light modulator drive unit is
By inverting the voltage of the common electrode of the liquid crystal display element at the timing, a positive / negative AC voltage is applied to the liquid crystal of the liquid crystal display element.
A voltage having an amplitude different from the amplitude between the forward gradation data and the inverted gradation data is supplied to the common electrode.
The first switching circuit and the first signal holding circuit constitute a first static random access memory.
The second switching circuit and the second signal holding circuit constitute a first dynamic random access memory.
The second signal holding circuit is composed of a capacitance.
Optical node device. The second switching circuit is a complementary switching circuit composed of a P-channel type transistor and an N-channel type transistor.
The optical node device according to claim 1. The first signal holding circuit is composed of a first inverter and a second inverter in which one output terminal is connected to the other input terminal.
The driving force of the transistor constituting the first inverter on the input side when viewed from the first switching circuit side is larger than the driving force of the transistor constituting the second inverter on the output side when viewed from the first switching circuit. ,
The optical node device according to claim 2. The first switching circuit is composed of one transistor.
The driving force of the transistor constituting the first switching circuit is larger than the driving force of the transistor constituting the second inverter.
The optical node device according to claim 3. The spatial light modulator drive unit is
The number of frames of the pixels in the region where the light of the spatial light modulator is not incident is made smaller than the number of frames of the pixels in the region where the light of the spatial light modulator is incident.
The optical node device according to claim 1.

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