JP2022077978A - Method and device for smoothing dynamic random access memory bit wire metal - Google Patents

Abstract

To provide a method for smoothing an upper surface of a bit wire metal of a memory structure for reducing the resistance of a bit wire laminate.SOLUTION: A device 200 deposits a titanium layer 220 of about 30 angstroms to 50 angstroms on a polysilicon layer 215 on a substrate 210, deposits a first titanium nitride layer 230 of about 15 angstroms to about 40 angstroms on the titanium layer 220, anneals the substrate at a temperature of about 700°C to about 850°C, deposits a second titanium nitride layer 230 of about 15 angstroms to about 40 angstroms on the first titanium nitride layer 230 after annealing, deposits a bit wire metal layer 240 of ruthenium on the second titanium nitride layer 230, anneals the bit wire metal layer 240 at a temperature of about 550°C to about 650°C, and immerses the bit wire metal layer 240 in a hydrogen-based environment for about 3 to about 6 minutes during the annealing.SELECTED DRAWING: Figure 2

Description

[0001] The embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More specifically, embodiments of the present disclosure provide an electronic device comprising a bit wire having a smooth top surface and a method of forming the electronic device thereof.

The conductive interconnect layers of modern integrated circuits are generally of very fine pitch and high density. A single small defect in the precursor metal film that ultimately forms the metal interconnect layer of the integrated circuit can be arranged so as to seriously damage the integrity of the operation of the integrated circuit. Bit wire laminate deposition faces many potential problems. Surface reactions of metal and silicon nitride hardmasks can occur due to the high deposition temperatures that occur in the formation of hardmasks. Bit wire resistance can be increased by the mutual diffusion of silicon into the bit wire and by the metal atoms into the silicon nitride hardmask. In addition, grain-growth metals can be difficult to use due to the roughness of the metal surface caused by the high temperatures during formation.

Therefore, the inventor has provided a method and an apparatus for smoothing the upper surface of the bit wire metal.

A method and apparatus for smoothing the top surface of a bit wire metal are provided herein.

In some embodiments, the method of smoothing the top surface of the bit wire metal of the memory structure is to deposit a titanium layer of about 30 ongstroms to about 50 ongstroms on the polysilicon layer on the substrate. Placing a first titanium nitride layer of about 15 angstroms to about 40 ongstroms on the titanium layer, annealing the substrate at a temperature of about 700 ° C to about 850 ° C, and after annealing, the first titanium nitride layer. A second titanium nitride layer of about 15 ongstroms to about 40 ongstroms is deposited on top, a bit wire metal layer of ruthenium is deposited on the second titanium nitride layer, and the bit wire metal layer is about 550 degrees. It involves annealing at a temperature of about 650 degrees Celsius and immersing the bit wire metal layer in a hydrogen-based environment for about 3 to about 6 minutes during annealing.

In some embodiments, the method further deposits a cap layer on a bit wire metal layer at a deposition temperature of about 350 ° C to about 400 ° C and deposits above about 500 ° C on the cap layer. By depositing a hardmask layer at temperature, the cap layer comprises one or more of silicon nitride or silicon carbide, the cap layer is from about 30 ongstroms to about 50 ongstroms, and the cap layer is Hardmask layer is deposited by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, the hardmask layer contains silicon nitride and the hardmask layer is deposited by a low pressure chemical vapor deposition (LPCVD) process. Placing a layer and depositing a hardmask layer on a bit wire metal layer at a deposition temperature of less than approximately 400 ° C., the hardmask layer is deposited by a low pressure chemical vapor deposition (LPCVD) process. And / or include depositing a hardmask layer in which the bit wire metal layer has a squared average square root (RMS) top surface roughness of 1.15 nm or less.

In some embodiments, the method of forming the memory structure is to form a barrier metal layer on a polysilicon layer on the substrate and to coat the barrier metal layer at a temperature of about 700 ° C to about 850 ° C. Annealing, forming a barrier layer on the barrier metal layer, depositing a bit wire metal layer on the barrier layer, and annealing the bit wire metal layer at a temperature of about 550 to about 650 degrees. And immersing the bit wire metal layer in a hydrogen-based environment for about 3 to about 6 minutes during annealing.

In some embodiments, the method further comprises a titanium layer having a barrier metal layer of about 30 ongstroms to about 50 angstroms formed on the polysilicon layer, and a titanium layer of about 15 angstroms formed on the titanium layer. It is a titanium nitride layer of about 40 angstroms from, annealing the barrier metal layer forms a titanium silicate layer on the polysilicon layer, the barrier layer is a titanium nitride layer of about 15 angstroms to about 40 angstroms. There is a chemical vapor phase deposition at a deposition temperature of about 350 ° C to about 400 ° C, that the bit wire metal layer is a crystal grain growth metal layer with a squared mean square root (RMS) top surface roughness of 1.15 nm or less. A cap layer is formed on the bit wire metal layer using a (CVD) or atomic layer deposition (ALD) process, and a low pressure chemical vapor deposition (LPCVD) process is performed at deposition temperatures above approximately 500 ° C. Using to form a hard mask layer on the cap layer, the cap layer is from about 30 ongstroms to about 50 ongstroems, and / or at a deposition temperature of less than about 400 ° C., low pressure chemical vapor deposition (low pressure chemical vapor deposition). The LPCVD) process may be used to deposit a hard mask layer on a bit wire metal layer.

In some embodiments, the method of smoothing the top surface of the bit wire metal of the memory structure is to use a plasma vapor deposition (PVD) chamber and approximately 30 angstroms on the polysilicon layer on the substrate. The substrate is annealed at a temperature of about 700 ° C to about 850 ° C without vacuum breakdown between the deposition of the titanium layer of about 50 angstroms and the deposition of the titanium layer and the annealing of the substrate. And, after annealing, depositing a titanium nitride layer of about 15 angstroms to about 40 angstroms on the titanium layer, depositing a bit wire metal layer of ruthenium on the titanium nitride layer, and depositing a bit wire metal layer. Annening at a temperature of about 550 to about 650 degrees and about 3 to about 6 minutes during annealing so that the top surface of the bit wire metal has a squared mean square root (RMS) roughness of 1.15 nm or less. It involves immersing the bit wire metal layer in a hydrogen-based environment.

In some embodiments, the method is to deposit the cap layer on the bit wire metal layer at a deposition temperature of about 350 ° C to about 400 ° C, and on the cap layer at a deposition temperature greater than about 500 ° C. It may further include depositing a hardmask layer or depositing a hardmask layer on a bit wire metal layer at a deposition temperature of less than approximately 400 ° C.

Other embodiments and further embodiments are disclosed below.

The embodiments of the Principles briefly summarized above and detailed below can be understood by reference to the exemplary embodiments of the Principles shown in the accompanying drawings. However, as the Principle may tolerate other equally valid embodiments, the accompanying drawings exemplify only typical embodiments of the Principle and should therefore be considered limiting scope. not.

[0013] A circuit diagram of a dynamic memory cell in a DRAM memory having improved characteristics according to some embodiments of this principle is shown. [0014] A cross-sectional view of a membrane laminate according to some embodiments of this principle is shown. [0015] A method of forming a film laminate according to some embodiments of the present principle. [0016] A method of forming a film laminate having a smooth bit wire metal layer according to some embodiments of the present principle. It is sectional drawing of the barrier metal layer by some embodiment of this principle. It is a top-down diagram of a cluster tool according to some embodiments of this principle. It is a substrate manufacturing method according to some embodiments of this principle. It is sectional drawing of the substrate by some embodiment of this principle. [0021] A method of smoothing the upper surface of a bit wire metal layer according to some embodiments of the present principle.

For ease of understanding, the same reference number was used to point to the same element common to multiple figures, where possible. The figures are not drawn to scale and may be simplified for clarity. The elements and features of one embodiment may be beneficially incorporated into other embodiments without further description.

A bit wire laminate and a method for forming a bit wire laminate with reduced resistance and bit wire surface roughness are provided. One or more embodiments of the present disclosure advantageously address the problem of reduced resistance despite the need to shrink the node. In some embodiments, the resistance of the bit wire is reduced by providing a cleaner interface with the existing bit wire metal and by reducing the surface roughness of the bit wire metal. Some embodiments of the present disclosure advantageously ensure flexibility in the choice of bit wire metal, temperature flexibility for silicon nitride hardmask deposition, and a clean metal-dielectric interface that results in lower resistance. Or provide one or more of minimizing or eliminating the risk of contamination of the high temperature silicon nitride hardmask deposition chamber with new bit wire metal.

Some embodiments of the present disclosure provide a low temperature deposition method using a cap layer to prevent roughening of the bit wire metal surface when the selected metal exhibits grain growth properties. do. In some embodiments, the dense non-porous membrane is used to act as a good diffusion barrier at high temperatures. Some embodiments provide a dielectric material such as Silicon Nitride (SiN) or Silicon Carbonitride (SiCN) and act as a good diffusion barrier for bit wire metals and SiN hardmasks during RC. It acts as a cap film to minimize or eliminate adverse effects on the constant. Some embodiments include annealing the metal layer prior to deposition of the grain-growth metal to reduce the surface roughness of the grain-growth metal and reduce resistance. Some embodiments include annealing the grain growth material used for the bit wire metal layer to reduce surface roughness while maintaining low resistance. The RC time constant is the time associated with charging the capacitor through the resistor to a percentage of full charge, or the time to discharge the capacitor to a portion of the initial voltage. The RC time constant is equal to the product of circuit resistance and circuit capacitance. Some embodiments of the invention advantageously provide a deposition process at low temperatures (eg, less than 500 ° C.). Some embodiments provide a deposition process compatible with lower bit wire metals to minimize or eliminate surface reactions during membrane deposition.

One or more embodiments of the disclosure are generally one or more formed from a thin film refractory metal (eg, tungsten) so that they can be implemented in bit line structures and / or gate laminates. Provides a structure that includes low resistance features. Some embodiments include methods for forming bit line laminates. As an example, the bit line laminate structure formed according to the embodiments of the present disclosure may be a memory type semiconductor device such as a DRAM type integrated circuit.

FIG. 1 shows a schematic circuit diagram 100 of a one-transistor-one-capacitor cell that can be used in a DRAM memory. The memory cell shown in FIG. 1 includes a storage capacitor 110 and a selection transistor 120. The selection transistor 120 is formed as a field effect transistor and has a first source / drain electrode 121 and a second source / drain electrode 123 in which an active region 122 is arranged. Above the active region 122 is a gate insulating layer or dielectric layer 124, typically a thermal growth oxide, and a gate electrode / metal 125 (called a word line in a memory device), which are collectively a plate capacitor. And can affect the charge density in the active region 122 to form or block a current conduction channel between the first source / drain electrode 121 and the second source / drain electrode 123. ..

The second source / drain electrode 123 of the selection transistor 120 is connected to the first electrode 111 of the storage capacitor 110 via the metal wire 114. The second electrode 112 of the storage capacitor 110 is then connected to a capacitor plate that may be common to the storage capacitors in the DRAM memory cell arrangement. The second electrode 112 of the storage capacitor 110 can be connected to electrical ground via the metal wire 115. The first source / drain electrode 121 of the selection transistor 120 is further connected to the bit line 116 so that the information stored in the storage capacitor 110 in the form of electric charge can be written and read. The write or read operation is controlled via the word line 117 of the selection transistor 120 or the gate electrode 125 and the bit line 116 connected to the first source / drain electrode 121. The write or read operation occurs by applying a voltage to create a current conduction channel in the active region 122 between the first source / drain electrode 121 and the second source / drain electrode 123.

FIG. 2 shows a portion of the memory device 200 according to one or more embodiments of the present disclosure. FIG. 3 shows an exemplary processing method 300 for forming the memory device 200 shown in FIG. Those skilled in the art will recognize that the membrane laminate shown in the drawings is an exemplary portion (bit line portion) of a memory device. Referring to FIGS. 2 and 3, the formation of the memory device 200 includes providing a substrate 210 on which the film laminate 205 can be formed in step 310. As used herein and in the appended claims, the term "provided" means that the substrate is made available for processing (eg, placed in a processing chamber). means.

As used herein and in the appended claims, the term "substrate" refers to the surface or portion of the surface on which the treatment acts. Unless otherwise stated in the context, references to a substrate may refer only to a portion of the substrate. Further, reference to deposition on a substrate can mean both a bare substrate and a substrate on which one or more films or features are deposited or formed on the surface. As used herein, "substrate" refers to any substrate on which a film treatment is performed during the manufacturing process, or any material surface formed on the substrate. For example, the surface of the substrate on which the treatment can be performed may be silicon, silicon oxide, strained silicon, silicon on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, depending on the application. Includes materials such as gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to the pretreatment process in order to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In the present disclosure, in addition to performing the film treatment directly on the surface of the substrate, any of the disclosed film treatment steps are formed on the substrate, as will be described in more detail below. It may be carried out in the lower layer. The term "substrate surface" is intended to include such underlayers as described in the context. Therefore, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0030] In some embodiments, the substrate 210 provided comprises a film laminate 205 comprising a polysilicon layer 215 and a bit wire metal layer 240. In some embodiments, the provided substrate 210 comprises a polysilicon layer 215 and the bit wire metal layer 240 is formed as part of method 300. In some embodiments, the substrate 210 comprises an oxide layer (not shown) on a silicon wafer. In some embodiments, the oxide layer is a natural oxide formed on a silicon wafer. In some embodiments, the oxide layer is intentionally formed on a silicon wafer and has a thickness greater than the thickness of the natural oxide film. Oxide layers can be formed by any suitable technique known to those of skill in the art, including but not limited to thermal oxidation, plasma oxidation, and exposure to atmospheric conditions.

In some embodiments, the substrate 210 provided in step 310 further comprises a barrier metal layer 220 (also referred to as a conductive layer) on top of the polysilicon layer 215. The barrier metal layer 220 can be any suitable conductive material. In some embodiments, the barrier metal layer 220 comprises one or more of titanium (Ti), tantalum (Ta), titanium silicate (TiSi), or tantalum silicate (TaSi). In some embodiments, the barrier metal layer 220 comprises titanium. In some embodiments, the barrier metal layer 220 is essentially made of titanium. In some embodiments, the barrier metal layer 220 comprises or consists essentially of tantalum. In some embodiments, the barrier metal layer 220 comprises or consists essentially of titanium silicate. In some embodiments, the barrier metal layer 220 comprises or consists essentially of tantalum silicate. When used in this way, the term "essentially consisting of" means that the membrane of interest is about 95%, 98%, 99% or 99.9% or more of the stated elements on an atomic basis. Or it means to include a composition. For example, the barrier metal layer 220 essentially made of titanium has a film that is about 95%, 98%, 99% or 99.5% or more titanium at the time of deposition.

[0032] In some embodiments, the substrate 210 provided in step 310 further comprises a barrier layer 230 on a conductive layer (barrier metal layer 220). The barrier layer 230 can be formed between the barrier metal layer 220 and the bit wire metal layer 240. In some embodiments, the method 300 comprises a step prior to step 310 in which the bit wire metal layer 240 is formed on the barrier layer 230. The barrier layer 230 can be any suitable barrier layer material. In some embodiments, the barrier layer 230 comprises one or more of the nitrides or oxides of the barrier metal layer 220. In some embodiments, the barrier layer 230 consists essentially of the nitride of the barrier metal layer 220. For example, in the barrier layer 230 essentially made of titanium nitride, the sum of titanium atoms and nitrogen atoms in the film is about 95%, 98%, 99% or 99.5 of the barrier layer 230 on an atomic basis at the time of deposition. It means that it constitutes% or more.

[0033] In some embodiments, the barrier metal layer 220 comprises titanium (Ti) and the barrier layer 230 comprises titanium nitride (TiN). In some embodiments, the barrier metal layer 220 is essentially made of titanium and the barrier layer 230 is essentially made of titanium nitride. In one or more embodiments, the barrier metal layer 220 comprises cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), Selected from one or more of platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), or tungsten (W). Contains metal. In one or more specific embodiments, the barrier metal layer 220 (conductive material) is of titanium (Ti), copper (Cu), cobalt (Co), tungsten (W), or ruthenium (Ru). Includes one or more. In some embodiments, the barrier layer 230 comprises a metal nitride, oxynitride, carbonitride, or acid-carbonitride in the barrier metal layer 220. In some embodiments, the barrier metal layer 220 comprises (or essentially consists of) tantalum or silicified tantalum, and the barrier layer 230 comprises (or essentially consists of) tantalum nitride. In some embodiments, the barrier metal layer 220 comprises (or essentially consists of) titanium or titanium silicate, and the barrier layer 230 comprises (or essentially consists of) titanium nitride.

[0034] In some embodiments, the bit wire metal layer 240 is included in the substrate provided in step 310 of method 300. The bit wire metal layer 240 can be deposited by any suitable technique known to those of skill in the art. In some embodiments, the bit wire metal layer 240 is one of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). Including multiple. In some specific embodiments, the bit wire metal layer 240 comprises or consists essentially of one or more of ruthenium or tungsten. Ruthenium requires a different treatment to replace tungsten in the bit wire metal layer. Tungsten usually has a lower surface roughness and resistance than ruthenium. The inventor has discovered that the method described below improves the surface roughness of ruthenium while keeping its resistance low, allowing ruthenium to replace tungsten. The thickness of the bit wire metal layer 240 can be changed. In some embodiments, the bit wire metal layer 240 has a thickness ranging from about 100 Å to about 300 Å, or from about 120 Å to about 250 Å, or from about 140 Å to about 200 Å, or from about 160 Å to about 180 Å. Has a bit. The bit wire metal layer 240 can be deposited by any suitable technique known to those of skill in the art. In some embodiments, the bit wire metal layer 240 is deposited by one or more of chemical vapor deposition, atomic layer deposition or physical vapor deposition.

In step 320, the cap layer 250 is formed on the bit wire metal layer 240. The cap layer 250 of some embodiments is deposited at a lower temperature than would normally be used to form the subsequent hardmask 260 layer. Without being bound by any particular theory of operation, the inventor believes that lower deposition temperatures minimize the diffusion of the cap layer 250 elements into the bit wire metal layer 240. In some embodiments, the inventor has found that cold deposition of the cap layer 250 minimizes grain growth at the interface of the bit wire metal layer 240, resulting in grain size and roughness on the resistance of the bit wire metal layer 240. We believe that the impact of

The cap layer 250 can be deposited by any suitable technique known to those of skill in the art. In some embodiments, the cap layer 250 is deposited by one or more of chemical vapor deposition or atomic layer deposition. The cap layer 250 of some embodiments contains the same compounds as the subsequent hardmask 260. In some embodiments, the cap layer 250 comprises one or more of silicon nitride, silicon nitride or silicon carbide. In some embodiments, the cap layer 250 is essentially made of silicon nitride. In some embodiments, the cap layer 250 is essentially made of silicon nitride. In some embodiments, the cap layer 250 consists essentially of silicon carbide. The thickness of the cap layer 250 can be varied to minimize the effects of high temperature formation on the hard mask 260. In some embodiments, the cap layer 250 has a thickness in the range of about 30 Å to about 50 Å. The deposition temperature of the cap layer 250 can be controlled, for example, to maintain the heat balance of the formed device. In some embodiments, the cap layer 250 is formed at a temperature of about 500 ° C., or about 450 ° C., or about 400 ° C., or about 350 ° C., or about 300 ° C. or lower. In some embodiments, the cap layer 250 is formed at a temperature in the range of about 350 ° C to about 550 ° C, or from about 400 ° C to about 500 ° C.

In step 330, the hard mask 260 is formed on the cap layer 250. The hard mask 260 of some embodiments is formed in a furnace at a temperature above about 500 ° C., above about 600 ° C., above about 650 ° C., above about 700 ° C., or above about 750 ° C., some embodiments. In form, the hard mask 260 contains the same composition as the cap layer 250. In some embodiments, the cap layer 250 and the hard mask 260 include or essentially include silicon nitride, silicon oxide or silicon nitride. In some embodiments, the hardmask 260 has a different density than the cap layer 250. In some embodiments, the hard mask 260 has a different porosity than the hard mask 260. In some embodiments, the hardmask 260 has a different deposition temperature than the cap layer 250.

In some embodiments, the bit wire metal layer 240 comprises or consists essentially of tungsten, and one or more of the cap layer 250 or the hard mask 260 comprises silicon nitride. Or it consists essentially of silicon nitride. In some embodiments, the bit wire metal layer 240 comprises or consists essentially of ruthenium, and one or more of the cap layer 250 or the hard mask 260 comprises silicon oxide or silicon nitride. Or essentially composed of silicon oxide or silicon nitride. In some embodiments, the elements of the hardmask 260 are substantially prevented from moving into the bit wire metal layer 240. For example, when the hard mask 260 contains silicon and nitrogen atoms, the silicon or nitrogen atoms are substantially prevented from moving into the bit wire metal layer 240. When used in this way, the term "substantially prevented" means that less than 10% or less than 5% of the hardmask 260 elements move through the cap layer 250 into the bit wire metal layer 240. Means to do.

[0039] The inventor has discovered that when the grain growth metal is annealed prior to the formation of the cap layer 250 to reduce the resistance, the annealing will calcify the underlying barrier metal layer 220. bottom. Further, silicon is diffused into the barrier layer 230. Further stress generated by annealing the grain-growth metal causes the surface 232 of the barrier layer 230 to burst. When the grain-growth metal of the bitline metal layer 240 grows on the ruptured surface of the barrier layer 230, the ruptured surface of the barrier layer 230 also has a roughened top surface 242 of the bitline metal layer 240. To. The roughness of the upper surface 242 of the bit wire metal layer 240 directly affects the resistance of the bit wire metal layer 240. By annealing the barrier metal layer 220 prior to the formation of the barrier layer 230, the inventor has significantly reduced or eliminated the effect of calcification caused by the annealing of the grain-growth metal of the bit wire metal layer 240, wherein the barrier metal layer 220 is annealed. It was found that the upper surface 242 of the bit wire metal layer 240 became smoother and reduced the resistance.

FIG. 4 is a method 400 for forming a film laminate having a smooth bit wire metal layer 240. In step 402, the barrier metal layer 220 is formed on the polysilicon layer 215 on the substrate 210. In some embodiments, the barrier metal layer 220 initially deposits a conductive material 502 of about 30 angstroms to about 50 angstroms (eg, titanium, tantalum, etc.) and then an oxygen barrier of about 15 angstroms to about 40 angstroms. It is formed by depositing layer 504 (see 500 in FIG. 5). In the process of using separate chambers for deposition and annealing, the substrate 210 is exposed to the atmosphere as it is transferred between the chambers. The oxygen barrier layer 504 (eg, titanium nitride, tantalum nitride, etc.) prevents the conductive material 502 from oxidizing when the substrate 210 is transferred. In some embodiments, the integrated tool 600 shown in FIG. 6 can be used to provide a process without air intrusion between the deposition process and the annealing process. In embodiments with the integrated cluster tool 600, the oxygen barrier layer 504 deposition process can be removed because the substrate is never exposed to the atmosphere and the deposited conductive material 603 is never oxidized. Is.

In step 404, the barrier metal layer 220 is annealed at a temperature of about 700 ° C to about 850 ° C. The temperature can vary depending on the composition of the barrier metal layer 220. During the annealing of the barrier metal layer 220, the conductive material 502 may be calcined and the oxygen barrier layer 504 may move silicon through the oxygen barrier layer 504, causing the surface 506 to burst. The annealing of the barrier metal layer 220 has an improved surface roughness RMS (root mean square) (atomic force) of about 1.7 nm, as opposed to a surface roughness RMS of about 2.2 nm without the barrier metal layer annealing process. It provides a ruthenium bit wire metal layer with (measured by a microscope (AFM)). In step 406, the barrier layer 230 is formed on the barrier metal layer 220. The barrier layer 230 can be from about 15 angstroms to about 40 angstroms in thickness. Defects on the surface 506 are blocked by the deposition of the barrier layer 230, thereby helping to provide roughness and resistance. The barrier layer 230 may include, for example, a variant of the nitride of the conductive material 502 used for the barrier metal layer 220.

In step 408, the bit wire metal layer 240 is formed on the barrier layer 230. The bit wire metal layer 240 is composed of, but not limited to, grain growth metals such as ruthenium that grow on the surface of the barrier layer 230 using the hydrogen annealing process shown in Method 900 of FIG. Briefly, ruthenium is used in Method 900 as an exemplary grain-growth metal material, but is not intended to be limited. At block 902, a ruthenium bit wire metal layer is deposited on the substrate in the deposition chamber. The deposition chamber may include a physical vapor phase deposition chamber, a chemical vapor deposition chamber, an atomic layer deposition chamber, and the like. In some embodiments, the ruthenium bit wire metal layer can be from about 100 angstroms to about 300 angstroms in thickness. In some embodiments, the ruthenium bit wire metal layer can be approximately 200 angstroms in thickness.

In block 904, after the deposition process, the substrate is transferred to an annealing chamber, such as a rapid heat treatment (RTP) chamber. At block 906, the substrate is then annealed at a temperature of about 550 ° C to about 650 ° C. At block 908, during the annealing process, the substrate is immersed in a hydrogen-based environment for approximately 3 to approximately 6 minutes. A hydrogen-based environment is provided by hydrogen gas and / or hydrogen radicals. The hydrogen annealing process of Method 900 promotes the crystal grain growth of the ruthenium bit wire metal layer by predominantly horizontal growth at a slower reaction rate, resulting in lower resistance and a smoother top surface of the ruthenium ruthenium bit wire metal layer. Due to the slow reaction rate of the hydrogen annealing process, longer annealing times are used. The hydrogen annealing process of Method 900 further improves the surface roughness of the ruthenium bit wire metal layer from 1.7 nm RMS (RMS improvement using the barrier metal layer annealing process, see below) to 1.15 nm or less. .. In some embodiments, the ruthenium bit wire metal layer is annealed at 550 ° C. for about 4 minutes to obtain a surface roughness RMS of about 1.1 nm with a sheet resistance (Rs) of about 5.55 ohms / cm2. .. In some embodiments, the ruthenium bit wire metal layer is annealed at 600 ° C. for about 5 minutes to obtain a surface roughness RMS of about 1.15 nm with Rs of about 5.5 ohms / cm2. Increasing the soaking duration helps reduce Rs while maintaining surface smoothness. The inventor has found that by shortening the immersion duration, the increase in Rs can be sacrificed, but the surface roughness can be reduced. Similarly, increasing the soaking duration sacrifices an increase in surface roughness, but Rs can be improved. The balance is selected so that an acceptable Rs value is obtained with an acceptable surface roughness RMS value.

The hydrogen annealing process provides a 20% to 30% improvement in top surface smoothness over a typical nitrogen or argon annealing process, while further maintaining the resistance (Rs) level of the nitrogen or argon annealing process. Have. Better grain growth is obtained through a high energy annealing process to keep resistance low, and the hydrogen environment provides a smoother top surface. Increasing the soaking duration (compared to the nitrogen or argon annealing process) allows slower grain growth to maintain low resistance with a smoother top surface. By using a temperature above 700 ° C. for a long duration (eg, 7 minutes or more), an increase in surface roughness (eg, RMS at 1.4 nm) will be sacrificed, but the Rs value will decrease. Various levels of Rs and surface smoothness can be obtained by varying the three key parameters of the annealing process: duration, temperature, and ambient gas.

In step 410, the cap layer 250 is optionally formed on the bit wire metal layer 240 at a temperature of about 350 ° C to about 400 ° C. The low process temperature helps to maintain the heat balance of the membrane laminate 205 and reduce the roughness of the surface of the bit wire metal layer. The inventor has found that if the temperature is too low, the density of the cap layer 250 is insufficient, and if the temperature is too high, the surface roughness of the bit wire metal layer increases. The temperature also depends on the bit wire metal layer material and is adjusted as appropriate. In step 412, the hard mask 260 is formed on the cap layer 250 at a temperature of approximately 650 ° C. as described above when the cap layer 250 is present. In the absence of the cap layer, the hardmask 260 can be formed at temperatures below 400 ° C. to retain the heat balance of the membrane laminate 205. The low temperatures used to form the hardmask 260 in the absence of the cap layer 250 increase the deposition time (eg, the hardmask can be approximately 1350 angstroms thick) and the lower density of the hardmask 260. Is a trade-off.

The methods described herein that are performed in a separate process can also be performed with a cluster tool, such as the cluster tool 600 or integrated tool described below with respect to FIG. The advantage of using the Cluster Tool 600 is that there is no vacuum break between deposition and processing and there is virtually no process lag. Examples of the Cluster Tool 600 include Applied Materials, Inc. of Santa Clara, California. Includes ENDURA® integrated tools commercially available from. However, the methods described herein can be practiced using other cluster tools with suitable processing chambers or within other suitable processing chambers. For example, in some embodiments, the original method described above may be advantageously implemented within a cluster tool so that there is no vacuum break between processes. For example, elimination of vacuum fracture can limit or prevent substrate contamination (oxidation) between processes.

FIG. 6 is a diagram of a cluster tool 600 configured for substrate manufacturing such as post-polyplug manufacturing. The cluster tool 600 includes one or more transfer modules (VTM; VTM601 and VTM602 shown in FIG. 6), a front-end module 604, and a plurality of processing chambers / modules 606, 608, 610, 612, 614, 616, and 618 and a process controller (controller 620) are included. In embodiments with more than one VTM as shown in FIG. 6, one or more pass-through chambers may be provided to facilitate vacuum transfer from one VTM to another. In an embodiment consistent with that shown in FIG. 6, two pass-through chambers may be provided (eg, pass-through chamber 640 and pass-through chamber 642). The front-end module 604 is configured to receive one or more substrates that will be processed using the Cluster Tool 600, for example from a FOUP (front opening unified pod) or other suitable substrate containing box or carrier. Includes the loaded loading port 622. The loading port 622 includes three loading areas 624a-624c, which can be used to load one or more boards. However, more or less loading areas may be used.

The front-end module 604 includes an atmospheric transfer module (ATM) 626 used to transfer the substrate loaded onto the loading port 622. More specifically, the ATM 626 is one or more robots configured to transfer the substrate from the loading area 624a-624c to the ATM 626 through a door 635 (indicated by a phantom) connecting the ATM 626 to the loading port 622. Includes arm 628 (indicated by phantom). Typically, there is one door for each loading port (624a-624c), allowing board transfer from individual loading ports to ATM626. The robot arm 628 is also configured to transfer the substrate from the ATM 626 to the airlocks 630a, 630b through a door 632 (indicated by a phantom, one for each airlock) that connects the ATM 626 to the airlocks 630a, 630b. Has been done. The number of airlocks may be more than or less than two, but for illustration purposes only, two airlocks (630a and 630b) are shown, each airlock connecting the airlock to the ATM 626. Has a door for.

The airlocks 630a, 630b are maintained in either an atmospheric pressure environment or a vacuum pressure environment under the control of the controller 620, and are intermediate or temporary holding spaces of the substrate transferred from / to the VTM601, 602. Can function as. The VTM601 is a substrate from the airlocks 630a, 630b to the plurality of processing chambers 606, without vacuum break, i.e., while maintaining a vacuum pressure environment within the VTM602, the plurality of processing chambers 606, 608, and the pass-through chambers 640 and 642. Includes a robot arm 638 (indicated by a phantom) configured to transfer to one or more of the 608s, or to one or more pass-through chambers 640 and 642. The VTM602 multiple substrates from the airlocks 630a, 630b without vacuum break, i.e., while maintaining a vacuum pressure environment within the VTM602 and the plurality of processing chambers 606, 608, 610, 612, 614, 616, and 618. Includes a robot arm 638 (indicated by a phantom) configured to transfer to one or more of the processing chambers 606, 608, 610, 612, 614, 616, and 618. In certain embodiments, the airlocks 630a, 630b can be omitted and the controller 620 may be configured to move the substrate directly from the ATM 626 to the VTM 602.

[0050] A door 634, such as a slit valve door, connects the individual airlocks 630a, 630b to the VTM601. Similarly, a door 636, such as a slit valve door, connects each processing module to a VTM (eg, either VTM601 or VTM602) to which the individual processing modules are connected. Multiple processing chambers 606, 608, 610, 612, 614, 616, and 618 are typically configured to carry out one or more processes relating to the post-polyplug production of the substrates described herein.

The controller 620 controls the overall operation of the cluster tool 600 and includes a memory 621 for storing data or commands / instructions relating to the operation of the cluster tool 600. For example, the controller 620 controls the robot arms 628, 638, 639 of the ATM 626, VTM 601 and VTM 602 to transfer the substrate from / to the VTM 601 and between the VTM 601 and the VTM 602, respectively. The controller 620 controls the opening and closing of the doors 632, 634, 636 and controls the pressure of the airlocks 630a, 630b, for example, the atmospheric pressure environment / vacuum pressure environment in the airlocks 630a, 630b in the substrate transfer process. Maintain as desired. The controller 620 also controls the operation of the individual processing chambers 606, 608, 610, 612, 614, 616, and 618 to perform the operations associated with it, as described in more detail below.

FIG. 7 is a method for performing one or more DRAM bit line laminate processes, post-polyplug manufacturing, using the cluster tool 600. For illustration purposes only, FIG. 8 shows, for example, a cross-sectional view of a portion of the substrate 800 containing the polyplug 802 after the polyplug 802 has been formed on the outer substrate 800 of the cluster tool 600. Prior to performing the method of FIG. 7, the substrate 800 may be loaded onto the loading port 622 via one or more of the loading areas 624a-624c. The robot arm 628 of the ATM 626 can transfer the substrate 800 having the polyplug 802 from the loading area 624a to the ATM 626 under the control of the controller 620.

[0053] The controller 620 can determine whether at least one of the airlocks 630a, 630b is in an atmospheric pressure environment, depending on whether one or both of the airlocks 630a, 630b are in use. For illustration purposes, it is assumed that only the airlock 630a is used. If the controller 620 determines that the airlock 630a is in an atmospheric pressure environment, the controller 620 can open the door (part of 632) that connects the ATM 626 to the airlock 630a. Conversely, if the controller 620 determines that the airlock 630a is not in the atmospheric pressure environment, the controller 620 can adjust the pressure in the airlock 630a to the atmospheric pressure environment (eg, to the airlocks 630a, 630b). The pressure in the airlock 630a can be re-inspected (via a pressure control valve that is operably connected and controlled by the controller 620). The controller matches the pressure in the airlock 630a with respect to the robot arm 628, for example, to transfer the substrate 800 from the ATM 626 to the airlock 630a and to close the door 632, for example, the vacuum pressure environment inside the VTM601. Or it can be ordered to adjust to a vacuum pressure environment that is substantially consistent.

The controller 620 can determine if the airlock 630a is in a vacuum pressure environment. If the controller 620 determines that the airlock 630a is in a vacuum pressure environment, the controller can open the door 634 connecting the VTM601 to the airlock 630a. Conversely, if the controller 620 determines that the airlock 630a is not in the vacuum pressure environment, the controller 620 can adjust the pressure in the airlock 630a to the vacuum pressure environment (eg, to the airlocks 630a, 630b). Recheck the pressure in the airlock 630a (via a pressure control valve that is operably connected and controlled by the controller 620).

The controller 620 controls the operation of the cluster tool 600 by controlling the computer (or controller) associated with the processing chamber and the cluster tool 600, using or alternative to direct control of the processing chamber. do. During operation, the controller 620 allows data collection and feedback from individual chambers and systems to optimize the performance of the Cluster Tool 600. The controller 620 generally includes a central processing unit (CPU) 619, a memory 621, and a support circuit 625. The CPU 619 can be any form of general purpose computer processor that can be used in an industrial environment. The support circuit 625 is conventionally connected to the CPU 619 and may include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. A software routine (such as the method described above) may be stored in memory 621 and, when executed by the CPU 619, may convert the CPU 619 into a special purpose computer (controller 620). Software routines may also be stored and / or executed by a second controller (not shown) located away from the cluster tool 600.

[0056] The memory 621 is in the form of a computer-readable storage medium containing commands, and when executed by the CPU 619, facilitates semiconductor processing and operation of the device. The instructions in memory 621 are in the form of a program product (eg, a program that implements the method of this principle). The program code may be compatible with any one of several different programming languages. In one example, the disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program of the program product defines the function of the embodiment, including the methods described herein. An exemplary computer-readable storage medium may be read by a non-writable storage medium (eg, a CD-ROM drive, flash memory, ROM chip, or any type of solid-state non-volatile semiconductor memory) in which information is permanently stored. Read-only memory devices in your computer, such as possible CD-ROM disks, and writable storage media that store changeable information (eg, floppy disks in diskette drives or hard disk drives, or any type of solid state). Random access semiconductor memory), but is not limited to these. Such a computer-readable storage medium is an embodiment of the present principle if it possesses a computer-readable instruction indicating the function of the method described in this document.

In step 700, the controller 620 commands the robot arm 638 to transfer the substrate 800 from the airlock 630a through the door 634 to the VTM601 and close the door 634. Alternatively, for example, the door 634 can be left open to receive the outbound board upon completion of processing within the cluster tool 600. In step 702, the controller 620 attaches the substrate 800 to the robot arm 638 so that the manufacture of the substrate can be completed, i.e., to complete the processing of the bit wire laminate on the polyplug 802 on the substrate 800. Order to transfer to one or more of the processing chambers. For example, in step 702, the controller 620 can instruct the robot arm 638 to open the door 636 corresponding to the processing chamber 606. When the door is opened, the controller 620 can instruct the robot arm 638 to transfer the substrate 800 to the pre-cleaning chamber (eg, processing chamber 606) (without vacuum breaking, ie, ie). A vacuum pressure environment is maintained in VTM601 and VTM602 while the substrate 800 is transferred between the processing chambers 606, 608, 610, 612, and 614). The processing chamber 606 can be used to perform one or more pre-cleaning processes to remove any contamination that may be present on the substrate 800, eg, natural oxidation that may be present on the substrate 800. One such pre-cleaning chamber is Applied Materials, Inc. of Santa Clara, California. It is a SiCoNi ^TM processing tool commercially available from.

Next, in step 704, the controller 620 opens the door 636 and orders the robot arm 638 to transfer the substrate 800 to the next processing chamber. For example, in step 704, the controller 620 can instruct the robot arm 638 to transfer the substrate 800 from the pretreatment chamber to the barrier metal deposition chamber without vacuum breakdown. For example, the controller 620 can instruct the robot arm 638 to transfer the substrate under vacuum from the processing chamber 606, for example, to the processing chamber 608. The processing chamber 608 is configured to perform a barrier metal deposition process on the substrate 800 (eg, to deposit the barrier metal 804 on the washed substrate 800 and the polyplug 802). The barrier metal can be one of titanium (Ti) or (Ta).

Next, in step 706, the controller 620 commands the robot arm 638 to transfer the substrate 800 from the barrier metal deposition chamber to the barrier layer deposition chamber or to the annealing chamber without vacuum breakdown. can do. When the substrate 800 is transferred to the annealing chamber, the substrate 800 will be returned to the barrier metal deposition chamber for antioxidant deposition (eg, a variant of the barrier metal nitride). After the barrier metal deposition chamber, the substrate 800 is transferred to the barrier layer deposition chamber. For example, the controller 620 can instruct the robot arm 638 to transfer the substrate under vacuum from the processing chamber 608 to either the pass-through chamber 640, 642, at which point the robot arm inside the VTM602. The 639 can pick up the substrate 800 and move it to, for example, the processing chamber 610. The processing chamber 610 is configured to perform a barrier layer deposition process on the substrate 800 (eg, to deposit the barrier layer 806 on the barrier metal 804). The barrier layer can be one of titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0060] Next, in step 708, the controller 620 may instruct the robot arm 639 to transfer the substrate 800 from the processing chamber 610 to, for example, the processing chamber 612, without vacuum break. can. The processing chamber 612 is configured to perform a bit wire metal deposition process on the substrate 800 (eg, to deposit the bit wire metal layer 808 on the barrier layer 806 deposited in 706). The bit wire metal can be one of tungsten (W), molybdenum (Mo), ruthenium (Ru), iridium (Ir), or rhodium (Rh). Next, in step 710, the controller 620 can instruct the robot arm 639 to transfer the substrate 800 from the processing chamber 612 to, for example, the processing chamber 614, without vacuum break. The processing chamber 614 is configured to perform a hardmask deposition process on the substrate 800 (eg, to deposit the hardmask layer 810 on the bit wire metal layer 808 deposited in 708). The hard mask can be one of silicon nitride (SiN), silicon oxide (SiO), or silicon carbide (SiC).

[0061] In some embodiments, the annealing process can be performed on the substrate 800 before or after deposition of the barrier layer 806, as shown in 705. The annealing process can be any suitable annealing process such as rapid heat treatment (RTP) annealing. For example, the substrate 800 may first be transferred to the processing chamber 616 before the substrate 800 is transferred from the processing chamber 608 to the processing chamber 610. The processing chamber 616 is configured to perform the annealing process on the substrate 800. After the annealing process, the annealed substrate 800 containing the barrier layer 806 is transferred under vacuum from the annealing chamber (eg, processing chamber 616) to the barrier layer deposition chamber (eg, processing chamber 610) using, for example, a robot arm 639. Can be done.

[0062] Or, in combination, the annealing process is performed on the substrate 800 after deposition of the bit wire metal layer 808 and prior to depositing the hardmask layer 810 on the bit wire metal layer 808, as shown in 709a. Can be done. For example, prior to transferring the substrate 800 from the processing chamber 612 to the processing chamber 614, the substrate 800 may first be transferred to the processing chamber 616 (ie, the annealing chamber). An annealing process, or if annealing was previously performed in 705, may be performed on the substrate 800 on which the bit wire metal layer 808 is deposited as described above. In some embodiments where the annealing process is carried out at 709a, the annealed substrate 800 is optionally transferred to another processing chamber and deposited on the bit wire metal layer 808, as shown in 709b. Can have a capping layer 809. For example, the annealed substrate 800 containing the bit wire metal layer 808 is transferred under vacuum from the annealing chamber (eg, processing chamber 616) to the capping layer deposition chamber (eg, processing chamber 618) using, for example, a robot arm 639. The capping layer may be deposited on the annealed bit wire metal layer 808.

[0063] In some embodiments, some metals, such as ruthenium (Ru), are grain-growth metals after the bit wire metal is deposited. The inventor has observed that the continuous deposition of a hardmask layer on such a bit wire metal at high temperatures undesirably degrades the surface roughness. The inventor has found that by hydrogen annealing the bit wire metal layer before the hard mask layer deposition, the post-deposition of the cold cap layer can advantageously improve the surface roughness of the bit wire metal layer. By performing each of the above sequences with an integrated tool (eg, Cluster Tool 600), oxidation of the bit wire metal during annealing for grain growth is further advantageously avoided.

Further processes not described herein can also be performed on the substrate 800, and some of the processes described herein can be omitted.

After the above processes relating to the processing chambers 608, 610, 612, and 614 (and the processing chambers 616, 618, if used) are performed on the substrate 800, the substrate 800 may be, for example, the substrate 800. Using the robot arm 639 in the VTM 602 to transfer to the pass-through chambers 640, 642, and the substrate 800 in the VTM 601 to transfer the substrate 800 from the pass-through chambers 640, 642 to one of the airlocks 630a, 630b. The robot arm 638 is used to feed back from the VTM 602 to the loading port 622. The robot arm 628 can then be used to return the substrate 800 into the empty slot of the FOUP in the loading port 622.

The cluster tool 600 and usage described herein is on a polyplug using a single machine that is configured for the user to maintain a vacuum pressure environment throughout the DRAM bit line process. It makes it possible to carry out the DRAM bit line process advantageously. Therefore, the possibility of oxidation occurring on the substrate during production after the substrate 800 is reduced, if not eliminated. Moreover, the choice of bit wire metal material is not limited to the crystal grain growth properties of the metal, as the vacuum pressure environment is maintained throughout the DRAM bit wire process.

[0067] "One (" a "and" an ")", "the" in the context of describing the materials and methods discussed herein (particularly in the context of the following claims). And the use of similar referents should be construed to include both singular and plural, unless otherwise indicated herein or where there is no clear conflict in context. The enumeration of numerical ranges herein is solely intended to serve as an abbreviation for individually referring to each distinct value within that range, unless otherwise noted herein. Each value is incorporated herein as if it were individually listed herein. All methods described herein may be performed in any suitable order, unless otherwise stated herein or expressly inconsistent in context. The use of any and all examples provided herein, or exemplary language (eg, "such as"), is merely intended to better describe the material and method. And, unless otherwise insisted, it does not limit the scope. No wording herein should be construed as indicating an element that has not been claimed as essential to the practice of the disclosed materials and methods.

[0068] Throughout the specification, references to "one embodiment," "specific embodiment," "one or more embodiments," or "embodiments" are described in relation to that embodiment. It is meant that a particular feature, structure, material, or property is included in at least one embodiment of the present disclosure. Thus, expressions such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in embodiments" are expressed at various points throughout the specification. , Do not necessarily refer to the same embodiment of the present disclosure. Moreover, specific features, structures, materials, or properties may be combined in any optimal manner in one or more embodiments.

Although the disclosure herein is described with reference to specific embodiments, these embodiments are merely exemplary of the principles and uses of the present disclosure. Those skilled in the art will recognize that various modifications and variations may be made to the methods and devices of the present disclosure without departing from the essence and scope of the present disclosure. Accordingly, the present disclosure includes improved and modified examples included in the appended claims and their equivalents.

Embodiments of this principle may be implemented in hardware, firmware, software, or any combination thereof. The embodiments may also be implemented as instructions stored using one or more computer-readable media that can be read and executed by one or more processors. Computer-readable media include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing platform or a "virtual machine" running on one or more computing platforms). Can be included. For example, computer readable media may include any suitable form of volatile or non-volatile memory. In some embodiments, the computer-readable medium may include a non-temporary computer-readable medium.

[0071] The above is intended for embodiments of this Principle, but other embodiments and further embodiments of this Principle may be devised as long as they do not deviate from the basic scope of this Principle.

100 Figure 110 Condenser 112 Electrode 114 Wire 116 Wire 117 Wire 120 Transistor 121 Electrode 122 Region 123 Electrode 124 Layer 125 Electrode 200 Device 205 Laminate 210 Board 215 Layer 220 Layer 230 Layer 232 Surface 240 Metal Layer 242 Surface 250 Layer 260 Hardmask 300 Method 310 Step 320 Step 330 Step 400 Degree 402 Step 404 Step 406 Step 408 Step 410 Step 412 Step 500 Degree 502 Material 504 Layer 506 Surface 600 Cluster Tool 601 VTM
602 VTM
604 Module 606 Chamber / Module 608 Chamber / Module 610 Chamber / Module 612 Chamber / Module 614 Chamber / Module 616 Chamber / Module 618 Chamber / Module 619 CPU
620 Controller 621 Memory 622 Port 624a-c Loading Area 626 ATM
628 Robot Arm 630ab Lock 632 Door 634 Door 635 Door 636 Door 638 Robot Arm 639 Robot Arm 640 Chamber 642 Chamber 700 Controller 702 Controller 704 Controller 705 Annealing 706 Controller 708 Controller 709ab Processing 710 Controller 800 Board 802 Polyplug 804 Metal 806 Barrier layer 808 Metal layer 809 Capping layer
810 Layer 900 Method 902 Block 904 Block 906 Block 908 Block

Claims (20)

A method of smoothing the top surface of bit wire metal in a memory structure.
By depositing a titanium layer of about 30 angstroms to about 50 angstroms on the polysilicon layer on the substrate,
By depositing a first titanium nitride layer of about 15 angstroms to about 40 angstroms on the titanium layer,
Annealing the substrate at a temperature of about 700 ° C to about 850 ° C and
After annealing, a second titanium nitride layer of about 15 angstroms to about 40 angstroms is deposited on the first titanium nitride layer.
By depositing a ruthenium bit wire metal layer on the second titanium nitride layer,
Annealing the bit wire metal layer at a temperature of about 550 to about 650 degrees and
A method comprising immersing the bit wire metal layer in a hydrogen-based environment for about 3 to about 6 minutes during annealing. Placing a cap layer on the bit wire metal layer at a deposition temperature of about 350 ° C to about 400 ° C.
The method of claim 1, further comprising depositing a hardmask layer on the cap layer at a deposition temperature greater than about 500 ° C. The method of claim 2, wherein the cap layer comprises one or more of silicon nitride or silicon nitride. The method of claim 2, wherein the cap layer is from about 30 angstroms to about 50 angstroms. The method of claim 2, wherein the cap layer is deposited by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The method according to claim 2, wherein the hard mask layer contains silicon nitride. The method of claim 2, wherein the hardmask layer is deposited using a low pressure chemical vapor deposition (LPCVD) process. The method of claim 1, further comprising depositing a hardmask layer on the bit wire metal layer at a deposition temperature of less than about 400 ° C. The method of claim 8, wherein the hardmask layer is deposited using a low pressure chemical vapor deposition (LPCVD) process. The method of claim 1, wherein the bit wire metal layer has an upper surface having a root mean square (RMS) roughness of 1.15 nm or less. A method of forming a memory structure
Forming a barrier metal layer on the polysilicon layer on the substrate,
Annealing the barrier metal layer at a temperature of about 700 ° C. to about 850 ° C.
Forming a barrier layer on the barrier metal layer and
By depositing a bit wire metal layer on the barrier layer,
Annealing the bit wire metal layer at a temperature of about 550 to about 650 degrees and
A method comprising immersing the bit wire metal layer in a hydrogen-based environment for about 3 to about 6 minutes during annealing. Claimed that the barrier metal layer is a titanium nitride layer of about 30 angstroms to about 50 angstroms formed on the polysilicon layer and a titanium nitride layer of about 15 angstroms to about 40 angstroms formed on the titanium layer. Item 10. The method according to Item 11. 12. The method of claim 12, wherein annealing the barrier metal layer forms a titanium silicate layer on the polysilicon layer. 11. The method of claim 11, wherein the barrier layer is a titanium nitride layer of from about 15 angstroms to about 40 angstroms. The method according to claim 11, wherein the bit wire metal layer is a crystal grain growth metal layer having a root mean square (RMS) top surface roughness of 1.15 nm or less. Using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process to form a cap layer on the bit wire metal layer at a deposition temperature of approximately 350 ° C to approximately 400 ° C.
11. The method of claim 11, further comprising forming a hardmask layer on the cap layer at a deposition temperature above approximately 500 ° C. using a low pressure chemical vapor phase deposition (LPCVD) process. 16. The method of claim 16, wherein the cap layer is from about 30 angstroms to about 50 angstroms. 11. The method of claim 11, further comprising depositing a hardmask layer on the bit wire metal layer using a low pressure chemical vapor phase deposition (LPCVD) process at a deposition temperature of less than about 400 ° C. A method of smoothing the top surface of bit wire metal in a memory structure.
Using a plasma vapor deposition (PVD) chamber to deposit a titanium layer of approximately 30 angstroms to approximately 50 angstroms on a polysilicon layer on a substrate,
Annealing the substrate, wherein the substrate is provided at a temperature of about 700 ° C. to about 850 ° C. without vacuum breakdown between the deposition of the titanium layer and the annealing of the substrate. Annealing and
After annealing, a titanium nitride layer of about 15 angstroms to about 40 angstroms is deposited on the titanium layer.
By depositing a ruthenium bit wire metal layer on the titanium nitride layer,
Annealing the bit wire metal layer at a temperature of about 550 to about 650 degrees and
The bit wire metal layer is immersed in a hydrogen-based environment for about 3 to about 6 minutes during annealing so that the top surface of the bit wire metal has a root mean square (RMS) roughness of 1.15 nm or less. Methods, including what to do. Placing a cap layer on the bit wire metal layer at a deposition temperature of about 350 ° C to about 400 ° C, and depositing a hardmask layer on the cap layer at a deposition temperature of more than about 500 ° C, or the bit. 19. The method of claim 19, further comprising depositing a hardmask layer on the wire metal layer at a deposition temperature of less than about 400 ° C.

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