JP2022074493A - Solid-state imaging device and electronic apparatus - Google Patents

Abstract

To suppress image quality degradation in a captured image.SOLUTION: A solid-state imaging device comprises a plurality of first semiconductor chips that each performs A/D conversion of a plurality of imaging signals. Each of the plurality of first semiconductor chips includes: a reference signal line that conveys a reference signal for the A/D conversion; a reference signal generation unit that generates the reference signal; and a plurality of analog to digital converters (ADCs) that converts the plurality of imaging signals into a plurality of digital signals on the basis of comparison between the plurality of imaging signals and the reference signal. The plurality of reference signal lines in the plurality of first semiconductor chips is electrically connected to one another. The reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines.SELECTED DRAWING: Figure 10

Description

The embodiments according to the present disclosure relate to a solid-state image sensor and an electronic device.

In the field of video equipment, CCD (Charge Coupled Device) type, MOS (Metal Oxide Semiconductor) type and CMOS (Complementary Metal-Oxide-Semiconductor) type solid-state imaging devices that detect light (an example of electromagnetic waves) among physical quantities are available. It is used. These read out the physical quantity distribution converted into an electric signal by a unit component (a pixel in a solid-state image sensor) as an electric signal. Here, "solid" means that it is made of a semiconductor.

The stacked image sensor as a solid-state image sensor can be obtained, for example, by attaching a logic chip having an AD (Analog to Digital) circuit and a logic circuit to a pixel chip. When making a chip having an area larger than the exposure range of an exposure apparatus, a process of sequentially exposing a plurality of mask patterns while joining them, that is, so-called joint exposure may be performed. For example, a pixel chip of a large sensor of 35 mm size or medium format size is manufactured by joint exposure. On the other hand, the logic chip of the large sensor may be divided into a plurality of individualized chips and bonded to the pixel chip instead of a single chip made by continuous exposure. In this case, each individualized chip is often made from the same design data. Therefore, each individualized chip has a circuit configuration similar to each other.

Further, as the AD circuit in the logic chip, for example, a slope type column ADC (Analog to Digital Converter) may be used. Normally, in a slope type column ADC, a reference RAMP signal is generated by one DAC (Digital to Analog Converter) and supplied to all column ADCs. In addition, in order to speed up the response of the long wiring or high load reference RAMP signal wiring and reduce the influence of kickback from the comparator in the column ADC, a circuit that buffers the reference RAMP signal in each column is provided. It may be inserted (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2007-19682

However, when the reference RAMP signal generated by the DACs in the plurality of individualized chips is simply supplied to the column ADC of each individualized chip, the reference RAMP is due to the circuit variation of the DAC for each individualized chip. The LSB (Least Significant Bit) weight of the signal may be different for each individualized chip. The LSB weight affects the slope of the reference RAMP signal. In this case, even if a uniform pixel input signal is input to each column ADC, the AD output level will be different for each individualized chip. As a result, for example, a step (shading) is visually recognized in the output image. That is, when the AD conversion is performed by a plurality of logic chips that are individualized, the AD output level may vary and the image quality may deteriorate.

Therefore, the present disclosure provides a solid-state image sensor and an electronic device capable of suppressing deterioration of the image quality of a captured image.

In order to solve the above problems, according to this disclosure,
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
A solid-state image pickup device is provided in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines.

At the time of the AD conversion, the reference signal generation unit in the chip other than the one chip may stop the generation of the reference signal.

According to the present disclosure, each includes a plurality of first semiconductor chips that AD-convert a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
It has an analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips, or a gain adjustment unit for adjusting the digital gain of the plurality of digital signals.
A solid-state image pickup device is provided in which a plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.

The gain adjusting unit may adjust the analog gain based on the ratio of the plurality of reference signals in the plurality of reference signal lines.

The gain adjusting unit may adjust the digital gain by comparing the plurality of digital signals output from each of the plurality of first semiconductor chips.

Each of the plurality of first semiconductor chips
A plurality of buffer units for buffering the reference signal on the reference signal line in association with each of the plurality of ADCs.
Further, it has an output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The plurality of output wirings in the plurality of first semiconductor chips may be electrically connected to each other.

Each of the plurality of first semiconductor chips has a plurality of the reference signal lines.
The corresponding reference signal lines in each of the plurality of first semiconductor chips are electrically connected to each other.
The reference signal generation unit in each of the plurality of first semiconductor chips may supply the reference signal to different reference signal lines.

The plurality of first semiconductor chips have two first semiconductor chips arranged in a predetermined direction.
Each of the two first semiconductor chips has the two reference signal lines.
The two reference signal lines of one of the two first semiconductor chips are electrically connected to the corresponding reference signal line of the other of the two first semiconductor chips.
The reference signal output from the reference signal generation unit of one of the two first semiconductor chips is supplied to one of the two reference signal lines.
The reference signal output from the reference signal generation unit of the other of the two first semiconductor chips may be supplied to the other of the two reference signal lines.

The two reference signal lines may be alternately connected to the plurality of ADCs.

The two reference signal lines may be alternately connected to the ADC in units of two or more predetermined number of the ADCs in the plurality of ADCs.

Each of the two first semiconductor chips has the plurality of buffer units and the output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The two output wirings of the two first semiconductor chips may be electrically connected to each other.

Each of the plurality of first semiconductor chips may have the same size, the same shape, and the same circuit configuration.

A second semiconductor chip that is laminated on the first semiconductor chip and has a pixel array unit that performs photoelectric conversion may be further provided.

The first semiconductor chip and the second semiconductor chip may be electrically connected by direct bonding between vias, bumps, or conductive materials.

A signal line for transmitting a plurality of imaging signals photoelectrically converted by a plurality of pixels arranged in a predetermined direction is connected to each of the plurality of ADCs.
The plurality of ADCs may convert the plurality of image pickup signals into the plurality of digital signals based on the comparison between the image pickup signal on the corresponding signal line and the reference signal.

The reference signal may be a signal whose voltage level changes with time.

According to the present disclosure, a solid-state image sensor that outputs a digital signal corresponding to an image pickup signal and
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
An electronic device is provided in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines.

According to the present disclosure, a solid-state image sensor that outputs a digital signal corresponding to an image pickup signal and
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of first semiconductor chips having a gain adjusting unit for adjusting the analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips or the digital gain of the plurality of digital signals. An electronic device is provided in which a plurality of the reference signal lines are electrically connected to each other.

It is a schematic block diagram of the CMOS solid-state image pickup apparatus which is one Embodiment of the semiconductor apparatus which concerns on this disclosure. It is a figure which shows the configuration example of a unit pixel, and the connection mode of a drive part, a drive control line, and a pixel transistor. It is a figure which shows the configuration example of a unit pixel, and the connection mode of a drive part, a drive control line, and a pixel transistor. It is a timing chart for demonstrating the signal acquisition difference processing which is a basic operation in a column AD circuit. It is an exploded perspective view which shows the outline of the laminated chip structure of a solid-state image sensor. It is a top view which shows an example of the structure and arrangement of a logic chip 102. It is a top view which shows an example of the structure and arrangement of the individualized logic chip. It is a top view which shows the 1st modification example of the structure and arrangement of the individualized logic chip. It is a top view which shows the 2nd modification example of the structure and arrangement of the individualized logic chip. It is a schematic diagram which shows an example of the laminated chip structure of the solid-state image sensor which concerns on a comparative example. It is a schematic diagram which shows an example of the laminated type chip structure of the solid-state image sensor which concerns on 1st Embodiment. It is sectional drawing which shows an example of the structure of the signal line connection part which concerns on 1st Embodiment. It is a top view which shows an example of the structure of the signal line connection part which concerns on 1st Embodiment. It is sectional drawing which shows the 1st modification of the structure of the signal line connection part which concerns on 1st Embodiment. It is a top view which shows the 1st modification of the structure of the signal line connection part which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of the structure of the reference signal supply IF part which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of the structure of the reference signal supply IF part which concerns on 1st Embodiment. It is a schematic block diagram which shows the 1st modification of the structure of the reference signal supply IF part which concerns on 1st Embodiment. It is a schematic block diagram which shows the 1st modification of the structure of the reference signal supply IF part which concerns on 1st Embodiment. It is a circuit diagram which shows an example of the structure of a buffer part. It is a schematic diagram which shows an example of the laminated type chip structure of the solid-state image sensor which concerns on 2nd Embodiment. It is a figure which shows an example of the gain adjustment which concerns on 2nd Embodiment. It is a figure which shows the 1st modification of the gain adjustment which concerns on 2nd Embodiment. It is a schematic diagram which shows an example of the laminated type chip structure of the solid-state image sensor which concerns on 3rd Embodiment. It is a schematic block diagram which shows an example of the structure of the reference signal supply IF part which concerns on 3rd Embodiment. It is a schematic block diagram which shows an example of the structure of the reference signal supply IF part which concerns on 3rd Embodiment. It is a schematic block diagram which shows the 1st modification of the structure of the reference signal supply IF part which concerns on 3rd Embodiment. It is a schematic block diagram which shows the 1st modification of the structure of the reference signal supply IF part which concerns on 3rd Embodiment. It is a figure which shows an example of the gain adjustment which concerns on 2nd Embodiment when the DAC linearity of a DA conversion circuit is good. It is a figure which shows an example of the gain adjustment which concerns on 2nd Embodiment when the DAC linearity of a DA conversion circuit is not good. It is a figure which shows an example of the output of the reference signal which concerns on 3rd Embodiment when the DAC linearity of a DA conversion circuit is not good. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.

Hereinafter, embodiments of a solid-state image sensor and an electronic device will be described with reference to the drawings. In the following, the main components of the solid-state image sensor and the electronic device will be mainly described, but the solid-state image sensor and the electronic device may have components and functions not shown or described. The following description does not exclude components or functions not shown or described.

In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state image sensor, is used as a device will be described as an example. Further, the CMOS image sensor will be described assuming that all the pixels are composed of an MIMO or a polyclonal.

However, this is only an example, and the target device is not limited to the MOS type imaging device. All of the semiconductor devices for physical quantity distribution detection, in which a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix, are all implemented as described later. The morphology is applicable as well.

In the present disclosure, the image pickup apparatus includes a plurality of detection units that detect changes in physical quantities and a unit signal generation unit that outputs a unit signal based on the changes in physical quantities detected by each detection unit. Included in. The image pickup device uses a device for detecting a physical quantity distribution in which the unit components are arranged in a predetermined order, and is a physical quantity for a predetermined purpose based on a unit signal acquired under predetermined detection conditions for the physical quantity. It is a general term for physical information acquisition devices that acquire information.

The electronic device according to the present disclosure is, for example, a computer using the solid-state image sensor 1. The electronic device includes a solid-state image sensor 1 and a signal processing unit. The solid-state image sensor 1 outputs a digital signal corresponding to the image pickup signal. The signal processing unit performs predetermined signal processing based on the digital signal. The details of the electronic device will be described later with reference to FIGS. 25 and 26.

<Structure of solid-state image sensor>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state image sensor (CMOS image sensor) according to an embodiment of the solid-state image sensor 1 according to the present disclosure.

The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal according to the amount of incident light are arranged in rows and columns (that is, in a two-dimensional matrix shape). However, the signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital converter (ADC; Analog Digital Converter), etc. are provided in parallel in a row. Is.

"The CDS processing function unit and the digital conversion unit are provided in parallel in the column" means that a plurality of CDS processing function units and the digital conversion unit are provided substantially in parallel with the vertical signal line 19 in the vertical column. Means to be. Each of the plurality of functional units is arranged only on one edge side (output side arranged at the lower side of the figure) in the column direction with respect to the pixel unit (imaging unit) 10 when the device is viewed in a plan view. One edge side in the column direction (output side arranged at the lower side of the figure) and the other edge side opposite to the pixel portion 10 (figure). It may be in the form of being divided into (upper side). In the latter case, it is preferable that the horizontal scanning unit that performs read scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

For example, as a typical example in which a CDS processing function unit or a digital conversion unit is provided in parallel in a column, a CDS processing function unit or a digital conversion unit is provided for each vertical column in a portion called a column area provided on the output side of the imaging unit. It is a column type that is provided in the above and is read out to the output side in sequence. Further, not limited to the column type, one CDS processing function unit or digital conversion unit is assigned to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), and every N lines (N is). It is also possible to adopt a form in which one CDS processing function unit or digital conversion unit is assigned to N vertical signal lines 19 (vertical columns) of positive integers; N-1 lines are arranged between them).

Except for the column type, in each form, since a plurality of vertical signal lines 19 (vertical columns) are configured to use one CDS processing function unit and a digital conversion unit in common, they are supplied from the pixel unit 10 side. A switching circuit (switch) for supplying pixel signals for a plurality of rows to one CDS processing function unit or digital conversion unit is provided. Depending on the processing in the subsequent stage, it may be necessary to take measures such as providing a memory for holding the output signal.

In any case, the signal processing of each pixel signal is read out in pixel column units by adopting a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). By performing the same signal processing later, the configuration in each unit pixel can be simplified as compared with the case where the same signal processing is performed in each unit pixel, and it is possible to cope with the increase in the number of pixels, the miniaturization, the cost reduction, and the like of the image sensor.

In addition, since a plurality of signal processing units arranged in parallel in columns can simultaneously process pixel signals for one row, one CDS processing function unit or digital conversion unit can be used on the output circuit side or outside the device. The signal processing unit can be operated at a lower speed than in the case of performing processing, which is advantageous in terms of power consumption, band performance, noise, and the like. Conversely, if the power consumption and bandwidth performance are the same, high-speed operation of the entire sensor becomes possible.

In the case of the column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, band performance, noise, etc., and also has an advantage that a switching circuit (switch) is not required. In the following embodiments, this column type will be described unless otherwise specified.

As shown in FIG. 1, in the solid-state imaging device 1, a pixel portion (imaging) in which a plurality of unit pixels (examples of unit components) 3 having a substantially square pixel shape are arranged in rows and columns (that is, in a square grid pattern). Section 10), a drive control section 7 provided outside the pixel section 10, and a read current source section 24 that supplies an operating current (read current) for reading a pixel signal to the unit pixel 3 of the pixel section 10. A column processing unit 26 having a column AD circuit 25 arranged for each column, a reference signal generation unit 27 that supplies a reference voltage for AD conversion to the column processing unit 26, and a reference signal generated by the reference signal generation unit 27. The reference signal supply interface (IF) unit 28 and the output unit 29 are provided. Each of these functional parts is separately provided on a plurality of semiconductor substrates to be joined (see FIG. 4).

If necessary, an AGC (Auto Gain Control) circuit or the like having a signal amplification function may be provided in the same semiconductor region as the column processing unit 26 in the front stage or the rear stage of the column processing unit 26. When AGC is performed in the front stage of the column processing unit 26, analog amplification is performed, and when AGC is performed in the rear stage of the column processing unit 26, digital amplification is performed. If the n-bit digital signal is simply amplified, the gradation may be impaired. Therefore, it is preferable to amplify the n-bit digital signal in analog and then perform digital conversion.

The drive control unit 7 has a control circuit function for sequentially reading out the signals of the pixel unit 10. For example, the drive control unit 7 includes a horizontal scanning unit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning unit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock. It is provided with a communication / timing control unit 20 having a function such as generation.

In FIG. 1, a part of rows and columns is omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column, and the pixel portion 10 is provided. It is composed. Of these, the portion excluding the reference pixel region such as the black pixels provided on the top, bottom, left, and right is the effective portion 10a related to the actual image formation. The unit pixel 3 is typically composed of a photodiode as a light receiving element (charge generation unit) and an in-pixel amplifier having a semiconductor element (for example, a transistor) for amplification.

As the in-pixel amplifier, for example, an amplifier having a floating diffusion amplifier configuration is used. As an example, for the charge generation unit, a read selection transistor which is an example of a charge reading unit (transfer gate unit / reading gate unit), a reset transistor which is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion. As a CMOS sensor having an amplification transistor having a source follower configuration, which is an example of a detection element for detecting a change in electric charge, a transistor having a configuration consisting of four general-purpose transistors can be used.

Alternatively, as described in Japanese Patent No. 2708455, an amplification transistor connected to a drain line (DRN) for amplifying a signal voltage corresponding to the signal charge generated by the charge generation unit, and a charge generation unit. It is also possible to use a transistor consisting of three transistors having a reset transistor for resetting the voltage and a read selection transistor (transfer gate portion) scanned from the vertical shift register via the transfer wiring (TRF). ..

The solid-state image sensor 1 can make the pixel unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, a color separation filter composed of a combination of color filters of a plurality of colors for capturing a color image on a light receiving surface on which an electromagnetic wave (light in this example) of each charge generating unit (photodiode or the like) in the pixel unit 10 is incident. By providing any of the color filters in the above, for example, in a so-called Bayer arrangement or the like, color image imaging is supported.

The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, and a column processing unit 26 provided with a column AD circuit 25 for each vertical column via a vertical signal line 19. Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

The horizontal scanning circuit 12 has a function of a read scanning unit that reads a count value from the column processing unit 26. Each element of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning circuit 14 is integrated with the pixel unit 10 in a semiconductor region such as single crystal silicon by using the same technique as the semiconductor integrated circuit manufacturing technique. It is formed and is configured as a solid-state image sensor (imaging device) which is an example of a semiconductor system.

The horizontal scanning unit 12 and the vertical scanning unit 14 are configured to include a decoder as described later, and start a shift operation (scanning) in response to the control signals CN1 and CN2 given from the communication / timing control unit 20. It has become. Therefore, the row control line 15 includes various pulse signals for driving the unit pixel 3 (for example, reset pulse RST, transfer pulse TRF, DRN control pulse DRN, etc.).

Although not shown, the communication / timing control unit 20 is mastered via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock required for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. It also includes a functional block of a communication interface that receives clock CLK0, receives data DATA that commands an operation mode or the like via terminal 5b, and outputs data including information of the solid-state imaging device 1.

For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each of the decoders 12a and 14a receives the output and selects the corresponding row or column.

At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, the analog pixel signals generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal line 19 are row-by-row (column parallel). (In this example) Access and capture (vertical) scan Read, then access in the row direction, which is the arrangement direction of the vertical columns, and read the pixel signal (digitized pixel data in this example) to the output side (horizontal) scan. It is preferable to speed up the reading of pixel signals and pixel data by reading. Of course, not limited to scan reading, random access to read only the necessary information of the unit pixel 3 is also possible by directly specifying the address of the unit pixel 3 to be read.

Further, in the communication / timing control unit 20, the device is a clock CLK1 having the same frequency as the master clock (master clock) CLK0 input via the terminal 5a, a clock obtained by dividing it by two, or a low-speed clock obtained by dividing it by two. It is supplied to each part of the inside, for example, a horizontal scanning unit 12, a vertical scanning unit 14, a column processing unit 26, and the like. Hereinafter, the clock divided by 2 and all the clocks having a frequency lower than that are collectively referred to as a low-speed clock CLK2.

The vertical scanning unit 14 selects a row of the pixel unit 10 and supplies the pulse required for that row. For example, the vertical decoder 14a that defines the reading line in the vertical direction (selects the line of the pixel unit 10) and the line control line 15 for the unit pixel 3 on the reading address (row direction) specified by the vertical decoder 14a. It has a vertical drive unit 14b that supplies and drives a pulse. The vertical decoder 14a selects not only a line for reading a signal but also a line for an electronic shutter.

The horizontal scanning unit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock CLK2, and guides the signal to the horizontal signal line (horizontal output line) 18. For example, each of the horizontal decoder 12a that defines the horizontal reading sequence (selects the individual column AD circuit 25 in the column processing unit 26) and the column processing unit 26 according to the reading address specified by the horizontal decoder 12a. It has a horizontal drive unit 12b that guides a signal to a horizontal signal line 18. In addition, 10 horizontal signal lines 18 are arranged corresponding to the number of bits n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, corresponding to the number of bits. ..

In the solid-state image sensor 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

Each column AD circuit 25 of the column processing unit 26 receives the analog signal So of one row of pixels and processes the analog signal So. For example, each column AD circuit 25 has an ADC (Analog Digital Converter) circuit that converts an analog signal into, for example, a 10-bit digital signal using, for example, the low-speed clock CLK2.

As the AD conversion process in the column processing unit 26, a method is adopted in which analog signals held in parallel in row units are AD-converted in parallel for each row by using a column AD circuit 25 provided for each column. In this case, for example, Patent Publication No. 2532374 and the academic document "CMOS image sensor equipped with a column-type AD converter without inter-column FPN" (Emotional Technique, IPU2000-57, pp.79-84), etc. The single slope integral type (or ramp signal comparison type) AD conversion method shown in is used. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

The configuration of the ADC circuit will be described in detail later, but the analog processing target signal is converted into a digital signal based on the time from the start of conversion until the reference voltage RAMP and the processing target signal voltage match. As a mechanism for this, in principle, a ramp-shaped reference voltage RAMP is supplied to the comparator, and at the same time, counting with a clock signal is started and input via the vertical signal line 19. AD conversion is performed by counting until a pulse signal is obtained by comparing the analog pixel signal with the reference voltage RAMP.

Further, at this time, by devising the circuit configuration, the signal level (noise level) immediately after the pixel reset and the true (noise level) and the true (noise level) of the voltage mode pixel signal input via the vertical signal line 19 together with the AD conversion are obtained. It is possible to perform a process of taking a difference from the signal level Vsig (according to the amount of received light). This makes it possible to remove noise signal components called fixed pattern noise (FPN; Fixed Pattern Noise) and reset noise.

The pixel data digitized by the column AD circuit 25 is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning unit 12, and further input to the output unit 29. To. Note that 10 bits is an example, and may be other bits such as less than 10 bits (for example, 8 bits) or more than 10 bits (for example, 14 bits).

With such a configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image, that is, a frame image corresponding to the pixel unit 10 in which the light receiving elements are arranged in a matrix is shown as a set of pixel signals of the entire pixel unit 10.

<Details of reference signal generator and column AD circuit>
The reference signal generation unit 27 includes a DA conversion circuit (DAC; Digital Analog Converter) 27a, which is a functional element that generates a reference signal for AD conversion. In the case of color image imaging support, the reference signal generation unit 27 has pixels so that individual reference signals having color-corresponding change characteristics (inclinations) and initial values can be supplied to the comparison circuit. A DA conversion circuit, which is a functional element that generates a reference signal for AD conversion, is individually provided according to the color type and arrangement of the color filters constituting the color separation filter in the unit 10, and the processing target is switched by switching the processing target row. It is advisable to provide a switching mechanism to deal with the switching of colors.

By doing so, the wiring from the reference voltage generator (corresponding to the DA conversion circuit in this example) and the reference voltage generator can be reduced to be smaller than the number of color filters constituting the color separation filter. In addition, a selection means for each vertical column that selectively outputs the analog reference voltage (corresponding to the reference signal in this example) from each reference voltage generator required when a reference voltage generator is prepared for each color filter. Since the (multiplexer) is not required, the circuit scale can be reduced. The number of signal lines that transmit the reference signal corresponding to the color pixel to the input side of the comparator can be smaller than the number of color components of the color filter for capturing a color image.

The control data CN4 supplied from the communication / timing control unit 20 to the DA conversion circuit 27a of the reference signal generation unit 27 also contains information indicating the slope (degree of change; time change amount) of the lamp voltage and the initial value for each comparison process. Includes.

The DA conversion circuit 27a receives the supply of the count clock CKdac for DAC from the communication / timing control unit 20, and generates, for example, a linearly decreasing stepped sawtooth wave (ramp waveform) in synchronization with the count clock CKdac. Then, the generated serrated wave is supplied to the column AD circuit 25 via the reference signal RAMP as a reference voltage (ADC reference signal) for AD conversion. Further, for example, the slope of the reference signal RAMP is changed by adjusting the cycle of the count clock CKdac, thereby adjusting the coefficient at the time of difference processing described later and controlling the analog gain at the time of AD conversion.

The column AD circuit 25 includes a reference signal RAMP generated by the DA conversion circuit 27a of the reference signal generation unit 27, and a vertical signal line 19 (H1, H2) from the unit pixel 3 for each row control line 15 (V1, V2, ...). , ...) The voltage comparison unit (comparator) 252 that compares with the analog pixel signal obtained via) and the counter unit 254 that counts the time until the voltage comparison unit 252 completes the comparison process and holds the result. It is configured with and has an n-bit AD conversion function.

The communication / timing control unit 20 is a function of a control unit that switches the mode of count processing in the counter unit 254 according to whether the voltage comparison unit 252 is performing comparison processing for the reset component ΔV or the signal component Vsig of the pixel signal. have. A control signal CN5 for instructing whether the counter unit 254 operates in the down count mode or the up count mode is input from the communication / timing control unit 20 to the counter unit 254 of each column AD circuit 25. There is.

The reference signal supply IF unit 28 receives the reference signal generated by the reference signal generation unit 27 via the reference signal line 251 and outputs the reference signal to the reference signal output line 281. In one input terminal RAMP of the voltage comparison unit 252, the stepped reference signal RAMP generated by the reference signal generation unit 27 is input from the reference signal output line 281 via the reference signal supply IF unit 28, and the other input. Vertical signal lines 19 in the corresponding vertical rows are connected to the terminals, and the pixel signal voltage from the pixel unit 10 is individually input.

Further, two types of reset signals PSET and NSET and other control signals (collectively referred to as comparison control signal CN7) are supplied to the voltage comparison unit 252 from the communication / timing control unit 20, and the voltage comparison unit 252 also supplies the voltage comparison unit 252. The output signal is supplied to the counter unit 254.

A count clock CK0 is input from the communication / timing control unit 20 to the clock terminal CK of the counter unit 254 in common with the clock terminal CK of the other counter units 254.

Although the configuration of the counter unit 254 is omitted from the illustration, it can be realized by changing the wiring form of the data storage unit generally configured by the latch to the synchronous counter type, and the input of one count clock CK0. So, it is designed to perform internal counting. The n-bit counter unit 254 can be realized by combining n latches, which is half the circuit scale of the data storage unit composed of two n latches. In addition, since the counter unit for each column is not required, the overall size is significantly reduced.

Here, although the details of the counter unit 254 will be described later, the counter unit 254 uses a common up / down counter (U / D CNT) regardless of the count mode to switch between the down count operation and the up count operation (specifically, the up count operation). It is configured to be able to perform counting processing (alternately). Further, the counter unit 254 uses a synchronization counter in which the count output value is output in synchronization with the count clock CK0.

In the case of a synchronous counter, the operation of all flip-flops (counter basic elements) is limited by the count clock CK0. Therefore, when higher frequency operation is required, the counter unit 254 uses an asynchronous counter suitable for high-speed operation because its operation limiting frequency is determined only by the limiting frequency of the first flip-flop (counter basic element). Is more preferable.

A control pulse is input to the counter unit 254 from the horizontal scanning unit 12 via the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until instructed by the control pulse via the control line 12c.

As described above, the column AD circuit 25 having such a configuration is arranged for each vertical signal line 19 (H1, H2, ...), And the column processing unit 26, which is an ADC block having a column parallel configuration, is configured. To.

The output side of each column AD circuit 25 is connected to the horizontal signal line 18. As described above, the horizontal signal line 18 has a signal line corresponding to the bit width of the column AD circuit 25, which is n bits wide, and passes through n sense circuits corresponding to each output line (not shown). Then, it is connected to the output unit 29.

In such a configuration, the column AD circuit 25 performs a counting operation during the pixel signal reading period and outputs a counting result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the lamp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and when both voltages are the same, the voltage comparison is performed. The comparator output of unit 252 is inverted (transition from H level to L level in this example).

The counter unit 254 starts the counting operation in the down count mode or the up count mode in synchronization with the lamp waveform voltage emitted from the reference signal generation unit 27, and the inverted information of the comparator output is notified to the counter unit 254. Then, the counting operation is stopped, and the AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

After that, the counter unit 254 sequentially stores and retains pixel data based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning unit 12 via the control line 12c at a predetermined timing. The data is output from the output terminal 5c to the outside of the column processing unit 26 or the outside of the chip having the pixel unit 10.

Although not shown in particular because it is not directly related to the description of the present embodiment, various other signal processing circuits and the like may be included in the components of the solid-state image sensor 1.

<Pixel part>
2A and 2B are diagrams showing a configuration example of a unit pixel 3 used in the solid-state image sensor 1 shown in FIG. 1 and a connection mode of a drive unit, a drive control line, and a pixel transistor. The configuration of the unit pixel (pixel cell) 3 in the pixel unit 10 is the same as that of a normal CMOS image sensor, and in the present embodiment, a general-purpose 4TR configuration as a CMOS sensor, or, for example, Japanese Patent No. 2708455 As described in the above, a 3TR configuration consisting of three transistors can be used. Of course, these pixel configurations are an example, and any ordinary CMOS image sensor array configuration can be used.

As the in-pixel amplifier, for example, an amplifier having a floating diffusion amplifier configuration is used. As an example, for the charge generation unit, a read selection transistor which is an example of a charge reading unit (transfer gate unit / reading gate unit), a reset transistor which is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion. As a CMOS sensor, a transistor having an amplification transistor having a source follower configuration, which is an example of a detection element for detecting a change in the potential of the above, can be used as a CMOS sensor having a configuration consisting of four transistors (hereinafter, also referred to as a 4TR configuration).

For example, the unit pixel 3 having a 4TR configuration shown in FIG. 2A has a charge generation unit 32 having both a photoelectric conversion function of receiving light and converting it into an electric charge and a charge accumulating function of accumulating the electric charge, and an electric charge generation unit. A read selection transistor (transfer transistor) 34, which is an example of a charge reading unit (transfer gate unit / reading gate unit), a reset transistor 36, which is an example of a reset gate unit, a vertical selection transistor 40, and a unit 32. It has an amplification transistor 42 having a source follower configuration, which is an example of a detection element that detects a change in the electric charge of the floating diffusion 38.

The unit pixel 3 has a pixel signal generation unit 5 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 38, which is an example of a charge injection unit having a function of a charge storage unit. The floating diffusion 38 is a diffusion layer having a parasitic capacitance.

The read selection transistor (second transfer unit) 34 is driven by the transfer drive buffer 250 to which the transfer signal φTRG is supplied via the transfer wiring (read selection line TX) 55. The reset transistor 36 is driven via the reset wiring (RST) 56 by the reset drive buffer 252 to which the reset signal φRST is supplied. The vertical selection transistor 40 is driven via the vertical selection line (SEL) 52 by the selection drive buffer 254 to which the vertical selection signal φVSEL is supplied. Each drive buffer can be driven by the vertical drive unit 14b of the vertical scanning unit 14.

In the reset transistor 36 in the pixel signal generation unit 5, the source is connected to the floating diffusion 38 and the drain is connected to the power supply Vdd, and the reset pulse RST is input to the gate (reset gate RG) from the reset drive buffer.

As an example, in the vertical selection transistor 40, the drain is connected to the source of the amplification transistor 42, the source is connected to the pixel line 51, and the gate (particularly referred to as the vertical selection gate SELV) is connected to the vertical selection line 52. Not limited to such a connection configuration, the drain may be connected to the power supply Vdd, the source may be connected to the drain of the amplification transistor 42, and the vertical selection gate SELV may be connected to the vertical selection line 52.

A vertical selection signal SEL is applied to the vertical selection line 52. The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the power supply Vdd via the vertical selection transistor 40, a source connected to the pixel line 51, and further connected to the vertical signal line 53 (19). It has become like.

Further, one end of the vertical signal line 53 extends to the column processing unit 26 side, and a read current source unit 24 is connected in the path thereof, and a substantially constant operating current (read) is connected to the vertical signal line 53 with the amplification transistor 42. A source follower configuration in which a current) is supplied is adopted.

Specifically, the read current source unit 24 includes a MOSFET-type transistor (particularly referred to as a load MOS transistor) 242 provided in each vertical column, a current generation unit 245 shared for all vertical columns, and a gate and drain. Is provided with a reference current source unit 244 having an MOSFET type transistor 246 to which the current source is commonly connected and the source is connected to the source line 248.

Each load MOS transistor 242 is connected to a vertical signal line 53 in which the drain corresponds to the corresponding row, and is commonly connected to a source line 248 whose source is the ground line. As a result, the load MOS transistors 242 in each vertical row are connected so as to form a current mirror circuit in which the gates are connected to each other with the transistor 246 of the reference current source unit 244.

The source line 248 is connected to the ground (GND) which is the substrate bias at the horizontal end (vertical row on the left and right in FIG. 1), and the operating current (read current) with respect to the ground of the load MOS transistor 242 is the left and right of the chip. It is configured to be supplied from both ends.

A load control signal SFLACT for outputting a predetermined current only when necessary is supplied to the current generation unit 245 from a load control unit (not shown). At the time of signal reading, the current generation unit 245 receives an active state of the load control signal SFLACT so that the load MOS transistor 242 connected to each amplification transistor 42 continues to flow a predetermined constant current. It has become. That is, the load MOS transistor 242 forms a source follower with the amplification transistor 42 in the selected row and supplies a read current to the amplification transistor 42 to output a signal to the vertical signal line 53.

In such a 4TR configuration, since the floating diffusion 38 is connected to the gate of the amplification transistor 42, the amplification transistor 42 outputs a signal corresponding to the potential of the floating diffusion 38 (hereinafter referred to as FD potential) in a voltage mode. It is output to the vertical signal line 19 (53) via the line 51.

The reset transistor 36 resets the floating diffusion 38. The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generation unit 32 to the floating diffusion 38. A large number of pixels are connected to the vertical signal line 19, but in order to select a pixel, only the selected pixel turns on the vertical selection transistor 40. Then, only the selected pixel is connected to the vertical signal line 19, and the signal of the selected pixel is output to the vertical signal line 19.

On the other hand, by adopting a configuration consisting of a charge generation unit and three transistors (hereinafter also referred to as a 3TR configuration), the area occupied by the transistors in the unit pixel 3 can be reduced and the pixel size can be reduced (for example, a patent). (See No. 2708455).

For example, the unit pixel 3 having a 3TR configuration shown in FIG. 2B is generated by a charge generation unit 32 (for example, a photodiode) that generates a signal charge corresponding to the received light by performing photoelectric conversion, and a charge generation unit 32. It has an amplification transistor 42 connected to a drain line (DRN) for amplifying a signal voltage corresponding to a signal charge, and a reset transistor 36 for resetting a charge generation unit 32, respectively. Further, a read selection transistor (transfer gate unit) 34 scanned from a vertical scanning circuit 14 (not shown) via the transfer wiring (TRF) 55 is provided between the charge generation unit 32 and the gate of the amplification transistor 42. ing.

The gate of the amplification transistor 42 and the source of the reset transistor 36 are connected to the charge generation unit 32 via the read-selection transistor 34, and the drain of the reset transistor 36 and the drain of the reset transistor 42 are connected to the drain line, respectively. Further, the source of the amplification transistor 42 is connected to the vertical signal line 53.

The read selection transistor 34 is driven by the transfer drive buffer 250 via the transfer wiring 55. The reset transistor 36 is driven by the reset drive buffer 252 via the reset wiring 56.

Both the transfer drive buffer 250 and the reset drive buffer 252 operate at two values of 0V, which is the reference voltage, and the power supply voltage. In particular, the low level voltage supplied to the gate of the read selection transistor 34 in this pixel is 0V.

In the unit pixel 3 of the 3TR configuration, since the floating diffusion 38 is connected to the gate of the amplification transistor 42 as in the 4TR configuration, the amplification transistor 42 transmits a signal corresponding to the potential of the floating diffusion 38 as a vertical signal. Output to line 53.

In the reset transistor 36, the reset wiring (RST) 56 extends in the row direction, and the drain line (DRN) 57 is common to most pixels. The drain line 57 is driven by a drain drive buffer (hereinafter referred to as a DRN drive buffer) 240 to which a drain drive signal φDRN is supplied. The reset transistor 36 is driven by the reset drive buffer 252 and controls the potential of the floating diffusion 38.

The drain line 57 is separated in the row direction, but since this drain line 57 must carry the signal current of one line of pixels, the wiring common to all lines so that the current can actually flow in the column direction. It becomes. The signal charge generated by the charge generation unit 32 (photoelectric conversion element) is transferred to the floating diffusion 38 by the read selection transistor 34.

Here, unlike the 4TR configuration, the unit pixel 3 in the 3TR configuration is not provided with the vertical selection transistor 40 connected in series with the amplification transistor 42. Although a large number of pixels are connected to the vertical signal line 53, the selection of pixels is performed by controlling the FD potential, not by the selection transistor. Normally, the FD potential is set to Low. When selecting a pixel, the FD potential of the selected pixel is set to High, so that the signal of the selected pixel is output to the vertical signal line 53. After that, the FD potential of the selected pixel is returned to low. This operation is performed simultaneously for one row of pixels.

In order to control the FD potential in this way, 1) when the selected row FD potential is set high, the drain line 57 is set high, and the FD potential is set high through the reset transistor 36 of the selected row 2). When the FD potential of the selected row is returned to low, the drain line 57 is lowered, and the FD potential is lowered through the reset transistor 36 of the selected row.

In order to drive the pixel unit 10 provided with the unit pixel 3 having such a 4TR or 3TR configuration, each drive buffer 240, 250, 252, 254 (collectively referred to as a drive unit) to drive each wiring 52 , 55, 56, 57 (collectively referred to as drive control lines) are used to drive the transistors 34, 36, 40 (collectively referred to as pixel transistors) constituting the unit pixel 3.

<Operation of solid-state image sensor>
FIG. 3 is a timing chart for explaining signal acquisition difference processing, which is a basic operation in the column AD circuit 25 of the solid-state image sensor 1 shown in FIG. 1.

As a mechanism for converting an analog pixel signal sensed by each unit pixel 3 of the pixel unit 10 into a digital signal, for example, in a ramp wave-shaped reference signal RAMP descending with a predetermined inclination and a pixel signal from the unit pixel 3. Search for a point that matches each voltage of the reference component and signal component, and from the time when the reference signal RAMP used in this comparison process is generated, the time when the electrical signal corresponding to the reference component and signal component in the pixel signal and the reference signal match. By counting (counting) up to, the count value corresponding to each size of the reference component and the signal component is adopted.

Here, in the pixel signal output from the vertical signal line 19, the signal component Vsig appears after the reset component ΔV including the noise of the pixel signal as the reference component as a time series. When the first processing is performed on the reference component (reset component ΔV), the second processing is the processing on the signal obtained by adding the signal component Vsig to the reference component (reset component ΔV). This will be described in detail below.

For the first read, the communication / timing control unit 20 first sets the mode control signal CN5 to a low level, sets the counter unit 254 to the down count mode, and activates the reset control signal CN6 for a predetermined period (high in this example). Level) and reset the count value of the counter unit 254 to the initial value “0” (t8).

Then, a certain row is selected by row scanning by the vertical scanning unit 14, and after the first reading from the unit pixel 3 of the selected row Vα to the vertical signal line 19 (H1, H2, ...) Is stable, the communication / timing The control unit 20 supplies the control data CN4 for generating the reference signal RAMP (here, including the offset OFF and the inclination β) to the reference signal generation unit 27.

At the same time, the communication / timing control unit 20 gives the reset signal PSET of the active L to the voltage comparison unit 252 for a short period of time (t9). As a result, the potential of each input end of the voltage comparison unit 252 is set to a predetermined potential, and the operating point of the voltage comparison unit 252 is determined to be an appropriate level for each row selection operation.

In the reference signal generation unit 27 to which the control data CN4 is supplied, first, the reference signal generation unit 27 has a slope β that matches the color pixel characteristics of the colors existing on the Vα row, and has a stepped shape that is time-changed in a sawtooth shape (RAMP shape) as a whole. A reference signal RAMP having the above waveform (RAMP waveform) is generated by the DA conversion circuit 27a and supplied as a comparison voltage to one input terminal RAMP of the voltage comparison unit 252 of the corresponding column AD circuit 25.

The voltage comparison unit 252 in each row compares the comparison voltage of the RAMP waveform with the pixel signal voltage of the vertical signal line 19 (Hα) in the corresponding row supplied from the pixel unit 10.

Further, in order to measure the comparison time in the voltage comparison unit 252 at the same time as the input of the reference signal RAMP to the input terminal RAMP of the voltage comparison unit 252 by the counter unit 254 arranged for each row, the reference signal generation unit 27 Synchronized with the emitted lamp waveform voltage (t10), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the down count is started from the initial value "0" as the first count operation. Start. That is, the counting process is started in the negative direction.

The voltage comparison unit 252 compares the lamp-shaped reference signal RAMP from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when both voltages become the same, The comparator output is inverted from the H level to the L level (t12). That is, the voltage signal corresponding to the reset component Vrst is compared with the reference signal RAMP, and an active low (L) pulse signal is generated after a lapse of time corresponding to the magnitude of the reset component Vrst and supplied to the counter unit 254. do.

In response to this result, the counter unit 254 stops the counting operation almost at the same time as the inversion of the comparator output, and latches (holds / stores) the count value at that time as pixel data to complete the AD conversion (t12). .. That is, the down count is started at the same time as the generation of the lamp-shaped reference signal RAMP supplied to the voltage comparison unit 252, and the clock CK0 counts (counts) until the active low (L) pulse signal is obtained by the comparison process. Obtain the count value corresponding to the magnitude of the reset component Vrst.

When the predetermined down count period elapses (t14), the communication / timing control unit 20 stops the supply of the control data to the voltage comparison unit 252 and the supply of the count clock CK0 to the counter unit 254. As a result, the voltage comparison unit 252 stops the generation of the lamp-shaped reference signal RAMP.

At the time of this first reading, since the reset level Vrst in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the counting operation is performed, the reset component ΔV of the unit pixel 3 is read.

Noise that varies from unit pixel 3 to the reset component ΔV is included as an offset. However, since the variation of the reset component ΔV is generally small and the reset level Vrst is generally common to all pixels, the output value of the reset component ΔV at the pixel signal voltage Vx of any vertical signal line 19 is approximately known.

Therefore, at the time of reading the reset component ΔV for the first time, the down count period (t10 to t14; comparison period) can be shortened by adjusting the change characteristic of the RAMP voltage, thereby shortening the comparison period for the first time. It is possible. In the present embodiment, the reset component ΔV is compared by setting the maximum period of the comparison process for the reset component ΔV to a count period (128 clocks) for 7 bits.

At the time of the subsequent second reading, in addition to the reset component ΔV, the electrical signal component Vsig corresponding to the amount of incident light for each unit pixel 3 is read, and the same operation as the first reading is performed. That is, first, the communication / timing control unit 20 sets the mode control signal CN5 to a high level and sets the counter unit 254 to the upcount mode (t18). Then, after the second reading from the unit pixel 3 of the selected line Vα to the vertical signal line 19 (H1, H2, ...) Is stable, the communication / timing control unit 20 performs AD conversion processing for the signal component Vsig. , The control data CN4 for generating the reference signal RAMP is supplied to the DA conversion circuit 27a. At this time, unlike the first processing, the communication / timing control unit 20 does not set the reset signal PSET to active L.

In response to this, in the reference signal generation unit 27, first, a stepped shape having a slope β matching the color pixel characteristics of a certain color existing on the Vα row and being changed over time in a sawtooth shape (RAMP shape) as a whole. The DA conversion circuit 27a generates a reference signal RAMP that has a waveform (RAMP waveform) and is offset OFF from the initial value Var for the reset component ΔV, and is generated by the voltage comparison unit 252 of the corresponding column AD circuit 25. It is supplied as a comparison voltage to one input terminal RAMP.

The voltage comparison unit 252 in each row compares the comparison voltage of the RAMP waveform with the pixel signal voltage of the vertical signal line 19 (Hα) in the corresponding row supplied from the pixel unit 10.

At the same time as the input of the reference signal RAMP to the input terminal RAMP of the voltage comparison unit 252, it is emitted from the reference signal generation unit 27 in order to measure the comparison time in the voltage comparison unit 252 by the counter unit 254 arranged for each row. Synchronized with the lamp waveform voltage (t20), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the unit pixel 3 acquired at the time of the first reading is performed as the second counting operation. From the count value corresponding to the reset component ΔV of, the up count is started in the reverse of the first time. That is, the counting process is started in the positive direction.

The voltage comparison unit 252 compares the lamp-shaped reference signal RAMP from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when both voltages become the same, The comparator output is inverted from the H level to the L level (t22). That is, the voltage signal corresponding to the signal component Vsig is compared with the reference signal RAMP, and an active low (L) pulse signal is generated after a lapse of time corresponding to the magnitude of the signal component Vsig and supplied to the counter unit 254. do.

In response to this result, the counter unit 254 stops the counting operation almost at the same time as the inversion of the comparator output, and latches (holds / stores) the count value at that time as pixel data to complete the AD conversion (t22). .. That is, the down count is started at the same time as the generation of the lamp-shaped reference signal RAMP supplied to the voltage comparison unit 252, and the clock CK0 counts (counts) until the active low (L) pulse signal is obtained by the comparison process. Obtain the count value corresponding to the magnitude of the signal component Vsig.

When the predetermined down count period elapses (t24), the communication / timing control unit 20 stops the supply of the control data to the voltage comparison unit 252 and the supply of the count clock CK0 to the counter unit 254. As a result, the reference signal generation unit 27 stops the generation of the lamp-shaped reference signal RAMP.

At the time of this second reading, since the signal component Vsig in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the counting operation is performed, the signal component Vsig of the unit pixel 3 is read.

Here, in the present embodiment, the counting operation in the counter unit 254 is a down count at the time of the first reading and an up counting at the time of the second reading, and the count result is held in the same storage location. The subtraction represented by the equation (1) is automatically performed, and the count value corresponding to the subtraction result is held in the counter unit 254.

Here, the equation (1) can be modified as in the equation (2), and as a result, the count value held in the counter unit 254 corresponds to the signal component Vsig. Here, in order to perform high-precision color image imaging, the black standard is also considered from the viewpoint of controlling the initial value and gain for each color correspondence, but in general (including monochrome imaging), the last one. It is also possible to ignore the black reference term of the term.

That is, in the series of operations as described above, the unit pixel is subjected to the subtraction processing in the counter unit 254 by the two reading and counting processing such as the down count at the first reading and the up counting at the second reading. It is possible to remove the reset component ΔV including the variation for each of 3 and the offset component for each column AD circuit 25. Further, only the digital signal of the signal obtained by adding the correction of the black reference component to the signal component Vsig according to the amount of incident light for each unit pixel 3 can be extracted with a simple configuration.

At this time, there is an advantage that circuit variation and reset noise can be removed. That is, the output value after the second count represents a pure digital signal amount with the noise component removed. Therefore, the column AD circuit 25 of the present embodiment operates not only as a digital conversion unit that converts an analog pixel signal into digital pixel data, but also as a CDS (Correlated Double Sampling) processing function unit. It will be.

Further, since the pixel data indicated by the count value obtained in the equation (2) indicates a positive signal voltage, complement calculation or the like becomes unnecessary, and the affinity with the existing system is high.

<Example of chip structure configuration>
As the chip (semiconductor integrated circuit) structure of the solid-state image sensor 1 according to the configuration example described above, for example, a laminated chip structure can be adopted. FIG. 4 is an exploded perspective view showing an outline of the laminated chip structure of the solid-state image sensor 1.

As shown in FIG. 4, the laminated chip structure, the so-called laminated structure, is a structure in which at least two chips of a pixel chip 101, which is a second semiconductor chip, and a logic chip 102, which is a first semiconductor chip, are laminated. It has become. Then, in the circuit configuration of the unit pixel 3 shown in FIG. 2A or FIG. 2B, each of the charge generation units 32 is arranged on the pixel chip 101, and all the elements other than the charge generation unit 32 and other circuits of the unit pixel 3 are arranged. The element or the like of the portion is arranged on the logic chip 102. The pixel chip 101 and the logic chip 102 are electrically connected via a connection portion such as a via (VIA), a Cu—Cu junction, or a bump.

Although the configuration example in which the charge generation unit 32 is arranged on the pixel chip 101 and the elements other than the charge generation unit 32 and the elements of other circuit portions of the unit pixel 3 are arranged on the logic chip 102 is illustrated here. It is not limited to this configuration example.

For example, in the circuit configuration of the unit pixel 3 shown in FIG. 2A or FIG. 2B, each element of the charge generation unit 32 and the read selection transistor 34 is arranged on the pixel chip 101, and other than the charge generation unit 32 and the read selection transistor 34. The element, the element of the other circuit portion of the unit pixel 3, and the like can be arranged on the logic chip 102. Further, the charge generation unit 32, the read selection transistor 34, the reset transistor 36, and the floating diffusion 38 can be arranged on the pixel chip 101, and the other elements can be arranged on the logic chip 102.

FIG. 5 is a plan view showing an example of the configuration and arrangement of the logic chip 102. It should be noted that the pixel chip 101 and the logic chip 102 in FIG. 5 are arranged upside down as compared with those in FIG. In the example shown in FIG. 5, a vertical scanning unit 14, a column processing unit 26, a DA conversion circuit 27a, and a logic circuit are arranged on the logic chip 102. The logic circuit is, for example, a circuit other than the pixel unit 10, the vertical scanning unit 14, the column processing unit 26, and the DA conversion circuit 27a (reference signal generation unit 27) in the circuit configuration shown in FIG. The logic chip 102 is bonded at the position shown by the broken line on the pixel chip 101 of FIG.

<Structure example of multi-chip structure>
In recent years, a large sensor has adopted a structure in which a plurality of individual logic chips 102 are bonded to a large pixel chip 101. That is, each of the solid-state image pickup devices 1 includes a plurality of logic chips that AD-convert a plurality of image pickup signals. FIG. 6 is a plan view showing an example of the configuration and arrangement of the individualized logic chip 102.

In the example shown in FIG. 6, the logic chips 102 divided into two are arranged side by side in the horizontal direction. Further, each of the two logic chips 102 has the same configuration and arrangement of the vertical scanning unit 14, the column processing unit 26, the DA conversion circuit 27a, the logic circuit, and the like. This is because, for example, the two logic chips 102 are designed with the same mask. The sum of the areas of the two logic chips 102 is substantially the same as the area of the logic chips 102 shown in FIG.

Usually, when manufacturing a chip having an area larger than the exposure range of an exposure apparatus, a process of sequentially exposing while connecting a plurality of mask patterns, so-called joint exposure, may be used. For example, a pixel chip 101 of a large sensor having a size of 35 mm or a medium format is manufactured by joint exposure. On the other hand, the logic chip 102 of the large sensor may be divided into a plurality of individualized chips and bonded to the pixel chip instead of a single chip made by joint exposure.

By dividing the logic chip 102 into individualized chips, joint exposure becomes unnecessary. Joint exposure requires special design rules, manufacturing equipment and manufacturing processes. As a result, the cost becomes high. By dividing the logic chip 102 into individualized chips, the logic chip 102 can be manufactured at low cost by batch exposure. In addition, the individualized logic chip can be designed with the same mask, and the mask cost can be reduced. Since each of the plurality of logic chips 102 is designed with the same mask, they have the same size, the same shape, and the same circuit configuration. Further, by selecting the individualized chips, selecting only non-defective products and attaching them to the pixel chip 101, the yield of the laminated chips can be improved.

FIG. 7 is a plan view showing a first modification example of the configuration and arrangement of the individualized logic chip 102. In the example shown in FIG. 7, the vertical scanning unit 14 is arranged not on the logic chip 102 but on the pixel chip 101 as compared with FIG. Even in this case, each of the two logic chips 102 has the same configuration and arrangement of the column processing unit 26, the DA conversion circuit 27a, the logic circuit, and the like.

FIG. 8 is a plan view showing a second modification of the configuration and arrangement of the individualized logic chip 102. In the example shown in FIG. 8, it is divided into four logic chips 102 as compared with FIG. 7. Further, the four logic chips are manufactured from the same design data by combining left-right and up-down inversion. Two of the four logic chips are attached to the upper and lower sides of the pixel chip 101 of FIG.

FIG. 9 is a schematic view showing an example of a laminated chip structure of the solid-state image sensor 1 according to a comparative example.

Each of the plurality of logic chips 102 has a reference signal line 251, a DA conversion circuit 27aL (reference signal generation unit 27), and a column processing unit 26. As shown in FIG. 1, the column processing unit 26 includes a plurality of column AD circuits 25. In the example shown in FIG. 9, two logic chips 102 are attached to the pixel chip 101 as shown in FIG. 6 or 7. Hereinafter, the two logic chips 102 will be referred to as a left chip 102L and a right chip 102R. The left chip 102L has a DA conversion circuit 27aL, a reference signal line 251L, and a column processing unit 26L. The right chip 102R has a DA conversion circuit 27aR, a reference signal line 251R, and a column processing unit 26R.

Further, the solid-state image sensor 1 further includes signal line pitch conversion units 103L and 103R. The signal line pitch conversion units 103L and 103R are vertical signals of the pixel chip 101 so that the vertical signal line 19 extending from the pixel array (pixel unit 10) in the pixel chip 101 can be connected to the left chip 102L and the right chip 102R. Convert the pitch between the lines 19. The signal line pitch conversion units 103L and 103R can, for example, adjust the position of the vertical signal line 19 arranged in the region between the left chip 102L and the right chip 102R in the pixel chip 101.

The signal line pitch conversion unit 103L is provided between the pixel chip 101 and the left chip 102L. The signal line pitch conversion unit 103R is provided between the pixel chip 101 and the right chip 102R. The connection unit 104 shown in FIG. 9 electrically connects between the left chip 102L and the signal line pitch conversion unit 103L, and between the right chip 102R and the signal line pitch conversion unit 103R. The connecting portion 104 is, for example, a via, a Cu—Cu junction, a bump, or the like described with reference to FIG.

However, in the example shown in FIG. 9, the LSB (Least Significant Bit) weights of the lamp-shaped reference signals RAMP_L and RAMP_R may differ for each of the logic chips 102L and 102R due to the circuit variation of the left and right DA conversion circuits 27aL and 27aR. There is sex. The LSB weight affects the slope of the reference signal RAMP. For example, the slope β of the reference signal RAMP shown in FIG. 3 differs depending on the variation in the resistance and the current value for generating the reference signal RAMP. In this case, even if a horizontally uniform pixel input signal is input to the left chip 102L and the right chip 102R, the AD output level differs between the left chip 102L and the right chip 102R. Due to the difference in the AD output level, a step (shading) is visually recognized in the center of the output image of the solid-state image sensor 1. That is, when the AD conversion is performed by a plurality of logic chips that are individualized, the AD output level may vary and the image quality may deteriorate.

<First Embodiment>
FIG. 10 is a schematic view showing an example of a laminated chip structure of the solid-state image sensor 1 according to the first embodiment.

In the example shown in FIG. 10, the solid-state image sensor 1 further includes a signal line connection unit 253 and switches 255L and 255R.

The signal line connection unit 253 electrically connects the reference signal line 251L of the left chip 102L and the reference signal line 251R of the right chip 102R. The signal line connecting portion 253 passes through the pixel chip 101. The details of the signal line connecting portion 253 will be described later with reference to FIGS. 11A and 11B.

The switch 255L is provided between the DA conversion circuit 27aL and the column processing unit 26L, and switches the electrical connection between the DA conversion circuit 27aL and the column processing unit 26L.

The switch 255R is provided between the DA conversion circuit 27aR and the column processing unit 26R, and switches the electrical connection between the DA conversion circuit 27aR and the column processing unit 26R.

In the example shown in FIG. 10, the switch 255L and the switch 255R are in the closed state and the open state, respectively. As a result, the DA conversion circuit 27aL can be enabled and the DA conversion circuit 27aR can be disabled. In this case, the reference signal RAMP_L generated by the DA conversion circuit 27aL of the left chip 102L is supplied to both the column processing units 26L and 26R via the reference signal lines 251L and 251R. As a result, the influence of the difference in LSB weight due to the circuit variation of the DA conversion circuits 27aL and 27aR described with reference to FIG. 9 can be suppressed. Therefore, it is possible to suppress deterioration of image quality such as steps in the output image and shading.

The DA conversion circuit 27aR shown by diagonal lines in FIG. 10 is in a standby state. In this case, the DA conversion circuit 27aR stops the generation of the reference signal RAMP_R. The DA conversion circuit 27aR cuts the internal current path and is in a power saving state.

It should be noted that the impedance of the output of the DA conversion circuit 27aR may be increased, not necessarily limited to the case where the switches 255L and 255R are provided. For example, the right chip 102R may be manufactured using a mask different from the mask used for manufacturing the left chip 102L so as to cut the wiring on the output side of the DA conversion circuit 27aR.

Next, the details of the signal line connecting portion 253 will be described.

FIG. 11A is a cross-sectional view showing an example of the configuration of the signal line connecting portion 253 according to the first embodiment. FIG. 11B is a plan view showing an example of the configuration of the signal line connecting portion 253 according to the first embodiment. Further, in the examples shown in FIGS. 11A and 11B, the connection portion 104 shown in FIG. 10 is a Cu—Cu connection or a bump connection. In FIGS. 11A and 11B, the signal line pitch conversion units 103L and 103R are omitted.

In the example shown in FIG. 11A, two logic chips 102L and 102R are laminated on the pixel chip 101. More specifically, from the lower side to the upper side of FIG. 11A, the substrate 1021 and the wiring layer 1022 of the logic chips 102L and 102R, and the wiring layer 1012 and the substrate 1011 of the pixel chip 101 are laminated in this order. The substrate 1011 and the substrate 1021 are, for example, silicon substrates. On the substrate 1011 of the pixel chip 101, a pixel array unit in which unit pixels 3 for performing photoelectric conversion are arranged is arranged. Subsequent circuits such as a column processing unit 26 are arranged on the substrate 1021 of the logic chips 102L and 102R. Each of the wiring layers 1012 and 1022 includes a single-layer or multi-layer insulating film and a single-layer or multi-layer wiring. Further, the logic chips 102L, 102R and the pixel chip 101 are electrically connected on the bonding surface S by bumps or direct bonding between conductive materials. The substrate 1021 and the substrate 1011 are electrically connected via the wiring layers 1012 and 1022.

The signal line connection unit 253 electrically connects the reference signal line 251L of the left chip 102L and the reference signal line 251R of the right chip 102R via the pixel chip 101. The signal line connecting portion 253 has a wiring W1, pads P1 and P2, and vias V1 and V2. The wiring W1, the pad P1, and the via V1 are arranged on the pixel chip 101. The pad P2 and the via V2 are arranged on the left chip 102L and the right chip 102R, which are logic chips. A conductive material is used as the material for the wiring W1, the pads P1, P2, and the vias V1 and V2.

The wiring W1 is provided on a certain layer in the wiring layer 1012 of the pixel chip 101. The pads P1 and P2 are provided to electrically connect the pixel chip 101 and the logic chip 102 on the bonding surface S. The via V1 is provided substantially parallel to the stacking direction of the chips, and electrically connects the wiring W1 and the pad P1. The via V2 is provided substantially parallel to the stacking direction of the chips, and electrically connects the reference signal line 251L and the pad P2. The via V2 may be provided so as to be electrically connected to a plurality of wiring layers.

As shown in FIG. 11A, the reference signal line 251L is electrically connected to the wiring W1 via the via V2, the pad P2, and the pad P1 on the left chip 102L side. Similarly, the reference signal line 251R is electrically connected to the wiring W1 via the via V2, the pad P2, and the pad P1 on the right chip 102R side. As a result, the reference signal lines 251L and 251R are electrically connected.

As shown in FIG. 11B, when viewed from above or below in FIG. 11A, the reference signal line 251L and the wiring W1 overlap at the positions of the vias V1 and V2 on the left chip 102L side. Similarly, the reference signal line 251R and the wiring W1 overlap at the positions of the vias V1 and V2 on the right chip 102R side.

FIG. 12A is a cross-sectional view showing a first modification of the configuration of the signal line connecting portion 253 according to the first embodiment. FIG. 12B is a plan view showing a first modification of the configuration of the signal line connecting portion 253 according to the first embodiment. Further, in the example shown in FIGS. 12A and 12B, the connection portion 104 shown in FIG. 10 is a TSV (Through Silicon Via). Therefore, the logic chips 102L, 102R and the pixel chip 101 are electrically connected on the bonding surface S by direct bonding between vias or conductive materials.

The signal line connecting portion 253 shown in FIGS. 12A and 12B has wirings W2 and W3 and vias V3 and V4. The wirings W2, W3 and via V4 are arranged on the pixel chip 101. The vias V3 and V4 are provided so as to penetrate the substrate 1011 (for example, a silicon substrate) of the pixel chip 101. Further, the via V3 is arranged so as to penetrate the pixel chip 101 and reach the left chip 102L and the right chip 102R. A conductive material is used as the material for the wirings W2 and W3 and the vias V3 and V4.

The wiring W2 is provided on the substrate 1011 of the pixel chip 101. The wiring W3 is provided in a layer in the wiring layer 1012 of the pixel chip 101. The via V3 is provided to electrically connect the pixel chip 101 and the logic chip 102. The via V3 is provided substantially parallel to the stacking direction of the chips, and electrically connects the wiring W2 with the reference signal line 251L and the reference signal line 251R. The via V4 is provided substantially parallel to the stacking direction of the chips, and electrically connects the wiring W2 and the wiring W3.

As shown in FIG. 12A, the reference signal line 251L is electrically connected to the wiring W3 via the via V3, the wiring W2, and the via V4 on the left chip 102L side. Similarly, the reference signal line 251R is electrically connected to the wiring W3 via the via V3, the wiring W2, and the via V4 on the right chip 102R side. As a result, the reference signal lines 251L and 251R are electrically connected.

As shown in FIG. 12B, when viewed from above or below in FIG. 12A, the reference signal line 251L and the wiring W2 on the left chip 102L side overlap at the position of the via V3 on the left chip 102L side. At the position of the via V4 on the left chip 102L side, the wiring W2 and the wiring W3 on the left chip 102L side overlap. Similarly, at the position of the via V3 on the right chip 102R side, the reference signal line 251R and the wiring W2 on the right chip 102R side overlap. At the position of the via V4 on the right chip 102R side, the wiring W2 and the wiring W3 on the right chip 102R side overlap.

Next, the details of the internal configuration of the reference signal supply IF unit 28 shown in FIG. 1 will be described.

13A and 13B are schematic configuration diagrams showing an example of the configuration of the reference signal supply IF unit 28 according to the first embodiment. 13A and 13B show the reference signal supply IF unit 28 of the left chip 102L and the right chip 102R, respectively.

In the example shown in FIG. 13A, the reference signal RAMP_L generated by the DA conversion circuit 27aL is supplied to the reference signal line 251L. A plurality of nodes NL corresponding to the number of column AD circuits 25 are provided on the reference signal line 251L. The node NL is connected to the reference signal output line 281 of the column AD circuit 25. As a result, the reference signal RAMP_L is supplied to each column AD circuit 25.

In the example shown in FIG. 13B, as described above, the reference signal line 251R of the right chip 102R is electrically connected to the reference signal line 251L of the left chip 102L. Therefore, the reference signal RAMP_L is supplied to the reference signal line 251R. A plurality of node NRs corresponding to the number of column AD circuits 25 are provided on the reference signal line 251R. The node NR is connected to the reference signal output line 281 of the column AD circuit 25. As a result, the reference signal RAMP_L is supplied to each column AD circuit 25.

14A and 14B are schematic configuration diagrams showing a first modification of the configuration of the reference signal supply IF unit 28 according to the first embodiment. 14A and 14B show the reference signal supply IF unit 28 of the left chip 102L and the right chip 102R, respectively.

In the example shown in FIGS. 14A and 14B, the reference signal supply IF unit 28 has a plurality of buffer units 282 and an output wiring 283.

The plurality of buffer units 282 buffer the reference signal RAMP on the reference signal line 251 in association with each of the plurality of column AD circuits 25. This makes it possible to speed up the response of the long wiring or high-load reference signal lines 251L and 251R, and to reduce the influence of kickback from the voltage comparison unit 252. A plurality of buffer units 282 are provided between the column AD circuit 25 and the node NL and the node NR.

The output wiring 283 electrically connects the output sides of the plurality of buffer units 282 so that the output nodes of the plurality of buffer units 282 are commonly connected. That is, the output wiring 283 can short-circuit the output of the buffer unit 282 between the plurality of buffer units 282. As a result, the output of the buffer unit 282 can be averaged, and the random noise generated from the buffer unit 282 can be reduced. A node NO is provided on the reference signal output line 281 between the buffer unit 282 and the column AD circuit 25. The node NO is electrically connected to the output wiring 283. Further, the output wiring 283 supplies the reference signal RAMP_O to each column AD circuit 25. The output wiring 283 of the left chip 102L and the output wiring 283 of the right chip 102R are electrically connected. More specifically, the output wiring 283 of the left chip 102L and the output wiring 283 of the right chip 102R are electrically connected via the pixel chip 101. Therefore, the output of the buffer unit 282 is averaged between the left chip 102L and the right chip 102R.

FIG. 15 is a circuit diagram showing an example of the configuration of the buffer unit 282. In the example shown in FIG. 15, the buffer unit 282 is a source follower circuit to which the reference signal RAMP_L is input and the reference signal RAMP_O is output.

The buffer unit 282 includes a transistor 2821 and a current source 2822. The transistor 2821 is, for example, a P-type transistor. The reference signal RAMP_L is input to the gate of the transistor 2821 connected to the reference signal lines 251L and 251R. The reference signal RAMP_O is output from the node between the source of the transistor 2821 and the current source 2822, which is connected to the output wiring 283.

As described above, in the first embodiment, the reference signal line 251L of the left chip 102L and the reference signal line 251R of the right chip 102R are electrically connected. The reference signal RAMP_L generated by the DA conversion circuit 27aL of the left chip 102L is supplied to the reference signal lines 251L and 251R. The DA conversion circuit 27aR of the right chip 102R is invalidated. Thereby, the influence of the variation of the LSB weight among the plurality of divided logic chips 102 can be suppressed. Therefore, it is possible to suppress variations in AD output among the plurality of divided logic chips 102. As a result, deterioration of image quality can be suppressed.

The number of divided logic chips 102 is not limited to two. The first embodiment can also be applied when the number of logic chips 102 is three or more. In this case, the plurality of reference signal lines 251 in the plurality of logic chips 102 are electrically connected to each other. The reference signal RAMP generated by the DA conversion circuit 27a in any one of the plurality of logic chips 102 is supplied to the plurality of reference signal lines 251. At the time of AD conversion, the DA conversion circuit 27a in the other logic chips 102 other than one logic chip 102 stops the generation of the reference signal RAMP. Further, with respect to the output wirings 283 shown in FIGS. 14A and 14B, the plurality of output wirings 283s in the plurality of logic chips 102 are electrically connected to each other.

<Second Embodiment>
FIG. 16 is a schematic view showing an example of a laminated chip structure of the solid-state image sensor 1 according to the second embodiment. The second embodiment is different from the first embodiment in that the DA conversion circuit 27aR of the right chip 102R is enabled.

The solid-state image sensor 1 further includes a signal level acquisition unit 105 and a gain adjustment unit 106. The signal level acquisition unit 105 and the gain adjustment unit 106 may be provided in a plurality of logic chips 102 (left chip 102L and right chip 102R), respectively.

The signal level acquisition unit 105 acquires the signal levels of the reference signals RAMP_L and RAMP_R. The signal level acquisition unit 105 acquires, for example, the LSB weights of the DA conversion circuits 27aL and 27aR.

The gain adjusting unit 106 performs signal correction processing based on the signal level acquired by the signal level acquisition unit 105. The gain adjusting unit 106 adjusts, for example, the analog gain of the reference signals RAMP_L and RAMP_R generated by the DA conversion circuits 27aR and 27aL, or adjusts the digital gain of the digital signal AD-converted by the column processing units 26R and 26L. ..

FIG. 17 is a diagram showing an example of gain adjustment according to the second embodiment.

In the example shown in FIG. 17, the LSB weight of the DA conversion circuit 27aL before adjustment is higher than the LSB weight of the DA conversion circuit 27aR. When the reference signal lines 251L and 251R are not short-circuited by the signal line connecting portion 253, there is a difference in the LSB weights as shown by the broken line. In this case, as in the comparative example described with reference to FIG. 9, a step is visually recognized in the center of the output image of the solid-state image sensor 1.

When the reference signal lines 251L and 251R are short-circuited by the signal line connecting portion 253, the LSB weight changes gently in the horizontal direction between the DA conversion circuit 27aL and the DA conversion circuit 27aR, as shown by the solid line. This is because the reference signal lines 251L and 251R and the signal line connection portion 253 have a finite impedance. This gently changing shape of the LSB weight leads to horizontal shading of the output image of the solid-state image sensor 1.

Next, a method for suppressing the influence of the difference in LSB weights will be described.

First, the signal level acquisition unit 105 acquires information on the amount of deviation of the LSB weights of the left and right DA conversion circuits 27aL and 27aR. The signal level acquisition unit 105 directly measures, for example, the outputs of the DA conversion circuits 27a and 27aR with a voltmeter (not shown) or the like. In addition, the signal level acquisition unit 105, for example, when a common signal amount is given to the vertical signal line 19 (vsl) of all columns from the test circuit, AD conversion output from the sensor (solid-state image sensor 1). From the result (for example, an image), it may be calculated from the output average difference between the left end and the right end.

Next, the signal level acquisition unit 105 measures the amount of deviation of the LSB weight at the time of sensor selection, and writes the acquired information in a storage unit such as a ROM (Read Only Memory). The signal level acquisition unit 105 may dynamically acquire the signal level for each actual operation of the sensor.

Next, the gain adjusting unit 106 adjusts the DA conversion circuits 27aL and 27R so that the LSB weights of the left and right DA conversion circuits 27aL and 27R are aligned from the acquired LSB weight deviation amount. An analog gain is used as an example of the adjusting means. The DA conversion circuit 27a of the slope type AD conversion circuit often has a function of setting an analog gain. The analog gain setting is often used, for example, for adjusting the ISO sensitivity and adjusting the RGB auto white balance. The set value of this analog gain is directly linked to the LSB weight. The gain adjusting unit 106 adjusts the analog gain based on the ratio of the plurality of reference signal RAMPs in the plurality of reference signal lines 251. For example, the gain adjusting unit 106 directly inputs the analog gain input to the sensor to the DA conversion circuit 27aL of the left chip 102L to the DA conversion circuit 27aL of the left chip 102L. On the other hand, the gain adjusting unit 106 multiplies the analog gain input to the DA conversion circuit 27aL by the deviation (ratio) of the LSB weights of the left and right DA conversion circuits 27aL to the DA conversion circuit 27aR of the right chip 102R. input. As a result, as shown in FIG. 17, the LSB weights after the analog gain adjustment are substantially the same in the left and right DA conversion circuits 27aL and 27aR. As a result, deterioration of image quality such as shading can be suppressed.

FIG. 18 is a diagram showing a first modification of the gain adjustment according to the second embodiment.

First, the column processing units 26L and 26R perform AD conversion of the signal while the LSB weights of the left and right DA conversion circuits 27aL and 27aR remain deviated. After that, the gain adjusting unit 106 gain-corrects the AD-converted signal by digital processing in the subsequent stage. Therefore, the gain adjusting unit 106 adjusts the digital gain by comparing the plurality of digital signals output from each of the plurality of logic chips 102. As shown in FIG. 18, the LSB weight changes depending on the position on the reference signal lines 251L and 251R, that is, the position of the column AD circuit 25. The gain adjusting unit 106 has, for example, a digital gain value and a shape so that the product of the digital gain value applied to the column AD circuit 25 and the LSB weight at the positions on the reference signal lines 251L and 251R is constant. To decide. The shape of the digital gain is a shape showing the value of the digital gain with respect to the positions on the reference signal lines 251L and 251R. The shape of the digital gain shown in FIG. 17 has a magnitude relationship opposite to that of the shape of the LSB weight. By correcting by digital processing in this way, as shown in FIG. 18, the shape of the digital signal level after the digital gain correction becomes substantially flat.

As described above, in the second embodiment, by correcting the difference in the signal level of the reference signal, even when the reference signals RAMP_L and RAMP_R are supplied from a plurality of DA conversion circuits 27aL or 27aR, the output image is horizontal. It is possible to suppress deterioration of image quality such as shading.

Further, in the second embodiment, since the plurality of DA conversion circuits 27aL and 27aR supply the reference signal RAMP as compared with the first embodiment, the response of the reference signal lines 251L and 251R can be accelerated. In addition, it is usually necessary to increase the area of analog elements such as transistors, resistors and capacitors in order to secure the analog characteristics of the DA conversion circuits 27aL and 27aR such as noise and linearity. In the second embodiment, by short-circuiting the left and right DA conversion circuits 27aL and 27aR, characteristics corresponding to a DA conversion circuit having an apparently twice the area can be obtained. That is, as compared with the first embodiment, the DA conversion circuit 27a duplicated by the same design data can be effectively used, and the area efficiency is high. Further, the area of each DA conversion circuit 27aL, 27aR can be reduced according to the required analog characteristics.

The internal configuration of the reference signal supply IF unit 28 according to the second embodiment is the same as the internal configuration of the reference signal supply IF unit 28 described with reference to FIGS. 13A and 13B or FIGS. 14A and 14B. ..

The number of divided logic chips 102 is not limited to two. The second embodiment can also be applied when the number of logic chips 102 is three or more.

<Third Embodiment>
FIG. 19 is a schematic view showing an example of a laminated chip structure of the solid-state image sensor 1 according to the third embodiment. The third embodiment is different from the first embodiment and the second embodiment in that the influence of the deviation of the LSB weight is suppressed by the connection relationship between the DA conversion circuits 27aL and 27aR and the column AD circuit 25. The third embodiment is common to the first embodiment in that the reference signal RAMP generated by one DA conversion circuit 27a is supplied to one reference signal line 251. The third embodiment is common to the second embodiment in that both the DA conversion circuits 27aL and 27aR are enabled. Further, in the third embodiment, the gain adjustment may not be performed.

In the example shown in FIG. 19, the reference signal line 251L of the left chip 102L includes a first reference signal line 251LL and a second reference signal line 251LR. The reference signal line 251R of the right chip 102R includes a first reference signal line 251RL and a second reference signal line 251RR. Note that FIG. 19 also shows the output wiring 283 described with reference to FIGS. 14A and 14B.

The first reference signal line 251LL of the left chip 102L and the first reference signal line 251RL of the right chip 102R are electrically connected via the signal line connecting portion 253.

The DA conversion circuit 27aL of the left chip 102L supplies the reference signal RAMP_L to the first reference signals 251LL and 251RL, but does not supply the reference signal RAMP_L to the second reference signals 251LR and 251RR.

The first reference signal line 251LL of the left chip 102L supplies the reference signal RAMP_L generated by the DA conversion circuit 27aL to the column processing unit 26L. The first reference signal line 251RL of the right chip 102R supplies the reference signal RAMP_L generated by the DA conversion circuit 27aL to the column processing unit 26R.

The second reference signal line 251LR of the left chip 102L and the second reference signal line 251RR of the right chip 102R are electrically connected via the signal line connecting portion 253.

The DA conversion circuit 27aR of the right chip 102R supplies the reference signal RAMP_R to the second reference signals 251LR and 251RR, but does not supply the reference signal RAMP_R to the first reference signals 251LL and 251RL.

The second reference signal line 251LR of the left chip 102L supplies the reference signal RAMP_R generated by the DA conversion circuit 27aR to the column processing unit 26L. The second reference signal line 251RR of the right chip 102R supplies the reference signal RAMP_L generated by the DA conversion circuit 27aR to the column processing unit 26R.

The output wiring 283 of the left chip 102L and the output wiring 283 of the right chip 102R are electrically connected via the signal line connecting portion 253.

Next, the internal configuration of the reference signal supply IF unit 28 shown in FIG. 1 and the details of the connection between the DA conversion circuit 27a and the column AD circuit 25 will be described.

20A and 20B are schematic configuration diagrams showing an example of the configuration of the reference signal supply IF unit 28 according to the third embodiment. 20A and 20B show the reference signal supply IF unit 28 of the left chip 102L and the right chip 102R, respectively.

In the example shown in FIG. 20A, the column AD circuit 25 of the left chip 102L is divided into a column AD circuit 25LL connected to the first reference signal line 251LL and a column AD circuit 25LR connected to the second reference signal line 251LR. .. The first reference signal line 251LL supplies the reference signal RAMP_L to the plurality of column AD circuits 25LL among the plurality of column AD circuits 25. The second reference signal line 251LR supplies the reference signal RAMP_R to the plurality of column AD circuits 25LR among the plurality of column AD circuits 25.

The column AD circuit 25LL and the column AD circuit 25LR are alternately arranged along the first reference signal line 251LL and the second reference signal line 251LL. That is, the first reference signal line 251LL and the second reference signal line 251LR are alternately connected to the plurality of column AD circuits 25.

In the example shown in FIG. 20A, the reference signal RAMP_L generated by the DA conversion circuit 27aL is supplied to the first reference signal line 251LL. A plurality of nodes NLL corresponding to the number of column AD circuits 25LL are provided on the first reference signal line 251LL. The node NLL is connected to the reference signal output line 281 of the column AD circuit 25LL.

Further, the reference signal RAMP_R generated by the DA conversion circuit 27aR is supplied to the second reference signal line 251LR. A plurality of node NLRs corresponding to the number of column AD circuits 25LR are provided on the second reference signal line 251LR. The node NLR is connected to the reference signal output line 281 of the column AD circuit 25LR.

In the example shown in FIG. 20B, the column AD circuit 25 of the right chip 102R is divided into a column AD circuit 25RL connected to the first reference signal line 251RL and a column AD circuit 25RR connected to the second reference signal line 251RR. .. The first reference signal line 251RL supplies the reference signal RAMP_L to the plurality of column AD circuits 25RL among the plurality of column AD circuits 25. The second reference signal line 251RR supplies the reference signal RAMP_R to the plurality of column AD circuits 25RR among the plurality of column AD circuits 25.

The column AD circuit 25RL and the column AD circuit 25RR are alternately arranged along the first reference signal line 251RL and the second reference signal line 251RR. That is, the first reference signal line 251RL and the second reference signal line 251RR are alternately connected to the plurality of column AD circuits 25.

In the example shown in FIG. 20B, the reference signal RAMP_L generated by the DA conversion circuit 27aL is supplied to the first reference signal line 251RL. A plurality of node NRLs corresponding to the number of column AD circuits 25RL are provided on the first reference signal line 251RL. The node NRL is connected to the reference signal output line 281 of the column AD circuit 25RL.

Further, the reference signal RAMP_R generated by the DA conversion circuit 27aR is supplied to the second reference signal line 251RR. A plurality of node NRRs corresponding to the number of column AD circuits 25RR are provided on the second reference signal line 251RR. The node NRR is connected to the reference signal output line 281 of the column AD circuit 25RR.

Here, the reference signal supply IF unit 28 has a plurality of buffer units 282 and an output wiring 283. The buffer unit 282 and the output wiring 283 shown in FIGS. 20A and 20B are the same as the buffer unit 282 and the output wiring 283 described with reference to FIGS. 14A and 14B.

The buffer unit 282 is provided between the column AD circuit LL and the node NLL, between the column AD circuit LR and the node NLR, between the column AD circuit RL and the node NRL, and between the column AD circuit RR and the node NRR. It is provided in multiple places.

The output wiring 283 shorts the output side of the plurality of buffer units 282. Thereby, the reference signal RAMP_L generated by the DA conversion circuit 27aL and the reference signal RAMP_O obtained by averaging the reference signal RAMP_R generated by the DA conversion circuit 27aR can be supplied to each column AD circuit 25. That is, even if there is a circuit variation between the DA conversion circuits 27aL and 27aR, a more uniform reference signal RAMP_O is supplied to each column AD circuit 25 regardless of the position on the reference signal lines 251L and 251R. As a result, deterioration of image quality such as shading of the output video can be suppressed. Further, the output wirings 283 of the left chip 102L and the right chip 102R are electrically connected to each other. As a result, the output of the buffer unit 282 can be averaged between the left chip 102L and the right chip 102R.

21A and 21B are schematic configuration diagrams showing a first modification of the configuration of the reference signal supply IF unit 28 according to the third embodiment. 21A and 21B show the reference signal supply IF unit 28 of the left chip 102L and the right chip 102R, respectively.

In the example shown in FIG. 21A, as compared to FIG. 20A, the column AD circuit 25LL and the column AD circuit 25LR are provided for every two column AD circuits 25 along the first reference signal line 251LL and the second reference signal line 251LR. Arranged alternately. That is, the first reference signal line 251LL and the second reference signal line 251LR are alternately connected to the column AD circuit 25 with two or more predetermined number of column AD circuits 25 in the plurality of column AD circuits 25 as the unit U.

Similarly, in the example shown in FIG. 21B, as compared to FIG. 20B, the column AD circuit 25RL and the column AD circuit 25RR are two column AD circuits along the first reference signal line 251RL and the second reference signal line 251RR. It is arranged alternately every 25. That is, the first reference signal line 251RL and the second reference signal line 251RR are alternately connected to the column AD circuit 25 with two or more predetermined number of column AD circuits 25 in the plurality of column AD circuits 25 as the unit U.

The larger the predetermined number of units U, the easier it is to manufacture the logic chip 102. On the other hand, as the predetermined number of units U becomes larger, shading may be more likely to occur. Therefore, the predetermined number of units U may be changed depending on the ease of manufacture and the required performance.

As described above, in the third embodiment, the reference signals RAMP_L and RAMP_R generated by the two DA conversion circuits 27aL and 27aR are alternately supplied to the plurality of column AD circuits 25 in which they are arranged. Further, the output side of the buffer unit 282 is short-circuited by the output wiring 283. Thereby, the LSB weight of the reference signal RAMP supplied to each column AD circuit 25 can be made more uniform regardless of the position on the reference signal lines 251L and 251R. Therefore, even if there are circuit variations in the left and right DA conversion circuits 27aL and 27aR, the reference signal RAMP generated by the DA conversion circuits 27aL and 27aR can be more appropriately averaged. As a result, deterioration of image quality such as horizontal shading of the output video can be suppressed.

Further, in the third embodiment, as in the second embodiment, the response of the reference signal lines 251L and 251R can be accelerated, and the area of each DA conversion circuit 27aL and 27aR can be reduced.

Further, in the third embodiment, the signal level acquisition unit 105 and the gain adjustment unit 106 are unnecessary as compared with the second embodiment. Further, in the third embodiment, even when the DAC linearity is poor, the outputs of the DA conversion circuits 27aL and 27aR can be more appropriately averaged, and shading can be suppressed. The DAC linearity indicates the linearity of the output characteristics between the ideal analog output and the actual analog output in the DA conversion circuit 27a.

FIG. 22 is a diagram showing an example of the output characteristics of the DA conversion circuits 27aL and 27aR according to the second embodiment when the DAC linearity of the DA conversion circuits 27aL and 27aR is good.

The output characteristics of the DA conversion circuit 27aL shown by the dotted line are substantially linear. The output characteristics of the DA conversion circuit 27aR shown by the broken line are substantially linear. Further, the actual output level at the intersection PL between the output characteristic (dotted line) of the DA conversion circuit 27aL and the ideal output level ref is the actual output level at the intersection PR between the output characteristic (broken line) of the DA conversion circuit 27aR and the ideal output level ref. Lower than the output level. The ideal output level ref is, for example, a certain ideal output level in which the deviation of the LSB weights of the left and right DA conversion circuits 27aL and 27aR is measured. The output characteristics of the DA conversion circuit 27aL shown by the solid line show the output characteristics of the DA conversion circuit 27aL whose analog gain has been adjusted so as to reduce the difference in the actual output level between the intersection PL and the intersection PR.

When the DAC linearity is good, the output characteristics of the DA conversion circuit 27aR shown by the broken line and the output characteristics of the DA conversion circuit 27aL shown by the solid line are almost the same in a wide range of the ideal output. Therefore, even if the LSB weight deviation acquired at one output level is applied to another output level, the error of the actual output level is small.

FIG. 23 is a diagram showing an example of the output characteristics of the DA conversion circuits 27aL and 27aR according to the second embodiment when the DAC linearity of the DA conversion circuits 27aL and 27aR is not good.

When the DAC linearity is not good, the output characteristics of the DA conversion circuit 27aR shown by the broken line and the output characteristics of the DA conversion circuit 27aL shown by the solid line do not match and shift at ideal outputs other than the ideal output level ref. Therefore, if the LSB weight deviation acquired at one output level is applied to another output level, a large error will occur in the actual output level.

FIG. 24 is a diagram showing an example of the output characteristics of the DA conversion circuits 27aL and 27aR according to the third embodiment when the DAC linearity of the DA conversion circuits 27aL and 27aR is not good.

In the third embodiment, the output characteristics of the DA conversion circuits 27aL and 27aR are averaged by the connection between the DA conversion circuits 27aL and 27aR and the column AD circuit 25 described with reference to FIGS. 20A and 20B. Can be done. The output characteristics of the averaged DA conversion circuits 27aL and 27aR shown by the alternate long and short dash line are the output characteristics obtained by averaging the output characteristics of the DA conversion circuit 27aL shown by the dotted line and the output characteristics of the DA conversion circuit 27aL shown by the broken line. be. The output characteristics are averaged over the entire range of ideal outputs. Therefore, in the third embodiment, even when the DAC linearity of the DA conversion circuits 27aL and 27aR is not good, the error of the actual output level can be suppressed, and the deterioration of the image quality such as shading can be suppressed. can.

The number of divided logic chips 102 is not limited to two. The third embodiment can also be applied when the number of logic chips 102 is three or more. In this case, each of the plurality of logic chips 102 has a plurality of reference signal lines 251. The corresponding reference signal lines 251 in each of the plurality of logic chips 102 are electrically connected to each other. The DA conversion circuit 27a in each of the plurality of logic chips 102 supplies the reference signal RAMP to the different reference signal lines 251.

Further, in the above embodiment, a CMOS type solid-state imaging device that is sensitive to an external electromagnetic wave such as light or radiation has been exemplified, but any device that detects a change in a physical quantity can be used in the above embodiment. The mechanism described above can be applied, and not limited to light, for example, a fingerprint authentication device that detects a fingerprint image based on changes in electrical characteristics and optical characteristics based on pressure (Japanese Patent Laid-Open No. 2002-7984). And Japanese Patent Laid-Open No. 2001-125734), the above embodiment is similarly applied as a noise countermeasure on the reference signal line when converting an analog signal into a digital signal in a mechanism for detecting other physical changes. be able to.

<Example of application to moving objects>
The technique according to the present disclosure (the present technique) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle outside information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information in the vehicle. For example, a driver state detection unit 12041 that detects a driver's state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio-image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 25, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 26 is a diagram showing an example of the installation position of the image pickup unit 12031.

In FIG. 26, the vehicle 12100 has image pickup units 12101, 12102, 12103, 12104, 12105 as image pickup units 12031.

The image pickup units 12101, 12102, 12103, 12104, 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The image pickup unit 12101 provided in the front nose and the image pickup section 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The image pickup units 12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100. The image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The images in front acquired by the image pickup units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 26 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the image pickup units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera including a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like that autonomously travels without relying on the driver's operation.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104. Such recognition of a pedestrian is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and pattern matching processing is performed on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the image pickup unit 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The example of the vehicle control system to which the technique according to the present disclosure can be applied has been described above. The technique according to the present disclosure can be applied to, for example, the image pickup unit 12031, 12101, 12102, 12103, 12104, 12105, the driver state detection unit 12041, and the like among the configurations described above. Specifically, for example, the solid-state image pickup device 1 of the present disclosure can be applied to these image pickup units and detection units. Then, by applying the technique according to the present disclosure, it is possible to suppress deterioration of the image quality of the captured image, so that safer vehicle driving can be realized. Further, the electronic device according to the present disclosure can be applied to, for example, the vehicle control system 12000. The signal processing unit in the electronic device may be applied to, for example, the microcomputer 12051.

The present technology can have the following configurations.
(1) Each is provided with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
A solid-state image pickup device in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines.
(2) The solid-state image pickup device according to (1), wherein when the AD conversion is performed, the reference signal generation unit in a chip other than the one chip stops the generation of the reference signal.
(3) Each is provided with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
It has an analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips, or a gain adjustment unit for adjusting the digital gain of the plurality of digital signals.
A solid-state image pickup device in which a plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
(4) The solid-state image pickup device according to (3), wherein the gain adjusting unit adjusts the analog gain based on the ratio of the plurality of reference signals in the plurality of reference signal lines.
(5) The solid-state image pickup device according to (3), wherein the gain adjusting unit adjusts the digital gain by comparing the plurality of digital signals output from each of the plurality of first semiconductor chips.
(6) Each of the plurality of first semiconductor chips is
A plurality of buffer units for buffering the reference signal on the reference signal line in association with each of the plurality of ADCs.
Further, it has an output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The solid-state image pickup device according to any one of (1) to (5), wherein the plurality of output wirings in the plurality of first semiconductor chips are electrically connected to each other.
(7) Each of the plurality of first semiconductor chips has a plurality of the reference signal lines.
The corresponding reference signal lines in each of the plurality of first semiconductor chips are electrically connected to each other.
The solid-state image pickup device according to (6), wherein the reference signal generation unit in each of the plurality of first semiconductor chips supplies the reference signal to different reference signal lines.
(8) The plurality of first semiconductor chips have two first semiconductor chips arranged in a predetermined direction.
Each of the two first semiconductor chips has the two reference signal lines.
The two reference signal lines of one of the two first semiconductor chips are electrically connected to the corresponding reference signal line of the other of the two first semiconductor chips.
The reference signal output from the reference signal generation unit of one of the two first semiconductor chips is supplied to one of the two reference signal lines.
The solid-state image pickup device according to (7), wherein the reference signal output from the reference signal generation unit of the other of the two first semiconductor chips is supplied to the other of the two reference signal lines.
(9) The solid-state image pickup device according to (8), wherein the two reference signal lines are alternately connected to the plurality of ADCs.
(10) The solid-state image pickup device according to (8), wherein the two reference signal lines are alternately connected to the ADC in units of two or more predetermined number of the ADCs in the plurality of ADCs.
(11) Each of the two first semiconductor chips has the plurality of buffer units and the output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The solid-state image pickup device according to any one of (8) to (10), wherein the two output wirings of the two first semiconductor chips are electrically connected to each other.
(12) The solid-state image pickup device according to any one of (1) to (11), wherein each of the plurality of first semiconductor chips has the same size, the same shape, and the same circuit configuration.
(13) The solid-state image pickup apparatus according to any one of (1) to (12), further comprising a second semiconductor chip laminated on the first semiconductor chip and having a pixel array unit for performing photoelectric conversion.
(14) The solid-state image pickup device according to (13), wherein the first semiconductor chip and the second semiconductor chip are electrically connected by direct bonding of vias, bumps, or conductive materials.
(15) A signal line for transmitting a plurality of imaging signals photoelectrically converted by a plurality of pixels arranged in a predetermined direction is connected to each of the plurality of ADCs.
The plurality of ADCs are any one of (1) to (14), which converts the plurality of image pickup signals into the plurality of digital signals based on the comparison between the image pickup signal on the corresponding signal line and the reference signal. The solid-state imaging device according to the section.
(16) The solid-state image sensor according to any one of (1) to (15), wherein the reference signal is a signal whose voltage level changes with time.
(17) A solid-state image sensor that outputs a digital signal according to the image pickup signal, and
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
An electronic device in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines.
(18) A solid-state image sensor that outputs a digital signal according to the image pickup signal, and
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of first semiconductor chips having a gain adjusting unit for adjusting the analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips or the digital gain of the plurality of digital signals. An electronic device in which a plurality of the reference signal lines are electrically connected to each other.

The aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.

1 solid-state imager, 3 unit pixel, 10 pixel part, 19 vertical signal line, 25 column AD circuit, 251 reference signal line, 251LL first reference signal line, 251RL first reference signal line, 251LR second reference signal line, 251RR 2nd reference signal line, 26 column processing unit, 27 reference signal generation unit, 27a DA conversion circuit, 28 reference signal supply IF unit, 32 charge generation unit, 101 pixel chip, 102 logic chip, 102L left chip, 102R right chip, 104 connection part, 105 signal level acquisition part, 106 gain adjustment part, 253 signal line connection part, 282 buffer part, 283 output wiring, RAMP reference signal, U unit

Claims (18)

Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
A solid-state image pickup device in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines. The solid-state image pickup device according to claim 1, wherein when the AD conversion is performed, the reference signal generation unit in a chip other than the one chip stops the generation of the reference signal. Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
It has an analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips, or a gain adjustment unit for adjusting the digital gain of the plurality of digital signals.
A solid-state image pickup device in which a plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other. The solid-state image sensor according to claim 3, wherein the gain adjusting unit adjusts the analog gain based on the ratio of the plurality of reference signals in the plurality of reference signal lines. The solid-state imaging device according to claim 3, wherein the gain adjusting unit adjusts the digital gain by comparing the plurality of digital signals output from each of the plurality of first semiconductor chips. Each of the plurality of first semiconductor chips
A plurality of buffer units for buffering the reference signal on the reference signal line in association with each of the plurality of ADCs.
Further, it has an output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The solid-state image pickup device according to claim 1, wherein the plurality of output wirings in the plurality of first semiconductor chips are electrically connected to each other. Each of the plurality of first semiconductor chips has a plurality of the reference signal lines.
The corresponding reference signal lines in each of the plurality of first semiconductor chips are electrically connected to each other.
The solid-state image pickup device according to claim 6, wherein the reference signal generation unit in each of the plurality of first semiconductor chips supplies the reference signal to different reference signal lines. The plurality of first semiconductor chips have two first semiconductor chips arranged in a predetermined direction.
Each of the two first semiconductor chips has the two reference signal lines.
The two reference signal lines of one of the two first semiconductor chips are electrically connected to the corresponding reference signal line of the other of the two first semiconductor chips.
The reference signal output from the reference signal generation unit of one of the two first semiconductor chips is supplied to one of the two reference signal lines.
The solid-state image pickup device according to claim 7, wherein the reference signal output from the reference signal generation unit of the other of the two first semiconductor chips is supplied to the other of the two reference signal lines. The solid-state image pickup device according to claim 8, wherein the two reference signal lines are alternately connected to the plurality of ADCs. The solid-state image pickup device according to claim 8, wherein the two reference signal lines are alternately connected to the ADC in units of two or more predetermined number of the ADCs in the plurality of ADCs. Each of the two first semiconductor chips has the plurality of buffer units and the output wiring to which the output nodes of the plurality of buffer units are commonly connected.
The solid-state image pickup device according to claim 8, wherein the two output wirings of the two first semiconductor chips are electrically connected to each other. The solid-state image pickup device according to claim 1, wherein each of the plurality of first semiconductor chips has the same size, the same shape, and the same circuit configuration. The solid-state image pickup device according to claim 1, further comprising a second semiconductor chip laminated on the first semiconductor chip and having a pixel array unit for performing photoelectric conversion. The solid-state image pickup device according to claim 13, wherein the first semiconductor chip and the second semiconductor chip are electrically connected by direct bonding of vias, bumps, or conductive materials. A signal line for transmitting a plurality of imaging signals photoelectrically converted by a plurality of pixels arranged in a predetermined direction is connected to each of the plurality of ADCs.
The solid-state imaging device according to claim 1, wherein the plurality of ADCs convert the plurality of imaging signals into the plurality of digital signals based on the comparison between the imaging signal on the corresponding signal line and the reference signal. The solid-state image sensor according to claim 1, wherein the reference signal is a signal whose voltage level changes with time. A solid-state image sensor that outputs a digital signal according to the image pickup signal,
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
It has a plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
The plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.
An electronic device in which the reference signal generated by the reference signal generation unit in any one of the plurality of first semiconductor chips is supplied to the plurality of reference signal lines. A solid-state image sensor that outputs a digital signal according to the image pickup signal,
A signal processing unit that performs predetermined signal processing based on the digital signal is provided.
The solid-state image sensor
Each is equipped with a plurality of first semiconductor chips for AD conversion of a plurality of imaging signals.
Each of the plurality of first semiconductor chips
A reference signal line that transmits the reference signal for AD conversion, and
A reference signal generation unit that generates the reference signal,
A plurality of ADCs (Analog to Digital Converters) that convert the plurality of image pickup signals into a plurality of digital signals based on the comparison between the plurality of image pickup signals and the reference signal.
It has an analog gain of the reference signal generated by the reference signal generation unit in the plurality of first semiconductor chips, or a gain adjustment unit for adjusting the digital gain of the plurality of digital signals.
An electronic device in which a plurality of reference signal lines in the plurality of first semiconductor chips are electrically connected to each other.

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