JP2022061684A - Oscillator circuit - Google Patents

Abstract

To suppress frequency jump and/or to suppress reference spurious.SOLUTION: A variable frequency oscillator 200 includes a variable delay circuit 210 and generates an oscillator clock CLK_OSC having frequency in accordance with a delay amount set at the variable delay circuit 210. A feedback circuit 300 controls the variable delay circuit 210 so that frequency of the oscillator clock CLK_OSC approaches target frequency in accordance with reference clock CLK_REF. An edge injection circuit 220 receives the oscillator clock CLK_OSC and the reference clock CLK_REF, generates an injection edge by performing phase interpolation of the oscillator clock CLK_OSC and the reference clock CLK_REF, and injects the injection edge in the variable frequency oscillator 200.SELECTED DRAWING: Figure 4

Description

The present invention relates to an oscillator circuit.

For various ICs (Integrated Circuits), frequency synthesizers that generate clocks of arbitrary frequencies from reference clocks are used. A PLL circuit is widely used as such a frequency synthesizer. 1 (a) to 1 (c) are block diagrams illustrating the basic architecture of a PLL circuit.

FIG. 1A shows an analog PLL circuit 1. The analog PLL circuit 1 includes a phase comparator (PFD: Phase Frequency Detector) 10, a charge pump circuit 12, a low-pass filter 14, a voltage controlled oscillator (VCO) 16, and a frequency divider 18. The VCO 16 oscillates at a frequency corresponding to the analog control voltage _VCTRL . The output clock CLK_VCO of the VCO 16 is divided by 1 / N by the frequency divider 18. The phase detector 10 detects the phase difference between the clock CLK_DIV and the reference clock CLK_REF after frequency division, and controls the charge pump circuit 12. The low-pass filter 14 is a loop filter that smoothes the output voltage of the charge pump circuit 12, and generates a control voltage _VCTRL .

The analog PLL circuit 1 of FIG. 1A has been used in various applications for a long time and has high reliability, but there is a problem that the chip size becomes large due to the loop filter. In addition, the circuit designer needs to optimize the circuit layout in order to achieve sufficient performance.

FIG. 1B shows a fully digital PLL circuit (ADPLL: All Digital PLL) 2. The ADPLL circuit 2 receives FCW (Frequency Control Word) and the reference clock CLK_REF, and generates an output clock CLK_DCO obtained by multiplying the reference clock CLK_REF according to FCW. The ADPLL circuit 2 includes a frequency phase detector 20, a digital filter 22, and a digital controlled oscillator (DCO) 24. The DCO 24 oscillates at a frequency corresponding to the input control code _DCTRL . The frequency phase comparator 20 has a function corresponding to the phase comparator 10, the charge pump circuit 12, and the frequency divider 18 in FIG. 1, and is composed of a TDC (time-digital converter), an adder, and a counter. The digital signal generated by the frequency phase comparator 20 is filtered by the digital filter 22 and input to the DCO 24.

Since the ADPLL circuit 2 of FIG. 1B can be configured by a digital circuit that is easy to design by a fine semiconductor process, there is an advantage that the chip area can be reduced. On the other hand, although it is all-digital, for the frequency phase comparator 20 and the DCO 24, it is necessary for the circuit designer to manually optimize the circuit layout in order to satisfy the desired specifications.

FIG. 1 (c) shows an injection synchronous PLL circuit 3 (also referred to as IL-PLL (Injection Locked PLL)). The IL-PLL circuit 3 can be designed with an analog circuit or a digital circuit architecture, but here, a case where the IL-PLL circuit 3 is configured with a digital circuit will be described. The IL-PLL circuit 3 includes a DCO 30, a feedback circuit 40, and an edge injection circuit 50. The IL-PLL circuit 3 is understood as a hybrid of feedback control and feed forward control, and the oscillation frequency of the DCO 30 is controlled by the feedback control by the feedback circuit 40 corresponding to the frequency phase comparator 20 and the digital filter 22 in FIG. 1 (b). Stabilize. The edge injection circuit 50 cuts out the edge of the reference clock CLK_REF, injects the cut out edge into the DCO 30, and realigns the phase of the output clock CLK_DCO. The IL-PLL circuit may also be referred to as an MDLL (Multiplying Delay Locked Loop) circuit depending on the method of edge injection.

In the IL-PLL circuit, (i) the loop band is widened by injection synchronization, so that low phase noise (low jitter) can be achieved, and when configured with a digital circuit, (ii) FIG. 1 (a). Since the phase comparator 10 and the charge pump circuit 12 do not exist, there is an advantage that noise can be reduced. In addition, (iii) it can be said that there is a high degree of freedom in layout because it is less susceptible to noise due to the feedback path, and therefore automatic placement and routing using design support tools such as P & R (Place and Route) tools is also desirable. It has the characteristic that the characteristics can be obtained.

JP-A-2017-143398

R. Farjad-rad et al., "A 0.2-2GHz 12mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips", 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No .02CH37315), San Francisco, CA, USA, 2002, pp. 56-400 S. Kundu, B. Kim and C. H. Kim, "A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection", 2016 IEEE International Solid -State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 326-327 R. Wang and F. F. Dai, "A 0.8-1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression", 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, pp . 1-4 H. C. Ngo, K. Nakata, T. Yoshioka, Y. Terashima, K. Okada and A. Matsuzawa, "A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO", 2017 IEEE International Solid -State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 150-151 S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple -Point Frequency / Phase / Slope Calibrator ", 2019 IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA, 2019, pp. 490-492. S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator ", IEEE Journal of Solid-State Circuits (Early Access) B. M. Helal, M. Z. Straayer, G. Wei and M. H. Perrott, "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance", IEEE Journal of Solid-State Circuits, vol . 43, no. 4, pp. 855-863, April 2008 Y. Lee, T. Seong, S. Yoo and J. Choi, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique", IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1192-1202, April 2018 G. Tak and K. Lee, "A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no . 2, pp. 485-497, Feb. 2018 T. Liao, J. Su and C. Hung, "Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 589-592, March 2013 N. Da Dalt, "An Analysis of Phase Noise in Realigned VCOs", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 3, pp. 143-147, March 2014 W. Deng et al., "A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique", 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3

Since the IL-PLL circuit has a wide band, it can generate a clock with very low phase noise (low jitter). However, the IL-PLL circuit has problems with frequency jumps and reference spurs, as described below.

FIG. 2A is a diagram showing a frequency change of a normal PLL circuit, and FIG. 2B is a diagram illustrating a frequency jump in the IL-PLL circuit. As shown in FIG. 2A, in a normal PLL circuit, when the frequency f _REF of the reference clock CLK_REF suddenly fluctuates from f _c1 to f _c2 , the frequency of the output clock gradually fluctuates with time. Approaching f _c2 .

On the other hand, in the IL-PLL circuit, as shown in FIG. 2B, when the frequency fluctuation of the reference clock CLK_REF occurs, the frequency jump is caused by the forced edge replacement by the feedforward control.

When the output clock CLK_DCO of the IL-PLL circuit is used as the system clock, the frequency jump of the system clock may cause a malfunction of the entire system.

One of the important characteristics of a frequency synthesizer is the reference spurious characteristic. FIG. 3 is a diagram illustrating a reference spurious. The reference spurious (Ref-Spur.) Is centered on the frequency (carrier frequency) fc of the output clock, and is an integral multiple (n = 1, 2, ...) Of the reference frequency f _REF , and the offset frequency f _c ± n × f _REF . Occur.

High spurious causes a decrease in the performance of the RF system and becomes an unnecessary noise component in the A / D converter and the D / A converter. Since the spectrum of the output clock of the conventional IL-PLL circuit contains a large amount of reference spurious, which is an unnecessary frequency component in principle, improvement is desired.

The present disclosure has been made in view of such issues, and one of the exemplary purposes of that embodiment is to provide an injection synchronous oscillator circuit capable of suppressing frequency jumps and / or suppressing reference spurious. be.

One aspect of the present disclosure relates to an injection synchronous oscillator circuit. The oscillator circuit receives a variable frequency oscillator that generates an oscillator clock, a feedback circuit that controls the variable frequency oscillator so that the frequency of the oscillator clock approaches the target frequency corresponding to the reference clock, and the oscillator clock and the reference clock. It includes a phase exchanger that generates an interpolation clock obtained by phase-oscillating a clock and a reference clock. The oscillator circuit is configured so that the oscillator clock of the variable frequency oscillator can be replaced by the interpolated clock.

Another aspect of the present disclosure is also an injection synchronous oscillator circuit. The oscillator circuit receives a window generator that generates a window signal, a variable delay circuit, an oscillator clock corresponding to the reference clock and the output of the variable delay circuit, and the output is connected to the input of the variable delay circuit (i). ) The phase interpolator and oscillator clock that output the oscillator clock during the period when the window signal is asserted, and (ii) output the oscillator clock during the period when the window signal is negated. It is provided with a phase comparator that generates an up / down signal according to the phase of the reference clock and a loop filter that controls the delay amount of the variable delay circuit according to the up / down signal.

It should be noted that an arbitrary combination of the above components or a conversion of the expression of the present invention between methods, devices and the like is also effective as an aspect of the present invention.

According to certain aspects of the present disclosure, frequency jumps can be suppressed and / or reference spurious can be suppressed.

1 (a) to 1 (c) are block diagrams illustrating the basic architecture of a PLL circuit. FIG. 2A is a diagram showing a frequency change of a normal PLL circuit, and FIG. 2B is a diagram illustrating a frequency jump in the IL-PLL circuit. It is a figure explaining the reference spurious. It is a block diagram of the PLL circuit which concerns on embodiment. It is a figure explaining the operation of a phase interpolator. It is operation waveform diagram of the PLL circuit of FIG. It is operation waveform diagram of the edge injection circuit of the PLL circuit of FIG. FIG. 8A is a diagram showing a frequency change of the PLL circuit of FIG. 4, and FIG. 8B is a diagram showing a frequency change of the conventional PLL circuit. 9 (a) to 9 (c) are diagrams illustrating the jitter of the oscillator clock. It is a circuit diagram which shows the structural example of a phase interpolator. It is a circuit diagram which shows the structural example of a PLL circuit. It is a circuit diagram of the PLL circuit which concerns on modification 1. FIG. It is a circuit diagram of the PLL circuit which concerns on modification 2. FIG.

(Outline of the embodiment)
Some exemplary embodiments of the present disclosure will be outlined. This overview simplifies and describes some concepts of one or more embodiments for the purpose of basic understanding of embodiments, as a prelude to the detailed description described below, and is an invention or disclosure. It does not limit the size. Also, this overview is not a comprehensive overview of all possible embodiments and does not limit the essential components of the embodiment. For convenience, "one embodiment" may be used to refer to one embodiment (examples or modifications) or a plurality of embodiments (examples or modifications) disclosed herein.

The injection synchronous oscillator circuit according to the embodiment includes a variable frequency oscillator, a feedback circuit, and an edge injection circuit. The variable frequency oscillator produces an oscillator clock. The feedback circuit controls the variable frequency oscillator so that the frequency of the oscillator clock approaches the target frequency corresponding to the reference clock. The edge injection circuit receives an oscillator clock and a reference clock, generates an injection edge by phase-interpolating the oscillator clock and the reference clock, and injects the injection edge into a variable frequency oscillator.

The frequency jump can be suppressed as compared with the conventional configuration in which the edge of the reference clock is used as the injection edge and replaced with the clock of the variable frequency oscillator. In addition, reference spurious can be suppressed.

In one embodiment, the edge injection circuit may include a phase interpolator that phase-interpolates the oscillator clock and the reference clock to generate an interpolated clock. The edge injection circuit may inject the interpolated clock into the variable frequency oscillator as the injection edge.

In one embodiment, the variable frequency oscillator may include a variable delay circuit. The interpolated clock may be supplied to the input of the variable delay circuit. The phase interpolator can switch between the enable state and the disable state. In the enable state, the interpolator clock has a phase obtained by internally dividing the phase of the oscillator clock and the reference clock according to the set value of the phase ratio. It is also good. In the disabled state, the interpolated clock may have a phase corresponding to the oscillator clock. According to this configuration, the phase interpolator can realize the operation equivalent to that of the multiplexer.

In one embodiment, the phase interpolator may include a capacitor and M drive units whose outputs are connected to the capacitor. Each of the M drive units receives a reference clock and an oscillator clock, drives the capacitor according to the reference clock in the first state, and drives the capacitor according to the oscillator clock in the second state. By substituting the input capacitance of the logic gate for the capacitor, this phase interpolator can be designed by logic synthesis / automatic placement and routing.

In one embodiment, during the period when the window signal is negated, all M drive units are in the second state, and during the period when the window signal is asserted, k (k ≦ M) of the M drive units. However, it may be in the first state.

In one embodiment, the oscillator circuit may further comprise a window generator that produces a window signal that is asserted once every N cycles (N ≧ 2) of the oscillator clock. The window open (assert) timing and window close (negate) timing specified by the window signal do not depend on the reference clock. Therefore, while the variable frequency oscillator is oscillating, the window can be reliably opened and closed regardless of the presence or absence of the reference clock. Further, by adjusting the timing so that the injection edge of the reference clock is surely included in the period when the window is open, glitches and harmonic oscillations derived from the window signal do not occur. If the transition (edge) of the reference clock does not occur during the period when the window is open, the oscillator clock cycle becomes longer at a rate of once in a predetermined cycle (multiplication), but the oscillation stops. There is no. In addition, when the injection intensity of the phase complementer is less than 1/2, the fluctuation of the period can be minimized. Thus, according to one embodiment, some of the conventional problems can be solved.

The injection synchronous oscillator circuit according to one embodiment receives a window generator that generates a window signal, a variable delay circuit, and an oscillator clock corresponding to the output of the reference clock and the variable delay circuit, and the output is a variable delay circuit. It is connected to the input and outputs the interpolated clock obtained by phase-interfering the reference clock and oscillator clock during the period when the window signal is asserted, and (ii) the oscillator clock during the period when the window signal is negated. A phase exchanger that outputs, a phase comparator that generates up-down signals according to the phase of the oscillator clock and the phase of the reference clock, and a loop filter that controls the delay amount of the variable delay circuit according to the up-down signal. To prepare for.

The phase interpolator may include a capacitor and M drive units. Each of the M drive units receives a reference clock and an internal clock, and their respective outputs are connected to the capacitor to drive the capacitor according to the reference clock in the first state and to drive the capacitor according to the oscillator clock in the second state. It may include M driving units to be driven.

(Embodiment)
Hereinafter, the present invention will be described with reference to the drawings based on the preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and duplicate description thereof will be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected to each other. It also includes cases of being indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects performed by the combination thereof.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and their electricity. It also includes cases of being indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects performed by the combination thereof.

FIG. 4 is a block diagram of the PLL circuit 100 according to the embodiment. The PLL circuit 100 is an injection synchronous oscillator circuit (frequency synthesizer), and includes a variable frequency oscillator 200, an edge injection circuit 220, a feedback circuit 300, and a window generator 400.

The variable frequency oscillator 200 includes a variable delay circuit 210 and an inverter 230, and generates an oscillator clock CLK_OSC having a frequency corresponding to a delay amount set in the variable delay circuit 210. This oscillator clock CLK_OSC is taken out as the output clock CLK_DCO of the PLL circuit 100. Further, the oscillator clock CLK_OSC at the output of the inverter 230 is referred to as an internal clock CLK_INT.

The feedback circuit 300 controls the delay amount of the variable delay circuit 210 so that the frequency of the oscillator clock CLK_OSC approaches the target frequency f _REF corresponding to the reference clock CLK_REF. The configuration and control method of the feedback circuit 300 are not particularly limited, and known techniques may be used.

The edge injection circuit 220 receives the oscillator clock CLK_OSC and the reference clock CLK_REF, generates the injection edge INJ_EDGE by phase-interpolating the oscillator clock CLK_OSC and the reference clock CLK_REF, and injects the injection edge INJ_EDGE into the variable frequency oscillator 200.

In the present embodiment, the edge injection circuit 220 is incorporated in the variable frequency oscillator 200, and the injection edge INJ_EDGE is output during the period when the window signal INJ_WIND is asserted, and the internal clock CLK_INT is output during the period when the window signal INJ_WIND is negated. Is output.

The window generator 400 generates the window signal INJ_WIND. This window signal INJ_WIND is a timing signal that defines the timing (period) of injection synchronization in the PLL circuit 100. That is, the edge injection circuit 220 injects the injection edge INJ_EDGE into the variable frequency oscillator 200 in response to the window signal INJ_WIND.

The edge injection circuit 220 includes a phase interpolator 250. The phase interpolator 250 phase-interpolates the oscillator clock CLK_OSC and the reference clock CLK_REF to generate the interpolated clock CLK_PI.

Specifically, the phase interpolator 250 receives the reference clock CLK_REF at the first input IN1 and the internal clock CLK_INT which is the oscillator clock CLK_OSC at the second input IN2. The phase interpolator 250 generates an interpolating clock CLK_PI obtained by phase-interlacing the signal of the first input IN1 (reference clock CLK_REF) and the signal of the second input IN2 (oscillator clock CLK_INT), and generates the interpolating clock CLK_PI at the output OUT. The edge injection circuit 220 injects the interpolated clock CLK_PI into the variable frequency oscillator 200 as the injection edge INJ_EDEG.

FIG. 5 is a diagram illustrating the operation of the phase interpolator 250. Here, the case where the phase (edge generation time) φ ₁ of the signal of the first input IN 1 is advanced and the phase φ ₂ of the signal of the second input IN 2 is delayed is taken as an example. The phase φ _OUT of the output of the phase interpolator 250 can be expressed by the equation (1).
φ _OUT = φ ₁ + k / M × (φ ₂ -φ ₁ ) + τ _DELAY
= {(M-k) x φ ₁ + k x φ ₂ } / M + τ _DELAY ... (1)
τ _DELAY is the inherent delay of the phase interpolator 250. M is the resolution (number of gradations) of the phase interpolator 250, and is a constant of 2 or more. k is a set value of the phase ratio, and k can be selected from 0 to M. FIG. 5 shows the case of M = 3. That is, for the phase φ _OUT of the output OUT of the phase interpolator 250, the delay _τDELAY is added to the phase obtained by interpolating the phases φ ₁ and φ ₂ of the two inputs IN 1 and IN 2 into k: (Mk). It is a thing. When k = 0, φ _OUT = φ ₁ + τ _DELAY , and when k = M, φ _OUT = φ ₂ + τ _DELAY .

Return to FIG. In the present embodiment, the output OUT of the phase interpolator 250 is connected to the input of the variable delay circuit 210, and the interpolation clock CLK_PI is supplied to the variable delay circuit 210.

The phase interpolator 250 is configured so that the enable state and the disable state can be switched according to the window signal INJ_WIND. The interpolated clock CLK_PI has a phase obtained by internally dividing the phases of the internal clock CLK_INT, which is an oscillator clock, and the reference clock CLK_REF, according to the set value of the phase ratio, in the enabled state. That is, in the enabled state, the phase interpolator 250 operates in a state where the phase ratio k ≠ M.

On the contrary, in the disabled state, the phase of the interpolated clock CLK_PI includes the phase information of only the oscillator clock CLK_INT and does not include the phase information of the reference clock CLK_REF. That is, in the disabled state, the phase interpolator 250 operates in the state of k = M.

The above is the configuration of the PLL circuit 100. Next, the operation will be described. FIG. 6 is an operation waveform diagram of the PLL circuit 100 of FIG. Here, for the sake of simplification of explanation and facilitation of understanding, the delay τ _DELAY of the edge injection circuit 220 (phase interpolator 250) is ignored.

The vertical and horizontal axes of the waveform charts and time charts referred to in the present specification are appropriately enlarged or reduced for easy understanding, and each waveform shown is also simplified for easy understanding. It is made, or exaggerated or emphasized.

The window signal INJ_WIND is asserted once every predetermined cycle of the reference clock CLK_REF. Of the interpolated clock CLK_PI obtained by phase-interpolating the reference clock CLK_REF and the internal clock CLK_INT, the portion of the interpolated clock CLK_PI in which the window signal INJ_WIND is included in the assert (high) section is used as the injection edge INJ_EDGE. When this injection edge INJ_EDGE is injected, the edge of the oscillator clock CLK_DCO is replaced with the edge of the injection edge INJ_EDGE, and forced phase synchronization is applied. UP_DN shows the result of the phase comparison in the feedback circuit 300.

FIG. 7 is an operation waveform diagram of the edge injection circuit 220 of the PLL circuit 100 of FIG. FIG. 7 shows an enlarged edge injection period. In this example, the resolution of the phase interpolator 250 is M = 3. While the window signal INJ_WIND is negate (low), the phase interpolator 250 is operating in the state of k = 3, and the output of the phase interpolator 250, that is, the oscillator clock CLK_DCO is τ _DELAY with respect to the internal clock CLK_INT. I'm late. That is, the phase interpolator 250 of the edge injection circuit 220 passes the internal clock CLK_INT to form a ring oscillator.

While the window signal INJ_WIND is asserted (high), the phase interpolator 250 operates in any of the states of k = 0, 1, 2, and 3. The output of the phase interpolator 250, that is, the oscillator clock CLK_DCO, is delayed by τ _DELAY + k × Δt with respect to the internal clock CLK_INT.
Δt = | _Tref -T _int | / 3
That is, the edge of the oscillator clock CLK_DCO is replaced by the injection edge of the interpolated clock CLK_PI.

6 and 7 show the case where the internal clock CLK_INT precedes, but the same operation occurs when the phase relationship is reversed.

FIG. 8A is a diagram showing a frequency change of the PLL circuit 100 of FIG. 4, and FIG. 8B is a diagram showing a frequency change of the conventional PLL circuit. According to the PLL circuit 100 of FIG. 4, the frequency jump can be suppressed as shown in FIG. 8 (a).

9 (a) to 9 (c) are diagrams illustrating the jitter of the oscillator clock. FIG. 9A shows the waveform of the oscillator clock CLK_DCO. 9 (b) shows the integrated value of the jitter of the conventional PLL circuit, and FIG. 9 (c) shows the integrated value of the jitter of the PLL circuit of FIG. According to this embodiment, the influence of reference spurious can be reduced. In this embodiment, the RMS jitter is slightly increased in exchange for the reduction of the reference spurious.

In the configuration of FIG. 4, the injection intensity can be adjusted according to the phase ratio k in the injection period in which the window signal INJ_WIND is asserted. Then, by adjusting the injection intensity according to the application of the PLL circuit 100, the degree of suppression of frequency jump and the degree of suppression of reference spurious can be adjusted.

Further, if k = M is set, it can be operated as a conventional PLL circuit, and if k = 0, it can be operated as a conventional injection synchronous type PLL circuit in which the reference clock CLK_REF is injected as it is.

FIG. 10 is a circuit diagram showing a configuration example of the phase interpolator 250. ENPI is a 2-bit set value that specifies the phase ratio k in the injection period. The phase interpolator 250 includes an encoder 252, logic gates 254, 256, M drive units 260_1 to 260_3 (M = 3 in this example), and a capacitor C _OUT . When designing by logic synthesis / automatic placement and routing, the capacitor C _OUT may be replaced with the input capacitance of the logic gate.

The encoder 252 converts the binary control code ENPI [1: 0] into a negative logic thermometer code PIB [2: 0]. The logic gate 254 logically inverts the window signal INJ_WIND and generates a negative logic window signal INJ_WINDB.

The logic gate 256 takes each bit of the thermometer code PIB [2: 0] and the negative OR of the window signal INJ_WINDB to generate the thermometer code PI [2: 0]. The thermometer code PI [2: 0] has a reversal logic of PIB [2: 0] in the window period (INJ_WIND = H, INJ_WINDB = L), and the other period (INJ_WIND = B, INJ_WINDB = H). In, it becomes all zero [000].

Each drive unit 260 receives input signals IN1 and IN2 (CLK_REF, CLK_INT) and thermometer codes PIB [2: 0], PI [2: 0].

Each drive unit 260 can switch between a first state in which its output changes according to the input signal IN1 (CLK_REF) and a second state in which its output changes according to the input signal IN2 (CLK_INT).

The state of each drive unit 260_i (i = 1 to 3) changes according to the window signal INJ_WINDB and the corresponding bit PIB [i-1] of the thermometer code PIB.

When INJ_WIND = 1, ENPI [11], all the drive units 260_1 to 260_3 are in the first state, and the drive units 260_1 to 260_M charge and discharge the output capacitor C _OUT according to the reference clock CLK_REF. As a result, the output clock CLK_DCO has a phase corresponding to the reference clock CLK_REF.

When INJ_WIND = 1, ENPI [00], all the drive units 260_1 to 260_3 are in the second state, and the drive units 260_1 to 260_M charge and discharge the output capacitor C _OUT according to the internal clock CLK_INT. As a result, the output clock CLK_DCO has a phase corresponding to the internal clock CLK_INT.

When INJ_WIND = 1, ENPI [01] or [10], one or two drive units 260 operate in the first state, and the rest operate in the second state. As a result, the output clock CLK_DCO has a phase in which the phases of the internal clock CLK_INT and the reference clock CLK_REF are interpolated.

When INJ_WIND = 0, all the drive units 260_1 to 260_3 are in the second state, and the output clock CLK_DCO has a phase corresponding to the internal clock CLK_INT.

The phase interpolator 250 can be designed by logic synthesis / automatic placement and routing.

As described above, the configurations of the variable frequency oscillator 200, the feedback circuit 300, and the window generator 400 may be configured by using known techniques, and are not particularly limited, but some configuration examples are shown below.

FIG. 11 is a circuit diagram showing a configuration example (100A) of the PLL circuit 100. The feedback circuit 300 includes a phase detector 310 and a loop filter 320. The phase detector 310 is enabled during the period when the window signal INJ_WIND is asserted, compares the phases of the reference clock CLK_REF with the oscillator clock (internal clock CLK_INT), and generates an up / down signal UP_DN. The loop filter 320 increases / decreases the delay amount of the variable delay circuit 210 according to the up / down signal UP_DN.

The phase detector is preferably a symmetric phase detector. By enabling the symmetric phase detector only for the period during which the window signal is asserted, the phase pull-in range can be extended to the range of one cycle of the reference clock.

Instead of the phase detector 310, the feedback circuit 300 is enabled during the period when the window signal INJ_WIND is asserted, compares the phase and frequency of the oscillator clock CKL_OSC and the reference clock CLK_ERF, and shows the up pulse and down pulse showing the comparison result. May be provided with a phase frequency detector that produces. By adopting a phase frequency detector that originally has a wide phase pull-in range and has a frequency pull-in function, and by enabling the phase frequency detector only during the period when the window signal is asserted, the phase pull-in range is substantially expanded. It can be expanded infinitely.

If the injection edge does not occur even though the window is open, the frequency of the variable frequency oscillator fluctuates in the short term every cycle of the reference clock. Therefore, the window generator may maintain negating of the window signal when it cannot detect the edge of the reference clock. As a result, even when the reference clock is stopped, the clock generation by the PLL circuit can be continued. Alternatively, by reducing the injection intensity of the phase complementer to less than 1/2, the fluctuation of the period can be minimized. Further, the frequency of the variable frequency oscillator fluctuates only immediately after the reference clock is lost, but can be kept constant thereafter.

The window generator 400 includes a counter 410 and a selection logic 420. The counter 410 asserts the output once every N cycles of the oscillator clock CLK_INT. The selection logic 420 cuts out the internal clock CLK_INT while the output of the counter 410 is asserted, and generates the window signal INJ_WIND.

It is understood by those skilled in the art that the embodiments are exemplary and that various modifications are possible for each of these components and combinations of processing processes, and that such modifications are also within the scope of the present invention. .. Hereinafter, such a modification will be described.

(Modification 1)
FIG. 12 is a circuit diagram of the PLL circuit 100B according to the first modification. The adaptive control unit 500 dynamically changes the phase ratio k (control code ENPI) of the phase interpolator 250 according to the operating state of the PLL circuit 100B.

For example, the adaptive control unit 500 includes a window monitor circuit 510. The window monitor circuit 510 determines whether or not the reference clock CLK_REF is included within the injection period specified by the window signal INJ_WIND. Then, when the reference clock CLK deviates from the injection period, the OUTSIDE signal is asserted (H). When the OUTSIDE signal is asserted, the setting circuit 520 outputs a preset phase ratio value and supplies it to the phase interpolator 250. The adaptive control unit 500 may include a delta-sigma modulator 530. This makes it possible to set a non-integer decimal phase ratio for the phase interpolator 250.

(Modification 2)
FIG. 13 is a circuit diagram of the PLL circuit 100C according to the second modification. The edge injection circuit 220 includes a phase interpolator 250 and a multiplexer 222. The multiplexer 222 selects the output CLK_PI of the phase interpolator 250 during the injection period in which the window signal INJ_WIND is asserted, and selects the internal clock CLK_INT during the period in which the window signal INJ_WIND is negated. Also in this modification, frequency jump can be suppressed or reference spurious can be suppressed.

(Modification 3)
The technique according to the present disclosure can be applied to an oscillator circuit in which an edge is injected by a selector, that is, an IL-PLL circuit or an MDLL (Multiplying Delay Locked Loop) circuit. This technique can be applied regardless of whether it is a digital PLL / DLL or an analog PLL / DLL, and the variable frequency oscillator 200 may be a DCO or a VCO.

The present invention has been described using specific terms and phrases based on the embodiments, but the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted within the scope of the above-mentioned idea of the present invention.

100 PLL circuit 200 Variable frequency oscillator 210 Variable delay circuit 220 Edge injection circuit 230 Inverter 250 Phase interpolator 260 Drive unit 300 Feedback circuit 310 Phase detector 320 Loop filter 400 Window generator 410 Counter 420 Selection logic 500 Adaptive control unit 510 Window monitor Circuit 520 setting circuit

Claims (8)

It is an injection-synchronized oscillator circuit.
A variable frequency oscillator that produces an oscillator clock,
A feedback circuit that controls the variable frequency oscillator so that the frequency of the oscillator clock approaches the target frequency corresponding to the reference clock.
An edge injection circuit that receives the oscillator clock and the reference clock, generates an injection edge by phase-interpolating the oscillator clock and the reference clock, and injects the injection edge into the variable frequency oscillator.
An oscillator circuit characterized by being equipped with. The edge injection circuit includes a phase interpolator that phase-interfers the oscillator clock and the reference clock to generate an interpolating clock, and injects the interpolating clock into the variable frequency oscillator as the injection edge. Item 1. The oscillator circuit according to Item 1. The variable frequency oscillator includes a variable delay circuit.
The interpolated clock is supplied to the input of the variable delay circuit.
The phase interpolator can be switched between an enable state and a disable state, and in the enable state, the phase of the oscillator clock and the reference clock is internally divided according to a set value of the phase ratio. The oscillator circuit according to claim 2, wherein the oscillator circuit has a phase and has a phase corresponding to the oscillator clock in the disabled state. The phase interpolator is
With capacitors
Each of the M drive units receives the reference clock and the oscillator clock, and their respective outputs are connected to the capacitor to drive the capacitor according to the reference clock in the first state. In the state, M drive units that drive the capacitor according to the oscillator clock, and
The oscillator circuit according to claim 2 or 3, wherein the oscillator circuit comprises. During the period when the window signal is negated, all the M drive units are in the second state.
The oscillator circuit according to claim 4, wherein k (k ≦ M) of the M drive units are in the first state during the period in which the window signal is asserted. Further provided is a window generator that produces a window signal that is asserted once every N cycles (N ≧ 2) of the oscillator clock.
The oscillator circuit according to any one of claims 1 to 5, wherein the edge injection circuit injects the injection edge in response to the window signal. It is an injection-synchronized oscillator circuit.
A window generator that produces a window signal and
Variable delay circuit and
It receives an internal clock corresponding to the reference clock and the output of the variable delay circuit, and the output is connected to the input of the variable delay circuit. (I) The reference clock and the internal clock during the period when the window signal is asserted. (Ii) A phase interpolator that outputs the internal clock during the period when the window signal is negated, and
A feedback circuit that controls the delay amount of the variable delay circuit according to the phase of the internal clock and the phase and / or frequency of each of the reference clocks.
An oscillator circuit characterized by being equipped with. The phase interpolator is
With capacitors
Each of the M drive units receives the reference clock and the internal clock, and their respective outputs are connected to the capacitor to drive the capacitor according to the reference clock in the first state. In the state, M drive units that drive the capacitor according to the internal clock, and
The oscillator circuit according to claim 7, wherein the oscillator circuit comprises.

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