JP2022051428A - Manufacturing method for image display device, and image display device - Google Patents

Abstract

To provide a manufacturing method for an image display device by which the transfer step for a light-emitting element is shortened and the yield is improved, and an image display device.SOLUTION: A manufacturing method for an image display device includes the steps of: preparing a first substrate including a circuit element, a first wiring layer 110, and a first insulating film 112 formed on a light-transmitting substrate 102; preparing a semiconductor layer; bonding the semiconductor layer to a second substrate through a first metal layer; bonding the semiconductor layer to the first substrate; forming a light-emitting element 150 including a light-emitting surface 151S and an upper surface by etching the semiconductor layer; forming an electrode 165a covering the upper surface and electrically connected thereto by etching the first metal layer; forming a second insulating film 156 covering the first insulating film, the light-emitting element, and the electrode; forming a first veer penetrating the first insulating film and the second insulating film; and forming a second wiring layer 160 on the second insulating film.SELECTED DRAWING: Figure 1

Description

An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device.

It is desired to realize a thin image display device having high brightness, wide viewing angle, high contrast and low power consumption. In order to meet such market demands, display devices using self-luminous elements are being developed.

As a self-luminous element, a display device using a micro LED, which is a fine light emitting element, is expected to appear. As a method of manufacturing a display device using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced. However, as the number of micro LED elements increases as the image quality becomes higher, such as full high-definition, 4K, 8K, etc., a large number of micro LEDs may be individually formed and transferred sequentially to the substrate on which the drive circuit or the like is formed. The transfer process requires a huge amount of time. Further, a poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.

A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the electrodes are attached to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2002-141492

One embodiment of the present invention provides a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved.

A method for manufacturing an image display device according to an embodiment of the present invention includes a circuit element formed on the first surface of a translucent substrate, a first wiring layer connected to the circuit element, the circuit element, and the circuit element. A step of preparing a first substrate including the first insulating film covering the first wiring layer, a step of preparing a semiconductor layer including a light emitting layer, and a second step of connecting the semiconductor layer via the first metal layer. The step of joining to the substrate, the step of bonding the semiconductor layer to the first substrate, the step of removing the second substrate, and the step of etching the semiconductor layer to obtain the light emitting surface on the first insulating film and the said. A step of forming a light emitting element including an upper surface provided facing the light emitting surface, and a step of etching the first metal layer to cover the upper surface and form an electrode electrically connected to the upper surface. A step of forming the first insulating film, a second insulating film covering the light emitting element and the electrode, a step of forming a first via penetrating the first insulating film and the second insulating film, and the first step. 2. The step of forming the second wiring layer on the insulating film is provided. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

A method for manufacturing an image display device according to an embodiment of the present invention includes a circuit element formed on the first surface of a translucent substrate, a first wiring layer connected to the circuit element, the circuit element, and the circuit element. A step of preparing a first substrate including the first insulating film covering the first wiring layer, a step of preparing a semiconductor layer including a light emitting layer, and a step of bonding the semiconductor layer to the first substrate. A step of forming a second metal layer on the semiconductor layer after the step of bonding the semiconductor layers, and a step of etching the semiconductor layer to form a light emitting surface on the first insulating film and an upper surface facing the light emitting surface. A step of forming a light emitting element including the above, a step of etching the second metal layer to cover the upper surface and forming an electrode electrically connected to the upper surface, the first insulating film, the light emitting element, and the like. A step of forming a second insulating film covering the electrode, a step of forming a first via penetrating the first insulating film and the second insulating film, and forming a second wiring layer on the second insulating film. It is provided with a process to be performed. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

The image display device according to an embodiment of the present invention includes a light transmissive member having a first surface, a circuit element provided on the first surface, and a first wiring electrically connected to the circuit element. A light emitting element comprising a layer, a first insulating film covering the first surface, the circuit element, and the first wiring layer, a light emitting surface on the first insulating film, and an upper surface facing the light emitting surface, said. It penetrates the electrode that covers the upper surface and is electrically connected to the upper surface, the first insulating film, the light emitting element, the second insulating film that covers the electrode, the first insulating film, and the second insulating film. The first via is provided and the second wiring layer provided on the second insulating film is provided. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

The image display device according to an embodiment of the present invention has a light transmissive member having a first surface, a plurality of transistors provided on the first surface, and a first, which is electrically connected to the plurality of transistors. A first including a wiring layer, a first insulating film covering the first surface, the plurality of transistors, and the first wiring layer, and a light emitting surface capable of forming a plurality of light emitting regions on the first insulating film. A semiconductor layer, a plurality of light emitting layers provided on the first semiconductor layer, and a plurality of second semiconductor layers provided on the plurality of light emitting layers and having a conductive shape different from that of the first semiconductor layer. A plurality of electrodes provided on the plurality of second semiconductor layers and electrically connected to the plurality of second semiconductor layers, the first insulating film, the first semiconductor layer, and the plurality of light emitting layers. A second insulating film covering the plurality of second semiconductor layers and the plurality of electrodes, a plurality of first vias provided so as to penetrate the first insulating film and the second insulating film, and the second insulating film. A second wiring layer provided above is provided. The plurality of first vias are provided between the first wiring layer and the second wiring layer, and electrically connect the first wiring layer and the second wiring layer.

The image display device according to an embodiment of the present invention includes a light transmissive member having a first surface, a circuit element provided on the first surface, and a first wiring electrically connected to the circuit element. A plurality of light emitting elements including a layer, a first insulating film covering the first surface, the circuit element, and the first wiring layer, and a light emitting surface and an upper surface facing the light emitting surface on the first insulating film. A plurality of electrodes that cover the upper surface and are electrically connected to the upper surface, a first insulating film, the plurality of light emitting elements, a second insulating film that covers the plurality of electrodes, the first insulating film, and the like. A first via provided so as to penetrate the second insulating film and a second wiring layer provided on the second insulating film are provided. The first via is provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

According to one embodiment of the present invention, a method for manufacturing an image display device that shortens the transfer process of a light emitting element and improves the yield is realized.

According to one embodiment of the present invention, an image display device that shortens the transfer process of the light emitting element and improves the yield is realized.

It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 1st Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on the modification of 1st Embodiment. It is a schematic block diagram illustrating the image display device of 1st Embodiment. It is a schematic plan view which illustrates a part of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic perspective view which illustrates a part of the manufacturing method of the image display apparatus of 1st Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus of 1st Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus of 1st Embodiment. It is a schematic perspective view which illustrates the image display device of 1st Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 2nd Embodiment. It is a schematic block diagram which illustrates the image display device of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 2nd Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 3rd Embodiment. It is a schematic block diagram which illustrates the image display device of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 3rd Embodiment. It is a schematic perspective view which illustrates the image display device of 3rd Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic sectional drawing illustrating a part of the manufacturing method of the image display apparatus of 4th Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 5th Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus of 5th Embodiment. 6 is a schematic cross-sectional view illustrating a part of the image display device according to the sixth embodiment. 6 is a schematic cross-sectional view illustrating a part of the image display device of the sixth embodiment. It is a block diagram which illustrates the image display device which concerns on 7th Embodiment. It is a block diagram which illustrates the image display device which concerns on the modification of 7th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
It should be noted that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, and the like are not necessarily the same as the actual ones. Further, even when the same part is represented, the dimensions and ratios may be different from each other depending on the drawing.
In addition, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

(First Embodiment)
FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
FIG. 1 schematically shows the configuration of the sub-pixel 20 of the image display device of the present embodiment. Of the present embodiment and other embodiments described later, the second embodiment, the fifth embodiment, and the sixth embodiment show an example in which a color filter is not attached. Therefore, for example, these are monochrome. In the case of an image display device or the like, the sub-pixel is one pixel. In the present specification, a light emitting element including one light emitting element is referred to as a subpixel regardless of whether one subpixel forms one pixel or a plurality of subpixels form one pixel. ..

In the following, it may be described using a three-dimensional coordinate system of XYZ. The light emitting elements 150 are arranged in a two-dimensional plane as shown in FIG. 11 described later. The light emitting element 150 is provided for each subpixel 20. The two-dimensional plane in which the subpixels 20 are arranged is defined as the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 represents a cross section seen from an arrow on the AA'line of FIG. 4, which will be described later, and is a cross-sectional view in which cross sections in a plurality of planes perpendicular to the XY plane are connected on one plane. Also in other figures, as in FIG. 1, in the cross-sectional view of a plurality of planes perpendicular to the XY plane, the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z axis is the XY plane.

In the following, the positive direction of the Z axis may be referred to as "up" or "upward", and the negative direction of the Z axis may be referred to as "down" or "downward", but gravity is not necessarily applied in the direction along the Z axis. It is not limited to the direction. The length in the direction along the Z axis may be referred to as height.

The subpixel 20 has a light emitting surface 151S substantially parallel to the XY plane. The light emitting surface 151S is a surface that mainly emits light in the negative direction of the Z axis orthogonal to the XY plane. In this embodiment and the modifications and all embodiments described below, the light emitting surface emits light in the negative direction of the Z axis.

As shown in FIG. 1, the subpixel 20 of the image display device includes a substrate (light transmitting member) 102, a transistor (circuit element) 103, a first wiring layer 110, and a first interlayer insulating film (first insulating film). The film) 112, the light emitting element 150, the electrode 165a having light reflectivity, the second interlayer insulating film (second insulating film) 156, the via (first via) 161d, and the second wiring layer 160. include.

In the present embodiment, the substrate 102 has two surfaces, and the TFT underlayer film 106 is provided on one surface 102a. A circuit element such as a transistor 103 is formed on the TFT lower layer film 106. The first surface 102a is a flat surface substantially parallel to the XY plane. When the image display device of the present embodiment is provided with a color filter, the color filter is formed on the other surface 102b of the substrate 102. The other surface 102b is a surface facing the one surface 102a. Also in the other embodiments described later, when the color filter is not provided, the color filter is provided on the surface of the two surfaces of the substrate facing the surface on which the light emitting element is formed, as described above. May be good. The substrate 102 is a translucent substrate, for example, a glass substrate.

A circuit 101 is formed on the substrate 102 via a TFT lower layer film 106, and the circuit 101 is covered with a first interlayer insulating film 112 having light transmission. The light emitting element 150 is provided on the first interlayer insulating film 112. The light emitting element 150 is driven by a transistor 103 provided via the first interlayer insulating film 112. The transistor 103 is a thin film transistor (TFT). The process of forming a circuit element including a TFT on a large glass substrate has been established for manufacturing liquid crystal panels, organic EL panels, and the like, and has the advantage that existing plants can be used.

Hereinafter, the configuration of the sub-pixel 20 will be described in detail.
The transistor 103 is formed on the TFT lower layer film 106. The TFT underlayer film 106 is provided to ensure flatness when the transistor 103 is formed and to protect the TFT channel of the transistor 103 from contamination and the like during heat treatment. The TFT lower layer film 106 is an insulating film such as SiO2 and has light transmittance.

In addition to the transistor 103, circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and the circuit 101 is formed by wiring or the like. For example, in FIG. 3, which will be described later, the transistor 103 corresponds to the drive transistor 26. In addition, in FIG. 3, the selection transistor 24, the capacitor 28, and the like are circuit elements. The circuit 101 includes a TFT channel 104, an insulating layer 105, an insulating film 108, vias 111s, 111d, and a first wiring layer 110.

The transistor 103 is a p-channel TFT in this example. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a Low Temperature Poly Silicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating a region of amorphous Si formed on the TFT underlayer film 106. For example, laser annealing with a laser is used for polycrystallization and activation of the amorphous Si region. The TFT formed by the LTPS process has sufficiently high mobility.

The TFT channel 104 includes regions 104s, 104i, 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The area 104i is provided between the area 104s and the area 104d. The regions 104s and 104d are doped with p-type impurities such as boron ion (B ⁺ ) or boron trifluoride ion (BF ²⁺ ), and are ohmic-connected to the vias 111s and 111d.

The insulating layer 105 is provided on the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is, for example, SiO ₂ . The insulating layer 105 may be a multi-layered insulating layer containing SiO ₂ or Si ₃ N ₄ depending on the covering region. The insulating layer 105 is formed sufficiently thin so as to have light transmission.

The gate 107 is provided on the TFT channel 104 via the insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 and the gate 107 and to insulate them from other adjacent circuit elements. When a potential lower than the region 104s is applied to the gate 107, a channel is formed in the region 104i, so that the current flowing between the regions 104s and 104d can be controlled.

The gate 107 may be formed of, for example, polycrystalline Si or a refractory metal such as W or Mo. When the gate 107 is formed by a polycrystalline Si film, it is formed by, for example, CVD or the like.

The insulating film 108 is provided on the insulating layer 105 and the gate 107. The insulating film 108 is formed of a light-transmitting insulating material, and is, for example, an inorganic film such as SiO ₂ or Si ₃ N ₄ . Preferably, the insulating film 108 is a laminated film such as SiO ₂ and Si ₃ N ₄ . The insulating film 108 is provided to separate circuit elements such as transistors 103 arranged adjacent to each other from each other. The insulating film 108 provides a surface having a flatness that does not hinder the formation of the first wiring layer 110.

The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 can include a plurality of wirings having different potentials. The first wiring layer 110 includes wirings 110s and 110d. The wirings 110s and 110d are formed separately and can be connected to different potentials.

In the cross-sectional views taken from FIG. 1 and thereafter, unless otherwise specified, the reference numeral representing the wiring layer shall be displayed next to the wiring constituting the wiring layer.

The wiring 110s is provided above the area 104s. The wiring 110s is connected to, for example, a power line 3 shown in FIG. 3 described later. The wiring 110d is provided above the area 104d. One end of the via 161d is connected to the wiring 110d. The other end of the via 161d is connected to the second wiring layer 160.

The vias 111s and 111d are provided so as to penetrate the insulating film 108 and the insulating layer 105. The via 111s is provided between the wiring 110s and the area 104s, and electrically connects the wiring 110s and the area 104s. The via 111d is provided between the wiring 110d and the area 104d, and electrically connects the wiring 110d and the area 104d.

The wiring 110s is connected to the region 104s via the via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to, for example, the power line 3 of the circuit of FIG. 3 via the via 111s and the wiring 110s.

The wiring 110d is connected to the region 104d via the via 111d. The region 104d is a drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the second wiring layer 160 via the via 111d, the wiring 110d, and the via 161d.

The first interlayer insulating film 112 is provided so as to cover the insulating film 108 and the first wiring layer 110. The first interlayer insulating film 112 is made of a light-transmitting material. The first interlayer insulating film 112 is formed of, for example, an organic resin and is an organic transparent resin. The first interlayer insulating film 112 provides a flattening surface 112F for bonding a semiconductor layer having a light emitting layer, as described in a manufacturing method described later.

The substrate 102, the TFT lower layer film 106, the circuit 101, and the first interlayer insulating film 112 constitute the drive circuit unit 100. The light emitting element 150 is provided on the drive circuit unit 100.

The light emitting element 150 includes a light emitting surface 151S provided on the flattening surface 112F. The light emitting element 150 includes an upper surface 153U provided so as to face the light emitting surface 151S. In this example, the outer peripheral shapes of the light emitting surface 151S and the upper surface 153U in XY plan view are square or rectangular, and the light emitting element 150 is a prismatic element having the light emitting surface 151S on the flattened surface 112F. The cross section of the prism may be a polygon of pentagon or more. The light emitting element 150 is not limited to a prismatic element, and may be a columnar element.

The light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the light emitting surface 151S toward the upper surface 153U. The light emitting surface 151S, which is the n-type semiconductor layer 151, is provided in contact with the flattening surface 112F. Therefore, the light emitting element 150 radiates light in the negative direction of the Z axis via the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102.

The n-type semiconductor layer 151 includes a connection portion 151a. The connecting portion 151a is provided so as to project on the flattening surface 112F from the n-type semiconductor layer 151 in one direction. The height of the connection portion 151a from the flattening surface 112F is the same as the height of the n-type semiconductor layer 151 from the flattening surface 112F, or lower than the height of the n-type semiconductor layer 151 from the flattening surface 112F. The connection portion 151a is a part of the n-type semiconductor layer 151. The connecting portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connecting portion 151a.

When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in XY plan view is, for example, substantially a square or a rectangle. When the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corner portion of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane view is a columnar shape, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting elements in a plan view, the degree of freedom in wiring layout and the like is improved.

As the light emitting device 150, for example, a gallium nitride based compound semiconductor including a light emitting layer such as In _X Al _Y Ga _1-XY N (0 ≦ X, 0 ≦ Y, X + Y <1) is preferably used. Hereinafter, the above-mentioned gallium nitride based compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of the light emitted by the light emitting element 150 may be any wavelength in the range from the near-ultraviolet region to the visible light region, and is, for example, about 467 nm ± 20 nm. The wavelength of the light emitted by the light emitting element 150 may be bluish-purple light emission of about 410 nm ± 20 nm. The wavelength of the light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be appropriate.

The light-reflecting electrode 165a is provided over the upper surface 153U. The electrode 165a is provided between the upper surface 153U and one end of the connecting portion 161a. The electrode 165a is made of a conductive material having a light-shielding property, and is formed with a sufficient thickness so as to exhibit the light-shielding property. The electrode 165a realizes ohmic connection with the p-type semiconductor layer 153. The electrode 165a is formed of a light-reflecting metal material or the like, and reflects synchrotron radiation or scattered light upward of the light-emitting element 150 toward the light-emitting surface 151S. As a result, in the light emitting element 150, the luminous efficiency is substantially improved.

The second interlayer insulating film 156 covers the flattening surface 112F, the light emitting element 150, and the electrode 165a. The second interlayer insulating film 156 separates the light emitting elements 150 arranged adjacent to each other. The second interlayer insulating film 156 also separates the electrodes 165a provided on the light emitting elements 150 arranged adjacent to each other. The second interlayer insulating film 156 protects the light emitting element 150 from the surrounding environment by covering the light emitting element 150. The surface of the second interlayer insulating film 156 may be flat enough to form the second wiring layer 160 on the interlayer insulating film 156.

The second interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used for the second interlayer insulating film 156 is preferably a white resin. By using the white resin as the second interlayer insulating film 156, it is possible to reflect the laterally emitted light of the light emitting element 150 and the return light caused by the interface between the light emitting surface 151S and the flattening surface 112F and the like. Therefore, the luminous efficiency of the light emitting element 150 is substantially improved.

The white resin is formed by dispersing scatterable fine particles having a Mie scattering effect in a silicon-based resin such as SOG (Spin On Glass) or a transparent resin such as a novolak-type phenol-based resin. The scattering fine particles are colorless or white, and have a diameter of about 1/10 to several times the wavelength of the light emitted by the light emitting element 150. The scatterable fine particles preferably used have a diameter of about ½ of the wavelength of light. For example, examples of such scattering fine particles include TiO ₂ , Al ₂ O ₃ , ZnO, and the like.

The white resin can also be formed by utilizing a large number of fine pores dispersed in the transparent resin. When the first interlayer insulating film 112 is whitened, for example, an ALD (Atomic-Layer-Deposition) or a SiO ₂ film formed by CVD may be used on top of the SOG or the like.

The second interlayer insulating film 156 may be a black resin. By using the black resin as the second interlayer insulating film 156, the scattering of light in the subpixel 20 is suppressed, and the stray light is suppressed more effectively. An image display device in which stray light is suppressed can display a sharper image.

The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 can include a plurality of wirings having different potentials. The second wiring layer 160 includes wirings 160k and 160a. The wirings 160k and 160a are separately formed and can be connected to different potentials.

A part of the wiring 160k is provided above the connection portion 151a. The other part of the wiring 160k is connected to, for example, the ground wire 4 of the circuit of FIG. A part of the wiring 160a is provided with a connection portion 161a between the wiring 160a provided above the upper surface 153U and the upper surface 153U, and the upper surface 153U is connected to the wiring 160a by the connection portion 161a. The other part of the wiring 160a is provided above the wiring 110d.

The via 161d is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. The via 161d is provided between the wiring (first wiring) 160a and the wiring 110d, and electrically connects the wiring 160a and the wiring 110d. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the electrode 165a, the connecting portion 161a, the wiring 160a, the via 161d, the wiring 110d, and the via 111d.

The via (second via) 161k is provided so as to penetrate the second interlayer insulating film 156 and reach the connecting portion 151a. The via 161k is provided between the wiring (second wiring) 160k and the connection portion 151a, and connects the wiring 160k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 3 via the connection portion 151a, the via 161k, and the wiring 160k.

The wiring layer 110, the connecting portion 161a, and the vias 111s, 111d, 161k, 161d are formed of, for example, an alloy of Al or Al, a laminated film of Al and Ti, or the like. For example, in a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

In order to protect from the external environment, a protective layer covering them may be provided over the second interlayer insulating film 156 and the second wiring layer 160.

FIG. 2 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the present embodiment.
In the modified example of FIG. 2, the shapes of the wirings 110s and 110d constituting the first wiring layer 110 are different from those of the first embodiment. Other components are the same as in the first embodiment. The same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
As shown in FIG. 2, the modified example image display device includes the subpixel 20a. The subpixel 20a includes a first wiring layer 110. The first wiring layer 110 includes wirings 110s1, 110d1. The wiring 110s1 is connected to the source region of the transistor 103 via the via 111s, and is connected to, for example, the power line 3 of the circuit of FIG. 3 described later. The wiring 110d1 is connected to the drain region of the transistor via the via 111d, and is connected to the wiring 160a via the via 161d.

In addition to such a circuit connection function, the wirings 110s1 and 110d1 function as a first portion that shields the TFT channel 104 from light. That is, in the first portion, at least one of the wirings 110s1 and 110d1 is provided so as to cover the TFT channel 104 of the transistor 103, and shields the light from the light emitting element 150. Wiring 110s1, 110d1 can cover the TFT channel 104 as the first part, or wiring 110s1 can alone cover the TFT channel as the first part, and wiring 110d1 can alone cover the TFT channel 104 as the first part. can. By covering most of the TFT channel 104 with the first portion, the light emitted from the light emitting element 150 is suppressed from reaching the TFT channel 104 by the first portion. Therefore, it is possible to prevent the transistor 103 from malfunctioning due to the irradiation of light.

FIG. 3 is a schematic block diagram illustrating an image display device according to the present embodiment.
As shown in FIG. 3, the image display device 1 of the present embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.

The image display device 1 further includes a power line 3 and a ground line 4. The power line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power supply line 3 and the ground line 4 are electrically connected to each subpixel 20, and power is supplied to each subpixel 20 from a DC power source connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with reference to the GND terminal 4a.

The image display device 1 further includes a scanning line 6 and a signal line 8. The scanning line 6 is laid out in a direction parallel to the X-axis. That is, the scanning lines 6 are laid out along the row direction arrangement of the subpixels 20. The signal line 8 is laid out in a direction parallel to the Y axis. That is, the signal line 8 is laid out along the arrangement of the subpixels 20 in the column direction.

The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the subpixels 20 in each column via the scanning line 6 to supply a selection signal to each subpixel 20.

The signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the subpixel 20 of each line via the signal line 8 to supply a signal voltage to each subpixel 20.

The subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28. In FIG. 3 and FIG. 4, which will be described later, the selection transistor 24 may be displayed as T1, the drive transistor 26 may be displayed as T2, and the capacitor 28 may be displayed as Cm.

The light emitting element 22 is connected in series with the drive transistor 26. In the present embodiment, the drive transistor 26 is a p-channel TFT, and the anode electrode of the light emitting element 22 is connected to the drain electrode of the drive transistor 26. The main electrodes of the drive transistor 26 and the selection transistor 24 are a drain electrode and a source electrode. The anode electrode of the light emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4. The drive transistor 26 corresponds to the transistor 103 in FIG. 1, and the light emitting element 22 corresponds to the light emitting element 150 in FIG. The current flowing through the light emitting element 22 is determined by the voltage applied between the gate and the source of the drive transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.

The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.

The row selection circuit 5 selects one row from the array of subpixels 20 in the m row and supplies the selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value for each subpixel 20 in the selected row. A signal voltage is applied between the gate and the source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by the capacitor 28. The drive transistor 26 causes a current corresponding to the signal voltage to flow through the light emitting element 22. The light emitting element 22 emits light with a brightness corresponding to the flowing current.

The row selection circuit 5 sequentially switches the rows to be selected and supplies the selection signal. That is, the row selection circuit 5 scans the row in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light emitting element 22 of the subpixels 20 that are sequentially scanned to emit light. The brightness of the subpixel 20 is determined by the current flowing through the light emitting element 22. The sub-pixel 20 emits light with a gradation based on the determined brightness, and the image is displayed in the display area 2.

FIG. 4 is a schematic plan view illustrating a part of the image display device of the present embodiment.
In FIG. 4, the AA'line represents a cutting line in a cross-sectional view such as FIG. In the present embodiment, the light emitting element 150 and the driving transistor 103 are laminated in the Z-axis direction via the first interlayer insulating film 112 and the second interlayer insulating film 156. The light emitting element 150 corresponds to the light emitting element 22 in FIG. The drive transistor 103 corresponds to the drive transistor 26 in FIG. 3, and is also referred to as T2.

As shown in FIG. 4, the anode electrode of the light emitting device 150 is provided by the p-type semiconductor layer 153 shown in FIG. The electrode 165a is provided on the upper surface 153U of the p-type semiconductor layer 153. The electrode 165a is connected to the wiring 160a via the connecting portion 161a. The wiring 160a is connected to the via 161d by the contact hole 161d1, and the wiring 160a is connected to the wiring 110d provided in the lower layer via the via 161d.

The wiring 110d is connected to the drain electrode of the transistor 103 via the via 111d shown in FIG. The drain electrode of the transistor 103 is the region 104d shown in FIG. The source electrode of the transistor 103 is connected to the wiring 110s via the via 111s shown in FIG. The source electrode of the transistor 103 is the region 104s shown in FIG. In this example, the first wiring layer 110 includes a power line 3, and the wiring 110s is connected to the power line 3.

The cathode electrode of the light emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided on the upper layer of the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 160k via the via 161k. More specifically, one end of the via 161k is connected to the connecting portion 151a. The other end of the via 161k is connected to the wiring 160k via the contact hole 161k1. The wiring 160k is connected to the ground wire 4.

As described above, the light emitting element 150 can electrically connect the first wiring layer 110 provided below the light emitting element 150 to the second wiring layer 160 by using the via 161d. By using the via 161k, the light emitting element 150 can electrically connect the connection portion 151a provided below the second wiring layer 160 to the second wiring layer 160.

The manufacturing method of the image display device 1 of this embodiment will be described.
5A to 8B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
As shown in FIG. 5A, in the manufacturing method of the image display device 1 of the present embodiment, the substrate 102 is prepared. The TFT underlayer film 106 is formed on the first surface 102a. The TFT underlayer film 106 is formed by, for example, a CVD method. The Si layer 1104 is formed on the formed TFT lower layer film 106. The Si layer 1104 is an amorphous Si layer at the time of film formation, and after film formation, for example, a polycrystallized Si layer 1104 is formed by scanning an excimer laser pulse a plurality of times.

As shown in FIG. 5B, the transistor 103 is formed at a predetermined position on the TFT underlayer film 106. For example, in the LTPS process, the transistor 103 is formed as follows.

The polycrystalline Si layer 1104 shown in FIG. 5A is processed into an island shape like the transistor 103 shown in FIG. 4, and the TFT channel 104 is formed. The insulating layer 105 is formed so as to cover the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104 via the insulating layer 105. The transistor 103 is formed by selectively doping the gate 107 with an impurity such as B ⁺ and thermally activating it. The regions 104s and 104d are p-shaped active regions, and function as source regions and drain regions of the transistor 103, respectively. The region 104i is an n-type active region and functions as a channel.

As shown in FIG. 6, the insulating film 108 is provided so as to cover the insulating layer 105 and the gate 107. An appropriate manufacturing method is applied to the formation of the insulating film 108 depending on the material of the insulating film 108. For example, when the insulating film 108 is formed of SiO ₂ , techniques such as ALD and CVD are used.

The flatness of the insulating film 108 may be such that the first wiring layer 110 can be formed, and the flattening step does not necessarily have to be performed. When the insulating film 108 is not subjected to the flattening step, the number of steps for the flattening step can be reduced.

Vias 111s and 111d are formed through the insulating film 108 and the insulating layer 105. The vias 111s are formed to reach the region 104s. The via 111d is formed so as to reach the region 104d. For example, RIE or the like is used for forming a via hole for forming the vias 111s and 111d.

The first wiring layer 110 including the wirings 110s and 110d is formed on the insulating film 108. The wiring 110s is connected to one end of the via 111s. The wiring 110d is connected to one end of the via 111d. The first wiring layer 110 may be formed at the same time as the vias 111s and 111d are formed.

The first interlayer insulating film (first insulating film) 112 is formed so as to cover the insulating film 108 and the first wiring layer 110. The surface of the first interlayer insulating film 112 is flattened by chemical mechanical polishing (CMP) or the like, and a flattened surface 112F is formed.

In this way, the drive circuit unit (first substrate) 100 including the substrate 102 is formed. The manufacturing process of the drive circuit unit 100 may be executed in a plant different from the wafer bonding process described later, or may be executed in the same plant as the wafer bonding process.

As shown in FIG. 7A, the semiconductor growth substrate 1194 is prepared. The semiconductor growth substrate 1194 includes a crystal growth substrate 1001 and a semiconductor layer 1150. The crystal growth substrate 1001 is, for example, a Si substrate, a sapphire substrate, or the like. Preferably, the Si substrate is used as the crystal growth substrate 1001. Further, when a low temperature crystal growth process such as a low temperature sputtering method is used, it is also possible to use a cheaper glass substrate or the like.

The semiconductor layer 1150 is formed on the crystal growth substrate 1001. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order from the side of the crystal growth substrate 1001.

For the formation of the semiconductor layer 1150, for example, a CVD method is used, and a metal organic chemical vapor deposition method (MOCVD method) is preferably used. Alternatively, by using the low temperature sputtering method, the epitaxial crystal growth of the semiconductor layer 1150 is possible even at a process temperature of 700 ° C. or lower. By using such a low temperature sputtering method, it becomes possible to use a glass substrate or an apparatus having low heat resistance, so that the manufacturing cost can be reduced.

The semiconductor layer 1150 includes, for example, GaN, and more particularly includes In _X Al _Y Ga _1-XY N (0 ≦ X, 0 ≦ Y, X + Y <1) and the like.

In the early stage of crystal growth, crystal defects due to inconsistency of crystal lattice constant may occur, and the crystal with crystal defects exhibits an n-shape. Therefore, when the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001 as in this example, a large margin in the production process can be obtained, and the yield can be easily improved. There is an advantage.

A metal layer (first metal layer) 1161 is formed on the p-type semiconductor layer 1153. The metal layer 1161 is formed on the exposed surface 1153E of the p-type semiconductor layer 1153.

When the semiconductor layer 1150 is formed on the crystal growth substrate 1001, although not shown in FIG. 7A, the semiconductor layer 1150 may be formed via a buffer layer. For the buffer layer, for example, a nitride such as AlN is used. By growing the semiconductor layer 1150 on the crystal growth substrate 1001 via the buffer layer, the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 can be alleviated. Therefore, it is expected that the quality of the semiconductor crystal of the semiconductor layer 1150 will be improved. On the other hand, in the present embodiment, since the n-type semiconductor layer 1151 is bonded to the flattening surface 112F, a step of removing the buffer layer is added before the bonding. The same applies to the other embodiments described later.

As shown in FIG. 7B, a support substrate (second substrate) 1190 is prepared. In the support substrate 1190, a metal layer (first metal layer) 1162 is formed on one surface 1190E. The support substrate 1190 is made of, for example, quartz glass, Si, or the like.

In the semiconductor growth substrate 1194, the metal layer 1161 formed on the semiconductor growth substrate 1194 is arranged so as to face the metal layer 1162 formed on the support substrate 1190. The semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layers 1161 and 1162. The metal layers 1161 and 1162 may be the same material or different materials as long as they are conductive materials having light reflectivity. The metal layer is either a semiconductor growth substrate 1194 or a support substrate 1190 as long as it has a thickness sufficient to realize sufficient light reflectivity by having a light-shielding property when molded into the electrode 165a shown in FIG. It may be formed on one side.

As shown in FIG. 8A, after the support substrate 1190 is bonded to the semiconductor layer 1150 via the metal layer (first metal layer) 1163, the crystal growth substrate 1001 shown in FIG. 7B is removed, and the substrate 1195 is removed. It is formed. The metal layer 1163 is a jointed product of two metal layers 1161,1162. For example, wet etching or laser lift-off is used to remove the crystal growth substrate 1001.

The semiconductor layer 1150 of the substrate 1195 is bonded to the flattening surface 112F. The surface bonded to the flattening surface 112F is the exposed surface 1151E of the n-type semiconductor layer 1151. After that, the support substrate 1190 is removed. Wet etching and laser lift-off are also used to remove the support substrate 1190.

In the process of bonding the substrates, for example, the substrates are bonded to each other by heating and thermocompression bonding each substrate. In addition to the above, the bonded surfaces of the respective substrates may be further flattened using CMP or the like, and then the bonded surfaces may be cleaned by plasma treatment in a vacuum so as to be brought into close contact with each other.

When the semiconductor layer 1150 is bonded to the drive circuit unit 100, one semiconductor layer 1150 may be bonded to one drive circuit unit 100, or a plurality of semiconductor layers 1150 may be bonded to one drive circuit unit 100. be. When one semiconductor layer 1150 is bonded to one drive circuit unit 100, the size of the substrate 102 constituting the drive circuit unit 100 can be, for example, a rectangular shape or a square shape of about several tens of mm square to 150 mm square. .. In this case, the semiconductor layer 1150 formed on the substrate 1195 can be sized according to the size of the substrate 102.

When the plurality of semiconductor layers 1150 are bonded to one drive circuit unit 100, for example, a substantially rectangular glass substrate having a size of about 1500 mm × 1800 mm can be used as the substrate 102 constituting the drive circuit unit 100. The semiconductor layer 1150 formed on the substrate 1195 has a rectangular shape or a square shape of about several tens of mm square to 150 mm square, and can have a size of, for example, about 4 inches to 6 inches in terms of wafer dimensions. The size of the substrate 102 is appropriately selected according to the size of the image display device and the like.

FIG. 9 is a perspective view illustrating a part of the manufacturing method of the image display device of the present embodiment.
FIG. 9 schematically shows an example in which a plurality of semiconductor layers 1150 are bonded to one drive circuit unit 100.
The figure above the arrow in FIG. 9 shows that the plurality of substrates 1195 are arranged in a grid pattern. The figure below the arrow in FIG. 9 shows that the drive circuit unit 100 on which the flattening surface 112F is formed is arranged. FIG. 9 shows by arrows that a plurality of substrates 1195 arranged in a grid pattern are bonded to each other at the positions of the alternate long and short dash lines.

Since the quality of the semiconductor crystal deteriorates at and near the end of the semiconductor layer 1150, care must be taken not to form the light emitting element 150 at or near the end of the semiconductor layer 1150.
As shown in FIG. 9, the end portion of the semiconductor layer 1150 is formed so as to substantially coincide with the end portion of the support substrate 1190. Therefore, the plurality of substrates 1195 are arranged in a grid pattern facing the drive circuit unit 100 so as not to form a gap between the adjacent substrates 1195 as much as possible, for example, as shown by the solid line in FIG. As shown by the alternate long and short dash line in FIG. 9, the semiconductor layer 1150 is bonded onto the flattening surface 112F of the drive circuit unit 100.

When a plurality of semiconductor layers 1150 are bonded to one drive circuit unit 100, in the subsequent steps, the drive circuit unit 100 to which the plurality of semiconductor layers 1150 are bonded is divided for each substrate 102 according to the number of divisions. It can be an image display device of different quantity and size. Since it is preferable that the end portion of the semiconductor layer 1150 in which the quality of the semiconductor crystal is deteriorated becomes the end portion of the display region, the unit to be divided is preferably set to match the shape of the substrate 1195.

In the wafer bonding manufacturing process, the process up to forming the semiconductor growth substrate 1194 and the process of performing the processing after forming the substrate 1195 may be executed in the same plant or in different plants. good. For example, the substrate 1195 may be manufactured in the first plant, the substrate 1195 may be carried into a second plant different from the first plant, and the bonding step may be executed.

The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and the following method can also be used. That is, the semiconductor layer 1150 is formed on the crystal growth substrate 1001 and then stored in a container. For example, in the container, the support substrate 1190 is mounted and stored. After storage, the semiconductor layer 1150 is taken out of the container and attached to the drive circuit unit 100. Further, the semiconductor layer 1150 is stored in a container without being mounted on the support substrate 1190. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the drive circuit unit 100 as it is.

10A and 10B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
As shown in FIG. 10A, the metal layer 1163 shown in FIG. 8B is processed into a predetermined shape by etching to form an electrode 165a. Dry etching or wet etching is used to form the electrode 165a.

The semiconductor layer 1150 shown in FIG. 8B is processed into a predetermined shape by etching to form a light emitting element 150. In the light emitting element 150, the connection portion 151a is formed, and then the other portion is formed by further etching. This makes it possible to form a light emitting element 150 having a connection portion 151a projecting from the n-type semiconductor layer 151 in one direction on the flattening surface 112F. For example, a dry etching process is used for forming the light emitting element 150, and anisotropic plasma etching (Reactive Ion Etching, RIE) is preferably used.

The second interlayer insulating film (second insulating film) 156 is formed so as to cover the flattening surface 112F, the light emitting element 150, and the electrode 165a.

As shown in FIG. 10B, the via 161d (first via) is formed by embedding a via hole that penetrates the second interlayer insulating film 156 and the first interlayer insulating film 112 and reaches the wiring 110d with a conductive material. The via (second via) 161k is formed by embedding a via hole that penetrates the second interlayer insulating film 156 and reaches the connecting portion 151a with a conductive material. The connecting portion 161a is formed by embedding a contact hole formed so as to reach the electrode 165a. For example, RIE is used for forming via holes and contact holes.

The second wiring layer 160 including the wirings 160a and 160k is formed on the second interlayer insulating film 156. The wiring 160a is connected to one end of the connection portion 161a and the via 161d. The wiring 160k is connected to one end of the via 161k. The second wiring layer 160 may be formed at the same time as the vias 161k, 161d and the connecting portion 161a are formed.

In the case of the sub-pixel 20a of the modification of the present embodiment shown in FIG. 2, in the process of forming the first wiring layer 110, the first portion including at least one of the wirings 110s1 and 110d1 covers the TFT channel 104. It is molded into a shape. After forming the first wiring layer 110, the subpixel 20a shown in FIG. 2 is formed by the same manufacturing process as in the case of the first embodiment described above.

In this way, the sub-pixels 20 and 20a are formed, and the image display device is formed.

FIG. 11 is a schematic perspective view illustrating the image display device of the present embodiment.
As shown in FIG. 11, in the image display device of the present embodiment, a light emitting circuit unit 172 having a large number of light emitting elements 150 is provided on the flattening surface 112F of the drive circuit unit 100. The light emitting circuit unit 172 is a structure including a light emitting element 150, an electrode 165a, a second interlayer insulating film 156 covering them, and a second wiring layer 160. As described above, the light emitting circuit unit 172 and the drive circuit unit 100 are electrically connected by the via 161d shown in FIG. 1 and the like.

The configuration shown in FIG. 11 is an example in the case where the color filter is not provided, and is applied when the color filter is not provided in other embodiments described later. Further, the color filter can be provided also in this embodiment by applying the case of the third embodiment shown in FIG. 19 and the fourth embodiment shown in FIG. 27, which will be described later.

The effect of the image display device 1 of the present embodiment will be described.
In the manufacturing method of the image display device 1 of the present embodiment, the semiconductor layer 1150 is bonded on the flattening surface 112F of the drive circuit unit 100, and then the semiconductor layer 1150 is etched to form the light emitting element 150. After that, the light emitting element 150 is covered with the second interlayer insulating film 156, and the first wiring layer 110 and the second wiring layer 160 for electrical connection with the external circuit are formed. Therefore, the manufacturing process is remarkably shortened as compared with transferring the individualized light emitting elements onto the flattened surface 112F individually.

For example, in a 4K image quality image display device, the number of subpixels exceeds 24 million, and in the case of an 8K image quality image display device, the number of subpixels exceeds 99 million. It would take an enormous amount of time to individually form such a large number of light emitting elements and mount them on a circuit board. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Further, if a large number of light emitting elements are individually mounted, the yield is reduced due to poor connection at the time of mounting, and further cost increase is unavoidable. However, the manufacturing method of the image display device of the present embodiment is as follows. The effect is obtained.

As described above, in the manufacturing method of the image display device 1 of the present embodiment, the light emitting element is formed by etching after the entire semiconductor layer 1150 is bonded to the flattening surface 112F, so that the transfer step of the light emitting element can be performed once. Complete. Therefore, in the manufacturing method of the image display device 1 of the present embodiment, the time of the transfer step can be shortened and the number of steps can be reduced as compared with the conventional manufacturing method.

Further, the semiconductor layer 1150 is bonded to the flattening surface 112F at the wafer level without disassembling the semiconductor layer 1150 in advance or forming an electrode at a position corresponding to the circuit element. Therefore, alignment at the bonding stage is not required. Therefore, the bonding process can be easily performed in a short time. Since it is not necessary to align the light emitting element 150 at the time of bonding, it is easy to reduce the size of the light emitting element 150, which is suitable for a high-definition display.

In the present embodiment, the drive circuit unit 100 can include a drive circuit including a TFT and the like, a scanning circuit, and the like. By using the LTPS process or the like, the circuit 101 constituting the drive circuit unit 100 can be built on a light-transmitting substrate such as a glass substrate, and the existing flat panel display manufacturing process or plant can be used. There is an advantage that it can be done.

In the present embodiment, the light emitting element 150 is formed in a layer above the transistor 103 and the like. They can be interconnected by forming a circuit 101 including a light emitting element 150 and a transistor 103 formed in different layers, a via 161d penetrating the second interlayer insulating film 156 and the first interlayer insulating film 112. By using the multi-layer wiring technology technically established in this way, a uniform connection structure can be easily realized and the yield can be improved. Therefore, the decrease in yield due to poor connection of the light emitting element or the like is suppressed.

In the image display device 1 of the present embodiment, the light output from the light emitting surface 151S is an image via an optical path including the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102. It is radiated to the outside of the display device 1. The total thickness of the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, and the TFT lower layer film 106 may range from, for example, about 1 μm to about several μm. That is, the light output from the light emitting surface 151S is radiated to the outside through an optical path of about 1 μm to several μm. Therefore, the light output from the light emitting surface 151S is attenuated according to the length of the optical path as compared with the case where it is directly radiated to the outside.

In the present embodiment, the electrode 165a is provided over the upper surface 153U provided so as to face the light emitting surface 151S. Therefore, the upward scattering of the light emitting element 150 is reflected by the electrode 165a toward the light emitting surface 151S.

The light emitting element 150 is covered with a second interlayer insulating film 156 except for the light emitting surface 151S and the upper surface 153U. By forming the second interlayer insulating film 156 with a material having high light reflectivity such as white resin, scattered light or the like to the side of the light emitting element 150 is reflected so as not to leak to the side of the light emitting element 150. can do.

As described above, in the image display device of the present embodiment, the light emitting element 150 can be covered with the electrode 165a and the second interlayer insulating film 156, and the light traveling in a direction other than the light emitting surface 151S can be confined in the light emitting element 150. .. The light confined in the light emitting element 150 is reflected at the interface between the light emitting element 150 and the second interlayer insulating film 156, and a part of the light is guided to the light emitting surface 151S side. Therefore, the light emitting element 150 substantially improves the luminous efficiency, has a long optical path from the light emitting surface 151S to the outside, and emits light of sufficient intensity to the outside even if the light intensity is attenuated. be able to.

In the present embodiment, as described above, light of sufficient intensity is output from the light emitting surface 151S, so that if the output light is applied to the TFT channel 104, the transistor 103 may malfunction. In the image display device of this modification, the first portion including at least one of the wirings 110s1 and 110d1 is provided so as to cover the TFT channel 104. Therefore, most of the light output from the light emitting surface 151S is shielded by the first portion, and the light output from the light emitting surface 151S is less likely to reach the TFT channel 104. Therefore, the malfunction of the transistor 103 due to the irradiation of light is suppressed.

(Second embodiment)
FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
As shown in FIG. 12, the image display device of the present embodiment includes a sub-pixel 220, and the sub-pixel 220 is the other embodiment described above in that the p-type semiconductor layer 253 provides a light emitting surface 253S. It is different from the case of. In the present embodiment, the configuration of the light emitting element 250 is different from that of the other embodiments described above, so that the configuration of the transistor 203 for driving the light emitting element 250 is also different. The same components as in the case of other embodiments are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

The subpixel 220 of the image display device of the present embodiment includes a substrate 102, a transistor 203, a first wiring layer 110, a first interlayer insulating film 112, a light emitting element 250, an electrode 265k, and a second interlayer insulating film. 156, via 161d, and a second wiring layer 160 are included.

The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like as in the case of the other embodiments described above. In the present embodiment, the circuit 101 includes a TFT channel 204, an insulating layer 105, an insulating film 108, vias 111s, 111d, and a first wiring layer 110.

The TFT channel 204 includes regions 204s, 204i, 204d. The regions 204s, 204i, 204d are provided on the TFT underlayer film 106. The regions 204s and 204d are doped with n-type impurities such as phosphorus ions (P ⁻ ). The region 204s is ohmic contacted with the via 111s. The area 204d is ohmic contacted with the via 111d.

The gate 107 is provided on the TFT channel 204 via the insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

In the transistor 203, when a voltage higher than the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage of the gate 107 with respect to the region 204s. The TFT channel 204 and the gate 107 are formed of the same material and manufacturing method as the TFT channel 104 and the gate 107 in the case of the above-mentioned other embodiments. The insulating layer 105 and the gate 107 are covered with the insulating film 108 as in the case of the other embodiments described above, and the first wiring layer 110 is provided on the insulating film 108.

The first wiring layer 110 includes wirings 110s and 110d. The wiring 110s is provided above the area 204s. The wiring 110s is connected to, for example, the ground wire 4 shown in FIG. 13 described later. The wiring 110d is provided above the area 204d. As in the case of the other embodiments described above, the wiring 110d is connected to the via 161d and is electrically connected to the second wiring layer 160 via the via 161d.

The via 111s is provided between the wiring 110s and the area 204s. The via 111s electrically connects the wiring 110s and the area 204s. The via 111d is provided between the wiring 110d and the area 204d. The via 111d electrically connects the wiring 110d and the area 204d. The vias 111s and 111d are formed of the same materials and manufacturing methods as in the other embodiments described above.

The first interlayer insulating film 112 is provided so as to cover the insulating film 108 and the first wiring layer 110, as in the case of the other embodiments described above, and includes the flattening surface 112F.

The light emitting element 250 is provided on the flattening surface 112F. The light emitting element 250 includes a light emitting surface 253S provided on the flattening surface 112F. The light emitting surface 253S is in contact with the flattening surface 112F. The light emitting element 250 includes an upper surface 251U provided so as to face the light emitting surface 253S. The light emitting element 250 is a prismatic or cylindrical element as in the case of the other embodiments described above.

The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the light emitting surface 253S toward the upper surface 251U. In this embodiment, the light emitting surface 253S is provided by the p-type semiconductor layer 253.

The light emitting element 250 includes a connection portion 253a. The connecting portion 253a is provided so as to project on the flattening surface 112F from the p-type semiconductor layer 253 in one direction. The height of the connection portion 253a from the flattening surface 112F is the same as or lower than the height of the p-type semiconductor layer 253 from the flattening surface 112F. The connection portion 253a is a part of the p-type semiconductor layer 253. The connection portion 253a is connected to one end of the via 261a, and the p-type semiconductor layer 253 is electrically connected to the second wiring layer 160 via the via 261a.

The light emitting element 250 has the same XY plan view shape as in the other embodiments described above. An appropriate shape is selected according to the layout of the circuit element and the like.

The light emitting element 250 is a light emitting diode similar to that of the other embodiments described above. That is, the wavelength of the light emitted by the light emitting element 250 is, for example, blue light emission of about 467 nm ± 20 nm or blue-purple light emission of about 410 nm ± 20 nm. The wavelength of the light emitted by the light emitting element 250 is not limited to the above-mentioned value, and may be appropriate.

As in the case of the other embodiments described above, the second interlayer insulating film 156 is provided so as to cover the flattening surface 112F and the light emitting element 250. A second wiring layer 160 is provided on the second interlayer insulating film 156.

The second wiring layer 160 includes wirings 260a and 260k. The wirings 260a and 260k are separately formed and can be connected to different potentials. A part of the wiring 260a is provided above the connection portion 253a. The other part of the wiring 260a is connected to, for example, the power line 3 of the circuit of FIG. A part of the wiring 260k is provided above the upper surface 251U. A connection portion 261k is provided between the wiring 260k and the upper surface 251U, and the upper surface 251U is connected to the wiring 260k by the connection portion 261k. The other part of the wiring 260k is provided above the wiring 110d.

The via 161d is provided between the wiring 260k and the wiring 110d, and electrically connects the wiring 260k and the wiring 110d. Therefore, the n-type semiconductor layer 251 is electrically connected to the drain region of the transistor 203 via an electrode 265k having light reflectivity, a wiring 260k, a via 161d, a wiring 110d, and a via 111d.

The via 261a is provided so as to penetrate the second interlayer insulating film 156 and reach the connecting portion 253a. The via 261a is provided between the wiring 260a and the connection portion 253a, and electrically connects the wiring 260a and the connection portion 253a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power line 3 of the circuit of FIG. 13 via the connection portion 253a, the via 261a, and the wiring 260a.

FIG. 13 is a schematic block diagram illustrating an image display device according to the present embodiment.
As shown in FIG. 13, the image display device 201 of the present embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, for example, the sub-pixels 220 are arranged in a grid pattern on the XY plane, as in the case of the other embodiments described above.

The subpixel 220 includes a light emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228. In FIG. 13, the selection transistor 224 may be displayed as T1, the drive transistor 226 may be displayed as T2, and the capacitor 228 may be displayed as Cm.

In the present embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the drive transistor 226 connected in series with the light emitting element 222 is provided on the ground line 4 side. That is, the drive transistor 226 is connected to the lower potential side than the light emitting element 222. The drive transistor 226 is an n-channel transistor.

A selection transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the drive transistor 226 and the ground wire 4.

The row selection circuit 205 and the signal voltage output circuit 207 supply the signal line 208 with a signal voltage having a polarity different from that of the other embodiments described above in order to drive the drive transistor 226 which is an n-channel transistor.

In this embodiment, since the polarity of the drive transistor 226 is n channels, the polarity of the signal voltage and the like are different from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 so as to sequentially select one row from the array of subpixels 220 in the m row. The signal voltage output circuit 207 supplies a signal voltage having the required analog voltage value for each subpixel 220 in the selected row. The drive transistor 226 of the subpixel 220 in the selected row causes a current corresponding to the signal voltage to flow through the light emitting element 222. The light emitting element 222 emits light with a brightness corresponding to the flowing current.

A method of manufacturing the image display device of the present embodiment will be described.

14A to 15 are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
As shown in FIG. 14A, the semiconductor growth substrate 1194 is prepared. The semiconductor growth substrate 1194 has already been described in relation to FIG. 7A, but in the present embodiment, the metal layer 1161 shown in FIG. 7A is not formed on the semiconductor layer 1150 of the semiconductor growth substrate 1194.

As shown in FIG. 14B, the semiconductor layer 1150 of the semiconductor growth substrate 1194 is bonded to the drive circuit unit 100. In this bonding step, the exposed surface 1153E of the p-type semiconductor layer 1153 is bonded to the flattening surface 112F.

After that, the crystal growth substrate 1001 is removed, and as shown in FIG. 15, a metal layer (second metal layer) 1164 is formed on the semiconductor layer 1150 bonded to the flattening surface 112F. The metal layer 1164 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151. As the metal layer 1164, the same material as the material for forming the metal layers 1161 and 1162 in the other embodiments described above can be used.

16A to 17B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
The steps shown in FIGS. 16A-17B are applied in place of the steps shown in FIGS. 14A-15. In the steps shown in FIGS. 16A to 17B, the semiconductor layer 1150 is transferred to the support substrate 1190 and then bonded to the drive circuit unit 100. The metal layers 1161 and 1162 are formed before the semiconductor layer 1150 is bonded to the drive circuit unit 100.

As shown in FIG. 16A, the semiconductor growth substrate 1294 is prepared. The semiconductor growth substrate 1294 has a different configuration from the semiconductor growth substrate 1194 shown in FIGS. 7A and 14A. In the semiconductor growth substrate 1294, the semiconductor layer 1150 is laminated in the order of the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 from the side of the crystal growth substrate 1001. The metal layer 1161 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151.

As shown in FIG. 16B, the support substrate 1190 is prepared. In the support substrate 1190, a metal layer 1162 is formed on one surface 1190E. The semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layers 1161 and 1162, and the substrate 1295 shown in FIG. 17A is prepared.

As shown in FIG. 17A, the substrate 1295 is attached to the drive circuit unit 100. In the substrate 1295, the semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layer 1163. The bonded surface with the flattening surface 112F is the exposed surface 1153E of the p-type semiconductor layer 1153.

As shown in FIG. 17B, the support substrate 1190 is removed. Wet etching and laser lift-off are used to remove the support substrate 1190 as in the other embodiments described above. In this way, the p-type semiconductor layer 1153 can be attached to the drive circuit unit 100.

18A and 18B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
As shown in FIG. 18A, the metal layer 1164 shown in FIG. 15 or the metal layer 1163 shown in FIG. 17B is processed into a predetermined shape to form an electrode 265k. The semiconductor layer 1150 shown in FIG. 15 or FIG. 17B is processed into a predetermined shape to form a light emitting element 250. In the formation of the light emitting element 250, the connection portion 253a is formed and other portions are formed as in the case of the other embodiments described above.

The second interlayer insulating film 156 is formed so as to cover the flattening surface 112F, the light emitting element 250, and the electrode 265k.

As shown in FIG. 18B, the via 161d is formed so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 110d. The via 261a is formed so as to penetrate the second interlayer insulating film 156 and reach the connecting portion 253a. The connection portion 261k is formed so as to reach the electrode 265k. A second wiring layer 160 including the wirings 260a and 260k is formed, the wiring 260a and the via 261a are connected, and the wiring 260k and the via 161d are connected. The wiring 260k is also connected to the connection portion 261k. The second wiring layer 160 may be formed at the same time as the vias 261a and 161d and the connection portion 261k are formed.

In this way, the sub-pixel 220 is formed and the image display device 201 is formed.

The effect of the image display device of this embodiment will be described.
In the image display device of the present embodiment, the time of the transfer step for forming the light emitting element 250 can be shortened and the number of steps can be reduced, as in the case of the other embodiments described above. In addition, in the crystal growth step of the semiconductor layer 1150, when the crystal is grown from the n-type semiconductor layer 1151, the transfer to the support substrate 1190 can be eliminated, so that the number of steps can be reduced.

In the image display device 201 of the present embodiment, since the p-type semiconductor layer 253 can be the light emitting surface 253S, the degree of freedom in the circuit configuration is increased, and the design efficiency of the product can be improved.

(Third embodiment)
FIG. 19 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
This embodiment differs from the other embodiments described above in that the n-type semiconductor layer 151 is a light emitting device 150 having a light emitting surface 151S1. In this embodiment, the light-shielding layer 330 is included. In the present embodiment, the color filter 180 is mounted on the light emitting surface 151S1 side. The same components as in the case of the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

As shown in FIG. 19, the subpixel 320 of the image display device of the present embodiment includes a color filter 180, a transistor 103, a first wiring layer 110, a light-shielding layer 330, a first interlayer insulating film 112, and light emission. It includes an element 150, an electrode 165a, a second interlayer insulating film 156, and a via 161d. The transistor 103 is a p-channel TFT, which is the same as in the first embodiment and the second embodiment. The light emitting element 150 provides a light emitting surface 151S1 having an n-type semiconductor layer 151. In this embodiment, the light emitting surface 151S1 is roughened.

The color filter 180 includes a light-shielding unit 181 and a color conversion unit 182. As described above, the color filter (wavelength conversion member) 180 includes a color conversion unit 182 having light transmission, and is therefore a light transmission member. The color conversion unit 182 is provided immediately below the light emitting surface 151S1 of the light emitting element 150 according to the shape of the light emitting surface 151S1. In the color filter 180, the portion other than the color conversion unit 182 is a light-shielding unit 181. The light-shielding unit 181 is a so-called black matrix, which reduces bleeding due to color mixing of light emitted from an adjacent color conversion unit 182 and makes it possible to display a sharp image.

The color conversion unit 182 has one layer or two or more layers. FIG. 19 shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one layer or two layers is determined by the color of the light emitted by the subpixel 320, that is, the wavelength. When the emission color of the subpixel 320 is red, the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing red light. When the emission color of the subpixel 320 is green, the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing green light. When the emission color of the subpixel 320 is blue, it is preferably one layer.

When the color conversion unit 182 has two layers, the first layer is the color conversion layer 183 and the second layer is the filter layer 184. The first color conversion layer 183 is provided at a position closer to the light emitting element 150. The filter layer 184 is laminated on the color conversion layer 183.

The color conversion layer 183 converts the wavelength of the light emitted by the light emitting element 150 into a desired wavelength. In the case of the subpixel 320 that emits red light, the light having a wavelength of 467 nm ± 20 nm, which is the wavelength of the light emitting element 150, is converted into light having a wavelength of, for example, about 630 nm ± 20 nm. In the case of the subpixel 320 that emits green light, the light having a wavelength of 467 nm ± 20 nm, which is the wavelength of the light emitting element 150, is converted into light having a wavelength of, for example, about 532 nm ± 20 nm.

The filter layer 184 blocks the wavelength component of blue light emission remaining without color conversion in the color conversion layer 183.

When the color of the light emitted by the subpixel 320 is blue, the color may be output as it is without passing through the color conversion layer 183 or the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is about 467 nm ± 20 nm, the light may be output without passing through the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is 410 nm ± 20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ± 20 nm.

Even in the case of the blue subpixel 320, the subpixel 320 may have a filter layer 184. By providing the filter layer 184 through which the blue light is transmitted to the blue subpixel 320, minute external light reflection other than the blue light generated on the surface of the light emitting element 150 is suppressed.

The color filter 180 has a first surface 180a. A transparent thin film adhesive layer 188 is provided on the first surface 180a. The drive circuit unit 100 is provided on the first surface 180a via the transparent thin film adhesive layer 188. In the present embodiment, the drive circuit unit 100 includes a TFT lower layer film 106, a circuit 101, and a first interlayer insulating film 112.

In the present embodiment, the p-channel transistor 103 is formed on the TFT lower layer film 106. The transistor 103 is a TFT, and its configuration and the like are the same as those of the first embodiment and the second embodiment described above, and detailed description thereof will be omitted.

In the present embodiment, the first interlayer insulating film 112 includes two insulating films 112a and 112b. The insulating films 112a and 112b are made of the same material to form the first interlayer insulating film 112. The insulating film (first insulating film) 112a is provided on the insulating film 108 and the first wiring layer 110. A light-shielding layer 330 is provided on the insulating film 112a. An insulating film (third insulating film) 112b is provided on the light-shielding layer 330, and the light-shielding layer 330 is provided between the insulating films 112a and 112b. The light-shielding layer 330 is provided on the entire surface of the first interlayer insulating film 112 and the second interlayer insulating film 156 except for a part thereof.

The light-shielding layer 330 may or may not be conductive as long as it is a light-shielding material, but is made of, for example, a light-reflecting metal material. The light-shielding layer 330 may be formed of a black resin. When the light-shielding layer 330 is formed of the black resin, the vias can be collectively formed together with the first interlayer insulating film 112 and the like without forming through holes larger than the diameter of the vias in advance.

The light emitting element 150 causes the emitted light to reach the color filter 180 via the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, and the TFT lower layer film 106. Therefore, the light-shielding layer 330 is provided with a through hole 331L in order to secure a path for the light emitted by the light emitting element 150. Since the via 161d is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112, when the light-shielding layer 330 is formed of a conductive material, a through hole 331d for passing the via 161d is provided. It is provided.

The light emitted from the light emitting element 150 is emitted from the overlapping region of the light emitting surface 151S1 and the through hole 331L. Therefore, if the positions of the two are displaced due to variations in manufacturing or the like, there is a possibility that the size of the region where light is emitted varies depending on the light emitting element 150. Therefore, it is desirable to set the inner diameter of the through hole 331L to include the outer periphery of the light emitting surface 151S1 in anticipation of manufacturing variations and the like. For example, the inner diameter of the through hole 331L is formed to be slightly larger than the outer circumference of the light emitting surface 151S1.

The light-shielding layer 330 includes a light-shielding portion 330a, and the light-shielding portion 330a is provided so as to cover most of the TFT channel 104. Preferably, the outer circumference of the light-shielding portion 330a is set to include the outer circumference of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding portion 330a in XY plan view.

By setting the light-shielding portion 330a in this way, even when light is radiated below the light emitting element 150, the scattered light or the like is shielded by the light-shielding portion 330a and hardly reaches the TFT channel 104. It is possible to suppress the malfunction of the transistor 103.

The light-shielding layer 330 may be provided in a limited area including a portion directly above the TFT channel 104, separated from other portions. In this example, the light-shielding layer 330 is not connected to any potential, but may be connected to a specific potential such as a ground potential or a power supply potential. When the light-shielding layer 330 has a plurality of separated portions, all of them may have a common potential or may be connected to different potentials for each portion.

The light emitting element 150 is provided on the flattening surface 112F. The light emitting surface 151S1 of the light emitting element 150 is roughened. A transparent flattening film 155 is provided between the light emitting surface 151S1 and the first interlayer insulating film 112. The transparent flattening film 155 provides a flattening surface so that the roughened light emitting surface 151S1 is in close contact with the flattening surface 112F.

The light emitting element 150 is a prismatic or columnar element including a light emitting surface 151S1 and an upper surface 153U. The light emitting surface 151S1 is in contact with the transparent thin film adhesive layer 188 via the transparent flattening film 155. The upper surface 153U is a surface provided so as to face the light emitting surface 151S1.

The light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the light emitting surface 151S1 toward the upper surface 153U.

The light emitting element 150 includes a connection portion 151a. The connecting portion 151a is formed so as to project in one direction from the n-type semiconductor layer 151 on the flattening surface 112F via the transparent flattening film 155. The connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and connects the n-type semiconductor layer 151 to the wiring 160k via the via 161k. Since the configuration of the light emitting element 150 is the same as that of the first embodiment described above except that the light emitting surface 151S1 is roughened, further detailed description will be omitted.

The electrode 165a is provided over the upper surface 153U. The electrode 165a is provided between the upper surface 153U and the connecting portion 161a. The electrode 165a is the same as the case of the other embodiment described above in that the light scattered to the upper surface 153U side of the light emitting element 150 is reflected to the light emitting surface 151S1 side to improve the luminous efficiency of the light emitting element 150. Further detailed description will be omitted.

The second interlayer insulating film 156 is provided so as to cover the flattening surface 112F, the light emitting element 150, and the transparent flattening film 155. The configurations of the via 161d, the connecting portion 161a, and the second wiring layer 160 are the same as those in the first embodiment described above, and detailed description thereof will be omitted.

FIG. 20 is a schematic block diagram illustrating the image display device of the present embodiment.
As shown in FIG. 20, in the image display device 301 of the present embodiment, the sub-pixels 320 are arranged in the display area 2. The sub-pixels 320 are arranged in a grid pattern, for example. For example, n subpixels 320 are arranged along the X axis, and m subpixels 320 are arranged along the Y axis.

Pixel 10 includes a plurality of subpixels 320 that emit light of different colors. The subpixel 320R emits red light. The subpixel 320G emits green light. The subpixel 320B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 320R, 320G, and 320B emitting light at a desired brightness.

One pixel 10 includes three sub-pixels 320R, 320G, 320B, and the sub-pixels 320R, 320G, 320B are arranged linearly on the X-axis, for example. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or sub-pixels of different colors may be arranged in each column as in this example.

In the image display device 301 of the present embodiment, the configurations of the power supply line 3, the ground line 4, the scanning line 6, and the signal line 8 are the same as those of the first embodiment described above. The image display device 301 is different from the case of the first embodiment in that the emission color and the brightness of one pixel 10 are determined by causing each of the three types of subpixels to emit light at a set brightness. Since it is the same as the example of FIG. 3 in the case of the first embodiment except that the signal configuration for that purpose may be different, detailed description of the circuit configuration will be omitted.

A method of manufacturing the image display device of the present embodiment will be described.
21A to 23B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
In the manufacturing method of the image display device of the present embodiment, the same manufacturing process is applied until the first wiring layer 110 is formed in the steps of preparing the drive circuit unit 100 shown in FIG. In the manufacturing method of this embodiment, the process after forming the first wiring layer 110 will be described.
As shown in FIG. 21A, the insulating film 112a is formed on the insulating film 108 and the first wiring layer 110. The light-shielding layer 330 including the through holes 331L and 331d is formed by forming a metal layer on, for example, the insulating film 112a and then processing it by etching. The light-shielding portion 330a is formed on the TFT channel 104 when the light-shielding layer 330 is formed.

As shown in FIG. 21B, the insulating film 112b is formed on the insulating film 112a and the light-shielding layer 330. The through holes 331L and 331d are embedded by the insulating film 112b, and the surface is flattened to form the flattened surface 112F.

As shown in FIG. 22A, the substrate 1195 shown in FIG. 8A is prepared. The steps described in FIGS. 7A to 8A are applied to the substrate 1195. The n-type semiconductor layer 1151 of the substrate 1195 is roughened to form a roughened exposed surface 1151E1. A transparent flattening film 1155 is formed over the exposed surface 1151E1. The transparent flattening film 1155 is a film having light transmittance. The exposed surface 1155E of the formed transparent flattening film 1155 is flattened. For example, CMP is used for flattening the exposed surface 1155E.

As shown in FIG. 22B, the semiconductor layer 1150 is bonded to the drive circuit unit 100. As for the bonded surface, the semiconductor layer 1150 is the exposed surface 1155E of the transparent flattening film 1155, and the drive circuit unit 100 is the flattening surface 112F.

The above description describes a step of forming a metal layer on at least one of a semiconductor layer 1150 and a support substrate 1190, transferring the semiconductor layer 1150 to the support substrate 1190 via the metal layer, and then attaching the semiconductor layer 1150 to the substrate 102. Is. As described with reference to FIGS. 14A to 15 in the second embodiment, the semiconductor layer 1150 is not transferred to the support substrate 1190, the semiconductor layer 1150 is bonded to the substrate 102, and then the metal layer is placed on the semiconductor layer 1150. May be formed.

As shown in FIG. 23A, the metal layer 1163 and the semiconductor layer 1150 shown in FIG. 22B are etched into a predetermined shape to form an electrode 165a and a light emitting element 150. The step of forming the electrode 165a and the light emitting element 150 is the same as that of the other embodiments described above. The transparent flattening film 155 is formed at the same time as the light emitting element 150 is formed. In this example, since the substrate 102 is removed later, the drive circuit unit 100 includes the TFT lower layer film 106, the circuit 101, and the first interlayer insulating film 112.

The second interlayer insulating film 156 is formed so as to cover the flattening surface 112F, the light emitting element 150, and the electrode 165a. When the transparent flattening film 155 is exposed on the side surface of the light emitting element 150, the second interlayer insulating film 156 is also provided so as to cover the transparent flattening film 155.

As shown in FIG. 23B, the vias 161d, 161k, the connection portion 161a, and the second wiring layer 160 are formed on the second interlayer insulating film 156 in the same manner as in the other embodiments described above.

As shown in FIG. 24A, an adhesive layer 1170 is formed on the second interlayer insulating film 156 and the second wiring layer 160, and the reinforcing substrate 1180 is adhered via the adhesive layer 1170. After that, the substrate 102 is removed to expose the forming surface 1192A of the color filter 180. Wet etching or laser lift-off is used to remove the substrate 102.

As shown in FIG. 24B, the color filter (wavelength conversion member) 180 is adhered to the forming surface 1192A via the transparent thin film adhesive layer 188.

The purpose of removing the substrate 102 when mounting the color filter 180 is to reduce the transmission loss of the synchrotron radiation from the light emitting surface 151S1. Therefore, when removing the substrate 102, the color filter 180 may be formed by removing not only the entire substrate 102 but also a part of the substrate 102, for example. Removing a part of the substrate 102 means thinning the substrate 102 by etching or the like. Alternatively, the substrate 102 may be configured in a multi-layer structure in advance with a transparent resin or the like, and a part of the layers may be peeled off to substantially thin the substrate 102.

25A to 25D are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
25A to 25D show a method of forming a color filter by an inkjet method. This manufacturing process is applied in place of the process shown in FIG. 24B described above.

As shown in FIG. 25A, the substrate 102 is removed and the structure 1192 with the forming surface 1192A exposed is prepared. The structure 1192 includes a drive circuit unit 100, a light emitting element 150, vias 161d, 161k, a second wiring layer 160, an adhesive layer 1170, and a reinforcing substrate 1180.

As shown in FIG. 25B, a light-shielding portion 181 is formed on the formation surface 1192A of the color filter. The light-shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.

As shown in FIG. 25C, the phosphor corresponding to the emission color is ejected from the inkjet nozzle to form the color conversion layer 183. The phosphor colors the region where the light-shielding portion 181 is not formed. As the fluorescent material, for example, a general fluorescent material, a perovskite fluorescent material, or a fluorescent paint using a quantum dot fluorescent material is used. When a perovskite phosphor material or a quantum dot phosphor material is used, it is preferable because each emission color can be realized, the monochromaticity is high, and the color reproducibility can be high. After drawing with an inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film at the time of coloring is set to be thinner than the thickness of the light-shielding portion 181.

As described above, for the subpixels that emit blue light, the color conversion layer 183 is not formed if the color conversion unit is not formed. Further, when the blue color conversion layer is formed for the blue emission sub-pixels, if the color conversion unit may be one layer, the thickness of the coating film of the blue phosphor is preferably the light-shielding portion 181. It is said to be about the same as the thickness of.

As shown in FIG. 25D, the paint for the filter layer 184 is ejected from the inkjet nozzle. The paint is applied over the coating film of the phosphor. The total thickness of the paint film of the phosphor and the paint is about the same as the thickness of the light-shielding portion 181.

Whether it is a film-type color filter or an inkjet-type color filter, it is desirable that the color conversion layer 183 is as thick as possible in order to improve the color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambersian, whereas the emission angle of the non-color-converted blue light is limited by the light-shielding portion 181. .. Therefore, there arises a problem that the display color of the display image is dependent on the viewing angle. In order to match the light distribution of the subpixels provided with the color conversion layer 183 with the light distribution of blue light that is not color-converted, the thickness of the color conversion layer 183 should be about half the opening size of the light-shielding portion 181. Is desirable.

For example, in the case of a high-definition image display device of about 250 ppi, the pitch of the subpixels 20 is about 30 μm, so that the thickness of the color conversion layer 183 is preferably about 15 μm. Here, when the color conversion material is made of spherical phosphor particles, it is preferable to stack them in a close-packed structure in order to suppress light leakage from the light emitting element 150. For that purpose, at least three layers of particles need to be formed. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably, for example, about 5 μm or less, and more preferably about 3 μm or less. Since the perovskite phosphor material, the quantum dot phosphor material, and the like are easily deteriorated by oxygen and moisture, it is preferable that the color conversion layer 183 is sealed with an inorganic film such as SiO ₂ .

FIG. 26 is a schematic perspective view illustrating the image display device of the present embodiment.
As shown in FIG. 26, in the image display device of the present embodiment, a drive circuit unit 100 is provided on the color filter 180. The light emitting circuit unit 172 having a large number of light emitting elements 150 is provided on the drive circuit unit 100. The light emitting circuit unit 172 and the drive circuit unit 100 are electrically connected by a via 161d.

In the present embodiment, the color filter 180 is provided to enable the configuration of the full-color image display device 301. However, as in the case of the other embodiments described above, the image display device is provided without the color filter. May be configured. In that case, for example, the substrate 102 may not be removed and may be left as it is.

The effect of the image display device 301 of this embodiment will be described.
According to the method of manufacturing the image display device 301 of the present embodiment, the time of the transfer step for forming the light emitting element 150 can be shortened and the number of steps can be reduced, as in the case of the other embodiments described above. In addition to the above effect, since the light emitting surface 151S1 is an n-type semiconductor layer 151 having a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thicker and the light emitting surface 151S1 can be sufficiently roughened.

In the image display device 301 of the present embodiment, since the synchrotron radiation is diffused by roughening the light emitting surface 151S1, even a small light emitting element 150 can be used as a light source having a sufficient light emitting area. can.

In the image display device 301 of the present embodiment, the light-shielding layer 330 is provided between the insulating films 112a and 112b. The light-shielding layer 330 is provided between the light emitting element 150 and the transistor 103. Therefore, even if the light emitting element 150 emits light, the emitted light does not easily reach the TFT channel 104, and the transistor 103 can be prevented from malfunctioning.

The light-shielding layer 330 can be formed of a conductive material such as metal, and the light-shielding layer 330 can be connected to any potential. For example, by arranging a part of the light-shielding layer 330 directly under a switching element such as a transistor 103 and connecting it to a ground potential, a power supply potential, or the like, it is possible to use it for noise suppression.

The light-shielding layer 330 is not limited to the case of the present embodiment, and can be applied in common to the subpixels of the other embodiments described above and other embodiments described later. Even when applied to other embodiments, the same effects as described above can be obtained.

In the above example, the configuration and manufacturing method of the light emitting element having the roughened light emitting surface have been described. In the light emitting element having a connecting portion, a roughened light emitting surface can be applied as in the case of the present embodiment. Specific applications include the light emitting device 150 in the case of the first embodiment and its modifications, the light emitting element 250 in the case of the second embodiment, and the semiconductor layer 650 in the sixth embodiment described later. By applying the roughening of the light emitting surface to the components of these light emitting elements, the above-mentioned effects can be obtained. Also in the case of other embodiments, roughening of the light emitting surface can be applied by applying the light emitting element provided with the connecting portion.

(Fourth Embodiment)
FIG. 27 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
This embodiment differs from the other embodiments described above in that a third wiring layer 440 is included between the light emitting element 150 and the flattening surface 112F. The third wiring layer 440 is formed of a light-transmitting conductive film, and is electrically connected to the light emitting element 150. The light emitting element 150 is connected to the third wiring layer 440 by the light emitting surface 151S. This embodiment differs from the other embodiments described above in that a structure including a light emitting element 150 is formed on a substrate 402 made of an organic transparent resin and a color filter 180 is provided via the substrate 402. .. In other respects, it is the same as in the case of the other embodiments described above, and the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.

As shown in FIG. 27, the subpixel 420 of the image display device of the present embodiment includes a color filter 180, a substrate (light transmitting member) 402, a transistor 103, a first wiring layer 110, and a first interlayer insulation. It includes a film 112, a third wiring layer 440, a light emitting element 150, an electrode 165a, a second interlayer insulating film 156, a via 161d, and a second wiring layer 160.

The substrate 402 is a substrate having light transmission property, for example, a substrate made of transparent resin. Preferably, as in this example, the TFT underlayer film 106 is formed on the first surface 402a, which is one surface of the substrate 402. A color filter (wavelength conversion member) 180 is provided on the other surface (second surface) 402b of the substrate 402. In the present embodiment, the drive circuit unit 100 includes a substrate 402, a TFT lower layer film 106, a circuit 101, and a first interlayer insulating film 112. The configuration of the drive circuit unit 100 is the same as that of the first embodiment and the second embodiment except for the substrate 402, and detailed description thereof will be omitted.

The third wiring layer 440 is provided on the flattening surface 112F. The third wiring layer 440 includes the wiring 440a. The wiring 440a is provided between the light emitting element 150 and the flattening surface 112F. The third wiring layer 440 includes a plurality of wirings 440a depending on the plurality of light emitting elements 150, and in this example, each wiring 440a is separated.

The third wiring layer 440 is formed of a light-transmitting conductive film. The conductive film is, for example, a transparent conductive film such as ITO or ZnO. The wiring 440a is also made of the same material.

The third wiring layer 440 and the wiring 440a are in contact with the flattening surface 112F. The light emitting element 150 is in contact with the wiring 440a on the light emitting surface 151S and is electrically connected to the wiring 440a. The outer circumference of the wiring 440a is set to include the outer circumference of the light emitting element 150 when the light emitting element 150 is projected onto the wiring 440a in XY plan view. The wiring 440a is provided so as to project in one direction on the flattening surface 112F from directly below the light emitting surface 151S. One end of the via 161k is connected to the protruding region of the wiring 440a. The via 161k electrically connects the wiring 160k and the wiring 440a between the wiring 160k and the wiring 440a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 20 described above via the wiring 440a, the via 161k, and the wiring 160k.

The color filter 180 is provided on the other surface 402b of the substrate 402. The color filter 180 is the same as that described in the third embodiment. The color filter 180 may be in the form of a pasted film or may be formed by an inkjet method.

Other configurations are the same as in the case of the first embodiment, and detailed description thereof will be omitted.

A method of manufacturing the image display device of the present embodiment will be described.
28A to 30B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
As shown in FIG. 28A, the substrate 1195 is prepared. The substrate 1195 is the same as that shown in FIG. 8A. The substrate 1195 is formed by the steps shown in FIGS. 7A and 7B. A light-transmitting conductive layer 1440 is formed on the n-type semiconductor layer 1151 of the substrate 1195. The conductive layer 1440 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151.

As shown in FIG. 28B, the drive circuit unit 100 formed on the substrate 102 is prepared. The semiconductor layer 1150 is bonded to the flattening surface 112F of the drive circuit unit 100 via the conductive layer 1440. The support substrate 1190 is then removed by wet etching or laser lift-off.

As shown in FIG. 29A, the metal layer 1163 and the semiconductor layer 1150 shown in FIG. 28B are each processed into a predetermined shape by etching, and an electrode 165a and a light emitting element 150 are formed, respectively.

The conductive layer 1440 is processed into a shape including the wiring 440a, and a third wiring layer 440 is formed. The step of forming the third wiring layer 440 and the wiring 440a may be before or after the step of forming the electrode 165a and the light emitting element 150.

After that, the second interlayer insulating film 156 is formed as in the case of other embodiments. The second interlayer insulating film 156 covers the flattening surface 112F, the third wiring layer 440, the light emitting element 150, and the electrode 165a.

As shown in FIG. 29B, the vias 161d, 161k, the connecting portion 161a, and the second wiring layer 160 are formed on the second interlayer insulating film 156 in the same manner as in the other embodiments described above. The via 161k is provided between the wiring 160k and the wiring 440a, and electrically connects the wiring 160k and the wiring 440a.

As shown in FIG. 30A, the substrate 102 is removed using wet etching or laser lift-off. Before removing the substrate 102, a reinforcing substrate may be provided on the side of the second wiring layer 160 via an adhesive layer, as in the case of the third embodiment.

As shown in FIG. 30B, the color filter (wavelength conversion member) 180 is formed on the second surface 402b. The color filter 180 may be formed in a film format or an inkjet method.

In the present embodiment, instead of the organic transparent resin substrate 402, the glass substrate is thinned or the glass substrate is completely removed to form a surface from which the glass substrate has been removed, as in the case of the third embodiment. A color filter 180 may be provided.

The effect of the image display device of this embodiment will be described.
The image display device of the present embodiment has the effect of shortening the time of the transfer step for forming the light emitting element 150 and reducing the number of steps, as in the case of the other embodiments described above. ..

Since the third wiring layer 440 and the wiring 440a are formed of a light-transmitting conductive film such as ITO, they are easy to process, and a series of manufacturing steps of the light emitting element 150, the electrode 165a, and the third wiring layer 440. May be shortened.

In the present embodiment, since the electrode is pulled out on the light emitting surface 151S side by using the third wiring layer 440 and the wiring 440a, the vertical light emitting element 150 can be obtained. In the vertical light emitting element 150, the current flowing through the semiconductor layer can be made to be in the direction substantially along the Z axis by reducing the component in the direction along the XY plane, so that the loss in the semiconductor layer can be reduced. There is a merit that it can be done.

In this embodiment, since the substrate 402 is made of an organic transparent resin, it has flexibility. Therefore, the image display device 401 can be bent, and can be attached to a curved surface, used for a wearable terminal, or the like without any discomfort.

In the present embodiment, the image display device includes the color filter 180, but may be configured not to include the color filter as in the other embodiments described above.

(Fifth Embodiment)
FIG. 31 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
In this embodiment, the configuration of the light emitting element 550 is different from that of the other embodiments. Other components are the same as in the other embodiments described above. The same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
As shown in FIG. 32, the third wiring layer 440 includes wiring 540a. The third wiring layer 440 and the wiring 540a are in contact with the flattening surface 112F. The light emitting element 550 is in contact with the wiring 540a on the light emitting surface 551S and is electrically connected to the wiring 540a. The outer circumference of the wiring 540a is set to include the outer circumference of the light emitting element 550 when the light emitting element 550 is projected onto the wiring 540a in XY plan view. The wiring 540a is provided so as to project in one direction on the flattening surface 112F from directly below the light emitting surface 551S. One end of the via 161k is connected to the protruding region of the wiring 540a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 3 described above via the wiring 540a, the via 161k, and the wiring 160k.

In this embodiment, the light-shielding layer 330 is provided. The light-shielding layer 330 is the same as that described with reference to FIG. 19 in the third embodiment. The light-shielding layer 330 includes a light-shielding portion 330a. Preferably, the outer circumference of the light-shielding portion 330a is set to include the outer circumference of the TFT channel 104 when the TFT channel 104 is projected onto the light-shielding portion 330a in XY plan view. The light-shielding layer 330 is provided with through holes 331L and 331d. The through hole 331L is provided for an optical path, and the through hole 331d is provided for insulation from the via 161d.

The light emitting element 550 is provided on the wiring 540a. The light emitting element 550 is a pyramidal trapezoidal or truncated cone-shaped element formed so that the area in the XY plane view becomes smaller toward the positive direction of the Z axis.

FIG. 32 is an enlarged view of the light emitting element 550 portion of FIG. 31, and shows the detailed positional relationship between the flattening surface 112F and the light emitting element 550.
As shown in FIG. 32, the flattening surface 112F is a plane substantially parallel to the XY plane. The light emitting element 550 is provided on the flattening surface 112F, and the light emitting surface 551S is a surface substantially parallel to the flattening surface 112F. Wiring 540a is provided on the flattening surface 112F, and the light emitting surface 551S is provided on the flattening surface 112F via the wiring 540a. The thickness of the wiring 540a shall be sufficiently thin, and the reflection and absorption of light shall be sufficiently small.

The light emitting element 550 has a side surface 555a. The side surface 555a is a surface between the upper surface 555U and the flattening surface 112F, and is a surface adjacent to the light emitting surface 551S. The internal angle θ of the angle formed between the side surface 555a and the flattening surface 112F is smaller than 90 °. Preferably, the internal angle θ is about 70 °. More preferably, the internal angle θ is smaller than the critical angle on the side surface 555a determined based on the refractive index of the light emitting element 550 and the refractive index of the second interlayer insulating film 156. The light emitting element 550 is covered with the second interlayer insulating film 156, and the side surface 555a is in contact with the second interlayer insulating film 156.

The critical angle θc of the internal angle θ formed by the side surface 555a of the light emitting element 550 and the flattening surface 112F is determined as follows, for example.
Assuming that the refractive index n0 of the light emitting element 550 and the refractive index n1 of the second interlayer insulating film 156, the critical angle θc of the light emitted from the light emitting element 550 to the second interlayer insulating film 156 is determined by using the following equation (1). Desired.

θc = 90 ° -sin ^-1 (n1 / n0) (1)

For example, it is known that the refractive index of a general transparent organic insulating material such as acrylic resin is around 1.4 to 1.5. Therefore, when the light emitting element 550 is formed of GaN and the second interlayer insulating film 156 is formed of a general transparent organic insulating material, the refractive index of the light emitting element 550 is n0 = 2.5, and the second interlayer insulation is provided. The refractive index of the film 156 can be n = 1.4. By substituting these values into the equation (1), the critical angle θc = 56 ° is obtained.

This means that when the internal angle θ formed by the flattening surface 112F and the side surface 555a is θc = 56 °, the light emitted from the light emitting layer 552 that is parallel to the flattening surface 112F is all on the side surface 555a. It shows that it is reflected. Further, it is shown that among the light emitted from the light emitting layer 552, the light having a component in the positive direction of the Z axis is also totally reflected by the side surface 555a. In the above, for the sake of simplicity, the second interlayer insulating film 156 is made of a transparent resin, but even when the transparent resin is made of white resin, the influence on the refractive index of the scattering fine particles due to the white resin is small. , Ignored in the above calculation.

On the other hand, among the light emitted from the light emitting layer 552, the light having a component in the negative direction of the Z axis is emitted from the side surface 555a at an emission angle corresponding to the refractive index on the side surface 555a. The light incident on the second interlayer insulating film 156 is emitted from the second interlayer insulating film 156 at an angle determined by the refractive index of the second interlayer insulating film 156.

The light totally reflected by the side surface 555a is reflected again by the electrode 565a having light reflectivity, and the light having a negative component in the Z axis of the light reflected again is emitted from the light emitting surface 551S and the side surface 555a. Ru. Light parallel to the flattening surface 112F and light having a component in the positive direction of the Z axis are totally reflected by the side surface 555a.

In this way, among the light emitted from the light emitting layer 552, the light parallel to the flattening surface 112F and the light having a component in the positive direction of the Z axis are in the negative direction of the Z axis by the side surface 555a and the electrode 565a. It is converted to light with a heading component. Therefore, in the light emitted from the light emitting element 550, the ratio toward the light emitting surface 551S increases, and the substantial luminous efficiency of the light emitting element 550 is improved.

By setting θ <θc, most of the light having a component parallel to the flattening surface 112F can be totally reflected in the light emitting element 550. Assuming that the refractive index of the second interlayer insulating film 156 is n = 1.4, the critical angle θc is about 56 °, so that the set internal angle θ is more preferably 45 °, 30 °, or the like. Further, the critical angle θc becomes smaller in the material having a larger refractive index n. However, even if the internal angle θ is set to about 70 °, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis. Then, for example, the internal angle θ may be set to 80 ° or less.

A method of manufacturing the image display device of the present embodiment will be described.
In the present embodiment, the manufacturing process of the light emitting element 550 and the electrode 565a is different from the case of the other embodiment, and the other manufacturing process can be applied to the case of the other embodiment described above. In the following, the different parts of the manufacturing process will be described.
In this embodiment, the following steps are executed in order to obtain the shape of the light emitting element 550 shown in FIG. 32.
The semiconductor layer 1150 shown in FIG. 28B is bonded to the flattening surface 112F and then processed by etching into the shape of the light emitting device 550 shown in FIG. 31. For molding the light emitting element 550, the etching rate is selected so that the side surface 555a shown in FIG. 32 forms an internal angle θ with respect to the flattening surface 112F. For example, for etching, a higher etching rate is selected as it is closer to the upper surface 553U. Preferably, the etching rate is set to increase linearly from the side of the light emitting surface 551S toward the side of the upper surface 553U.

Specifically, for example, the resist mask pattern at the time of dry etching is devised at the time of exposure so that it gradually becomes thinner toward the end portion. As a result, the etching amount can be gradually increased from the light emitting surface 551S toward the upper surface 553U by gradually retreating from the thin portion of the resist during dry etching. As a result, the side surface 555a of the light emitting element 550 is formed so as to form a constant angle with respect to the flattening surface 112F. Therefore, in the light emitting element 550, the area of each layer from the upper surface 553U in XY flat view is formed so that the area of the p-type semiconductor layer 553, the light emitting layer 552, and the n-type semiconductor layer 551 increases in this order.

Then, as in the other embodiments, the subpixel 520 is formed.

The effect of the image display device of this embodiment will be described.
The image display device of the present embodiment has the effect of shortening the time of the transfer step for forming the light emitting element 550 and reducing the number of steps, similarly to the image display device of the other embodiments described above. In addition, it has the following effects.
In the image display device of the present embodiment, the light emitting element 550 is formed so as to have a side surface 555a forming an internal angle θ with respect to the flattened surface 112F provided with the light emitting element 550. The internal angle θ is smaller than 90 ° and is set based on the critical angle θc determined by the refractive index of each material of the light emitting element 550 and the second interlayer insulating film 156. The internal angle θ can convert the light emitted from the light emitting layer 552 toward the side or the upper side of the light emitting element 550 into the light toward the light emitting surface 551S side and emit the light. By sufficiently reducing the internal angle θ, the luminous efficiency of the light emitting element 550 is substantially improved.

In the present embodiment, the light emitting element 550 is a vertical element and is connected to the via 161k by using the third wiring layer 440. Not limited to this, the light emitting element may be provided with a connecting portion formed on the flattening surface 112F and may be connected to the via 161k via the connecting portion.

(Sixth Embodiment)
FIG. 33 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
The present embodiment differs from the other embodiments in that the image display device includes a subpixel group 620 including a plurality of light emitting regions on one light emitting surface. The same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
As shown in FIG. 33, the image display device of the present embodiment includes a subpixel group 620. The subpixel group 620 includes a substrate 102, a plurality of transistors 103-1 and 103-2, a first wiring layer 110, a first interlayer insulating film 112, a semiconductor layer 650, and electrodes 660a1 having light reflectivity. 660a2, a second interlayer insulating film 156, and vias 661d1 and 661d2 are included. The semiconductor layer 650 is provided on the flattening surface 112F.

In this embodiment, by turning on the transistors 103-1 and 103-2 of the p-channel, holes are injected from one of the semiconductor layers 650 via the first wiring layer 110 and the vias 661d1 and 661d2. By turning on the transistors 103-1 and 103-2 of the p-channel, electrons are injected from the other side of the semiconductor layer 650 via the second wiring layer 160. Holes and electrons are injected into the semiconductor layer 650, and the separated light emitting layers 652a1 and 652a2 emit light due to the bonding of holes and electrons. As the drive circuit for driving the light emitting layers 652a1 and 652a2, for example, the circuit configuration shown in FIG. 2 is applied. Using the example of the second embodiment, the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer can be interchanged to drive the semiconductor layer with n-channel transistors. In that case, the circuit configuration of FIG. 13 is applied to the drive circuit.

The configuration of the subpixel group 620 will be described in detail.

The TFT underlayer film 106 is formed on the first surface 102a. The TFT underlayer film 106 is flattened, and TFT channels 104-1, 104-2, etc. are formed on the TFT underlayer film 106.

The insulating layer 105 covers the TFT underlayer film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. Transistor 103-1 includes a TFT channel 104-1 and a gate 107-1. Transistor 103-2 includes TFT channel 104-2 and gate 107-2.

The TFT channel 104-1 contains a p-shaped doped region 104s1,104d1, and the region 104s1,104d1 is a source region and a drain region of the transistor 103-1. The region 104i1 is doped in an n-shape and forms a channel of the transistor 103-1. Similarly, the TFT channel 104-2 includes a p-shaped doped region 104s2, 104d2, and the region 104s2, 104d2 is a source region and a drain region of the transistor 103-2. The region 104i2 is doped in the n form and forms the channel of the transistor 103-2.

The insulating film 108 covers the insulating layer 105 and the gates 107-1 and 107-2. In the present embodiment, the circuit 101 includes TFT channels 104-1 and 104-2, an insulating layer 105, an insulating film 108, vias 111s1,111d1,111s2,111d2, and a first wiring layer 110.

The first wiring layer 110 is provided on the insulating film 108. The first wiring layer 110 includes wirings 610f, 610s1, 610s2, 610d1, 610d2.

The wiring (second portion) 610f is provided between the light emitting regions 651R1 and 651R2. The wiring 610f is not electrically connected to any of the circuit elements illustrated in FIG. 33 in this example, but can be connected to any potential or circuit element. The wiring 610f is arranged between the light emitting regions 651R1 and 651R2 to shield the light emitted from each of the light emitting regions 651R1 and 651R2.

The wiring 610s1 is provided above the area 104s1. The via 111s1 is provided between the wiring 610s1 and the region 104s1, and electrically connects the wiring 610s1 and the region 104s1. The wiring 610s2 is provided above the area 104s2. The via 111s2 is provided between the wiring 610s2 and the area 104s2, and electrically connects the wiring 610s2 and the area 104s2. The wirings 610s1 and 610s2 are connected to, for example, the power line 3 of the circuit shown in FIG.

The wiring 610d1 is provided above the area 104d1. The via 111d1 is provided between the wiring 610d1 and the area 104d1, and electrically connects the wiring 610d1 and the area 104d1. The wiring 610d1 is connected to one end of the via 661d1. The wiring 610d2 is provided above the area 104d2. The via 111d2 is provided between the wiring 610d2 and the area 104d2, and electrically connects the wiring 610d2 and the area 104d2. The wiring 610d2 is connected to one end of the via 661d2.

The first interlayer insulating film 112 is provided so as to cover the insulating film 108 and the first wiring layer 110. The first interlayer insulating film 112 has a flattening surface 112F.

The semiconductor layer 650 has a light emitting surface 651S in contact with the flattening surface 112F. The light emitting surface 651S is a surface of the n-type semiconductor layer 651. The light emitting surface 651S includes a plurality of light emitting regions 651R1 and 651R2.

The semiconductor layer 650 includes an n-type semiconductor layer 651, a light emitting layer 652a1,652a2, and a p-type semiconductor layer 653a1, 653a2. The light emitting layer 652a1 is provided on the n-type semiconductor layer 651. The light emitting layer 652a2 is separated from and separated from the light emitting layer 652a1 and is provided on the n-type semiconductor layer 651. The p-type semiconductor layer 653a1 is provided on the light emitting layer 652a1. The p-type semiconductor layer 653a2 is provided on the light emitting layer 652a2 separately from and separated from the p-type semiconductor layer 653a1.

The p-type semiconductor layer 653a1 has an upper surface 653U1 provided so as to face the surface on which the light emitting layer 652a1 is provided. The p-type semiconductor layer 653a2 has an upper surface 653U2 provided so as to face the surface on which the light emitting layer 652a2 is provided.

The light emitting region 651R1 is a region of the light emitting surface 651S that substantially coincides with the region facing the upper surface 653U1. The light emitting region 651R2 is a region of the light emitting surface 651S that substantially coincides with the region facing the upper surface 653U2.

FIG. 34 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
FIG. 34 is a schematic diagram for explaining the light emitting regions 651R1 and 651R2.
As shown in FIG. 34, the light emitting regions 651R1 and 651R2 are surfaces on the light emitting surface 651S. In FIG. 34, the portions of the semiconductor layer 650 including the light emitting regions 651R1 and 651R2 are referred to as light emitting units R1 and R2, respectively. The light emitting unit R1 includes a part of the n-type semiconductor layer 651, a light emitting layer 652a1 and a p-type semiconductor layer 653a1. The light emitting unit R2 includes a part of the n-type semiconductor layer 651, a light emitting layer 652a2, and a p-type semiconductor layer 653a2.

The semiconductor layer 650 includes a connection portion R0. The connecting portion R0 is provided between the light emitting portions R1 and R2, and is a part of the n-type semiconductor layer 651. One end of the via 661k shown in FIG. 33 is connected to the connecting portion R0 to provide a current path between the light emitting portions R1 and R2.

In the light emitting unit R1, the electrons supplied via the connection unit R0 are supplied to the light emitting layer 652a1. In the light emitting unit R1, the holes supplied through the electrode 660a1 are supplied to the light emitting layer 652a1. The electrons and holes supplied to the light emitting layer 652a1 are combined and emit light. The light emitted by the light emitting layer 652a1 reaches the light emitting surface 651S through the portion of the n-type semiconductor layer 651 of the light emitting unit R1. Since the light travels substantially straight in the light emitting portion R1 along the Z-axis direction, the light emitted from the light emitting surface 651S is the light emitting region 651R1. Therefore, in this example, the light emitting region 651R1 substantially coincides with the region surrounded by the outer periphery of the light emitting layer 652a1 projected on the light emitting surface 651S in XY plan view.

The light emitting unit R2 is the same as the light emitting unit R1. That is, in the light emitting unit R2, the electrons supplied via the connecting unit R0 are supplied to the light emitting layer 652a2. In the light emitting unit R2, the holes supplied through the electrodes 660a2 are supplied to the light emitting layer 652a2. The electrons and holes supplied to the light emitting layer 652a2 are combined and emit light. The light emitted by the light emitting layer 652a2 reaches the light emitting surface 651S through the portion of the n-type semiconductor layer 651 of the light emitting portion R2. Since the light travels substantially straight in the light emitting portion R2 along the Z-axis direction, the light emitted from the light emitting surface 651S is the light emitting region 651R2. Therefore, in this example, the light emitting region 651R2 substantially coincides with the region surrounded by the outer periphery of the light emitting layer 652a2 projected on the light emitting surface 651S in the XY plan view.

In this way, the semiconductor layer 650 can share the n-type semiconductor layer 651 to form a plurality of light emitting regions 651R1 and 651R2 on the light emitting surface 651S.

In the present embodiment, the semiconductor layer 650 is formed by forming a part of the n-type semiconductor layer 651 as a connecting portion R0 in the plurality of light emitting layers 652a1,652a2 and the plurality of p-type semiconductor layers 653a1, 653a2 of the semiconductor layer 650. can do. Therefore, the semiconductor layer 650 can be formed in the same manner as the method for forming the light emitting devices 150 and 250 in the case of the first embodiment and the second embodiment described above.

Returning to FIG. 33, the description will be continued.
The second interlayer insulating film 156 is provided on the flattening surface 112F, the semiconductor layer 650, and the electrodes 660a1, 660a2.

The second wiring layer 160 is provided on the second interlayer insulating film 156. The second wiring layer 160 includes wirings 660d1, 660d2, 660k. The wiring 660d1 is connected to the electrode 660a1 via the connecting portion 661a1. The wiring 660d2 is connected to the electrode 660a2 via the connecting portion 661a2. The wiring 660k is connected to, for example, the ground wire 4 of the circuit of FIG.

The via 661d1 is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 610d1. The via 661d1 is provided between the wiring 660d1 and the wiring 610d1, and electrically connects the wiring 660d1 and the wiring 610d1. The via 661d2 is provided so as to penetrate the second interlayer insulating film 156 and the first interlayer insulating film 112 and reach the wiring 610d2. The via 661d2 is provided between the wiring 660d2 and the wiring 610d2, and electrically connects the wiring 660d2 and the wiring 610d2.

The via 661k is provided so as to penetrate the second interlayer insulating film 156 and reach the n-type semiconductor layer 651. The via 661k electrically connects the wiring 660k and the n-type semiconductor layer 651 between the wiring 660k and the n-type semiconductor layer 651.

For example, transistors 103-1 and 103-2 are driving transistors of adjacent subpixels and are driven sequentially. When the holes supplied from the transistor 103-1 are injected into the light emitting layer 652a1 and the electrons supplied from the wiring 660k are injected into the light emitting layer 652a1, the light emitting layer 652a1 emits light and light is emitted from the light emitting region 651R1. To. When the holes supplied from the transistor 103-2 are injected into the light emitting layer 652a2 and the electrons supplied from the wiring 660k are injected into the light emitting layer 652a2, the light emitting layer 652a2 emits light and light is emitted from the light emitting region 651R2. To.

The effect of the image display device of this embodiment will be described.
The image display device of the present embodiment has the effect that the time of the transfer step for forming the semiconductor layer 650 can be shortened and the number of steps can be reduced, similarly to the image display device of the other embodiments described above. Play. In addition, since the connection unit R0 can be shared by the plurality of light emitting units R1 and R2, the number of vias 661k provided in the connection unit R0 can be reduced. By reducing the number of vias, it becomes possible to reduce the pitch of the light emitting units R1 and R2 constituting the sub-pixel group 620, and it becomes possible to make a small-sized, high-definition image display device.

In the present embodiment, the light emitting regions 651R1 and 651R2 need to pass through the first interlayer insulating film 112, the insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the substrate 102 before the emitted light is emitted to the outside. There is. Therefore, it is conceivable that the light spreads along the path until it is radiated to the outside. In the present embodiment, since the wiring 610f is provided in the middle of the path until the light is radiated to the outside, the light emitted from the adjacent pixels is prevented from being mixed by blocking the spreading light. .. Therefore, it is possible to realize a high-quality image display device by narrowing the pixel pitch. In this example, the case of two light emitting regions has been described, but the number of light emitting regions formed on the light emitting surface is not limited to two, and may be any number of three or more.

(7th Embodiment)
The image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.

FIG. 35 is a block diagram illustrating an image display device according to the present embodiment.
FIG. 35 shows the main parts of the configuration of a computer display.
As shown in FIG. 35, the image display device 701 includes an image display module 702. The image display module 702 is, for example, an image display device having the configuration of the first embodiment described above. The image display module 702 includes a display area 2, a row selection circuit 5, and a signal voltage output circuit 7 in which a plurality of subpixels including the subpixel 20 are arranged.

The image display device 701 further includes a controller 770. The controller 770 inputs a control signal separated and generated by an interface circuit (not shown) to control the drive and drive order of each subpixel to the row selection circuit 5 and the signal voltage output circuit 7.

(Modification example)
The image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.

FIG. 36 is a block diagram illustrating an image display device according to a modified example of the present embodiment.
FIG. 36 shows the configuration of a high-definition flat-screen television.
As shown in FIG. 36, the image display device 801 includes an image display module 802. The image display module 802 is, for example, an image display device 1 having the configuration of the first embodiment described above. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the drive order of each subpixel in the display area 2 based on the control signal supplied by the bus 840. The frame memory 880 stores display data for one frame and is used for processing such as smooth moving image reproduction.

The image display device 801 has an I / O circuit 810. The I / O circuit 810 is simply referred to as "I / O" in FIG. The I / O circuit 810 provides an interface circuit or the like for connecting to an external terminal, a device, or the like. The I / O circuit 810 includes, for example, a USB interface for connecting an external hard disk device or the like, an audio interface, or the like.

The image display device 801 has a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to the receiving unit 820, and a necessary signal is separated and generated from the radio wave received by the antenna 822. The signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 820 is converted into image data, audio data, etc. by the signal processing unit 830. Separated and generated.

By using the receiving unit 820 and the signal processing unit 830 as high-frequency communication modules for transmitting and receiving mobile phones, for WiFi, and for GPS receivers, other image display devices can also be used. For example, an image display device provided with an image display module having an appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.

The image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, and may be a modification thereof or the case of another embodiment. As shown in FIGS. 9 and 26, the image display module in the case of the present embodiment and the modified example is configured to include a large number of subpixels.

According to the embodiment described above, it is possible to realize a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved.

Although some embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention and its equivalents described in the claims. In addition, each of the above-described embodiments can be implemented in combination with each other.

1,201,301,701,801 Image display device, 2 display area, 3 power supply line, 4 ground line, 5,205 line selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8,208 signal Line, 10 pixels, 20,220,320,420,520 subpixels, 22,222 light emitting elements, 24,224 selection transistors, 26,226 drive transistors, 28,228 capacitors, 100 drive circuits, 101 circuits, 102, 402 Substrate, 103a, 180a, 402a First surface, 103,103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulation layer, 107,107-1,107 -2 Gate, 108 Insulation film, 110 1st wiring layer, 112 1st interlayer insulation film, 150, 250, 550 light emitting element, 151S, 151S1,253S, 551S, 651S light emitting surface, 156th second interlayer insulating film, 165a, 265k, 565a, 660a1, 660a2 electrode, 161d, 161k, 661k via, 172 light emitting circuit part, 180 color filter, 620 subpixel group, 661a1,661a2 connection part, 1001 crystal growth substrate, 1150 semiconductor layer, 1161,1162 1163, 1164 Metal layer, 1180 Reinforcing substrate, 1190 Support substrate, 1192 structure, 1194, 1294 Semiconductor growth substrate

Claims (24)

A first including a circuit element formed on the first surface of the translucent substrate, a first wiring layer connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer. 1 The process of preparing the board and
The process of preparing the semiconductor layer including the light emitting layer and
A step of joining the semiconductor layer to the second substrate via the first metal layer,
The step of bonding the semiconductor layer to the first substrate and
The process of removing the second substrate and
A step of etching the semiconductor layer to form a light emitting element including a light emitting surface on the first insulating film and an upper surface provided facing the light emitting surface.
A step of etching the first metal layer to cover the upper surface and form an electrode electrically connected to the upper surface.
A step of forming the first insulating film, the light emitting element, and the second insulating film covering the electrodes.
The step of forming the first insulating film and the first via penetrating the second insulating film, and
The step of forming the second wiring layer on the second insulating film and
Equipped with
The first via is provided between the first wiring layer and the second wiring layer, and is a method for manufacturing an image display device that electrically connects the first wiring layer and the second wiring layer. The method for manufacturing an image display device according to claim 1, wherein the step of preparing the semiconductor layer includes a step of forming the first metal layer on the semiconductor layer after forming the semiconductor layer. The method for manufacturing an image display device according to claim 1, further comprising a step of forming the first metal layer on a joining surface of the second substrate before the step of joining the semiconductor layers. A first including a circuit element formed on the first surface of the translucent substrate, a first wiring layer connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer. 1 The process of preparing the board and
The process of preparing the semiconductor layer including the light emitting layer and
The step of bonding the semiconductor layer to the first substrate and
After the step of bonding the semiconductor layers, a step of forming a second metal layer on the semiconductor layer and a step of forming the second metal layer.
A step of etching the semiconductor layer to form a light emitting element including a light emitting surface on the first insulating film and an upper surface facing the light emitting surface.
A step of etching the second metal layer to cover the upper surface and form an electrode electrically connected to the upper surface.
A step of forming the first insulating film, the light emitting element, and the second insulating film covering the electrodes.
The step of forming the first insulating film and the first via penetrating the second insulating film, and
The step of forming the second wiring layer on the second insulating film and
Equipped with
The first via is provided between the first wiring layer and the second wiring layer, and is a method for manufacturing an image display device that electrically connects the first wiring layer and the second wiring layer. Claims 1 to 4 further include a step of roughening the exposed surface of the semiconductor layer and forming a film having light transmission over the roughened surface before the step of laminating the semiconductor layers. The method for manufacturing an image display device according to any one of them. A step of forming a second via penetrating the second insulating film is further provided.
The light emitting element includes a connection portion formed on the first insulating film.
The second via is provided between the second wiring layer and the connection portion, and according to any one of claims 1 to 5, the second wiring layer and the connection portion are electrically connected to each other. How to manufacture an image display device. Before the step of bonding the semiconductor layer to the first substrate, a step of forming a light-transmitting conductive layer on the semiconductor layer and a step of forming the conductive layer.
After the step of bonding the semiconductor layer to the first substrate, the step of etching the conductive layer to form the third wiring layer, and the step of forming the third wiring layer.
The method for manufacturing an image display device according to any one of claims 1 to 4, further comprising. A step of forming a second via penetrating the second insulating film is further provided.
The image display device according to claim 7, wherein the second via is provided between the second wiring layer and the third wiring layer, and electrically connects the second wiring layer and the third wiring layer. Manufacturing method. The method for manufacturing an image display device according to any one of claims 1 to 8, wherein the step of preparing the first substrate includes a step of forming a light-shielding layer covering the circuit element. The method for manufacturing an image display device according to any one of claims 1 to 9, wherein the semiconductor layer includes a gallium nitride based compound semiconductor. The method for manufacturing an image display device according to any one of claims 1 to 10, further comprising a step of forming a wavelength conversion member on the second surface facing the first surface. The method for manufacturing an image display device according to any one of claims 1 to 10, further comprising a step of removing the translucent substrate and forming a wavelength conversion member in place of the translucent substrate. A light transmissive member having a first surface and
The circuit element provided on the first surface and
The first wiring layer electrically connected to the circuit element and
A first insulating film covering the first surface, the circuit element, and the first wiring layer,
A light emitting element including a light emitting surface and an upper surface facing the light emitting surface on the first insulating film.
An electrode that covers the upper surface and is electrically connected to the upper surface,
The first insulating film, the light emitting element, and the second insulating film covering the electrodes.
The first via provided through the first insulating film and the second insulating film, and
The second wiring layer provided on the second insulating film and
Equipped with
The first via is an image display device provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer. Further, a second via provided so as to penetrate the second insulating film is provided.
The light emitting element includes a connection portion formed on the first insulating film.
The second wiring layer includes a first wiring and a second wiring separated from the first wiring.
The first via is provided between the first wiring and the first wiring layer, and electrically connects the first wiring and the first wiring layer.
The image display device according to claim 13, wherein the second via is provided between the second wiring and the connection portion, and electrically connects the second wiring and the connection portion. The image display device according to claim 13 or 14, wherein the light emitting surface is roughened. A third wiring layer having light transmittance provided between the first insulating film and the light emitting surface,
The second via provided through the second insulating film and
Further prepare
The second wiring layer includes a first wiring and a second wiring separated from the first wiring.
The first via is provided between the first wiring and the first wiring layer, and electrically connects the first wiring and the first wiring layer.
The image display device according to claim 13, wherein the second via is provided between the second wiring and the third wiring layer, and electrically connects the second wiring and the third wiring layer. The image display device according to claim 16, wherein the angle formed by the light emitting surface and the side surface of the light emitting element is smaller than 90 °. The image display device according to any one of claims 13 to 17, wherein the first wiring layer includes a first portion that covers the circuit element. The light-shielding layer provided on the first insulating film and
A third insulating film provided between the light-shielding layer and the second insulating film,
The image display device according to any one of claims 13 to 18, further comprising. The image display device according to any one of claims 13 to 19, wherein the light emitting device includes a gallium nitride based compound semiconductor. The image display device according to any one of claims 13 to 20, further comprising a wavelength conversion member provided on the second surface facing the first surface. A light transmissive member having a first surface and
A plurality of transistors provided on the first surface and
A first wiring layer electrically connected to the plurality of transistors,
A first insulating film covering the first surface, the plurality of transistors, and the first wiring layer.
A first semiconductor layer including a light emitting surface capable of forming a plurality of light emitting regions on the first insulating film,
A plurality of light emitting layers provided on the first semiconductor layer, and
A plurality of second semiconductor layers provided on the plurality of light emitting layers and having a conductive shape different from that of the first semiconductor layer, and a plurality of second semiconductor layers.
A plurality of electrodes provided on the plurality of second semiconductor layers and electrically connected to the plurality of second semiconductor layers, and a plurality of electrodes.
The first insulating film, the first semiconductor layer, the plurality of light emitting layers, the plurality of second semiconductor layers, and the second insulating film covering the plurality of electrodes.
A plurality of first vias provided through the first insulating film and the second insulating film, and
The second wiring layer provided on the second insulating film and
Equipped with
The plurality of second semiconductor layers, the plurality of light emitting layers, and the plurality of electrodes are separated by the second insulating film.
The plurality of first vias are provided between the first wiring layer and the second wiring layer, and are an image display device that electrically connects the first wiring layer and the second wiring layer. The plurality of light emitting regions are formed according to the positions of the plurality of light emitting layers in a plan view.
The image display device according to claim 21, wherein the first wiring layer includes a second portion provided between light emitting regions formed adjacent to each other among the plurality of light emitting regions. A light transmissive member having a first surface and
The circuit element provided on the first surface and
The first wiring layer electrically connected to the circuit element and
A first insulating film covering the first surface, the circuit element, and the first wiring layer,
A plurality of light emitting elements including a light emitting surface and an upper surface facing the light emitting surface on the first insulating film, and
A plurality of electrodes that cover the upper surface and are electrically connected to the upper surface,
The first insulating film, the plurality of light emitting elements, and the second insulating film covering the plurality of electrodes.
The first via provided through the first insulating film and the second insulating film, and
The second wiring layer provided on the second insulating film and
Equipped with
The first via is an image display device provided between the first wiring layer and the second wiring layer, and electrically connects the first wiring layer and the second wiring layer.

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