JP2022042183A - Memory device, video server, broadcasting system, and memory access control method - Google Patents

Abstract

To improve a throughput of a memory access.SOLUTION: According to an embodiment of the present invention, a memory device has a plurality of memory storage units. Each of the plurality of memory storage units has a memory chip capable of being accessed by a page unit, and a memory controller. The memory chip is connected to a common bus line in each area. The memory controller controls access to the memory chip by a unit of the area formed of the plurality of memory chips connected to different bus lines. The memory controller has an access control unit. The access control unit processes the access to the memory chip in parallel with switching the area by a page unit.SELECTED DRAWING: Figure 5

Description

Embodiments of the present invention relate to a memory device, a video server, a broadcasting system, and a memory access control method.

It is essential that the video server (sending server) can reproduce video and audio in real time in synchronization with a video frame of 33 msec. Therefore, a non-volatile memory is used as a data storage medium. Non-volatile memory represented by NAND Flash is becoming smaller and more integrated with intensifying competition among semiconductor manufacturers. However, if the storage capacity is increased and the cost is reduced by miniaturization, processing such as read retry is required to ensure reliability. Therefore, memory access (Read / Write / Erase) takes time, and speed is sacrificed.

Japanese Unexamined Patent Publication No. 2018-128963 Japanese Unexamined Patent Publication No. 2012-253733 Japanese Unexamined Patent Publication No. 2015-114856

In the 4K / 8K era that has already arrived, the bit rate (size) per content material is much higher than that of the conventional 2K material. Further increase in capacity of the video server is required, but if the memory access time becomes long, the video frame time is compressed, and there is a possibility that the specifications of the device such as the number of playback channels cannot be guaranteed. Therefore, there is a demand for a technique capable of improving throughput without sacrificing storage capacity.

An object of the present invention is to provide a memory device, a video server, a broadcasting system, and a memory access control method with improved throughput.

According to the embodiment, the memory device includes a plurality of memory storage units. Each of the plurality of memory storage units includes a memory chip that can be accessed on a page-by-page basis and a memory controller. The memory chip is connected to a common bus line in each area. The memory controller controls access to the memory chips using the above area consisting of a plurality of memory chips connected to different bus lines as a processing unit. The memory controller includes an access control unit. The access control unit processes access to the memory chip in parallel by switching areas on a page-by-page basis.

FIG. 1 is a diagram for explaining an area. FIG. 2 is a sequence chart showing a known example of processing timing between areas. FIG. 3 is a diagram showing a pipeline of processes in the sequence shown in FIG. FIG. 4 is a functional block diagram showing an example of a video server according to an embodiment. FIG. 5 is a block diagram showing an example of the memory storage unit 100. FIG. 6 is a diagram for explaining switching of areas on a page-by-page basis in an embodiment. FIG. 7 is a sequence chart showing an example of processing timing between areas in the embodiment.

In the storage using the non-volatile memory, the processing speed can be improved by operating a plurality of non-volatile memories in parallel. In order to increase the storage capacity, it is possible to cope with it by providing a plurality of processing units (referred to as "areas") composed of a plurality of non-volatile memories mounted in parallel.

FIG. 1 is a diagram for explaining an area. The storage shown in FIG. 1 includes four areas as an example, and each area has eight memories. The operation of the storage is controlled by the memory controller.

When operating memories in parallel for each area, increasing the number of memories per area is the key to speeding up. However, the cost and size increase by the number of increased memories, and the power consumption also increases. In addition, memory controller constraints also have a significant effect. That is, in order to increase the number of memories per area, the bus width (control / address / data) of the memory controller must be increased. However, since there is an upper limit to the number of buses (number of pins) of devices such as FPGAs (Field Programmable Gate Arrays), they are bound by the restrictions.

FIG. 2 is a sequence chart showing an example of processing timing between areas in the configuration of FIG. 1. If the memory shown in FIG. 1 is, for example, a NAND flash type, the write / read process is in NAND page units. However, in the parallel operation, since the same memory in the area is continuously processed, the processing of the next page cannot be started until the processing of one page is completed.

In FIG. 2, C is the time required to issue a command, and T is the period required to transfer data from the I / O register (not shown) or the latch circuit to the memory cell. A memory cell is a minimum unit of a storage element constituting a memory chip MC. BUSY is a busy period required for the operation of the memory, and after that, a status check period S for confirming (verifying) whether the data is correctly written to the memory element is provided.

With the existing technology shown in FIG. 2, the control process to the next page can be performed only after the C, T, BUSY, and S processes are executed in order. That is, since the plurality of chips in the area are processed in parallel but the pages are sequentially processed, the pipeline (FIG. 3) is not efficient and there is a limit to the speedup. The technology that makes it possible to deal with such a situation will be described below.

FIG. 4 is a functional block diagram showing an example of a video server according to an embodiment. The video server 10 provided in the broadcasting system 1 sends broadcast contents to the broadcasting equipment 6. This broadcast content is monitored by the monitor device 7.

The video server 10 includes an input unit 11, a memory device 12, an output unit 13, and a control unit 14. Of these, the control unit 14 is a processor such as a CPU (Central Processing Unit), and receives a user operation given from the operation terminal 2.

The input unit 11 is provided so as to be connectable to a transmission device such as a camera device 3, a playback device 4, and an editing device 5. The input unit 11 acquires broadcast content data from the transmission device. The various acquired data are written to the memory device 12 and read out. The read content data is transmitted to the broadcasting equipment 6 via the output unit 13.

Content data includes video data, audio data, and metadata associated with these data. Content data is often exchanged in the MXF (Material eXchange Format) file format, but it can also be exchanged in the SDI (Serial Digital Interface) format.

The memory device 12 stores content data under the control of the control unit 14. The memory device 12 includes a plurality of memory storage units 100 and a memory management unit 120 that manages the memory storage unit 100. For example, the memory management unit 120 adds error correction data such as a Reed-Solomon code to the content data input to the memory device 12, and stores it in any of the memory storage units 100. Further, the memory management unit 120 reads the data stored in the memory storage unit 100 and outputs the read content data to the output unit 13.

FIG. 5 is a block diagram showing an example of the memory storage unit 100. The memory storage unit 100 includes a plurality of memory chip MCs and a memory controller 101 that controls writing / reading / erasing to each memory chip MC. Each memory chip MC is connected to the memory controller 101 via the bus line BL and the control bus CB.

Here, the memory storage unit 100 is a non-volatile memory typified by a NAND flash memory that can be accessed on a page-by-page basis. In addition to the SLC (Single Level Cell) type memory chip, an MLC (Multi Level Cell), a TLC (Tri Level Cell), or a higher multi-level cell can also be used.

The bus line BL has a function as a data bus and an address bus. That is, the bus line BL is shared by data transfer / address designation. In the address specification, the bus line BL specifies the address of the memory chip MC to be accessed. In data transfer, the bus line BL transfers data for writing to the specified address or data read from the specified address. The control bus CB outputs signals such as a chip select signal and a read / write signal in synchronization with the synchronization signal 102 given to the memory controller 101 from the clock generator (not shown).

In the embodiment, each memory chip MC belongs to any of areas A1 to A4. An area is a unit consisting of a group of memory chip MCs connected to different bus lines. In some cases, a unit consisting of a group of memory chips connected to the same bus line is referred to as an area, but in this embodiment, an area different from such a case will be described. In the embodiment, four areas are assumed, but the same argument as below holds for a memory storage unit including eight areas or a number of other areas.

The memory controller 101 is an integrated circuit such as an FPGA (Field Programmable Gate Array), and controls writing / reading / erasing to each memory chip MC based on the address signal 103 and the data signal 104 from the memory management unit 120. do. The memory controller 101 controls access to such a memory chip MC in units of areas.

By the way, the memory controller 101 includes an access control unit 101a as a processing function that is written in advance in the FPGA and can be implemented as software. The access control unit 101a processes access to the memory chip MC in parallel by switching areas on a page-by-page basis. That is, the access control unit 101a performs access processing in parallel while sequentially switching areas for each page of the memory chip MC.

As shown in FIG. 6, if the number of areas is 4, the access control unit 101a issues a processing command for area A2 after issuing a processing command for area A1, which is the first area (1). ), After issuing the processing command of the area A2, the processing command of the area A3 is issued (2). Then, when the processing command to the area A4 is issued (3), the access control unit 101a returns the processing target to the area A1 again and issues the processing command to the area A1 (4). In this way, the access control unit 101a realizes parallel processing between areas by performing processing while switching areas on a page-by-page basis.

FIG. 7 is a sequence chart showing an example of processing timing between areas in the embodiment. FIG. 7 shows a sequence during the writing process. In FIG. 7, the memory controller 101 executes a processing sequence in the following order.

(S1) A write command is issued to all memory chip MCs in the area A1.
(S2) A write command is issued to all memory chip MCs in the area A2.
(S3) A write command is issued to all memory chip MCs in the area A3.
(S4) A write command is issued to all memory chip MCs in the area A4.
(S5) When the write process by the write command issued in (S1) is completed (when the status check is completed), the write command on the next page is issued.
(S6) When the write process by the write command issued in (S2) is completed (when the status check is completed), the write command on the next page is issued.
(S7) When the write process by the write command issued in (S3) is completed (when the status check is completed), the write command on the next page is issued.
(S8) When the write process by the write command issued in (S4) is completed (when the status check is completed), the write command on the next page is issued.

In FIG. 7, as soon as the memory chip MC enters the BUSY status, a command to the next area is issued. By performing the writing process while switching the area as in (S1) to (S8) in this way, the processing speed can be increased. If the number of areas is 4, as shown in FIGS. 5 and 6, access to the four areas is processed in parallel. Therefore, the processing time is 1/4 of the existing parallel processing in the area. That is, since it is possible to bring out four times the processing performance, it is possible to dramatically improve the throughput. In the above configuration, since the number of parallels is proportional to the number of areas, it is possible to promote higher speed as the number of areas increases.

As described above, in this embodiment, the access control unit 101a performs access processing in parallel while sequentially switching areas for each page of the memory chip MC.

In the existing technology, if it is attempted to process a plurality of memories in parallel in only one area, it is difficult to increase the number of memories per area. Even if you try to increase the number of devices, the cost will increase. FPGAs, which are examples of memory controller implementations, have an increasing number (number of pins) for serial interfaces and SERDES, but tend not to increase the number of parallel buses.

In NAND Flash memory after MLC, the index of read retry is greatly related to throughput. Read retry is a specification that when an ECC error occurs during reading, the data must be discarded and the data at the same address must be read again. In the broadcasting field, where real-time restrictions are severe, repeated read retries affect product specifications. Extremely, it exceeds the frame synchronization period of 33 msec, which leads to broadcasting failure.

In particular, in NAND Flash memory having a three-dimensional structure represented by BiCS (Bit Cost scalable) NAND, which is expected to become mainstream in the future, the number of read retries may increase, and it has been desired to deal with it.

According to the embodiment, it is possible to meet such needs and increase the speed of storage without increasing the number of memories per area. As a result, it is possible to promote high-speed storage without being bound by the limitation of the number of pins of the memory controller. In addition, there is no cost increase, size increase, and power consumption increase.

Moreover, as can be seen from the comparison between FIGS. 1 and 6, the hardware configuration does not require a large change. That is, the function of the access control unit 101a described above can be realized by changing the internal logic and software mounted on the memory controller 101.

From these things, according to the embodiment, it becomes possible to provide a memory device, a video server, a broadcasting system, and a memory access control method with improved throughput.

The present invention is not limited to the above embodiment. For example, the number of areas is not limited to 4, and the same argument holds for 3 or 2. When the number of areas is 2, the memory controller 101 issues a write command to the page of the memory chip in the first area, issues a write command to the page of the memory chip in the second area, and writes to the first area. Is completed, a write command to the next page of the memory chip in the first area is issued, and when the writing process to the second area is completed, a write command to the next page of the memory chip in the second area is issued. Issue. Based on the procedure in the case where the number of areas is 2, the sequence shown in FIG. 7 is uniquely derived.

Although embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. This novel embodiment can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Broadcast system, 2 ... Operation terminal, 3 ... Camera device, 4 ... Playback device, 5 ... Editing device, 6 ... Broadcasting equipment, 7 ... Monitor device, 10 ... Video server, 11 ... Input unit, 12 ... Memory device, 13 ... Output unit, 14 ... Control unit, 100 ... Memory storage unit, 101 ... Memory controller, 101a ... Access control unit, 102 ... Synchronous signal, 103 ... Address signal, 104 ... Data signal, 120 ... Memory management unit, MC ... Memory chip, BL ... Bus line.

Claims (7)

Equipped with multiple memory storage units
Each of the plurality of memory storage units
Multiple memory chips connected to a common bus line and accessible on a page-by-page basis,
It is provided with a memory controller that controls access to the memory chips in units of areas consisting of a plurality of memory chips connected to different bus lines.
The memory controller is
A memory device including an access control unit that processes access to the memory chip in parallel by switching the area in units of pages. The access control unit
Issue a command to write to the page of the memory chip in the first area,
Issue a write command to the page of the memory chip in the second area,
When the writing process to the first area is completed, a write command to the next page of the memory chip in the first area is issued.
The memory device according to claim 1, wherein when the writing process to the second area is completed, a write command to the next page of the memory chip in the second area is issued. Input section for inputting content data and
A memory device that stores the acquired content data,
It includes an output unit that reads out the content data from the memory device and sends it out.
The memory device includes a plurality of memory storage units, and the memory device includes a plurality of memory storage units.
Each of the plurality of memory storage units
Multiple memory chips connected to a common bus line and accessible on a page-by-page basis,
It has a memory controller that controls access to the memory chip in units of an area composed of a plurality of memory chips connected to different bus lines.
The memory controller is
A video server including an access control unit that processes access to the memory chip in parallel by switching the area in units of pages. The access control unit
Issue a command to write to the page of the memory chip in the first area,
Issue a write command to the page of the memory chip in the second area,
When the writing process to the first area is completed, a write command to the next page of the memory chip in the first area is issued.
The video server according to claim 3, which issues a write command to the next page of the memory chip in the second area when the writing process to the second area is completed. The video server according to claim 3 or 4,
A transmission device that transmits the content data to the video server, and
A broadcasting system including broadcasting equipment for broadcasting the content data transmitted from the video server. A plurality of memory chips connected to a common bus line and accessible on a page-by-page basis, and a memory controller that controls access to the memory chips in units of an area consisting of a plurality of memory chips connected to different bus lines. It is an access control method applicable to a memory device having a plurality of memory storage units.
A memory access control method comprising the memory controller processing the access to the memory chip in parallel by switching the area in the page unit. The memory controller is
Issue a command to write to the page of the memory chip in the first area,
Issue a write command to the page of the memory chip in the second area,
When the writing process to the first area is completed, a write command to the next page of the memory chip in the first area is issued.
The memory access control method according to claim 6, wherein when the write process to the second area is completed, a write command to the next page of the memory chip in the second area is issued.

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