JP2022037455A - Liquid discharge head drive circuit - Google Patents

Abstract

To provide a liquid discharge head drive circuit capable of driving a liquid discharge head in a stable discharge characteristic by suppressing for example, a characteristic variation between semiconductor wafers or an adverse effect on characteristic change due to the temperature at operation in the semiconductor substrate forming a drive circuit.SOLUTION: A liquid discharge head drive circuit in this embodiment comprises a multi-output actuator charge/discharge circuit, an inverting buffer circuit and an adjustment part. The multi-output actuator charge/discharge circuit comprises plural first transistors imparting a drive waveform to each of plural capacitive actuators. The inverting buffer circuits of the same number as that of the first transistors drive those, respectively. The adjustment part adjusts the power source voltage of the inverting buffer circuit independently from the power source voltage of the multi-output drive circuit.SELECTED DRAWING: Figure 6

Description

Embodiments of the present invention relate to a liquid discharge head drive circuit.

A liquid discharge device that supplies a predetermined amount of liquid to a predetermined position is known. The liquid discharge device is mounted on, for example, an inkjet printer, a 3D printer, a dispensing device, or the like. The inkjet printer ejects ink droplets from an inkjet head to print an image or the like on the surface of a recording medium or the like. The 3D printer ejects droplets of the modeling material from the modeling material ejection head and cures them to form a three-dimensional modeled object. The dispensing device ejects droplets of the sample and supplies a predetermined amount to a plurality of containers or the like.

The multi-nozzle inkjet head, which is one of the liquid ejection heads, has a plurality of channels including nozzles and actuators for forming dots. The actuators for each channel are individually driven by a multi-output liquid discharge head drive circuit. The drive waveform given to the actuator was either determined by the ON resistance of the drive circuit and the capacitance of the actuator, or a circuit that determines the drive waveform was added separately from the ON / OFF control. However, in the former case, there is a drawback that the ejection characteristics are changed due to the influence of the variation in the characteristics of the semiconductor substrate forming the drive circuit, for example, between the semiconductor wafers and the characteristic change due to the temperature during operation. Further, in the latter case, there is a drawback that a plurality of circuits are arranged in series in the high output drive current path, and the area of the semiconductor substrate serving as the drive circuit becomes large.

Japanese Unexamined Patent Publication No. 2008-188889 Japanese Patent Application Laid-Open No. 2003-58264 Japanese Unexamined Patent Publication No. 2001-191531 Japanese Unexamined Patent Publication No. 10-138484

The problem to be solved by the present invention is to suppress the influence of the variation in the characteristics of the semiconductor substrate forming the drive circuit, for example, between the semiconductor wafers and the characteristic change due to the temperature during operation, and to provide a liquid discharge head with stable discharge characteristics. It is an object of the present invention to provide a liquid discharge head drive circuit which can be driven.

The liquid discharge head drive circuit according to the embodiment of the present invention includes a multi-output actuator charge / discharge circuit, an inverting buffer circuit, and an adjusting unit. The multi-output actuator charge / discharge circuit includes a plurality of first transistors that give a drive waveform to each of the plurality of capacitive actuators. The inverting buffer circuit is a circuit that drives a plurality of first transistors, respectively. The number of inverting buffer circuits is the same as that of the first transistor. The adjusting unit adjusts the power supply voltage of the inverting buffer circuit independently of the power supply voltage of the multi-output drive circuit.

It is an overall block diagram of the inkjet printer provided with the inkjet head drive circuit according to 1st Embodiment. It is a perspective view of the inkjet head included in the said inkjet head printer. It is a partial cross-sectional view of the actuator board of the above-mentioned inkjet head. It is a figure explaining the operation of ejecting ink of the said inkjet head. It is a block block diagram of the control system of the said inkjet printer. It is an overall block diagram of the said inkjet head drive circuit. It is a circuit diagram of an actuator drive circuit. It is a figure explaining ON / OFF of a drive transistor and a drive waveform. It is an overall block diagram of the inkjet head drive circuit according to 2nd Embodiment. It is a figure explaining ON / OFF and ON resistance of the sub-transistor of the said inkjet head drive circuit. It is a figure explaining the arrangement on the semiconductor substrate of a plurality of current mirror circuits included in the inkjet head drive circuit according to 3rd Embodiment. It is a circuit diagram of the 1st current mirror circuit of the said inkjet head drive circuit. It is a circuit diagram of the 2nd and 3rd current mirror circuits of the said inkjet head drive circuit.

Hereinafter, the liquid discharge head drive circuit according to the embodiment will be described in detail with reference to the accompanying drawings. In each figure, the same configurations are designated by the same reference numerals.

(First Embodiment)
An inkjet printer 10 that prints an image on a recording medium will be described as an image forming apparatus equipped with a multi-nozzle liquid ejection device 1. FIG. 1 shows a schematic configuration of an inkjet printer 10. Inside the housing 11 of the inkjet printer 10, a cassette 12 for storing a sheet S, which is an example of a recording medium, an upstream transport path 13 for the sheet S, a transport belt 14 for transporting the sheet S taken out from the cassette 12, and a transport belt. Inkjet heads 100 to 103 for ejecting ink droplets toward the sheet S on the sheet S, a downstream transport path 15 for the sheet S, an ejection tray 16, and a control board 17 are arranged. The operation unit 18, which is a user interface, is arranged on the upper side of the housing 11. The inkjet head 100 is an example of a liquid ejection head.

The image data to be printed on the sheet S is generated by, for example, a computer 200 which is an externally connected device. The image data generated by the computer 200 is sent to the control board 17 of the inkjet printer 10 through the cables 201 and the connectors 202 and 203.

The pickup roller 204 supplies the sheets S one by one from the cassette 12 to the upstream transport path 13. The upstream transport path 13 is composed of feed rollers 131 and 132 and seat guide plates 133 and 134. The sheet S is sent to the upper surface of the transport belt 14 via the upstream transport path 13. The arrow 104 in the figure indicates a transport path of the sheet S from the cassette 12 to the transport belt 14.

The transport belt 14 is a net-like endless belt having a large number of through holes formed on its surface. The three rollers, the drive roller 141 and the driven rollers 142, 143, rotatably support the transport belt 14. The motor 205 rotates the conveyor belt 14 by rotating the drive roller 141. The motor 205 is an example of a drive device. In the figure, 105 indicates the rotation direction of the transport belt 14. The negative pressure container 206 is arranged on the back surface side of the transport belt 14. The negative pressure container 206 is connected to the depressurizing fan 207. The fan 207 creates a negative pressure in the negative pressure container 206 by the air flow formed, and adsorbs and holds the sheet S on the upper surface of the transport belt 14. In the figure, 106 shows the flow of airflow.

The inkjet heads 100 to 103 are arranged so as to face the sheet S adsorbed and held on the transport belt 14 with a slight gap of, for example, 1 mm. The inkjet heads 100 to 103 eject ink droplets toward the sheet S, respectively. The inkjet heads 100 to 103 print an image when the sheet S passes below. Each inkjet head 100 to 103 has the same structure except that the color of the ink to be ejected is different. The ink colors are, for example, cyan, magenta, yellow, and black.

Each of the inkjet heads 100 to 103 is connected to the ink tanks 315 to 318 and the ink supply pressure adjusting devices 321 to 324, respectively, via the ink flow paths 311 to 314. At the time of image formation, the inks in the ink tanks 315 to 318 are supplied to the inkjet heads 100 to 103 by the ink supply pressure adjusting devices 321 to 324.

After forming the image, the sheet S is sent from the transport belt 14 to the downstream transport path 15. The downstream transport path 15 is composed of feed roller pairs 151, 152, 153, 154 and sheet guide plates 155, 156 that define the transport path of the sheet S. The sheet S is sent from the discharge port 157 to the discharge tray 16 via the downstream transport path 15. Arrow 107 in the figure indicates a transport path of the sheet S.

Subsequently, the configuration of the inkjet head 100 will be described with reference to FIGS. 2 to 4. Since the inkjet heads 101 to 103 have the same structure as the inkjet head 100, detailed description thereof will be omitted.

FIG. 2 is a perspective view of the inkjet head 100. The inkjet head 100 includes a nozzle head portion 2, a flexible printed wiring board 21, and a relay board 22, which are examples of a liquid ejection portion. The nozzle 23 of each channel for ejecting ink is formed on the lower surface of the nozzle head portion 2. The nozzle plate on which the nozzle 23 is formed may be provided on the lower surface of the nozzle head portion 2. The nozzles 23 are arranged, for example, in a row along the longitudinal direction (X direction) of the nozzle head portion 2. Further, it may be arranged in the Y direction. The nozzle density is set, for example, in the range of 150 to 1200 dpi. The ink discharged from each nozzle 23 is supplied from the ink supply pipe 24 into the nozzle head portion 2. The ink supply pipe 24 is connected to the ink supply pressure adjusting device 321 via the ink flow path 311 (see FIG. 1).

FIG. 3 is a partial cross-sectional view of the actuator substrate 25 in the nozzle head portion 2. As shown in FIG. 3, the actuator substrate 25 includes an ink pressure chamber 26 that communicates with the nozzle 23. The ink pressure chamber 26 is formed by at least the number of channels according to the arrangement of the nozzles 23. The pressure chamber 26 forms, for example, a concave groove extending in the Z direction on one surface of the actuator substrate 25, and the upper surface thereof is sealed with an elastic plate 27. The actuator substrate 25 is, for example, an insulating ceramic substrate. The elastic plate 27 is formed of, for example, an insulating ceramic material. The pressure chamber 26 communicates with the nozzle 23 on one end side and communicates with the common ink chamber 28 on the other end side. The common ink chamber 28 extends in the X direction, for example, and communicates with the pressure chamber 26 of each channel. Further, the ink supply port 29 formed in the common ink chamber 28 communicates with the ink supply pipe 24. As a result, the ink is supplied to the pressure chamber 26 of each channel via the common ink chamber 28.

The actuator 3 is arranged on the outer surface of the elastic plate 27. The capacitive actuator 3 has a configuration in which an individual electrode 32 and a common electrode 33 are laminated on both surfaces of the piezoelectric member 31. The individual electrode 32 is an electrode that individually applies a drive voltage to the channel for ejecting ink among the plurality of channels. The common electrode 33 is an electrode that faces the individual electrode 32 via the piezoelectric member 31 and is connected to a plurality of channels to give a reference potential common to each channel. The piezoelectric member 31 is formed of, for example, lead zirconate titanate (PZT), and is polarized so as to bulge outward when a positive driving voltage is applied to the individual electrodes 32. Therefore, as shown in FIG. 4, when the actuator 3 is charged by applying a driving voltage, the piezoelectric member 31 expands the elastic plate 27 to the outside to expand the pressure chamber 26 and draw ink from the common ink chamber 28. Subsequently, when the actuator 3 is discharged, the pressure chamber 26 returns to the original state, the ink pressure in the chamber rises, and ink droplets are ejected from the nozzle 23. That is, it is an example of a pulling drive waveform. However, the ink ejection operation is not limited to this. Further, the positions of the individual electrodes 32 sandwiching the piezoelectric member 31 and the common electrodes 33 may be reversed. In that case, the polarization direction of the piezoelectric element 31 and the order in which the waveform is generated are also changed.

Returning to FIG. 2, the individual electrodes 32 and the common electrodes 33 of each channel are electrically connected to the flexible printed wiring board 21, and the flexible printed wiring board 21 is electrically connected to the relay board 22. A drive IC (Integrated Circuit) 34 is mounted on the flexible printed wiring board 21 (hereinafter referred to as a drive IC). The drive IC 34 temporarily stores the print data from the control board 17 of the inkjet printer 10, and applies a drive voltage to the actuator 3 so as to eject ink at a predetermined timing.

FIG. 5 is a block configuration diagram of the control system of the inkjet printer 10. The control board 17 as a control unit includes a CPU 170, a ROM 171 and a RAM 172, an I / O port 173 as an input / output port, and an image memory 174. The CPU 170 controls the motor 205, the ink supply pressure adjusting devices 321 to 324, the operation unit 18, and various sensors through the I / O port 173. The image data from the computer 200, which is an externally connected device, is transmitted to the control board 17 through the I / O port 173 and stored in the image memory 174. The CPU 170 transmits the image data stored in the image memory 174 to the drive circuit 35 in the drawing order. The drive circuit 35 is included in the drive IC 34 (see FIG. 2).

The drive circuit 35 includes a print data buffer 36, a decoder 37, and a drive driver 38. The print data buffer 36 stores image data in time series for each channel. The decoder 37 controls the drive driver 38 based on the image data stored in the print data buffer 36 for each channel. The drive driver 38 applies a drive voltage to the actuator 3 of each channel under the control of the decoder 37.

FIG. 6 shows the overall configuration of the inkjet head drive circuit 4, which is an example of the liquid discharge head drive circuit. The inkjet head drive circuit 4 is, for example, a part of the drive circuit 35. The inkjet head drive circuit 4 includes a drive circuit board 41, a detection unit 42, a microprocessor 43, an A / D converter 44, a D / A converter 45, an amplifier circuit 46, 47, and the like. A multi-output drive circuit that applies a drive voltage to the actuator 3 of each channel is formed on the drive circuit board 41. That is, it is a charge / discharge circuit that charges / discharges a plurality of capacitive actuators 3. The detection unit 42 includes detection transistors 61 and 62 that are paired with the drive transistors 51 and 52 of the multi-output drive circuit. The microprocessor 43, the D / A converter 45, and the amplifier circuits 46, 47 constitute an adjustment unit described later.

FIG. 7 shows an actuator drive circuit 5 extracted from the inkjet head drive circuit 4 of FIG. The inkjet head drive circuit 4 has at least as many actuator drive circuits 5 as there are channels. First, the configuration of the actuator drive circuit 5 and the operation of the circuit will be described with reference to FIG. 7. The actuator drive circuit 5 includes a high-side drive transistor 51 and a low-side drive transistor 52. The high-side drive transistor 51 is, for example, a P-channel MOS transistor. The low-side drive transistor 52 is, for example, an N-channel MOS transistor. The drive transistor 51 and the drive transistor 52 have different polarities in the N channel and the P channel, but both correspond to the "first transistor" that drives the actuator 3.

The high-side and low-side drive transistors 51 and 52 are connected to each other's drains and further connected to one terminal of the actuator 3. One terminal of the actuator 3 is, for example, an individual electrode 32. The other terminal of the actuator 3 is, for example, a common electrode 33. The common electrode 33 is connected to, for example, a voltage V0 (for example, 0V). The source of the high-side drive transistor 51 is connected to the first potential. The first potential is a voltage V1 (eg, a positive voltage of 15V). The source of the low-side drive transistor 52 is connected to a second potential that is lower than the first potential. The second potential is a voltage V0 (eg, 0V).

The actuator drive circuit 5 includes an inverting buffer circuit 53 that drives the gate of the high-side drive transistor 51 and an inverting buffer circuit 54 that drives the gate of the low-side drive transistor 52. The high-side inverting buffer circuit 53 includes a "second transistor 55" that turns off the high-side drive transistor 51 and a "third transistor 56" that turns it on. The second transistor 55 is, for example, a P-channel MOS transistor. The third transistor 56 is, for example, an N-channel MOS transistor. That is, the inverting buffer circuit 53 pairs two transistors 55 and 56 having opposite polarities. Then, a third transistor 56 having a polarity opposite to that of the driving transistor 51 is assigned to the transistor that turns on the driving transistor 51, which is the first transistor.

The second transistor 55 and the third transistor 56 are connected to each other's drains and further connected to the gate of the driving transistor 51. The source of the second transistor 55 is connected to the first potential. The first potential is the voltage V1 (15V positive voltage in this example). The source of the third transistor 56 is connected to the adjusting unit. The adjusting unit is a circuit that adjusts the power supply voltage VdH of the inverting buffer circuit 53, that is, the source voltage of the third transistor 56, based on the detection result of the detection unit 42, which will be described in detail later. In the circuit of FIG. 6, the adjusting unit is composed of the microprocessor 43, the D / A converter 45, and the amplifier circuit 46, but in the circuit of FIG. 7, it is represented by a DC “variable voltage source 531” for convenience of drawing. The variable voltage source 531 adjusts the power supply voltage VdH of the inverting buffer circuit 53, for example, in the range of 0 to 15V.

The input of the inverting buffer circuit 53, that is, the drive of the gates of the second transistor 55 and the third transistor 56 is performed by giving the drive waveform data input via the level shifter 59. When a voltage V1 is applied to the inverting buffer circuit 53 via the level shifter 59, for example, the second transistor 55 is turned off and the third transistor 56 is turned on. VdH (that is, a low level with respect to the voltage V1) is given, and the driving transistor 51 is turned ON. Further, when a voltage V0 is applied to the inverting buffer circuit 53 via the level shifter 59, for example, the third transistor 56 is turned off, the second transistor 55 is turned on, and the driving transistor 51 is turned off. The back gate of the third transistor 56 may not be connected to the source of the third transistor 56, or may be individually wired and excluded from the control target.

The low-side inverting buffer circuit 54 includes a "second transistor 57" that turns off the low-side drive transistor 52 and a "third transistor 58" that turns it on. The second transistor 57 is, for example, an N-channel MOS transistor. The third transistor 58 is, for example, a P-channel MOS transistor. That is, the inverting buffer circuit 54 pairs two transistors having opposite polarities. Then, a third transistor 58 having a polarity opposite to that of the driving transistor 52 is assigned to the transistor that turns on the driving transistor 52, which is the first transistor.

The second transistor 57 and the third transistor 58 are connected to each other's drains and further connected to the gate of the driving transistor 52. The source of the second transistor 57 is connected to the second potential. The second potential is the voltage V0 (0V in this example). The source of the third transistor 58 is connected to the adjusting unit. As described above, the adjustment unit is composed of the microprocessor 43, the D / A converter 45, and the amplifier circuit 47 in the circuit of FIG. 6, but in the circuit of FIG. 7, a DC “variable voltage source” is used for convenience of drawing. It is represented by "541". The variable voltage source 541 adjusts the power supply voltage VdL of the inverting buffer circuit 54, for example, in the range of 0 to 15V.

The input of the inverting buffer circuit 54, that is, the drive of the gates of the second transistor 57 and the third transistor 58 is performed by giving the drive waveform data input via the level shifter 59. When a voltage V0 is applied to the inverting buffer circuit 54 via the level shifter 59, for example, the second transistor 57 is turned off and the third transistor 58 is turned on. VdL (that is, a high level with respect to the voltage V0) is given, and the driving transistor 52 is turned ON. Further, when a voltage V1 is applied to the inverting buffer circuit 54 via the level shifter 59, for example, the third transistor 58 is turned off, the second transistor 57 is turned on, and the driving transistor 52 is turned off. The back gate of the third transistor 58 may not be connected to the source of the third transistor 58, or may be individually wired and excluded from the control target.

Subsequently, the operation of the circuit and the drive waveform given to the actuator 3 will be described with reference to FIG. As described above, the high-side drive transistor 51 operates ON when a low level is applied to the gate voltage VGH. The low-side drive transistor 52 operates ON when a high level is applied to the gate voltage VGL. Therefore, when a low level is applied to both the gate voltage VGL and the gate voltage VGH, the output voltage becomes a high level and the actuator 3 is charged. When the actuator 3 is charged, the pressure chamber 26 expands to draw ink into the room (see charging in FIG. 4). Subsequently, when a high level is applied to both the gate voltage VGL and the gate voltage VGH, the output voltage becomes a low level and the actuator 3 is discharged. When the actuator 3 is discharged, the pressure chamber 26 returns to the original state, the ink pressure in the chamber increases, and the ink is discharged from the nozzle 23 (see the discharge in FIG. 4).

Here, when the high-side variable voltage source (that is, the adjusting unit) 531 is controlled to throttle the power supply voltage VdH, the amplitude of the gate voltage VGH of the high-side driving transistor 51 becomes smaller, and the output current of the driving transistor 51 becomes smaller. Can be restricted. Similarly, when the low-side variable voltage source (that is, the adjusting unit) 541 is controlled to throttle the power supply voltage VdL, the amplitude of the gate voltage VGL of the low-side driving transistor 52 becomes small, and the output current of the driving transistor 52 is limited. can. As a result, the time required to charge the actuator 3 to the voltage V1 or the time required to discharge the actuator 3 to the voltage V0 becomes long, and as shown in the figure, for example, when the power supply voltages VdH and VdL are not throttled. Compared with (indicated by the broken line), the rising and falling edges of the drive waveform OUT can be relaxed. That is, the rising and falling edges of the drive waveform can be variably adjusted. When the rise / fall time of the drive waveform is narrowed, the contraction operation and the return operation of the actuator 3 become slower by that amount, so that the ink ejection speed changes by adjusting the power supply voltages VdH and VdL.

If the voltages of the power supplies VdH and VdL by the variable voltage sources 531,541 can be adjusted in, for example, three steps, the gradient of the rising and falling edges of the drive waveform can be controlled in three steps. Of course, the adjustment of the voltages of the power supplies VdH and VdL by the variable voltage sources 531,541 does not have to be in three steps. Further, since the inverting buffer circuits 53, 54 and the variable voltage sources 531, 541 are provided on both the high side and the low side, it is possible to independently adjust the rising and falling edges of the drive waveform.

If the inverting buffer circuits 53, 54 and the variable voltage sources 531, 541 are not provided, the expansion / recovery time of the pressure chamber 26 is fixed by the characteristics of the driving transistors 51, 52 and the capacitance of the piezoelectric member 31 of the actuator 3. It is fixed and cannot be adjusted variably. On the other hand, if the inverting buffer circuits 53, 54 and the variable voltage sources 531, 541 are provided so that the rising and falling edges of the drive waveform can be adjusted, the output current of the drive transistors 51, 52 is limited. be able to. As a result, the slope (transition time) of the voltage waveform at the time of expansion / recovery of the pressure chamber 26 can be adjusted, and the ink ejection characteristics of the inkjet head 100 can be improved.

Returning the description to the inkjet head drive circuit 4 of FIG. 6, the detection unit 42 includes two detection transistors 61 and 62 having different polarities. One detection transistor 61 is a diode-connected P-channel transistor. The P channel detection transistor 61 is for measuring the forward voltage of the P channel transistor. That is, the detection target is the high-side drive transistor 51, which is also a P-channel transistor. The group of the detection transistor 61 and the drive transistor 51 is formed on a common semiconductor substrate. At this time, it is desirable to make the transistors close to each other and arrange them collectively on the semiconductor substrate. Further, it is preferable to grasp the characteristic ratio of the detection transistor 61 with the drive transistor 51 to be detected in advance. The characteristic ratio is, for example, the size ratio of a transistor. The size ratio of the transistor is specified by, for example, the ratio of the ratio of the channel width to the channel length.

The other detection transistor 62 is an N-channel transistor connected by a diode. The N-channel detection transistor 62 is for measuring the forward voltage of the N-channel transistor. That is, the detection target is the low-side drive transistor 52, which is also an N-channel transistor. The group of the detection transistor 62 and the drive transistor 52 is formed on a common semiconductor substrate. At this time, it is desirable to make the transistors close to each other and arrange them collectively on the semiconductor substrate. Further, it is preferable that the detection transistor 62 has a characteristic ratio with that of the drive transistor 62 to be detected in advance. The characteristic ratio is, for example, the size ratio of a transistor. The size ratio of the transistor is specified by, for example, the ratio of the ratio of the channel width to the channel length.

The three resistors 63, 64, 65 and the two transistors 66, 67 connected in parallel are current switching circuits that adjust the forward current flowing through the detection transistors 61, 62 connected in series. Specifically, by combining ON and OFF of the two transistors 66 and 67, a current flows only through the resistance 63, a current flows through the resistance 63 and the resistance 64, a current flows through the resistance 63 and the resistance 65, and the resistance 63 to Forward current can be passed through the detection transistors 61 and 62 in four patterns of passing current through all of 65. The microprocessor 43 controls the current switching circuit to measure the forward voltage of the detection transistor 61 when a predetermined forward current is passed through the differential amplifier circuit 71. Similarly, the microprocessor 43 controls the current switching circuit to measure the forward voltage of the detection transistor 62 when a predetermined forward current is passed through the differential amplifier circuit 72.

The microprocessor 43 controls the output values from the output ports DO1 and DO2 (DO; digital output). The microprocessor 43 determines the output value from the output ports DO1 and DO2, controls ON / OFF of the transistors 66 and 67 via the inverters 74 and 75, and determines a predetermined current to be passed through the detection transistors 61 and 62. Further, the microprocessor 43 measures the voltage drop generated in the resistors 63 to 65 via the differential amplifier circuit 73, and calculates the current value flowing through the detection transistors 61 and 62. If the voltage V1 and the voltage V0 are stable, the differential amplifier circuit 73 may be omitted.

The microprocessor 43 executes, for example, a program stored in a memory or the like to determine the power supply voltage VdH of the high-side inverting buffer circuit 53. Then, the microprocessor 43 applies the power supply voltage VdH to the high-side inverting buffer circuit 53 via the D / A converter 45 and the amplifier circuit 46. Further, the microprocessor 43 monitors the power supply voltage VdH of the high-side inverting buffer circuit 53 with the differential amplifier circuit 77. Further, the microprocessor 43 executes the program in the same manner to determine the power supply voltage VdL of the low-side inverting buffer circuit 54. Then, the microprocessor 43 applies the power supply voltage VdL to the low-side inverting buffer circuit 54 via the D / A converter 45 and the amplifier circuit 47. Further, the microprocessor 43 monitors the power supply voltage VdL of the low-side inverting buffer circuit 54 by the differential amplifier circuit 76. The amplifier circuits 46 and 47 may be built in the drive circuit board 41.

In this way, the inkjet head drive circuit 4 composed of the drive transistors 51 and 52 and the detection transistors 61 and 62 via the inverting buffer circuits 53 and 54 operates as follows. The microprocessor 43 first determines the output values from the output ports DO1 and DO2 to predetermined values for ON / OFF control of the transistors 66 and 67, and determines the set current to be passed through the detection transistors 61 and 62 connected to the diode. .. Since the detection transistors 61 and 62 are formed on the same semiconductor substrate by the same process as the drive transistors 51 and 52 to be detected, the set currents are the detection transistors 61 and 62 and the drive transistors 51, respectively. The current is set so that the operations are similar according to the size ratio of each of 52. Since the detection transistors 61 and 62 and the drive transistors 51 and 52 are formed on the same semiconductor substrate by the same process, there is a similar relationship even if there are variations between the semiconductor wafers or the temperature changes. Because it is maintained. In the inkjet head drive circuit 4 of the present embodiment, the detection unit 42 and the adjustment unit are independent, and the A / D converter 44, the D / A converter 45, and the microprocessor 43 are interposed between them. The operation of the circuit is similar to that of the current mirror circuit, and can be seen as a modification of the current mirror circuit. Since the configuration of this circuit intervenes the microprocessor 43, there is an advantage that fine adjustment is possible as compared with a normal current mirror circuit configured only by hardware.

As an example, if the channel width of the detection transistor 61 is 1/5 times and the channel length is twice the transistor size of the drive transistor 51, the detection transistor 61 has 1 of the operating current of the drive transistor 51. The set current is a current that is / 10 times larger.

The voltage drop of the detection transistor 61 at that time, that is, the forward voltage is taken into the microprocessor 43 via the differential amplifier 71 and the A / D converter 44. Since the captured voltage should be the voltage to be applied to the gate of the drive transistor 51, the microprocessor 43 transfers the voltage to the power supply voltage VdH of the inverting buffer circuit 53 via the D / A converter 45 and the amplifier 46. give. As described above, when a high level is applied to the input of the inverting buffer circuit 53 via the level shifter 59, the drive transistor 51 is turned on, and the applied power supply voltage VdH is directly applied to the gate of the drive transistor 51. Therefore, when the drive transistor 51 is turned on to charge the actuator 3, the output current of the drive transistor 51 is limited to be a current corresponding to the set current. As a result, the time required for expansion of the pressure chamber 26 can be adjusted to a desired time.

For the low side as well, in the same series of operations as for the high side, when the drive transistor 52 is turned on and the actuator 3 is discharged, the output current of the drive transistor 52 is limited to be the current corresponding to the set current. .. As a result, the time required for the pressure chamber 26 to return to the original state can be adjusted to a desired time. In the circuit of FIG. 6, the power supply voltages VdH and VdL of the inverting buffer circuits 53 and 54 are controlled via the microprocessor 43, but the present invention is not limited to this. For example, the forward voltage of the detection transistors 61 and 62 may be the power supply voltages VdH and VdL of the inverting buffer circuits 53 and 54, respectively, by hardware without going through the microprocessor 43 or via the voltage follower.

(Second Embodiment)
Subsequently, the inkjet head drive circuit 8 of the second embodiment will be described with reference to FIG. 9. The inkjet head drive circuit 4 of the first embodiment described above has a configuration in which the power supply voltages VdH and VdL of the inverting buffer circuits 53 and 54 are adjusted to limit the output current of the drive transistor. The inkjet head drive circuit 8 has a configuration in which the drive transistor is divided into a plurality of sub-transistors to limit the output current. The same configuration as that of the first embodiment is designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, the inkjet head drive circuit 8 divides the high-side drive transistor into a first subtransistor 81 and a second subtransistor 82 having the same polarity but different sizes. The first subtransistor 81 and the second subtransistor 82 are, for example, P-channel MOS transistors. As the first subtransistor 81, for example, a transistor having a shorter channel width is used in comparison with the second subtransistor 82. The drive of the gates of the first subtransistor 81 and the second subtransistor 82 is controlled via the NAND circuit 83. That is, the first subtransistor 81 and the second sub of the high side are determined by the combination of the value of the drive waveform data input given to the channel for ejecting ink and the output value from the output ports DO5 and DO6 controlled by the microprocessor 43. Controls ON and OFF of transistor 82

Similarly, the low-side drive transistor is divided into a first subtransistor 84 and a second subtransistor 85 having the same polarity but different sizes. The first subtransistor 84 and the second subtransistor 85 are, for example, N-channel MOS transistors. As the first subtransistor 84, for example, a transistor having a shorter channel width is used in comparison with the second subtransistor 85. The drive of the gates of the first subtransistor 84 and the second subtransistor 85 is controlled via the AND circuit 86 and the NOT circuit 87. That is, depending on the combination of the value of the drive waveform data input given to the channel for ejecting ink and the output value from the output ports DO3 and DO4 controlled by the microprocessor 43, the low-side first subtransistor 84 and the second subtransistor It controls ON and OFF of 85.

As an example, the ratio of the channel widths of the first subtransistors 81,84 and the second subtransistors 82,85 is set to, for example, 1: 2 on both the high side and the low side. In this case, as shown in FIG. 10, depending on which of the first subtransistors 81, 84 and the second subtransistors 82, 85 is driven, both the high side and the low side are r, r / 2, r. Switching of ON resistance can be realized with 3 types of / 3. The channel width ratio does not necessarily have to be the same on the high side and low side.

The inkjet head drive circuit 8 composed of the first and second subtransistors 81, 82, 84, 85 and the detection unit 42 operates as follows. Similar to the first embodiment, the microprocessor 43 first determines the output from the output ports DO1 and DO2 to a predetermined value, and determines the set current to be passed through the detection transistors 61 and 62 connected to the diode. The microprocessor 43 takes in the voltage drop of the detection transistor 61 at that time, that is, the forward voltage, via the differential amplifier 71 and the A / D converter 44, and takes in the voltage drop of the detection transistor 62, that is, the forward voltage. , Taken in via the differential amplifier 72 and the A / D converter 44.

The microprocessor 43 determines whether to drive the first sub-transistor 81 or the second transistor 82 connected in parallel according to the forward voltage of the captured detection transistor 61. Further, the microprocessor 43 determines whether to drive the first sub-transistor 84 or the second transistor 85 connected in parallel according to the forward voltage of the captured detection transistor 62. Then, the microprocessor determines the output from the output ports DO3 to DO6 to a predetermined value and gives the output to the NAND circuit 83 and the NOT circuit 87. On the other hand, a drive waveform data input of a predetermined value is given to the NAND circuit 83 and the AND circuit 86 of the channel for ejecting ink, and the first subtransistor 81 (84) is combined with the output from the output ports DO3 to DO6. ) Only, only the second transistor 82 (85) can be driven by either the first subtransistor 81 (84) and the second transistor 82 (85). As a result, the output current of the subtransistor is adjusted to adjust the rising and falling times of the drive waveform. As a result, the time required for expansion / restoration of the pressure chamber 26 can be adjusted, and good discharge characteristics can be obtained.

(Third Embodiment)
Subsequently, the inkjet head drive circuit 9 of the third embodiment will be described with reference to FIGS. 11 to 13. On the other hand, in the inkjet head drive circuit 9 of the third embodiment, a plurality of drive transistors 51 and 52 in the multi-output drive circuit are grouped to form a plurality of stages of current mirror circuits. Hereinafter, the configuration of the circuit will be described in detail, but the same configuration as that of the first embodiment will be described in detail by adding the same reference numerals. Further, although FIGS. 11 to 13 do not show the detection unit 42, the detection unit 42 may be combined with the detection unit 42 as in the first embodiment.

When the multi-output drive circuit for driving the multi-nozzle inkjet head 100 is manufactured on a common semiconductor substrate, it tends to be an elongated semiconductor integrated circuit along the arrangement direction of the nozzles 23. A semiconductor substrate having an elongated shape is easily affected by the distribution of impurities in the longitudinal direction thereof. It is also susceptible to changes in transistor characteristics due to differences in temperature in the longitudinal direction. Therefore, when constructing the current mirror circuit, the current cannot be set accurately unless the characteristics of the transistor to be controlled and the transistor connected to the diode of the control target are the same.

Therefore, in the present embodiment, the multi-output drive circuit is divided into a plurality of groups to form a first to third multi-stage current mirror circuit. The multi-output drive circuit and the first to third current mirror circuits divided into a plurality of groups are arranged on the semiconductor substrate 90, for example, as schematically shown in FIG.

As shown in FIG. 12, the portion of the multi-output drive circuit in the inkjet head drive circuit 9 groups a plurality of channels into a plurality of groups. For example, if the number of channels is 1000, divide them into 4 groups of 250 along the longitudinal direction. Of course, the number of groups may increase or decrease. Then, as the detection transistors 91 and 92, which are an example of the first diode, diode-connected transistors are provided in the group, respectively. The detection transistors 91 and 92 paired with the drive transistors 51 and 52 form a first current mirror circuit, respectively, via the inverting buffer circuits 53 and 54. Although not shown, the same applies to other groups.

The high-side detection transistor 91 constitutes a high-side drive transistor 51 and a first current mirror circuit via an inverting buffer circuit 53. The detection transistor 91 is a transistor having the same P channel as the paired drive transistor 51. The detection transistor 91 and the drive transistor 51 are preferably transistors having the same size. However, even if the sizes are different, the relationship may be similar as long as the size ratio is grasped. The low-side detection transistor 92 constitutes a low-side drive transistor 52 and a first current mirror circuit via an inverting buffer circuit 54. The detection transistor 92 is a transistor having the same N channel as the paired drive transistor 52. The detection transistor 92 and the drive transistor 52 are preferably transistors having the same size. However, even if the sizes are different, the relationship may be similar as long as the size ratio is grasped.
When the number of inverting buffer circuits 53 connected to one high-side detection transistor 91 and the drive transistor 51 beyond it is large, high-side detection is performed to stabilize the output voltage of the high-side detection transistor 91. A buffer by a voltage follower circuit or the like may be provided between the transistor 91 and the plurality of inverting buffer circuits 53. Similarly, when the number of the inverting buffer circuit 54 connected to one low-side detection transistor 92 and the drive transistor 52 beyond it is large, the low-side detection is performed to stabilize the output voltage of the low-side detection transistor 92. A buffer by a voltage follower circuit or the like may be provided between the transistor 92 and the inverting buffer circuit 54.

The detection transistors 91 and 92 are arranged close to a group of paired drive transistors 51 and 52, respectively. That is, the first current mirror circuit by the detection transistors 91 and 92 is arranged in the vicinity of the drive transistors 51 and 52 of each group, respectively. As a result, the transistor characteristics of the detection transistors 91 and 92 and the drive transistors 51 and 52 can be made uniform in each group.

The first reference current to be passed through the first current mirror circuit of each group is generated by the second current mirror circuit shown in FIG. The high-side output circuit control transistor 93 controlled by the second current mirror circuit is electrically connected to the high-side detection transistor 91 of the first current mirror circuit. A plurality of transistors 93 connected in parallel are aligned with transistors having the same polarity and size. The low-side output circuit control transistor 94, which is also controlled, is electrically connected to the low-side detection transistor 92 of the first current mirror circuit. A plurality of transistors 94 connected in parallel are aligned with transistors having the same polarity and size.

In the second current mirror circuit, a diode-connected transistor is provided as the output circuit control transistors 95 and 96, which is an example of the second diode. That is, the gate voltage of the transistors 93 and 94 to be controlled is controlled by the paired transistors 95 and 96, respectively. The transistor 95 for controlling the high-side output circuit forms a second current mirror circuit with the transistor 93 for controlling the high-side output circuit to be paired with the transistor 95. The transistor 95 is the same N-channel transistor as the transistor 93. The transistor 95 and the transistor 93 are preferably transistors having the same size. However, even if the sizes are different, the relationship may be similar as long as the size ratio is grasped. The transistor 96 for controlling the low-side output circuit forms a second current mirror circuit with the transistor 94 for controlling the low-side output circuit to be paired with the transistor 96. The transistor 96 is a transistor having the same P channel as the transistor 94. The transistor 96 and the transistor 94 are preferably transistors having the same size. However, even if the sizes are different, the relationship may be similar as long as the size ratio is grasped.

The output circuit control transistors 95 and 96 are arranged in a concentrated manner on a part of the semiconductor substrate 90 at a distance close to a group of paired output circuit control transistors 93 and 94 (see FIG. 11). That is, the transistors 93 and 94 are not arranged in the vicinity of each group, but are collectively arranged in the second current mirror circuit. As a result, the transistor characteristics of the plurality of transistors 93 (94) can be made uniform. Further, the transistor characteristics can be made uniform between the transistor 95 and the transistor 93 to be controlled and between the transistor 96 and the transistor 94 to be controlled. As a result, the accuracy of the current controlled by the second current mirror circuit can be maintained.

The third current mirror circuit reverses the direction of the current flowing through the transistor 96 for controlling the low-side output circuit of the second current mirror circuit, and sets the direction of the output current IsL of the D / A converter 45 to the high-side output circuit. This is a circuit for making the direction of the current IsH flowing through the control transistor 95 the same. The third current mirror circuit is formed by a transistor 97 and a transistor 98 to be controlled, which is a pair thereof. The transistor 97 for controlling the output circuit, which is an example of the third diode, is a diode-connected transistor. The current flowing through the transistor 96 for controlling the low-side output circuit of the second current mirror circuit is controlled by the current output D / A converter 45. However, the third current mirror circuit is provided so that the current IsL flowing through the transistor 97 and the current IsH flowing through the transistor 95 can be controlled by a common method, and is essential if they are controlled by different methods. It is not a circuit of.

The inkjet head drive circuit 9 described above operates as follows. That is, first, the current values of the currents IsH and IsL output from the D / A converter 45 are determined. The D / A converter 45 is controlled by, for example, the microprocessor 43. The set currents of the currents IsH and IsL are values obtained by adding a proportionality constant according to the size ratio of the transistors to the currents to be output to the driving transistors 51 and 52. That is, it is a set current value for adjusting the time required for expansion / recovery of the pressure chamber 26 to a desired time, and if the transistor size of each stage is scaled, the current value is scaled according to the ratio. Set. Looking at the high side, the current IsH output from the D / A converter 45 is given to the transistor 95 of the second current mirror circuit as the second reference current. Then, the same gate voltage as that of the transistor 95 is applied to each transistor 93 of the second current mirror circuit. Therefore, a current corresponding to the current IsH flows through each transistor 93. Further, a current corresponding to the current IsH is applied as the first reference current to the detection transistor 91 of the first current mirror circuit electrically connected to each transistor 93.

In the first current mirror circuit, a current corresponding to the current IsH flows through the detection transistor 91, so that a voltage corresponding to the gate voltage of the detection transistor 91 is given as a power supply voltage (VdH) of the inverting buffer circuit 53. If the third transistor 56 is ON, the power supply voltage (VdH) is given as the gate voltage of the drive transistor 51 as it is, so that a current corresponding to the current IsH flows through the drive transistor 51. The low-side current IsL is the same as that of the high-side, except that the direction of the current is changed via the third current mirror circuit. As a result, the time required for expansion / restoration of the pressure chamber 26 can be adjusted, and good discharge characteristics can be obtained. The current control does not necessarily have to be the D / A converter 45, but may be a constant current circuit or a fixed resistance that outputs a predetermined current.

According to the inkjet head drive circuits 4, 8 and 9 of any of the above-described embodiments, there are variations in the characteristics of the semiconductor substrate forming the multi-output drive circuit, for example, between semiconductor wafers, and the influence of the characteristic changes due to the operating temperature. The inkjet head 100 can be driven with stable ejection characteristics. Although the inkjet head drive circuits 4, 8 and 9 described above use a MOS transistor as an example of each transistor, a bipolar transistor may be used.

That is, the liquid discharge head drive circuit according to the embodiment is as follows.
(1) A multi-output actuator charge / discharge circuit including a plurality of first transistors that give drive waveforms to a plurality of capacitive actuators, and the first transistor that drives the plurality of first transistors, respectively. It includes the same number of inverting buffer circuits and an adjusting unit that adjusts the power supply voltage of the inverting buffer circuit independently of the power supply voltage of the multi-output drive circuit.
(2) The inverting buffer circuit includes a series circuit of a second transistor having the same polarity as the first transistor and a third transistor having the same polarity as the first transistor, and drains the second transistor. And the drain of the third transistor are connected, further connected to the gate of the first transistor, the source of the second transistor and the source of the first transistor are connected in common, and the third The voltage applied to the source of the transistor is the power supply voltage of the inverting buffer circuit, and the gate of the second transistor and the gate of the third transistor are the inputs of the inverting buffer circuit.
(3) The input of the inverting buffer circuit controls ON / OFF of the first transistor.
(4) The power supply voltage of the inverting buffer circuit is controlled by a microprocessor via a D / A converter.
(5) A diode connected between the power supply of the inverting buffer circuit and the source of the first transistor and controlling the power supply voltage of the inverting buffer circuit is provided, and the first transistor paired with the diode is current. A mirror circuit is configured, and the maximum value of the current flowing through the first transistor is determined by the current flowing through the diode.
(6) The inverting buffer circuit includes a series circuit of a second transistor having the same polarity as the first transistor and a third transistor having the same polarity as the first transistor, and is a collector of the second transistor. And the collector of the third transistor are connected, further connected to the base of the first transistor, the emitter of the second transistor and the emitter of the first transistor are connected in common, and the third transistor is connected in common. The voltage applied to the emitter of the transistor is the power supply voltage of the inverting buffer circuit, and the base of the second transistor and the base of the third transistor are the inputs of the inverting buffer circuit.
(7) A diode connected between the power supply of the inverting buffer circuit and the emitter of the first transistor and controlling the power supply voltage of the inverting buffer circuit is provided, and the first transistor paired with the diode is current. A mirror circuit is configured, and the maximum value of the current flowing through the first transistor is determined by the current flowing through the diode.
(8) The transistor is a MOS transistor.
(9) The first to third transistors are MOS transistors, and the diode is a diode-connected MOS transistor having the same polarity as the first transistor.
(10) The plurality of first transistors drive each nozzle of a multi-nozzle inkjet head.

The inkjet head 100 is not limited to the configuration of the actuator 3 illustrated in FIG. For example, it may be a shear mode type actuator. Further, for example, a plurality of both the nozzle 23 and the actuator 3 may be arranged on the surface of the nozzle plate. Another drop-on-demand piezo type actuator 3 may be used.

In the above-described embodiment, the inkjet head 100 of the inkjet printer 10 has been described as an example of the liquid ejection device, but the liquid ejection device may be a modeling material ejection head of a 3D printer or a sample ejection head of a dispensing device.

The embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 Inkjet printer 100-103 Inkjet head 2 Nozzle head part 23 Nozzle 3 Actuator 4 Inkjet head drive circuit 41 Drive circuit board 42 Detection part 43 Micro processor 45 D / A converter 46, 47 Amplifier circuit 51, 52 Drive transistor 53, 54 Inverted buffer circuit 61,62 Detection transistor 81,84 First subtransistor 82,85 Second subtransistor

Claims (5)

A multi-output actuator charge / discharge circuit with multiple first transistors each giving a drive waveform to multiple capacitive actuators.
An inverting buffer circuit having the same number as the first transistor for driving the plurality of first transistors, respectively.
A liquid discharge head drive circuit comprising: an adjusting unit for adjusting the power supply voltage of the inverting buffer circuit independently of the power supply voltage of the multi-output drive circuit. The inverting buffer circuit includes a series circuit of a second transistor having the same polarity as the first transistor and a third transistor having the same polarity as the first transistor.
The drain of the second transistor and the drain of the third transistor are connected, and further connected to the gate of the first transistor.
The source of the second transistor and the source of the first transistor are connected in common,
The voltage applied to the source of the third transistor is the power supply voltage of the inverting buffer circuit.
The liquid discharge head drive circuit according to claim 1, wherein the gate of the second transistor and the gate of the third transistor are inputs of the inverting buffer circuit. The liquid discharge head drive circuit according to claim 1 or 2, wherein the power supply voltage of the inverting buffer circuit is controlled by a microprocessor via a D / A converter. A diode connected between the power supply of the inverting buffer circuit and the source of the first transistor and controlling the power supply voltage of the inverting buffer circuit is provided.
The first transistor paired with the diode constitutes a current mirror circuit, and the maximum value of the current flowing through the first transistor is determined by the current flowing through the diode. The liquid discharge head drive circuit according to any one. The first transistor is a MOS transistor and is
The liquid discharge head drive circuit according to claim 4, wherein the diode is a diode-connected MOS transistor having the same polarity as the first transistor.

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